FAN6756AMRMY [FAIRCHILD]
FAN6756â mWSaver⢠PWM Controller; FAN6756â ???? mWSaverâ ?? ¢ PWM控制器
| 型号： | FAN6756AMRMY |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | FAN6756â mWSaver⢠PWM Controller |
| 文件： | 总20页 (文件大小：1707K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
January 2013
FAN6756— mWSaver™ PWM Controller
Features
Description
The FAN6756 is a next-generation Green Mode PWM
controller with innovative mWSaver™ technology, which
dramatically reduces standby and no-load power
consumption, enabling compliance with worldwide
Standby Mode efficiency guidelines.
An innovative AX-CAP® method minimizes losses in the
EMI filter stage by eliminating the X-cap discharge
.
.
Single-Ended Topologies, such as Flyback and
Forward Converters
mWSaver™ Technology
-Achieves Low No-Load Power Consumption:
< 30 mW at 230 VAC (EMI Filter Loss Included)
-Eliminates X Capacitor Discharge Resistor Loss
with AX-CAP® Technology
resistors
while
meeting
IEC61010-1
safety
requirements. “Deep” Burst Mode clamps feedback
voltage and modulates feedback impedance with an
impedance modulator during Burst Mode operation,
which forces the system to operate in a Deep Burst
Mode with minimum switching losses.
-Linearly Decreases Switching Frequency to
23 kHz
-Burst Mode Operation at Light-Load Condition
-Impedance Modulation in “Deep” Burst Mode
-Low Operating Current (450 µA) in Deep Burst
Protections ensure safe operation of the power system
in various abnormal conditions. A proprietary frequency-
hopping function decreases EMI emission and built-in
synchronized slope compensation allows more stable
Peak-Current-Mode control over a wide range of input
voltage and load conditions. The proprietary internal line
compensation ensures constant output power limit over
the entire universal line voltage range.
Mode
-500 V High-Voltage JFET Startup Circuit to
Eliminate Startup Resistor Loss
.
.
Highly Integrated with Rich Features
-Proprietary Frequency Hopping to Reduce EMI
-High-Voltage Sampling to Detect Input Voltage
-Peak-Current-Mode Control with Slope
Requiring a minimum number of external components,
FAN6756 provides a basic platform that is well suited for
cost-effective flyback converter designs that require
extremely low standby power consumption.
Compensation
-Cycle-by-Cycle Current Limiting with Line
Compensation
-Leading Edge Blanking (LEB)
-Built-In 7 ms Soft-Start
Applications
Flyback power supplies that demand extremely low
standby power consumption, such as:
Advanced Protections
-Brown-in / Brownout Recovery
.
.
Adapters for Notebooks, Printers, Game Consoles,
etc.
-Internal Overload / Open-Loop Protection (OLP)
-VDD Under-Voltage Lockout (UVLO)
-VDD Over-Voltage Protection (VDD OVP)
-Over-Temperature Protection (OTP)
-Current-Sense Short-Circuit Protection (SSCP)
Open-Frame SMPS for LCD TV, LCD Monitors,
Printer Power, etc.
Related Resources
.
Evaluation Board: FEBFAN6756MR_T03U065A
Ordering Information
Protections(1)
Operating
Temperature Range
Packing
Method
Part Number
Package
OLP OVP OTP SSCP
FAN6756MRMY
FAN6756MLMY
A/R
L
L
L
L
L
A/R
A/R
8-Pin, Small Outline
Package (SOP)
-40 to +105°C
Tape & Reel
Note:
1. A/R = Auto Recovery Mode protection, L = Latch Mode protection.
© 2011 Fairchild Semiconductor Corporation
FAN6756 • Rev. 2.0.0
www.fairchildsemi.com
Application Diagram
Figure 1. Typical Application
Internal Block Diagram
Figure 2. Functional Block Diagram
© 2011 Fairchild Semiconductor Corporation
FAN6756 • Rev. 2.0.0
www.fairchildsemi.com
2
Marking Information
Z - Plant Code
X - 1-Digit Year Code
Y - 1-Digit Week Code
TT - 2-Digit Die Run Code
T - Package Type (M=SOP)
P - Y: Green Package
M - Manufacture Flow Code
ZXYTT
6756ML
TPM
ZXYTT
6756MR
TPM
Figure 3. Top Mark
Pin Configuration
SOP-8
GND
FB
1
2
3
4
8
7
6
5
GATE
VDD
SENSE
RT
NC
HV
Figure 4. Pin Configuration (Top View)
Pin Definitions
Pin # Name Description
1
2
3
GND
Ground. Placing a 0.1 µF decoupling capacitor between VDD and GND is recommended.
Feedback. The output voltage feedback information from the external compensation circuit is fed
into this pin. The PWM duty cycle is determined by comparing the FB signal with the current-
sense signal from the SENSE pin.
FB
NC
No Connection
High-Voltage Startup. The HV pin is typically connected to the AC line input through two external
diodes and one resistor (RHV). This pin is used, not only to charge the VDD capacitor during
startup, but also to sense the line voltage. The line voltage information is used for brownout
protection and power-limit line compensation. This pin also is used to intelligently discharge the
EMI filter capacitor when removal of the AC line voltage is detected.
4
5
HV
RT
Over-Temperature Protection. An external NTC thermistor is connected from this pin to GND.
Once the voltage of the RT pin drops below the threshold voltage, the controller latches off the
PWM. The RT pin also provides external latch protection. If the RT pin is not connected to the
NTC resistor for over-temperature protection, it is recommended to place a 100 kΩ resistor to
ground to prevent noise interference.
Current Sense. The sensed voltage is used for Peak-Current-Mode control, short-circuit
protection, and cycle-by-cycle current limiting.
6
7
8
SENSE
VDD
Power Supply of IC. Typically a hold-up capacitor connects from this pin to ground. A rectifier
diode, in series with the transformer auxiliary winding, connects to this pin to supply bias during
normal operation.
Gate Drive Output. The totem-pole output driver for the power MOSFET; internally limited to
GATE
VGATE-CLAMP
.
© 2011 Fairchild Semiconductor Corporation
FAN6756 • Rev. 2.0.0
www.fairchildsemi.com
3
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
VVDD
VFB
Parameter
Min.
Max.
30
Unit
V
DC Supply Voltage(2,3)
FB Pin Input Voltage
-0.3
-0.3
-0.3
7.0
V
VSENSE
VRT
SENSE Pin Input Voltage
RT Pin Input Voltage
7.0
V
7.0
V
VHV
HV Pin Input Voltage
500
400
150
+125
+150
+260
V
Power Dissipation (TA＜50°C)
PD
mW
Thermal Resistance (Junction-to-Air)
Operating Junction Temperature
JA
TJ
C/W
C
-40
-55
TSTG
TL
Storage Temperature Range
C
Lead Temperature (Wave Soldering or IR, 10 Seconds)
C
Human Body Model,
All Pins Except HV Pin(4)
JEDEC:JESD22-A114
6000
2000
ESD
V
Charged Device Model,
All Pins Except HV Pin(4)
JEDEC:JESD22-C101
Notes:
2. All voltage values, except differential voltages, are given with respect to the network ground terminal.
3. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
4. ESD level on HV pin is CDM=1250 V and HBM=500 V.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. We does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
Parameter
Min.
Typ.
Max.
Unit
RHV
Resistance on HV Pin
150
200
250
kΩ
© 2011 Fairchild Semiconductor Corporation
FAN6756 • Rev. 2.0.0
www.fairchildsemi.com
4
Electrical Characteristics
VDD=15 V and TJ=TA=25°C unless otherwise noted.
Symbol
Parameter
Condition
Min.
Typ.
Max.
Unit
VDD Section
VDD-ON Threshold Voltage to Startup
VDD Rising
16
17
18
V
V
Threshold Voltage to Stop
VUVLO
VDD Falling
VDD Falling
VDD Falling
VDD Falling
VDD Falling
5.5
6.5
7.5
Switching in Normal Mode
Threshold Voltage to Enable HV
VRESTART Startup to Charge VDD in Normal
Mode
4.7
11
7
V
V
V
V
Threshold Voltage to Stop
VDD-OFF
10
6
12
8
Operating in Protection Mode
Threshold Voltage to Enable HV
VDD-OLP Startup to Charge VDD in
Protection Mode
Threshold Voltage to Release
Latch Mode
VDD-LH
3.5
4.0
4.5
Threshold Voltage of VDD pin for
Enabling Brown-in
VUVLO
+2.5
VUVLO
+3.5
VDD-AC
VUVLO+3
V
IDD-ST
Startup Current
VDD=VDD-ON – 0.16 V
30
µA
mA
VDD=15 V, VFB = 3 V,
Gate Open
IDD-OP1 Supply Current in PWM Operation
1.8
VDD=15 V, VFB <1.4 V,
IDD-OP2 Supply Current when PWM Stops Deep Burst Mode,
Gate Off
450
µA
Internal Sink Current,
VDD=
VDD-OLP
+ 0.1 V
FAN6756MRMY
FAN6756MLMY
90
140
210
190
260
µA
µA
IDD-OLP VDD-OLP<VDD<VDD-OFF
,
160
Protection Mode
Internal Sink Current, VDD<VDD-OLP
Latch-Protection Mode
,
ILH
VDD = 5 V
30
µA
V
Threshold Voltage for VDD
Over-Voltage Protection
VDD-OVP
tD-VDDOVP
23.5
110
24.5
205
25.5
300
VDD Over-Voltage Protection
Debounce Time
µs
VDD Threshold Voltage for FB-Pin
VDD-ZFBR Impedance Modulation in Deep
Burst Mode
7
V
Continued on the following page…
© 2011 Fairchild Semiconductor Corporation
FAN6756 • Rev. 2.0.0
www.fairchildsemi.com
5
Electrical Characteristics (Continued)
VDD=15 V and TJ=TA=25C unless otherwise noted.
Symbol
Parameter
Condition
Min.
Typ.
Max.
Unit
HV Section
VAC=90 V(VDC=120 V),
IHV
Maximum Supply Current, HV Pin
mA
V
1.50
90
3.25
100
110
12
5.00
110
120
16
VDD=0 V
DC Source Series
R=200 kꢀ to HV Pin
VAC-OFF Threshold Voltage for Brownout
VAC-ON Threshold Voltage for Brown-in
DC Source Series
R=200 kꢀ to HV Pin
V
100
8
DC Source Series
R=200 kꢀ to HV Pin
△VAC
VAC-ON – VAC-OFF
V
tD-AC-OFF Debounce Time for Brownout
ms
ms
ms
V
40
95
65
90
Work Period of HV-Sampling
tS-WORK
Deep Burst Mode,
VFB<VFB-ZDC-DBM
140
260
185
320
Circuit in Deep Burst Mode
Rest Period of HV-Sampling
tS-REST
Deep Burst Mode,
VFB<VFB-ZDC-DBM
180
Circuit in Deep Burst Mode
(5)
(5)
(5)
VDC
VDC
VDC
VHV-DIS X-Cap. Discharge Threshold
RHV=200 kꢀ to HV Pin
×0.45
75
×0.51
115
×0.56
155
Debounce Time for Triggering
tD-HV-DIS
ms
ms
X-Cap. Discharge
Discharge Time when X-Cap.
tHV-DIS
360
510
660
Discharge is Triggered
Oscillator Section
62
65
68
Center Frequency
Hopping Range
VFB>VFB-G
Switching Frequency when
VFB>VFB-N
fOSC
kHz
±3.55
5.12
±4.25
6.40
±4.95
7.68
tHOP
Hopping Period(6)
ms
Switching Frequency when
VFB<VFB-G
fOSC-G
VFB<VFB-G
20
23
26
5
kHz
Frequency Variation vs. VDD
Deviation
fDV
fDT
VDD=11 to 22 V
%
%
Frequency Variation vs.
Temperature Deviation
5
TA=-40 to 105C
Continued on the following page…
© 2011 Fairchild Semiconductor Corporation
FAN6756 • Rev. 2.0.0
www.fairchildsemi.com
6
Electrical Characteristics (Continued)
VDD=15 V and TJ=TA=25C unless otherwise noted.
Symbol
Parameter
Condition
Min.
Typ.
Max.
Unit
Feedback Input Section
Feedback Voltage to Current-
Sense Attenuation
AV
1/4.5
1/4.0
8.5
1/3.5
V/V
kꢀ
V
Regular FB Internal Pull-High
Impedance
ZFB
VFB-OPEN FB Internal Biased Voltage
VFB-OLP Threshold Voltage for OLP
FB Pin Open
5.2
4.3
45.0
2.6
2.1
1.9
1.8
5.4
5.6
4.9
70.0
3.0
2.5
2.3
2.2
4.6
V
tD-OLP
VFB-N
Delay for OLP
57.5
2.8
ms
V
Threshold Voltage for Maximum
Switching Frequency
Threshold Voltage for Minimum
Switching Frequency
VFB-G
2.3
V
FB Threshold Voltage for Zero-
Duty Recovery
VFB-ZDCR
VFB-ZDC
2.1
V
FB Threshold Voltage for Zero-
Duty
2.0
V
FB Threshold Voltage for Zero-
Duty Recovery in Deep Burst
Mode
VFB-ZDCR-
VDD=VUVLO+0.3 V
2.5
2.7
2.9
V
DBM
VFB-ZDC- FB Threshold Voltage for Zero-
2.35
2.55
7.5
2.75
V
Duty in Deep-Burst Mode
DBM
Condition of Triggering Deep
Burst Mode
VFB<VFB-ZDC Repeats 3
Times Continuously
tDBM
ms
ms
Delay time of Entering Deep Burst
tD-DBM
Mode
600
Deep Burst Mode,
VFB-
RECOVER
Threshold Voltage for Leaving
Deep Burst Mode Immediately
VDD>VDD-ZFBR and Gate
0.9
V
Off
Current-Sense Section
tPD
Propagation Delay to Output
100
265
250
330
ns
ns
tLEB
Leading Edge Blanking Time
200
Current Limit at Low Line
(VAC-RMS=86 V)
V
DC=122 V, Series
VLIMIT-L
VLIMIT-H
VSSCP-L
VSSCP-H
tON-SSCP
0.43
0.46
0.39
50
0.49
0.42
70
V
V
R=200 kꢀ to HV
Current Limit at High Line
(VAC-RMS=259 V)
VDC=366 V, Series
0.36
30
R=200 kꢀ to HV
Threshold Voltage for SSCP at
Low Line (VAC-RMS=86 V)
VDC=122 V, Series
mV
mV
µs
R=200 kꢀ to HV
Threshold Voltage for SSCP at
High Line (VAC-RMS=259 V)
VDC=366 V, Series
R=200 kꢀ to HV
80
100
4.55
120
5.10
Minimum On-time of Gate to
Trigger SSCP
VSENSE<VSSCP-(L/H)
4.00
tD-SSCP Debounce Time for SSCP
tSS Soft-Start Time
VSENSE<VSSCP-(L/H)
Startup
110
5
170
7
230
9
µs
ms
Continued on the following page…
© 2011 Fairchild Semiconductor Corporation
FAN6756 • Rev. 2.0.0
www.fairchildsemi.com
7
Electrical Characteristics (Continued)
VDD=15V and TJ=TA=25C unless otherwise noted.
Symbol
Parameter
Condition
Min.
Typ.
Max. Unit
GATE Section
DCYMAX Maximum Duty Cycle
VGATE-L Gate Low Voltage
VGATE-H Gate High Voltage
75.0
82.5
90.0
1.5
%
V
VDD=15 V,
IO=5 mA
VDD=1 V, IO=5 mA
VDD=1 V, CL= nF
VDD=15 V, CL=1 nF
8
V
tr
tf
Gate Rising Time
Gate Falling Time
110
40
ns
ns
VGATE-
CLAMP
Gate Output Clamping Voltage
VDD=22 V
11.0
14.5
112
18.0
V
Continuously Gate Switching Number for
Leaving Deep-Burst Mode(6)
nSKIP
pulses
RT Section
IRT
Output Current of RT Pin
100
µA
V
VRTTH2 < VRT
<VRTTH1, Latch Off
After 14.5 ms
Threshold Voltage for Over-Temperature
Protection
VRTTH1
1.000
1.035
1.070
VRT < VRTTH2
,
VRTTH2
Threshold Voltage for Latch Triggering
Latch Off After
185 µs
0.65
9.66
0.70
0.75
V
Maximum External Resistance of RT Pin to
Trigger Latch Protection
ROTP
tD-OTP1
tD-OTP2
10.50
11.34
kꢀ
Debounce Time for Over-Temperature
Protection Triggering
VRTTH2 < VRT
VRTTH1
<
11.0
110
14.5
185
18.0
260
ms
µs
Debounce Time for Latch Triggering
VRT < VRTTH2
Over-Temperature Protection Section (OTP)
TOTP
Protection Junction Temperature(6,7)
TRESTART Restart Junction Temperature(6)
+135
°C
°C
TOTP-25
Notes:
5.
VDC is VAC × √2.
6. Guaranteed by design.
7. When activated, the output is stopped until junction temperature drops below TRESTART
.
© 2011 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN6756 • Rev. 2.0.0
8
Typical Performance Characteristics
Figure 6. Operation Supply Current (IDD-OP1
vs. Temperature
)
Figure 5. Startup Current (IDD-ST) vs. Temperature
Figure 7. Start Threshold Voltage (VDD-ON
)
Figure 8. Minimum Operating Voltage (VUVLO
vs. Temperature
)
vs. Temperature
Figure 9. OFF-State Internal Sink Current Under
Protection Mode (IDD-OLP) vs. Temperature
Figure 10. Minimum Operating Voltage Under
Protection Mode (VDD-OFF) vs. Temperature
Figure 11. Threshold Voltage to Enable HV startup in Figure 12. Threshold Voltage to Release Latch Mode
Protection Mode (VDD-OLP)vs. Temperature (VDD-LH) vs. Temperature
© 2011 Fairchild Semiconductor Corporation
FAN6756 • Rev. 2.0.0
www.fairchildsemi.com
9
Typical Performance Characteristics (Continued)
Figure 13. VDD Over-Voltage Protection (VDD-OVP
vs. Temperature
)
Figure 14. Frequency in Normal Mode (fOSC
)
vs. Temperature
70
65
60
55
50
45
40
35
30
25
20
2.1
2.3
2.5
2.7
2.9
3.1
3.3
Figure 15. PWM Switching Frequency vs. Feedback
Voltage (VFB
Figure 16. Maximum Duty Cycle (DCYMAX
vs. Temperature
)
)
0.56
0.54
0.52
0.5
RHV= 200kꢀ
0.48
0.46
0.44
0.42
0.4
0.38
0.36
100
150
200
250
300
350
400
Figure 18. FB-Pin Internal Bias Voltage (VFB-OPEN
)
Figure 17. Current Limit (VLIMIT) vs. HV Voltage (VHV
)
vs. Temperature
Figure 19. Open-Loop Protection Triggering
Level (VFB-OLP) vs. Temperature
Figure 20. Delay Time of Open-Loop Protection (tD-OLP
)
vs. Temperature
© 2011 Fairchild Semiconductor Corporation
FAN6756 • Rev. 2.0.0
www.fairchildsemi.com
10
Typical Performance Characteristics (Continued)
Figure 21. Brown-in (VAC-ON) vs. Temperature
Figure 22. Brownout (VAC-OFF) vs. Temperature
Figure 23. Inherent Current Limit of HV-Pin (IHV
)
Figure 24. Output Current from RT Pin (IRT
)
vs. Temperature
vs. Temperature
Figure 25. Over-Temperature Protection Threshold
Voltage (VRTTH1) vs. Temperature
Figure 26. Over-Temperature Protection Threshold
Voltage (VRTTH2) vs. Temperature
© 2011 Fairchild Semiconductor Corporation
FAN6756 • Rev. 2.0.0
www.fairchildsemi.com
11
Functional Description
Current Mode Control
fS
fOSC
FAN6756 employs Peak-Current Mode control, as
shown in Figure 27. An opto-coupler (such as the
H11A817A) and a shunt regulator (such as the KA431)
are typically used to implement the feedback network.
Comparing the feedback voltage with the voltage
across the Rsense resistor makes it possible to control
the switching duty cycle. The built-in slope
compensation stabilizes the current loop and prevents
sub-harmonic oscillation.
fOSC-G
VFB-ZDC1 VFB-ZDCR1VFB-G
VFB-N
VFB
Figure 28. VFB vs. PWM Frequency
Figure 27. Current-Mode Control Circuit Diagram
Leading-Edge Blanking (LEB)
Figure 29. Burst Switching in Green Mode
Each time the power MOSFET is switched on, a turn-on
spike occurs on the sense resistor. To avoid premature
termination of the switching pulse, a leading-edge
blanking time, tLEB, is introduced. During this blanking
period, the current-limit comparator is disabled and
cannot switch off the gate driver.
Deep Burst Mode & Feedback Impedance Switching
Deep Burst Mode is defined as a special operational
mode to minimize power consumption at extremely light-
load or no-load condition where, not only the switching
loss, but also power consumption of the FAN6756 itself,
are reduced further than in Green Mode. Deep Burst
Mode is initiated when the non-switching state of burst
switching in Green Mode persists longer than tDBM
(7.5 ms) for three consecutive burst switchings (as
shown in Figure 30). To prevent entering Deep Burst
Mode during dynamic load change, there is tD-DBM
(>600 ms) delay. If there are more than 112 consecutive
switching pulses during the tD-DBM delay, the FAN6756
does not go into Deep Burst Mode.
mWSaver™ Technology
Green-Mode
FAN6756 modulates the PWM frequency as a function
of the FB voltage to improve the medium- and light-load
efficiency, as shown in Figure 28. Since the output
power is proportional to the FB voltage in Current-Mode
control, the switching frequency decreases as load
decreases. In heavy-load conditions, the switching
frequency is fixed at 65 kHz. Once VFB decreases below
VFB-N (2.8 V), the PWM frequency starts linearly
decreasing from 65 kHz to 23 kHz to reduce switching
losses. As VFB drops to VFB-G (2.3 V), where switching
frequency is decreased to 23 kHz, the switching
frequency is fixed to avoid acoustic noise.
Once the FAN6756 enters Deep Burst Mode, the
feedback impedance, ZFB, is modulated by the
impedance modulator, as shown in Figure 31. When VFB
is under a threshold level, the impedance modulator
clamps VFB and disables switching. When VDD drops to
VDD-ZFBR (7 V, which is 0.5 V higher than VUVLO), the
impedance modulator controls ZFB, allowing VFB to rise
and resume switching operation. As shown in Figure 32,
by clamping VFB to disable switching while modulating
ZFB to enable switching, the system is forced into a
“Deep” Burst Mode to reduce switching loss.
When VFB falls below VFB-ZDC (2.0 V) as load decreases
further, the FAN6756 enters Burst Mode, where PWM
switching is disabled. Then the output voltage starts to
drop, causing the feedback voltage to rise. Once VFB
rises above VFB-ZDCR (2.1 V), switching resumes. Burst
Mode alternately enables and disables switching,
thereby reducing switching loss for lower power
consumption, as shown in Figure 29.
Deep Burst Mode maintains VDD as low as possible so
power consumption can be minimized. When the
FAN6756 enters Deep Burst Mode, several blocks are
disabled and the operation current is reduced from
IDD-OP1 (1.8 mA) to IDD-OP2 (450 µA).
© 2011 Fairchild Semiconductor Corporation
FAN6756 • Rev. 2.0.0
www.fairchildsemi.com
12
The feedback voltage thresholds where FAN6756
enters and exits Burst Mode change from VFB-ZDC (2.0 V)
and VFB-ZDCR (2.1 V) to VFB-ZDC-DBM (2.55 V) and VFB-ZDCR-
High-Voltage Startup and Line Sensing
The HV pin is typically connected to the AC line input
through two external diodes and one resistor (RHV), as
shown in Figure 33. When the AC line voltage is
applied, the VDD hold-up capacitor is charged by the line
voltage through the diodes and resistor. After VDD
voltage reaches the turn-on threshold voltage (VDD-ON),
the startup circuit charging the VDD capacitor is switched
off and VDD is supplied by the auxiliary winding of the
transformer. Once the FAN6756 starts, it continues
operating until VDD drops below 6.5 V (VUVLO). IC startup
time with a given AC line input voltage is given as:
(2.7 V) in Deep Burst Mode. This reduces the
DBM
switching loss more by increasing the energy delivered
to the load per switching operation, which eventually
reduces the total switching for a given load condition.
The FAN6756 exits Deep Burst Mode after more than
112 consecutive switching pulses in Deep Burst Mode.
Once the FAN6756 exits Deep Burst Mode, the feedback
impedance is modulated to 8.5 k to keep the original
loop response. The FAN6756 also exits Deep Burst
Mode when the opto-coupler transistor current is
virtually zero and VFB rises above VFB-RECOVER (0.9 V)
while switching is suspended.
2 2
VACIN
tSTARTUP RHV CDD ln
(1)
2 2
VACIN
VDDON
Figure 30. Entering Deep Burst Mode
FAN6756
5.4V
Figure 33. Startup Circuit
The HV pin detects the AC line voltage using a switched
VDD
Impedance
Modulator
voltage divider that consists of external resistor (RHV
)
ZFB
and internal resistor (RLS), as shown in Figure 33. The
internal line-sensing circuit detects line voltage using a
sampling circuit and peak-detection circuit. Since the
voltage divider causes power consumption when it is
switched on, the switching is driven by a signal with a
very narrow pulse width to minimize power loss. The
sampling frequency is adaptively changed according to
the load condition to minimize power consumption in
light-load condition.
Sensed Current
Signal
+
-
3R
1R
VFB
FB
CFB
2
PWM
Comparator
Based on the detected line voltage, brown-in and
brownout thresholds are determined as:
Figure 31. Feedback Impedance Modulation
R
200k
V
HV
AC ON
V
V
(RMS)
BROWN-IN
(2)
(3)
2
R
200k
V
AC OFF
HV
(RMS)
BROWNOUT
2
Since the internal resistor (RLS=1.6 kꢀ) of the voltage
divider is much smaller than RHV, the thresholds are
given as a function of RHV
.
Note:
8. VDD must be larger than VDD-AC to start, even though
the sensed line voltage satisfies Equation (2), as
shown in Figure 34.
Figure 32. Operation in Deep Burst Mode
© 2011 Fairchild Semiconductor Corporation
FAN6756 • Rev. 2.0.0
www.fairchildsemi.com
13
High / Low Line Compensation for
Constant Power Limit
FAN6756 has pulse-by-pulse current limit as shown in
Figure 35, which limits the maximum input power with a
given input voltage. If the output consumes beyond this
maximum power, the output voltage drops, triggering
the overload protection.
As shown in Figure 35, based on the line voltage,
VLINEPK; the high/low line compensation block adjusts the
current limit level, VLIMIT, defined as:
V
LIMITH V
R
RHV
3VLIMITL V
LIMITH
LIMITL V PK
LS
VLIMIT
(4)
LINE
2
2
To maintain the constant output power limit regardless
of line voltage, the cycle-by-cycle current limit level,
VLIMIT, decreases as line voltage increases. The current
limit level is proportional to the RHV resistor value and
power limit can be tuned using the RHV resistor. Figure
36 shows how the pulse-by-pulse current limit changes
with the line voltage for different RHV resistors.
Figure 34. Timing Diagram for Brown-in Function
AX-CAP® Discharge
Figure 35. Pulse-by-Pulse Current Limit Circuit
The EMI filter in the front end of the switched-mode
power supply (SMPS) typically includes a capacitor
across the AC line connector (CX). Most of the safety
regulations, such as UL 1950 and IEC61010-1, require
that the capacitor be discharged to a safe level within a
given time when the AC plug is abruptly removed from
its receptacle. Typically, discharge resistors across the
capacitor are used to make sure that capacitor is
discharged naturally, which introduces power loss as
long as it is connected to the receptacle.
Fairchild’s innovative AX-CAP® technology intelligently
discharges the filter capacitor only when the power
supply is unplugged from the power outlet. Since the
discharging circuit is disabled in normal operation, the
power loss in the EMI filter can be virtually removed.
0.48
0.46
0.44
0.42
0.4
0.38
0.36
0.34
0.32
0.3
100
150
200
250
300
350
400
Figure 36. Current Limit vs. Line Voltage
The discharge of the capacitor is achieved through the
HV pin. Once AC outlet detaching is detected, the HV
pin behaves as a resistor to ground, so the charges on
the capacitor can be discharged through the RHV in
series with the internal resistor of the HV pin. Since the
HV-pin internal resistor is much smaller than RHV, the
time constant of discharging process is almost RHV•CX.
Soft-Start
An internal soft-start circuit progressively increases the
pulse-by-pulse current-limit level of MOSFET for 7 ms
during startup to establish the correct working conditions
for transformers and capacitors.
© 2011 Fairchild Semiconductor Corporation
FAN6756 • Rev. 2.0.0
www.fairchildsemi.com
14
Open-Loop / Overload Protection (OLP)
Protections
Because of the pulse-by-pulse current-limit capability,
the maximum peak current is limited and, therefore, the
maximum input power is also limited. If the output
consumes more than this limited maximum power, the
output voltage (VO) drops below the set voltage. Then
the currents through the opto-coupler and transistor
become virtually zero and VFB is pulled HIGH. Once VFB
is higher than VFB-OLP (4.6 V) for longer than tD-OLP
(57.5 ms), OLP is triggered. OLP is also triggered when
the feedback loop is open by soldering defect.
FAN6756 provides full protection functions, including
Overload / Open-Loop Protection (OLP), VDD Over-
Voltage Protection (OVP), Over-Temperature Protection
(OTP), and Current-Sense Short-Circuit Protection
(SSCP). SSCP is implemented as Auto-Restart Mode,
while OVP and OTP are implemented as Latch Mode
protections.
OLP
is
Auto-Restart
Mode
for
FAN6756MRMY and Latch Mode for FAN6756MLMY.
When an Auto-Restart Mode protection is triggered,
switching is terminated and the MOSFET remains off,
causing VDD to drop. When VDD drops to the VDD-OFF
(11 V), the protection is reset. When VDD drops further to
VDD-OLP (7 V), the internal startup circuit is enabled and
the supply current drawn from HV pin charges the hold-
up capacitor. When VDD reaches the turn-on voltage of
17 V, normal operation resumes. In this manner, auto
restart alternately enables and disables the MOSFET
switching until the abnormal condition is eliminated.
Sense Short-Circuit Protection (SSCP)
The FAN6756 provides safety protection for Limited
Power Source (LPS) test. When the current-sense
resistor is short circuited by a soldering defect during
production, current-sensing information is not properly
obtained, resulting in unstable power supply operation.
To protect the power supply against a short circuit across
the current-sense resistor, FAN6756 shuts down when
current sense voltage is very low; even with a relatively
large duty cycle. As shown in Figure 37, the current-
sense voltage is sampled tON-SSCP (4.55 µs) after the gate
turn-on. If the sampled voltage (VS-CS) is lower than VSSCP
for 11 consecutive switching cycles (170 µs), the
FAN6756 shuts down immediately. VSSCP varies linearly
with line voltage. At 122 V DC input, it is typically 50 mV
(VSSCP-L); at 366 V DC, it is typically 100 mV (VSSCP-H).
When a Latch Mode protection is triggered, PWM
switching is terminated and the MOSFET remains off,
causing VDD to drop. When VDD drops to the VDD-OLP
(7 V), the internal startup circuit is enabled without
resetting the protection and the supply current drawn
from HV pin charges the hold-up capacitor. Since the
protection is not reset, the IC does not resume PWM
switching even when VDD reaches the turn-on voltage of
17 V, disabling HV startup circuit. Then VDD drops again
down to 7 V. In this manner, the Latch Mode protection
alternately charges and discharges VDD until there is no
more energy delivered into HV pin. The protection is
reset when VDD drops to 4 V, which is allowed only after
power supply is unplugged from the AC line.
VDD Over-Voltage Protection (OVP)
VDD over-voltage protection prevents IC damage from
voltage exceeding the IC voltage rating. When the VDD
voltage exceeds 24.5 V, the protection is triggered. This
protection is typically caused by an open circuit in the
secondary-side feedback network.
Figure 37. Timing Diagram of SSCP
Two-Level Under-Voltage Lockout (UVLO)
As shown in Figure 38, as long as protection is not
triggered, the turn-off threshold of VDD is fixed internally
at VUVLO (6.5 V). When a protection is triggered, the VDD
level to terminate PWM gate switching is changed to
VDD-OFF (11 V), as shown in Figure 39. When VDD drops
below VDD-OFF, the switching is terminated and the
operating current from VDD is reduced to IDD-OLP to slow
Over-Temperature Protection (OTP) and External
Latch Triggering
The RT pin provides adjustable Over-Temperature
Protection (OTP) and external latch triggering function.
For OTP, an NTC thermistor, RNTC, usually in series with
a resistor RA, is connected between the RT pin and
ground. The internal current source, IRT (100 µA),
introduces voltage on RT as:
down the discharge of VDD until VDD reaches VDD-OLP
.
This delays re-startup after shutdown by protection to
minimize the input power and voltage / current stress of
switching devices during a fault condition.
(5)
VRT IRT (RNTC RA )
At high ambient temperature, RNTC decreases, reducing
VRT. When VRT is lower than VRTTH1 (1.035 V) for longer
than tD-OTP1 (14.5 ms), the protection is triggered and the
FAN6756 enters Latch Mode protection.
The OTP can be trigged by pulling down the RT pin
voltage using an opto-coupler or transistor. Once VRT is
less than VRTTH2 (0.7 V) for longer than tD-OTP2 (185 µs),
the protection is triggered and the FAN6756 enters
Latch Mode protection.
When OTP is not used, place a 100 kꢀ resistor between
this pin and ground to prevent noise interference.
Figure 38. VDD UVLO at Normal Mode
© 2011 Fairchild Semiconductor Corporation
FAN6756 • Rev. 2.0.0
www.fairchildsemi.com
15
VDD
Gate Output / Soft Driving
17V
VDD-ON
The BiCMOS output stage has a fast totem-pole gate
driver. The output driver is clamped by an internal
14.5 V Zener diode to protect the power MOSFET gate
from over voltage. A soft driving is implemented to
minimize Electromagnetic Interference (EMI) by
reducing the switching noise.
11V
7V
VDD-OFF
VDD-OLP
GATE
t
Figure 39. VDD UVLO at Protection Mode
Typical Application Circuit
Application
PWM Controller
FAN6756MRMY
Input Voltage Range
Output
65 W Notebook Adapter
85 VAC ~ 265 VAC
19 V, 3.42 A
Figure 40. Schematic of Typical Application Circuit
© 2011 Fairchild Semiconductor Corporation
FAN6756 • Rev. 2.0.0
www.fairchildsemi.com
16
Transformer Schematic Diagram
.
.
Core: Ferrite Core RM-10
Bobbin: RM-10
Figure 41. Transformer Specification
Winding Specification
Pin (Start --> Finish)
Wire
Turns
Winding Method
Remark
N1
4 → 5
0.5φ×1
19
Solenoid Winding
Enameled Copper Wire
Insulation: Polyester Tape, t = 0.025 mm, 1-Layer
Shielding: Adhesive Tape of Copper Foil, t = 0.025×7 mm, 1.2-Layer Open Loop, Connected to Pin 4.
Insulation: Polyester Tape t = 0.025 mm, 3-Layer
N2
Insulation: Polyester Tape, t = 0.025 mm, 3-Layer
N3 9 → 7 0.4φ×1
Insulation: Polyester Tape, t = 0.025 mm, 1-Layer
S → F
0.9φ×1
8
Solenoid Winding
Triple Insulated Wire
7
Solenoid Winding
Enameled Copper Wire
Shielding: Adhesive Tape of Copper Foil, t = 0.025×7mm, 1.2-Layer Open Loop, Connected to Pin 4.
Insulation: Polyester Tape t = 0.025 mm, 3-Layer
N4
5 → 6
0.5φ×1
19
Solenoid Winding
Enameled Copper Wire
Insulation: Polyester Tape t = 0.025 mm, 3-Layer
Electrical Characteristics
Pin
Specification
510 H ±5%
Remark
1 kHz, 1 V
Primary-Side Inductance
4－6
4－6
Primary-Side Effective Leakage Inductance
Short All Other Pins
20 H Maximum
Typical Performance
Power Consumption
Input Voltage
Output Power
No Load
Actual Output Power
Input Power
0.024 W
Specification
Input Power < 0.03 W
Input Power < 0.5 W
Input Power < 1 W
0 W
230 VAC
0.25 W
0.232 W
0.495 W
0.339 W
0.5 W
0.643 W
Efficiency
Output Power
115 V, 60 Hz
230 V, 60 Hz
16.25 W
88.48%
88.00%
32.5 W
88.58%
87.89%
48.75 W
65 W
Average
87.68%
87.82%
87.45%
87.92%
86.22%
87.47%
© 2011 Fairchild Semiconductor Corporation
FAN6756 • Rev. 2.0.0
17
Physical Dimensions
5.00
4.80
A
0.65
3.81
8
5
B
1.75
6.20
5.80
4.00
3.80
5.60
1
4
PIN ONE
INDICATOR
1.27
1.27
(0.33)
M
0.25
C B A
LAND PATTERN RECOMMENDATION
SEE DETAIL A
0.25
0.10
0.25
0.19
C
1.75 MAX
0.10
C
0.51
0.33
OPTION A - BEVEL EDGE
0.50
0.25
x 45°
R0.10
R0.10
GAGE PLANE
OPTION B - NO BEVEL EDGE
0.36
NOTES: UNLESS OTHERWISE SPECIFIED
8°
0°
0.90
A) THIS PACKAGE CONFORMS TO JEDEC
MS-012, VARIATION AA, ISSUE C,
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
FLASH OR BURRS.
SEATING PLANE
(1.04)
0.406
D) LANDPATTERN STANDARD: SOIC127P600X175-8M.
E) DRAWING FILENAME: M08AREV13
DETAIL A
SCALE: 2:1
Figure 42. 8-Pin SOP-8 Package
Package drawings are provided as a service to customers considering our components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact our representative to verify or obtain the most recent
revision. Package specifications do not expand the terms of our worldwide terms and conditions, specifically the warranty therein,
which covers our products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2011 Fairchild Semiconductor Corporation
FAN6756 • Rev. 2.0.0
18
© 2011 Fairchild Semiconductor Corporation
FAN6756 • Rev. 2.0.0
19
Mouser Electronics
Authorized Distributor
Click to View Pricing, Inventory, Delivery & Lifecycle Information:
Fairchild Semiconductor:
FAN6756MLMY FAN6756MRMY FAN6756AMRMY FAN6756AMLMY
©2020 ICPDF网 联系我们和版权申明