FAN7316M [FAIRCHILD]
LCD Backlight Inverter Drive IC; LCD背光逆变器驱动IC
| 型号： | FAN7316M |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | LCD Backlight Inverter Drive IC |
| 文件： | 总21页 (文件大小：1103K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
January 2008
FAN7316
LCD Backlight Inverter Drive IC
Features
Description
The FAN7316 is a LCD backlight inverter drive IC that
controls N-N half-bridge topology. The FAN7316 can
also drive push-pull topology.
High-Efficiency Single-Stage Power Conversion
Wide Input Voltage Range: 4.5V to 24V
Backlight Lamp Ballast and Soft Dimming
Reduces Required External Components
Precision Voltage Reference Trimmed to 2%
N-N Half-Bridge Topology
The FAN7316 provides a low-cost solution by integrating
the external open-lamp protection circuit. The operating
voltage of the FAN7316 is wide, so the FAN7316 doesn’t
need an external regulator to supply the voltage to the
IC. The FAN7316 has the internal bootstrap driver, so
the external fast recovery diode can be avoided.
PWM Control at Fixed Frequency
Analog and Burst Dimming Function
Selectable Burst Dimming Polarity by ADIM Voltage
Striking Frequency Depending on Normal
Frequency
The FAN7316 provides various protections, such as
open-lamp regulation, arc protection, open-lamp
protection, short-circuit protection, and CMP-high
protection to increase the system reliability. The
FAN7316 provides analog dimming, burst dimming, and
burst dimming polarity selection functions.
Open-Lamp Protection
Open-Lamp Regulation
Short-Circuit Protection
The FAN7316 is available in a 20-SOIC package.
20-Pin SOIC
Applications
LCD TV
LCD Monitor
Ordering Information
Part Number
Package
Operating Temperature
Packing Method
FAN7316M
20-SOIC
20-SOIC
-25 to +85°C
-25 to +85°C
RAIL
FAN7316MX
TAPE & REEL
All packages are lead free per JEDEC: J-STD-020B standard.
Protected under U.S. patent number 5,652,479.
© 2007 Fairchild Semiconductor Corporation
FAN7316 • 1.0.1
www.fairchildsemi.com
Block Diagram
Figure 1. Internal Block Diagram
© 2007 Fairchild Semiconductor Corporation
FAN7316 • 1.0.1
www.fairchildsemi.com
2
Pin Assignments
20
19
18
17
16
15
14
13
12
11
F
PXYTT
FAN7316
1
2
3
4
5
6
7
8
9
10
F : Fairchild logo
P : Assembly site code
XY : Year & weekly code
TT : Die run code
FAN7316 : Device name
Figure 2. Package Diagram
© 2007 Fairchild Semiconductor Corporation
FAN7316 • 1.0.1
www.fairchildsemi.com
3
Pin Definitions
Pin #
Name
Description
This pin is for open-lamp protection. If OLP is lower than 1.5V at initial operation, the IC
operates at striking mode for BCT 450 cycles. If OLP is lower than 1.5V in normal mode, the
IC is shut down after a delay of three BCT cycles.
1
OLP1
2
OLP2
Error amplifier output. A compensation capacitor should be connected between this pin and
ground.
3
4
5
CMP
FB
Error amplifier inverting input. This pin voltage is regulated at 2V or ADIM voltage.
This pin is for burst dimming input. The voltage range of 0.5 to 2V at this pin controls burst
mode duty cycle from 0% to 100%.
BDIM
This pin is for positive analog dimming input. This voltage to 2V at this pin controls the
amplitude of the lamp current.
6
ADIM
7
8
ENA
GND
This pin is for turning on/off the IC.
Ground.
Low-side driver output. The output stage can deliver about 500mA source and sink current,
typically.
9
OUTL
10
11
VREF
VIN
6V reference voltage.
IC supply voltage.
High-side floating supply. The bootstrap capacitor should be connected between this pin
and VS pin, which can be fed by an internal bootstrap MOSFET.
12
13
14
15
16
VB
OUTH
VS
High-side driver output. The output stage can deliver about 500mA source and sink current,
typically.
High-side floating supply return. Layout care should be taken to avoid below-ground spikes
on this pin.
This pin is for short-circuit protection. If SCP is higher than 2V, IC enters shutdown mode
after a delay of 32 BCT cycles.
SCP
RT
This pin programs the switching frequency. The resistor should be connected between this
pin and ground.
This pin programs the burst dimming frequency. A capacitor should be connected between
this pin and ground. The waveform of this pin is the triangular waveform whose amplitude is
from 0.5V to 2V. This pin voltage goes up to 4V when the IC enters shutdown mode.
17
18
BCT/FT
OLR
This pin is for open-lamp regulation. If the voltage at OLR reaches 2V, the IC makes this pin
voltage be controlled not to exceed 2V. If OLR voltage is higher than 1.75V, the IC enters
shutdown mode after delays of 451 BCT cycles in striking mode and three BCT cycles in
normal mode, respectively. If this pin voltage is higher than 3V, the IC enters shutdown
mode without delay.
This pin is for open lamp protection. If OLP is lower than 1.5V at initial operation, the IC
operates at striking mode for BCT 450 cycles. If OLP is lower than 1.5V in normal mode, the
IC is shut down after a delay of three BCT cycles.
19
20
OLP4
OLP3
© 2007 Fairchild Semiconductor Corporation
FAN7316 • 1.0.1
www.fairchildsemi.com
4
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In
addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
VIN
Parameter
Min.
4.5
Max.
24
Unit
V
IC Supply Voltage
VB
High-Side Floating Supply
-0.3
-2(3)
-40
33
V
VS
High-Side Floating Supply Return
Operating Junction Temperature
Storage Temperature Range
Thermal Resistance Junction-Air(1,2)
Power Dissipation
VB-7
+150
+150
90
V
TJ
°C
TSTG
θJA
-65
°C
°C /W
W
PD
1.4
Notes:
1. Thermal resistance test board. Size: 76.2mm x 114.3mm x 1.6mm (1S0P); JEDEC standard: JESD51-2, JESD51-3.
2. Assume no ambient airflow.
Recommended Operating Ratings
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
Parameter
Min.
Max.
22
Unit
V
VIN
VB
VS
TA
IC Supply Voltage
4.5
High-Side Floating Supply
VS-0.3
(3)
VS+6.5
25
V
High-Side Floating Supply Return
Operating Ambient Temperature
V
-25
+85
°C
Notes:
3. The VS is tolerant to short negative transient spikes.
Pin Breakdown Voltage
Pin #
Name
OLP1
OLP2
CMP
FB
Value
Unit
Pin #
11
Name
Value
Unit
1
2
7
7
7
7
7
7
7
VIN
VB
24
33
7
12
3
13
OUTH
VS
4
14
33
7
5
BDIM
ADIM
ENA
15
SCP
RT
V
V
6
16
7
7
17
BCT/FT
OLR
OLP4
OLP3
7
8
GND
OUTL
VREF
18
7
9
7
7
19
7
10
20
7
© 2007 Fairchild Semiconductor Corporation
FAN7316 • 1.0.1
www.fairchildsemi.com
5
Electrical Characteristics
For typical values, TA=25°C, VIN=18V, and -25°C ≤ TA ≤ 85°C, unless otherwise specified. Specifications to -25°C ~
85°C are guaranteed by design based on final characterization results.
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
VREF Section (Recommend X7R Capacitor)
V6
6V Regulation Voltage
6V Line Regulation
6V Load Regulation
CMP=0V
5.76
6.00
6.24
25
V
V6line
V6load
VIN=7V, 18V
mV
mV
60
10µA≤16≤5mA
Oscillator Section (Main)
Vfbth
Vcth
Vctl
FB Threshold Voltage
ADIM=1, OLP=0V
0.45
2.0
V
V
V
CT High Voltage(4)
CT Low Voltage(4)
0.5
Oscillator Section (Burst)
TA=25°C, BCT=10nF
BCT=10nF
288
282
300
300
2
312
318
Hz
Hz
V
foscb
Oscillation Frequency
Vbcth
Vbctl
Vbctft
BCT High Voltage
BCT Low Voltage
BCT Fault Voltage
BCT=10nF
BCT=10nF
0.5
4
V
SCP=2.5V
V
Error Amplifier Section
Gm1
AV
Error Amplifier Trans-conductance
Error Amplifier Open-loop Gain(4)
CMP=1, ADIM=1V
100
360
50
600
umho
dB
TA=25°C, ADIM=2.5V
1.97
2.00
2.03
V
V2
2V Regulation Voltage
260
100
-100
1.6
0
ppm/°C
µA
lsin
CMP Sink Current
ADIM=1V, FB=2.5V
CMP=1V, FB=0V
1.75V<OLR<2V
OLR>2V
66
134
-66
lsur1
Isur2
Isur3
CMP Source Current 1
CMP Source Current 2
CMP Source Current 3(4)
-134
µA
µA
µA
Under-Voltage Lockout Section (UVLO)
Vth
Start Threshold Voltage
Start Threshold Voltage Hysteresis
Start-up Current
ENA=2.5V
ENA=2.5V
VIN=Vth-0.2
Not switching
3.9
0.2
20
4.2
0.4
60
4.5
0.6
150
2.0
V
V
Vthhys
Ist
µA
mA
Iop
ENA Section
Vena
Operating Supply Current
1.5
Enable State Input Voltage
Disable Stage Input Voltage
Stand-by Current
2
5
V
V
Vdis
0.7
150
Isb
ENA=0
100
µA
Note:
4. These parameters, although guaranteed, are not 100% tested in production.
© 2007 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN7316 • 1.0.1
6
Electrical Characteristics (Continued)
For typical values, TA=25°C, VIN=18V, and -25°C ≤ TA ≤ 85°C, unless otherwise specified. Specifications to -25°C ~
85°C are guaranteed by design based on final characterization results.
Symbol
Parameter
Test Conditions
Min.
Typ.
Max. Unit
Protection Section
Vscp
Vcmpr
Volp
Short-Circuit Protection Voltage
CMP Protection Voltage
1.9
2.8
2.0
3.0
2.1
3.2
V
V
Open-Lamp Protection Voltage
Over-Voltage Protection
1.4
1.5
1.6
V
Vovp
Volr1
Volr2
Volrhy
2.85
1.60
1.9
3.00
1.75
2.0
3.15
1.90
2.1
V
Open-Lamp Regulation Voltage 1
Open-Lamp Regulation Voltage 2
Open-Lamp Regulation Hysteresis(5)
V
V
250
1.5
mV
s
Striking, foscb=300Hz
Normal, foscb=300Hz
Striking, foscb=300Hz
Normal, foscb=300Hz
Striking, foscb=300Hz
Normal, foscb=300Hz
Striking, foscb=300Hz
Normal, foscb=300Hz
1.4
80
1.4
80
1.4
6
1.6
120
1.6
120
1.6
10
tscp
tcmp
tolp
Short-Circuit Protection Delay(5)
100
1.5
ms
s
CMP Protection Delay(5)
100
1.5
ms
s
Open-Lamp Protection Delay(5)
ms
s
1.4
80
1.5
100
150
1.6
120
tolr
Open-Lamp Regulation Delay(5)
Thermal Shutdown(5)
ms
°C
TSD
Output Section
47.4
47
49.0
49
50.6
51
TA=25°C, RT=27kΩ
RT=27kΩ
fnrmo Output Normal Frequency
kHz
kHz
61.5
61
64.0
64
66.4
67
TA=25°C, RT=27kΩ
RT=27kΩ
fstr
Output Striking Frequency
Vouvh
Vouvl
Vosth
Vost
OUTH Voltage Before Start-up
OUTL Voltage Before Start-up
High-Side Output Voltage at VENA=0V
Low-Side Output Voltage at VENA=0V
High-Side Output Voltage
VIN=Vth-0.6
VIN=Vth-0.6
VIN=18V
-0.45
-0.45
-0.45
-0.45
5.5
0
0.45
0.45
0.45
0.45
6.5
V
V
0
0
V
VIN=18V
0
V
Vohh
Vohl
VIN=18V
6.0
6.0
500
500
500
500
500
V
Low-Side Output Voltage
VIN=18V
5.5
6.5
V
Idsurh
Idsinh
Idsurl
Idsinl
tdead
High-Side Output Drive Source Current(5)
High-Side Output Drive Sink Current(5)
Low-Side Output Drive Source Current(5)
Low-Side Output Drive Sink Current(5)
Dead Time(5)
VIN=18V
mA
mA
mA
mA
ns
VIN=18V
VIN=18V
VIN=18V
Note:
5. These parameters, although guaranteed, are not 100% tested in production.
© 2007 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN7316 • 1.0.1
7
Typical Performance Characteristics
Figure 3. Start Threshold Voltage vs. Temp.
Figure 5. Start-up Current vs. Temp.
Figure 4. Start Threshold Voltage Hys. vs. Temp.
Figure 6. Standby Current vs. Temp.
Figure 7. Operating Frequency vs. Temp.
Figure 8. Striking Frequency vs. Temp.
© 2007 Fairchild Semiconductor Corporation
FAN7316 • 1.0.1
www.fairchildsemi.com
8
Typical Performance Characteristics (Continued)
Figure 9. Burst Dimming Frequency vs. Temp.
Figure 10. VREF Voltage vs. Temp.
Figure 12. VREF Load Regulation Voltage vs. Temp.
Figure 14. CMP Source Current 1 vs. Temp.
Figure 11. VREF Line Regulation Voltage vs. Temp.
Figure 13. CMP Sink Current vs. Temp.
© 2007 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN7316 • 1.0.1
9
Typical Performance Characteristics (Continued)
Figure 15. CMP Source Current 2 vs. Temp.
Figure 16. Operating Current vs. Temp.
Figure 18. Open-Lamp Protection Voltage vs. Temp.
Figure 20. Over-Voltage Protection vs. Temp.
Figure 17. Error Amplifier 2V Voltage vs. Temp.
Figure 19. Open-Lamp Regulation Voltage 2 vs. Temp.
© 2007 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN7316 • 1.0.1
10
Typical Performance Characteristics (Continued)
Figure 21. Short-Circuit Protection Voltage vs. Temp.
Figure 23. Low-Side Output Voltage vs. Temp.
Figure 22. High-Side Output Voltage vs. Temp.
© 2007 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN7316 • 1.0.1
11
Functional Description
UVLO: The under-voltage lockout (UVLO) circuit
guarantees the stable operation of the IC’s control circuit
by stopping and starting it as a function of the VIN value.
The UVLO circuit turns on the control circuit when VIN
exceeds 4.5V. When VIN is lower than 3.9V, the IC’s
start-up current is less than 150µA.
tch
tdch
2V
-
9µA
Ich
+
S
R
Q
Q
BCT
-
18µA
Idch
ENA: Applying voltage higher than 2V to the ENA pin
enables the IC. Applying voltage lower than 0.7V to the
ENA pin disables the IC.
0.5V
+
Internal Main Oscillator: The internal timing capacitor
(CT), 20pF, is charged by the reference current source,
which is formed by the timing resistor (RT). The RT
voltage is regulated at 1.728V. The sawtooth waveform
charges up to 2V. Once CT voltage is reached, the CT
begins discharging down to 0.5V. Next, the CT starts
charging again and a new switching cycle begins, as
shown in Figure 24. The main frequency is programmed
by adjusting the RT value. The main frequency is
calculated as:
Figure 25. Burst Dimming Oscillator Circuit
Analog Dimming: There are two kinds of analog
dimming polarity: positive analog dimming and negative
analog dimming.
For positive analog dimming, the lamp intensity is
controlled with the ADIM signal. The lamp intensity is
proportional to ADIM signal; as ADIM voltage increases,
the lamp intensity increases. Figure 26 shows how to
implement negative analog dimming circuit and Figure
27 shows the lamp current waveform vs. DIM in positive
analog dimming mode.
2736
fOSC
≈
[KHz]
(1)
RT [KΩ]
Figure 24. Main Oscillator Circuit
Figure 26. Positive Analog Implementation Circuit
The striking frequency is 1.3 times as high as the main
frequency.
Burst Dimming Oscillator: The burst capacitor timing
(BCT) is charged by the internal reference current
source. The triangular waveform charges up to 2V. Once
the BCT voltage is reached, the capacitor begins
discharging down to 0.5V. Next, the BCT starts charging
again and a new switching cycle begins, as shown in
Figure 25. The burst dimming frequency is programmed
by adjusting BCT value. The burst dimming frequency is
calculated as:
3 •103
BCT[nF]
fOSCB
≈
[Hz]
(2)
Figure 27. Positive Analog Dimming Waveform
To avoid visible flicker, the burst dimming frequency
should be greater than 120Hz.
© 2007 Fairchild Semiconductor Corporation
FAN7316 • 1.0.1
www.fairchildsemi.com
12
For negative analog dimming, the lamp intensity is
controlled with the external DIM signal and the resistors.
The lamp intensity is inversely proportional to DIM
voltage. As DIM voltage increases, the lamp intensity
decreases. Figure 28 shows how to implement a
negative analog dimming circuit and Figure 29 shows the
lamp current waveform vs. DIM in negative analog
dimming mode.
2V
BDIM
BCT
0.5V
3.5V
ADIM
Lamp
current
0V
6V
OUTH
6V
OUTL
Figure 28. Negative Analog Implementation Circuit
Figure 31. Negative Burst Dimming Chosen
Burst Dimming: There are also two kinds of burst
dimming polarity: positive analog dimming and negative
analog dimming. The lamp intensity is controlled with the
BDIM voltage. By comparing the BDIM voltage with the
0.5~2V triangular waveform of burst dimming oscillator
(BCT), the PWM pulse is generated. The PWM pulse
controls the CMP voltage by discharging and charging
the CMP capacitor.
For positive burst dimming, when BDIM voltage is higher
than BCT voltage, the lamp current is turned on. So, 2V
on BDIM commands full brightness. The duty cycle of the
PWM pulse determines the lamp brightness. The lamp
intensity is proportional to BDIM voltage. As BDIM
voltage increases, the lamp intensity also increases.
Figure 32 shows the lamp current waveform vs. DIM in
positive analog dimming mode.
Figure 29. Negative Analog Dimming Waveform
Burst Dimming Polarity Selection: FAN7316 provides
the function to select burst dimming polarity by ADIM pin
voltages. If ADIM pin voltage is lower than 3V, positive
burst dimming is chosen. Refer to Figure 30.
2V
BDIM
BCT
0.5V
2V
Disharge
current
100uA
Charge
current
100uA
BDIM
CMP
FB
BCT
0.5V
0.5V
0V
ADIM3.0V
0V
0V
Lamp
current
0V
Lamp
current
6V
OUTH
6V
6V
OUTH
OUTL
OUTL
6V
Figure 30. Positive Burst Dimming Chosen
If the ADIM pin voltage is higher than 3.5V, negative
dimming polarity is chosen. Refer to Figure 31.
Figure 32. Positive Burst Dimming Operation
© 2007 Fairchild Semiconductor Corporation
FAN7316 • 1.0.1
www.fairchildsemi.com
13
For negative burst dimming, when BDIM voltage is lower
than BCT voltage, the lamp current is turned on. So, 0V
on BDIM commands full brightness. The duty cycle of the
PWM pulse determines the lamp brightness. The lamp
intensity is inversely proportional to BDIM voltage. As
BDIM voltage increases, the lamp intensity decreases.
Figure 32 shows the lamp current waveform vs. DIM in
negative analog dimming mode.
Positive dimming polarity
2V
BDIM
BCT
0.5V
1.5V
6V
Lamp isn t ignited
Lamp is ignited
OLP
OUTH
6V
OUTL
Burst dimming disable
Burst dimming enable
Figure 33. Positive Burst Dimming Operation
Burst dimming can be implemented by not only DC
voltage, also PWM pulse as BDIM signal. Figure 34
shows how to implement burst dimming by using PWM
pulse as BDIM signal.
Figure 35. Burst Dimming During Striking Mode
Output Drives: FAN7316 is designed to drive high-side
and low-side MOSFETs with symmetrical duty cycle. A
fixed dead time of 500ns is introduced between two
outputs at maximum duty cycle, as shown Figure 36.
tch
tdch
2V
-
Ich
+
9µA
S
R
Q
Q
BCT
-
Idch
18µA
0.5V
+
Comparator
External
Pulse Signal
-
Burst Signal
to Error Amplifier
BDIM
+
Figure 34. Burst Dimming Using an External Pulse
During striking mode, burst dimming operation is
disabled to guarantee the continuous striking time.
Figure 35 shows that burst dimming is disabled during
striking mode.
Figure 36. MOSFETs Gate Drive Signal
© 2007 Fairchild Semiconductor Corporation
FAN7316 • 1.0.1
www.fairchildsemi.com
14
Bootstrap Operation: To choose the proper CBS value,
the external MOSFET can be seen as an equivalent
capacitor. This capacitor, CIN, is related to the MOSFET
total gate charge as:
QGATE
CIN
=
(3)
VGATE
The ratio between capacitors CIN and CBS is proportional
to the cyclical voltage loss:
CBS >> CIN
(4)
For example: if QGATE is 24nC and VGATE is 10V, CIN is
2.4nF. With CBS=100nF, the drop is 240mV.
The bootstrap driver introduces a voltage drop due to
MOSFET RDSON (typical value: 100Ω). The following
equation is useful to compute the voltage drop on the
bootstrap MOSFET:
QGATE
VDROP = ICHARGE •RDSON → VDROP
=
•RDSON
(5)
TCHARGE
Figure 37. Open-Lamp Regulation in Striking Mode
where QGATE is the gate charge of the external MOSFET,
RDSON is the on resistance of the bootstrap MOSFET,
and TCHARGE is the charging time of the bootstrap
capacitor.
For example: If QGATE is 24nC and TCHARGE is 10µs, the
drop on the bootstrap MOSFET is about 0.24V.
24nC
VDROP
=
•100Ω = 0.24V
(6)
10µs
Protections: The FAN7316 has several protections:
Open-Lamp Regulation (OLR), Arc Protection, Open-
Lamp Protection (OLP), Short-Circuit Protection (SCP),
CMP-High Protection, and Thermal Shutdown (TSD). All
protections are latch-mode protections. The latch is reset
when VIN falls to the UVLO voltage or ENA is pulled
down to GND.
Open-Lamp Regulation: When a voltage higher than
2V is applied to the OLR pin, the IC enters regulation
mode and controls CMP voltage. The IC limits the lamp
voltage by decreasing CMP source current. If the OLR
voltage is higher than 1.75V, CMP source current
decreases from 100µA to 1.6µA. If the OLR voltage
reaches at 2V, CMP source current decreases to 0µA,
so CMP voltage remains constant and the lamp voltage
also remains constant, as shown in Figure 37. At the
same time, the counter based on BCT time starts
counting 450 cycles and 32 cycles at striking mode and
normal mode, respectively, then the IC enters shutdown,
as shown in Figure 38 and Figure 39.
Figure 38. Open-Lamp Regulation in Striking Mode
Figure 39. Open-Lamp Regulation in Normal Mode
© 2007 Fairchild Semiconductor Corporation
FAN7316 • 1.0.1
www.fairchildsemi.com
15
Arc Protection: If OLR voltage is higher than 3V, the IC
enters shutdown mode after a delay of two CT cycles, as
shown in Figure 40.
Short-Circuit Protection: If SCP is higher than 2V, the
counter based on BCT time starts counting 450 cycles
and 32 cycles at striking mode and normal mode,
respectively, then the IC enters shutdown, as shown in
Figure 43 and Figure 44.
4V
Striking time=1.5s @ BCT=300Hz
2V
BCT
0.5V
450 cycles
Lamp isn’t ignited
1.5V
OLP
2V
SCP
6V
OUTH
6V
OUTL
Figure 40. Arc Protection
Open-Lamp Protection: If OLP is lower than 1.5V at
initial operation, the IC operates at striking mode for BCT
450 cycles, as shown in Figure 41. If OLP is lower than
1.5V at normal mode, the IC is shut down after a delay of
three BCT cycles, as shown in Figure 42.
Shutdown
Figure 43. Short-Circuit Protection in Striking Mode
4V
Protection Delay 100ms @ BCT=300Hz
2V
BCT
0.5V
32 cycles
Lamp is ignited
1.5V
2V
OLP
SCP
6V
6V
Shutdown
Figure 41. Open-Lamp Protection in Striking Mode
Figure 44. Short-Circuit Protection in Normal Mode
CMP-High Protection: If CMP is higher than 3V, the
counter based on BCT time starts counting 450 cycles
and 32 cycles at striking mode and normal mode,
respectively, then the IC enters shutdown, as shown in
Figure 45 and Figure 46.
Figure 42. Open-Lamp Protection in Normal Mode
© 2007 Fairchild Semiconductor Corporation
FAN7316 • 1.0.1
www.fairchildsemi.com
16
CMP-High Protection: If CMP is higher than 3V, the
counter based on BCT time starts counting 450 cycles
and 32 cycles at striking mode and normal mode,
respectively, then the IC enters shutdown, as shown in
Figure 45 and Figure 46.
4V
Striking time=1.5s @ BCT=300Hz
2V
BCT
0.5V
450 cycles
Lamp isn’t ignited
1.5V
OLP
3V
CMP
6V
OUTH
6V
OUTL
Shutdown
Figure 45. CMP-High Protection in Striking Mode
Figure 46. CMP-High Protection in Normal Mode
Thermal Shutdown: The IC provides the function to
detect the abnormal over-temperature. If the IC
temperature exceeds approximately 150°C, the thermal
shutdown triggers.
© 2007 Fairchild Semiconductor Corporation
FAN7316 • 1.0.1
www.fairchildsemi.com
17
Typical Application Circuit (LCD Backlight Inverter)
Application
Device
Input Voltage Range
Number of lamps
19-Inch LCD Monitor
FAN7316
14.5±10%
4
1. Features
High-Efficiency Single-Stage Power Conversion
N-N Half-Bridge Topology
Reduces Required External Components
Enhanced System Reliability through Protection Functions
F1
CN2
35001WR-02A
LTM190EX
TX1
1
FUSE
C1
330u
C2
1u
C3
1u
1
CN1
0
2
35001WR-02A
2
0
0
1
0
0
0
1
OLP3 OLP4 OLR
C9
0
C8
3p
3p
2
C6
1u
2
C5
R1
R24
0R
R2
R3
10n 30k
OLP4
OLP3
100k 100k
R4
C10
R5
10k
C11
M1
D2
10k
2.7n
2.7n
BAV70
CN5
SN1
DN1
DN1
DN2
DN2
R6
680
R7
680
0
0
0
0
1
2
3
4
5
6
7
8
9
10
IC1
R31
D3
BAV70
15V
GN1
SN2
GN2
10R
0
C4 10u
C7 10u
CN4
0
0
FAN7316
35001WR-02A
DIM(0~3.3V)
ON/OFF
R30
TX2
1
1
10R
CN3
AOP800
2
35001WR-02A
2
12505WR-10
1
0
1
R8
R9
0
100k 100k
R25
N.C.
C15
3p
C16
3p
0
2
C12
33n
2
OLP2
OLP1
R22
0R
OLP1 OLP2
REF
C13
1u
R27
10k
R14 C18
10k 2.7n
R15 C19
10k 2.7n
0
R13
100k
R29
D4
0
BAV70
C23 R23
N.C. N.C.
0
OLR
R10
12k
R12
75k
R17
680
R16
680
0
0
0
0
D5
BAV70
R18
0
0
100k
C21
R11
4.7n
0
0
C14
9.1k
0.1u
0
0
R28
0
0
R20
10k
20k
R21
C20
1n
R19
10k
C17
10n
20k
0
0
0
Figure 47. Typical Application Circuit
2. Transformer Schematic Diagram
Figure 48. Transformer Schematic Diagram
3. Core & Bobbin
Core: EFD2126
Material: PL7
Bobbin: EFD2126
© 2007 Fairchild Semiconductor Corporation
FAN7316 • 1.0.1
www.fairchildsemi.com
18
4. Winding Specification
Pin No.
5 Æ 2
Wire
Turns
12
Inductance
94µH
Leakage Inductance
Remarks
1kHz, 1V
1kHz, 1V
9.1µH
1 UEW 0.45φ
1 UEW 0.04φ
3.88H
420mH
7 Æ 9
2560(=0+360•7)
5. BOM of the Application Circuit
Part Ref.
Value
Fuse
Description
Part Ref.
Value
Description
C5
10nF
1µF
50V 1608 K
50V 2012 K
16V 3216
F1
24V 3A
FUSE
C6
Resistor (SMD)
C7
10µF
2.7nF
2.7nF
33nF
1µF
R1
R2
30k
100k
100k
10k
1608 F
1608 J
1608 J
1608 F
1608 F
1608 F
1608 F
1608 J
1608 J
1608 F
1608 F
1608 F
1608 J
1608 F
1608 F
1608 F
1608 F
1608 F
1608 F
1608 J
1608 F
C10
C11
C12
C13
C14
C17
C18
C19
C20
C21
C23
50V 1608 K
50V 1608 K
50V 1608 K
50V 3216 K
50V 1608 K
50V 1608 K
50V 1608 K
50V 1608 K
50V 1608 K
50V 1608 K
R3
R4
R5
10k
10nF
10nF
2.7nF
2.7nF
1nF
R6
680
R7
680
R8
100k
100k
12k
R9
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
R23
R24
R25
R27
R28
R29
R30
R31
4.7nF
NC
9.1k
75k
Capacitor (DIP)
100k
10k
C8
C9
3p
3p
3p
3p
3KV
3KV
3KV
3KV
10k
C15
C16
680
680
Diode (SMD)
100k
10k
D2
D3
D4
D5
BAV70
BAV70
BAV70
BAV70
Fairchild Semiconductor
Fairchild Semiconductor
Fairchild Semiconductor
Fairchild Semiconductor
10k
20k
0
Electrolytic capacitor
NC
C1
M1
330µ
25V
0
MOSFET (SMD)
NC
AOP800
Alpha & Omega
10k
1608 F
1608 F
Wafer (SMD)
20k
CN1
CN2
CN3
CN4
CN5
35001WR-02A
35001WR-02A
35001WR-02A
35001WR-02A
12505WR-10
0
10
1608 J
1608 J
10
Capacitor (SMD)
1µF
1µF
10µF
C2
C3
C4
50V 3216 K
50V 3216 K
16V 3216
Transformer (DIP)
TX1
TX2
EFD2126
EFD2126
© 2007 Fairchild Semiconductor Corporation
FAN7316 • 1.0.1
www.fairchildsemi.com
19
Physical Dimensions
13.00
12.60
A
11.43
20
11
B
9.50
10.65 7.60
10.00 7.40
2.25
1
PIN ONE
INDICATOR
10
0.65
0.51
0.35
1.27
1.27
M
0.25
C B A
LAND PATTERN RECOMMENDATION
SEE DETAIL A
2.65 MAX
0.33
0.20
C
0.10
C
0.30
0.10
SEATING PLANE
0.75
0.25
X 45°
NOTES: UNLESS OTHERWISE SPECIFIED
(R0.10)
(R0.10)
A) THIS PACKAGE CONFORMS TO JEDEC
MS-013, VARIATION AC, ISSUE E
GAGE PLANE
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
FLASH OR BURRS.
0.25
8°
0°
D) CONFORMS TO ASME Y14.5M-1994
1.27
0.40
SEATING PLANE
E) LANDPATTERN STANDARD: SOIC127P1030X265-20L
F) DRAWING FILENAME: MKT-M20BREV3
(1.40)
DETAIL A
SCALE: 2:1
Figure 49. 20-SOIC Package
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
© 2007 Fairchild Semiconductor Corporation
FAN7316 • 1.0.1
www.fairchildsemi.com
20
© 2007 Fairchild Semiconductor Corporation
FAN7316 • 1.0.1
www.fairchildsemi.com
21
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