FAN7385M [FAIRCHILD]
Dual-Channel High-Side Gate-Drive IC; 双通道高侧栅极驱动IC
| 型号： | FAN7385M |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Dual-Channel High-Side Gate-Drive IC |
| 文件： | 总15页 (文件大小：1835K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
February 2007
FAN7385
Dual-Channel High-Side Gate-Drive IC
Features
Description
Floating Channel for Bootstrap Operation to +600V
The FAN7385 is a monolithic high side gate drive IC
designed for high voltage, high speed driving MOSFETs
and IGBTs operating up to +600V.
Typically 350mA/650mA Sourcing/Sinking Current
Driving Capability
Extended Allowable Negative VS Swing to -9.8V for
Fairchild’s high-voltage process and common-mode
noise canceling technique provide stable operation of
high-side drivers under high-dv/dt noise circumstances.
Signal Propagation at VDD=VBS=15V
High-Side Output In-Phase of Input Signal
VDD & VBS Supply Range from 10V to 20V
3.3V and 5V Input Logic Compatible
An advanced level-shift circuit allows high-side gate
driver operation up to VS = -9.8V (typical) for VBS = 15V.
Built-in Common Mode dv/dt Noise Canceling Circuit
Built-in UVLO Functions for Both Channels
The UVLO circuits prevent malfunction when VBS1 and
VBS2 are lower than the specified threshold voltage.
Output drivers typically source/sink 350mA/650mA,
respectively, which is suitable for dual high-side switches
and half-bridge inverters.
Applications
Normal Half-Bridge and Full-Bridge Driver
PDP Energy Recovery Switch Control Driver
Switching Mode Power Supply
14-SOP
Ordering Information
Operating Temperature
Part Number
FAN7385M(1)
FAN7385MX(1)
Package
Pb-Free
Range
Packing Method
Tube
14-SOP
Yes
-40°C ~ 125°C
Tape & Reel
Note:
1. These devices passed wave soldering test by JESD22A-111.
© 2006 Fairchild Semiconductor Corporation
FAN7385 Rev. 1.0.2
www.fairchildsemi.com
Typical Application Diagrams
VS
RBOOT
DBOOT1
Q3
D3
D4
FAN7385
15V
L1
VB1
1
2
3
4
5
6
7
14
13
12
11
10
To
Pannel
VDD
NC
HO1
D1
Q1
D2
CBOOT1
Q4
IN1
NC
VS1
NC
IN1
IN2
DBOOT2
IN2
VB2
Buffer IC
Q2
C1
NC
9
8
HO2
VS2
CBOOT2
GND
HVIC
FAN7380
FAN7382
C2
Energy Recovery
Sustain Driver
FAN7385 Rev.01
Figure 1. Floated Bidirectional Switch Control for PDP application
VDC
RBOOT1
DBOOT1
Full-Bridge Converter
15V
VB1
1
2
3
4
5
6
7
14
13
12
11
10
VDD
NC
HO1
CBOOT1
IN1
NC
IN2
VS1
NC
VB2
NC
9
8
HO2
VS2
C1
Load
GND
CBOOT2
Controller
RBOOT2
DBOOT2
L-CH Output
R-CH Output
FAN7385 Rev.01
Figure 2. Full-Bridge Power Supply Application
RBOOT
DBOOT
VDC
Q1
Resonant Converter
15V
VB1
1
2
3
4
5
6
7
14
13
12
11
10
VDD
NC
HO1
CBOOT
L
C
IN1
NC
IN2
VS1
NC
INPUT1
Vout
VB2
INPUT2
Q2
Co
NC
9
8
HO2
VS2
C1
C2
GND
FAN7385 Rev.01
Figure 3. Half-Bridge LCC Resonant Converter Application
© 2006 Fairchild Semiconductor Corporation
FAN7385 Rev. 1.0.2
www.fairchildsemi.com
2
Internal Block Diagram
14
13
12
10
9
VB1
HO1
VS1
UVLO
R
1
VDD
R
NOISE
CANCELLER
S
Q
3
5
IN1
IN2
500K
500K
SCHMITT
TRIGGER INPUT
VB2
UVLO
HO2
VS2
R
R
S
NOISE
CANCELLER
Q
8
7
GND
Pin 2, 4, 6 and 11 are not connection
FAN7385 Rev.01
Figure 4. Functional Block Diagram
© 2006 Fairchild Semiconductor Corporation
FAN7385 Rev. 1.0.2
www.fairchildsemi.com
3
Pin Configuration
VDD
VB1
1
2
3
4
5
6
7
14
13
12
HO1
VS1
NC
IN1
NC
IN2
NC
FAN7385
11
NC
10 VB2
HO2
VS2
9
8
GND
FAN7385 Rev.00
Figure 5. Pin Configuration (Top View)
Pin Definitions
Pin #
1
Name
Description
VDD
NC
Power supply
2
Not connection
3
IN1
NC
Channel 1 control input
Not connection
4
5
IN2
NC
Channel 2 control input
Not connection
6
7
GND
VS2
HO2
VB2
NC
Ground
8
Channel 2 floating supply return
Channel 2 output
9
10
11
12
13
14
Channel 2 floating supply
Not connection
VS1
HO1
VB1
Channel 1 floating supply return
Channel 1 output
Channel 1 floating supply
© 2006 Fairchild Semiconductor Corporation
FAN7385 Rev. 1.0.2
www.fairchildsemi.com
4
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be opera-
ble above the recommended operating conditions and stressing the parts to these levels is not recommended. In addi-
tion, extended exposure to stresses above the recommended operating conditions may affect device reliability. The
absolute maximum ratings are stress ratings only. TA=25°C, unless otherwise specified.
Symbol
VS
Parameter
High-side offset voltage VS1 ,VS2
High-side floating supply voltage VB1 ,VB2
High-side floating output voltage HO1, HO2
Low-side and logic-fixed supply voltage
Logic input voltage (IN1, IN2)
Logic ground
Min.
VB-25
-0.3
Max.
VB+0.3
625
Unit
V
VB
V
VHO
VS-0.3
-0.3
VB+0.3
25
V
VDD
V
VIN
-0.3
VDD+0.3
VDD+0.3
50
V
GND
dVS/dt
VDD-25
V
Allowable offset voltage slew rate
Power dissipation
V/ns
W
(2)(3)(4)
PD
1.0
θJA
TJ
Thermal resistance, junction-to-ambient
Junction temperature
110
°C/W
°C
°C
150
TS
Storage temperature
150
Notes:
2. Mounted on 76.2 x 114.3 x 1.6mm PCB (FR-4 glass epoxy material).
3. Refer to the following standards:
JESD51-2: Integral circuits thermal test method environmental conditions - natural convection
JESD51-3: Low effective thermal conductivity test board for leaded surface mount packages
4. Do not exceed PD under any circumstances.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
VB
Parameter
Condition
Min.
VS+10
6-VDD
10
Max.
VS+20
600
Unit
V
High-side floating supply voltage
High-side floating supply offset voltage
Supply voltage
VS
V
VDD
VHO
VIN
20
V
High-side (HO1, HO2) output voltage
Logic input voltage (IN1, IN2)
Ambient temperature
VS
VB
V
GND
-40
VDD
125
V
TA
°C
© 2006 Fairchild Semiconductor Corporation
FAN7385 Rev. 1.0.2
www.fairchildsemi.com
5
Electrical Characteristics
VBIAS (VDD, VBS1, VBS2) = 15.0V, TA = 25°C, unless otherwise specified. The VIN and IIN parameters are referenced to
GND. The VO and IO parameters are referenced to VS1 and VS2 and are applicable to the respective outputs HO1 and
HO2.
Symbol
SUPPLY CURRENT SECTION
IQDD Quiescent VDD supply current
IPDD Operating VDD supply current
Characteristics
Condition
VIN1=VIN2=0V or 5V
Min. Typ. Max. Unit
28
35
50
70
μA
μA
fIN1=fIN2=10kHz, rms value
BOOTSTRAPPED POWER SUPPLY SECTION
VBS1 and VBS2 supply under-voltage
VBSUV+
VBS1=VBS2=Sweep
8.2
7.6
9.1 10.2
V
V
V
positive going threshold
VBS1 and VBS2 supply under-voltage
VBSUV-
VBS1=VBS2=Sweep
8.5
0.6
9.6
negative going threshold
VBS1 and VBS2 supply under-voltage
lockout hysteresis
VBSHYS
VBS1=VBS2=Sweep
VB=VS=600V
ILK
Offset supply leakage current
10
85
μA
μA
μA
IQBS1,2 Quiescent VBS1 and VBS2 supply current VIN1=0V or 5V
IPBS1,2 Operating VBS1 and VBS2 supply current fIN1=10kHz, rms value
GATE DRIVER OUTPUT SECTION
50
220 300
VOH
VOL
IO+
High-level output voltage, VBIAS-VO
Low-level output voltage, VO
IO=0mA (No Load)
30
30
mV
mV
mA
mA
IO=0mA (No Load)
Output HIGH short-circuit pulse current
VO=0V, VIN=5V with PW<10µs
250 350
500 650
IO-
Output LOW short-circuit pulsed current VO=15V, VIN=0V with PW<10µs
Allowable negative VS pin voltage for IN
signal propagation to HO
VS
-9.8 -7.0
V
LOGIC INPUT SECTION (IN1 AND IN2)
VIH
VIL
IIN+
IIN-
RIN
Logic "1" input voltage
2.5
V
V
Logic "0" input voltage
1.3
20
Logic "1" input bias current
Logic "0" input bias current
Input pull-down resistance
VIN=5V
VIN=0V
10
μA
μA
2.0
400 500 600 KΩ
Dynamic Electrical Characteristics
TA=25°C, VBIAS (VDD, VBS1, VBS2) = 15.0V, VS1 = VS2 = GND, CLoad = 1000pF unless otherwise specified.
Symbol
Parameter
Turn-on propagation delay
Turn-off propagation delay
Turn-on rise time
Conditions
VS=0V
VS=0V or 600V(5)
Min.
Typ.
110
110
50
Max.
180
180
90
Unit
ns
ton
toff
tr
ns
ns
tf
Turn-off fall time
30
70
ns
Delay matching, Channel 1 & 2 turn-
on/off
MT
0
ns
Notes:
5. This parameter guaranteed by design.
© 2006 Fairchild Semiconductor Corporation
FAN7385 Rev. 1.0.2
www.fairchildsemi.com
6
Typical Characteristics
10.00
9.75
9.50
9.25
9.00
8.75
8.50
8.25
8.00
9.0
8.8
8.6
8.4
8.2
8.0
-40 -20
0
20
40
60
80 100 120
-40 -20
0
20
40
60
80 100 120
Temperature [°C]
Temperature [°C]
Figure 6. VBS UVLO (+) vs. Temperature
Figure 7. VBS UVLO (-) vs. Temperature
70
1.0
0.8
0.6
0.4
0.2
0.0
VIN1= VIN2=GND
60
50
40
30
20
10
0
-40 -20
0
20
40
60
80 100 120
-40 -20
0
20
40
60
80 100 120
Temperature [°C]
Temperature [°C]
Figure 8. VBS UVLO Hysteresis vs. Temperature
Figure 9. VDD Quiescent Current vs. Temperature
70
80
70
60
50
40
30
20
10
VIN1= VIN2=GND
60
50
40
30
20
10
0
-40 -20
0
20
40
60
80 100 120
-40 -20
0
20
40
60
80 100 120
Temperature [°C]
Temperature [°C]
Figure 10. VBS Quiescent Current vs. Temperature
Figure 11. VDD Operating Current vs. Temperature
© 2006 Fairchild Semiconductor Corporation
FAN7385 Rev. 1.0.2
www.fairchildsemi.com
7
Typical Characteristics (Continued)
300
275
250
225
200
175
150
125
100
20
18
16
14
12
10
8
6
4
2
0
-40 -20
0
20
40
60
80 100 120
-40 -20
0
20
40
60
80 100 120
Temperature [°C]
Temperature [°C]
Figure 12. VBS Operating Current vs. Temperature
Figure 13. Logic High Input Current vs. Temperature
2.7
2.6
2.5
2.4
2.3
2.2
2.1
2.0
2.0
1.5
1.0
0.5
0.0
-0.5
-1.0
-1.5
-2.0
-40 -20
0
20
40
60
80 100 120
-40 -20
0
20
40
60
80 100 120
Temperature [°C]
Temperature [°C]
Figure 14. Logic Low Input Current vs. Temperature
Figure 15. Logic Input High Voltage vs. Temperature
2.0
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
1000
800
600
400
200
0
-40 -20
0
20
40
60
80 100 120
-40 -20
0
20
40
60
80 100 120
Temperature [°C]
Temperature [°C]
Figure 16. Logic Input Low Voltage vs. Temperature
Figure 17. Logic Input Resistance vs. Temperature
© 2006 Fairchild Semiconductor Corporation
FAN7385 Rev. 1.0.2
www.fairchildsemi.com
8
Typical Characteristics (Continued)
100
90
80
70
60
50
40
30
20
10
80
70
60
50
40
30
20
10
0
-40 -20
0
20
40
60
80 100 120
-40 -20
0
20
40
60
80 100 120
Temperature [°C]
Temperature [°C]
Figure 18. Rising Time vs. Temperature
Figure 19. Falling Time vs. Temperature
180
170
160
150
140
130
120
110
100
90
180
170
160
150
140
130
120
110
100
-40 -20
0
20
40
60
80 100 120
-40 -20
0
20
40
60
80 100 120
Temperature [°C]
Temperature [°C]
Figure 20. Turn-On Delay Time vs. Temperature
Figure 21. Turn-Off Delay Time vs. Temperature
20
15
10
5
-14
-12
-10
-8
0
-5
-10
-6
-15
-40 -20
0
20
40
60
80 100 120
-40 -20
0
20
40
60
80 100 120
Temperature [°C]
Temperature [°C]
Figure 22. Delay Matching Time vs. Temperature
Figure 23. Allowable Negative VS Voltage for Signal
Propagation to High Side vs. Temperature
© 2006 Fairchild Semiconductor Corporation
FAN7385 Rev. 1.0.2
www.fairchildsemi.com
9
Typical Characteristics (Continued)
400
380
360
340
320
300
750
700
650
600
550
500
-40 -20
0
20
40
60
80 100 120
-40 -20
0
20
40
60
80 100 120
Temperature [°C]
Temperature [°C]
Figure 24. Output High Short-Circuit Pulse Current
vs. Temperature
Figure 25. Output Low Short-Circuit Pulse Current
vs. Temperature
80
60
40
20
0
80
60
40
20
0
0
5
10
15
20
25
0
5
10
15
20
Supply Voltage [V]
Supply Voltage [V]
Figure 26. VDD Quiescent Current vs.
Supply Voltage
Figure 27. VDD Operating Current vs.
Supply Voltage
250
80
70
60
50
40
30
20
10
200
150
100
50
0
0
5
10
15
20
10 11 12 13 14 15 16 17 18 19 20
Supply Voltage [V]
Supply Voltage [V]
Figure 28. VBS Operating Current vs. Supply Voltage
Figure 29. Rising Time vs. Supply Voltage
© 2006 Fairchild Semiconductor Corporation
FAN7385 Rev. 1.0.2
www.fairchildsemi.com
10
Typical Characteristics (Continued)
50
40
30
20
160
150
140
130
120
110
100
90
10
80
10 11 12 13 14 15 16 17 18 19 20
10 11 12 13 14 15 16 17 18 19 20
Supply Voltage [V]
Supply Voltage [V]
Figure 30. Falling Time vs. Supply Voltage
Figure 31. Turn-On Delay Time vs. Supply Voltage
500
450
400
350
300
250
160
150
140
130
120
110
100
90
200
80
10 11 12 13 14 15 16 17 18 19 20
10 11 12 13 14 15 16 17 18 19 20
Supply Voltage [V]
Supply Voltage [V]
Figure 32. Turn-Off Delay Time vs. Supply Voltage
Figure 33. Output Source Current vs. Supply Voltage
1000
900
800
700
600
500
-4
-6
-8
-10
-12
-14
-16
400
10 11 12 13 14 15 16 17 18 19 20
10 11 12 13 14 15 16 17 18 19 20
Supply Voltage [V]
Supply Voltage [V]
Figure 34. Output Sink Current vs. Supply Voltage
Figure 35. Allowable Negative VS Voltage for Signal
Propagation to High Side vs. Supply Voltage
© 2006 Fairchild Semiconductor Corporation
FAN7385 Rev. 1.0.2
www.fairchildsemi.com
11
Switching Time Definitions
HVIC
10μF
0.1μF
50%
50%
VDD
IN
15V
ton tr
toff tf
10μF
0.1μF
VB
VS
GND
IN
15V
90%
90%
HO
IN
1000pF
OUT
10%
10%
(B)
(A)
FAN7385 Rev.00
Figure 36. Switching Time Test Circuit
IN1
IN2
HO1
HO2
FAN7385 Rev.00
Figure 37. Input / Output Waveforms
© 2006 Fairchild Semiconductor Corporation
FAN7385 Rev. 1.0.2
www.fairchildsemi.com
12
Typical Application Information
2.2 Gate Drive Loop
1. Under-Voltage Lockout (UVLO)
The FAN7385 has an under-voltage lockout (UVLO)
protection circuit to prevent malfunction when VBS1 and
Current loops behave like antennae, able to receive and
transmit noise. To reduce the noise coupling/emission
and improve the power switch turn-on and off perfor-
mances, gate drive loops must be reduced as much as
possible.
VBS2 are lower than the specified threshold voltage. The
UVLO circuit monitors the bootstrap capacitor voltages
(VBS1, VBS2) independently.
2.3 Ground Plane
2. Layout Consideration
To minimize noise coupling, avoid placing the ground
plane under or near the high-voltage floating side.
For optimum performance, considerations must be given
during printed circuit board (PCB) layout.
2.1 Supply Capacitors
If the output stages are able to quickly turn on a switch-
ing device with a high current value, the supply capaci-
tors must be placed as close as possible to the device
pins (VDD and GND for the ground-tied supply, VB and
VS for the floating supply) to minimize parasitic induc-
tance and resistance.
© 2006 Fairchild Semiconductor Corporation
FAN7385 Rev. 1.0.2
www.fairchildsemi.com
13
Package Dimensions
14-SOP
Dimensions are in millimeters unless otherwise noted.
0.05
0.002
MIN
1.55 0.10
0.061 0.004
#14
#1
#8
#7
6.00 0.30
0.236 0.012
1.80
MAX
0.071
3.95 0.20
0.156 0.008
5.72
0.225
0.60 0.20
0.024 0.008
January 2001, Rev. A
14sop225b_dim.pdf
Figure 38. 14-Lead Small Outline Package (SOP)
© 2006 Fairchild Semiconductor Corporation
FAN7385 Rev. 1.0.2
www.fairchildsemi.com
14
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As used herein:
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when properly used in accordance with instructions for use
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PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Formative or In Design
This datasheet contains the design specifications for product
development. Specifications may change in any manner without notice.
Preliminary
First Production
Full Production
Not In Production
This datasheet contains preliminary data; supplementary data will be
published at a later date. Fairchild Semiconductor reserves the right to
make changes at any time without notice to improve design.
No Identification Needed
Obsolete
This datasheet contains final specifications. Fairchild Semiconductor
reserves the right to make changes at any time without notice to improve
design.
This datasheet contains specifications on a product that has been
discontinued by Fairchild Semiconductor. The datasheet is printed for
reference information only.
Rev. I23
© 2006 Fairchild Semiconductor Corporation
FAN7385 Rev. 1.0.2
www.fairchildsemi.com
15
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