FAN7387 [FAIRCHILD]
Self-Oscillated, High-Voltage Gate Driver; 自振荡，高压栅极驱动器
| 型号： | FAN7387 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Self-Oscillated, High-Voltage Gate Driver |
| 文件： | 总17页 (文件大小：1619K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
May 2008
FAN7387
Self-Oscillated, High-Voltage Gate Driver
Features
Description
Internal Clock Using RCT
External Sync Function Using RCT
Dead Time Control Using Resistor
Shut Down (Disable Mode)
Internal Shunt Regulator
The FAN7387 is a simple control IC for common half-
bridge inverters, SMPS, and ballast for fluorescent and
HID lamps. The FAN7387 has an oscillating circuit using
an external resistor and capacitor. The frequency
variation is very stable across a wide temperature range.
The FAN7387 has a external pin for dead time control
and shutdown. Using this resistor, the designer can
choose the optimum dead time to reduce power loss on
switching devices, such as transistors and MOSFETs.
UVLO Function, High and Low Side
Applications
Half-Bridge Inverter
SMPS
8-SOP
8-DIP
Ballast Solution for High-Intensity Discharge
(HID) Lamp
Ballast for Fluorescent Lamp
Ordering Information
Part Number
FAN7387M(1)
FAN7387MX(1)
FAN7387N
Package
8-SOP
Operating Temperature Range
Packing Method
Tube
-40°C ~ 125°C
Tape & Reel
Tube
8-DIP
All standard Fairchild Semiconductor products are RoHS compliant and many are also “GREEN” or going green. For Fairchild’s
definition of “green” please visit: http://www.fairchildsemi.com/company/green/rohs_green.html.
Note:
1. These devices passed wave soldering test by JESD22A-111.
© 2008 Fairchild Semiconductor Corporation
FAN7387 Rev. 1.0.0
www.fairchildsemi.com
Typical Application Diagrams
C1
VDC
D1
C2
C3
VDD
CT
D2
D3
RCT
VB
HO
VS
LO
1
2
3
4
8
7
6
5
R1
R2
M1
M2
RT1
RDT
VDD
C5
C4
DT/ SD
Q1
Q2
GND
Cb* RT2
C6
Frequency
Shutdown
Control
GND
FAN7387 Rev1.0
* Note: This capacitor, Cb, is for system stability and must use at least 470nF.
Figure 1. Typical Application Circuit for SMPS (Self Oscillation Method)
C1
VDC
D1
VDD
C2
C3
R1
R2
D2
D3
RCT
VB
HO
VS
LO
1
2
3
4
8
7
6
5
R3
R4
M1
M2
VDD
C5
RDT
C4
PWM
Q1
DT/ SD
GND
Shutdown
Cb*
Q2
C6
GND
FAN7387 Rev.1.0
* Note: This capacitor, Cb, is for system stability and must use at least 470nF.
Figure 2. Typical Application Circuit for SMPS Using External Signal
© 2008 Fairchild Semiconductor Corporation
FAN7387 Rev. 1.0.0
www.fairchildsemi.com
2
C1
VDC
GND
VDD
D1
D4
C2
C3
CT
RT
RCT
VB
HO
VS
LO
VB
HO
VS
LO
RCT
1
2
3
4
8
7
6
5
8
7
6
4
1
2
3
5
RDT1
RDT2
Q2
R3
R4
R5
R6
C5
M1
M2
M1
M2
VDD
VDD
HID Lamp
L
DT/ SD
DT/ SD
Q1
GND
GND
Cb*
Cb*
Shutdown2
C4
Shutdown1
GND
GND
R2
R1
* Note: This capacitor, Cb, is for system stability and must use at least 470nF.
FAN7387 Rev.1.0
Figure 3. Typical Application Circuit for Full-Bridge Converter
R1
D5
D1
D3
CT
RCT
VDD
VB
HO
VS
LO
1
2
3
4
8
7
6
5
RDT
C3
R4
R5
D6
C4
C1
M1
M2
AC Input
C5
L
C6
DT/ SD
GND
R2
Q1
C2
RT1
Q2
R6
R7
D2
D4
Cb*
C7
D7
RT2
R3
Lamp
C8
Over-Voltage Protection
FAN7387 Rev1.0
ZD1
* Note: This capacitor, Cb, is for system stability and must use at least 470nF.
Figure 4. Typical Application Circuit for Fluorescent Lamp Ballast
© 2008 Fairchild Semiconductor Corporation
FAN7387 Rev. 1.0.0
www.fairchildsemi.com
3
Internal Block Diagram
HIGH-SIDE DRIVER
VB
VDD
2
8
VB
UVLO
UVLO
S
R
Q
Q
Noise
Canceller
7
6
HO
VS
S
R
Q
Internal CLK
(Frequency Divider)
SET
D
Q
VDD/4
Q
RESET
External
Sync
HIN
CLK/Sync
Determination
IN
RCT
1
3
VDD
Logic Detection
Level
DT
LIN
DT/SD
5
DELAY
LO
SHUTDOWN
LOW-SIDE GATE DRIVER
Always LIN
First
HIN
LIN
GND
4
Figure 5. Functional Block Diagram
© 2008 Fairchild Semiconductor Corporation
FAN7387 Rev. 1.0.0
www.fairchildsemi.com
4
Pin Configuration
VB HO VS LO
8
7
6
5
FAN7387
YWW
( YWW: Work Week Code)
1
2
3
4
RCT VDD DT/SD GND
Figure 6. Pin Configuration (Top View)
Pin Definitions
Pin #
Name
Description
1
2
3
4
5
6
7
8
RCT
VDD
DT/SD
GND
LO
Oscillator frequency set resistor and capacitor
Supply voltage
Dead-time control and shutdown (active LOW)
Signal ground
Low-side output
VS
High-side floating supply return
High-side output
HO
VB
High-side floating supply
© 2008 Fairchild Semiconductor Corporation
FAN7387 Rev. 1.0.0
www.fairchildsemi.com
5
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be opera-
ble above the recommended operating conditions and stressing the parts to these levels is not recommended. In addi-
tion, extended exposure to stresses above the recommended operating conditions may affect device reliability. The
absolute maximum ratings are stress ratings only. TA=25°C unless otherwise specified.
Symbol
VB
Parameter
High-side floating supply voltage
Min.
-0.3
-0.3
Typ.
Max.
625.0
600.0
VCL
Unit
V
VS
High-side offset voltage
V
VRCT
ICL
RCT pins input voltage
V
Clamping current level(2)
Allowable offset voltage slew rate
Operating temperature range
Storage temperature range
25
mA
V/ns
°C
dVS/dt
TA
50
-40
-65
+125
+150
TSTG
°C
8-DIP
8-SOP
8-DIP
8-SOP
1.2
0.625
100
PD
Power dissipation
W
θJA
Thermal resistance (Junction-to-Air)
°C/W
200
Note:
2. Do not supply a low-impedance voltage source to the internal clamping Zener diode between the GND and the VDD
pin of this device.
Recommended Operating Ratings
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings
Symbol
VB
Parameter
High-side floating supply voltage
High-side offset voltage
Min.
VS+11
6-VDD
11
Max.
VS+14
600
Unit
V
VS
V
VDD
VHO
VLO
VIH
Low-side supply voltage
14
V
High-side (HO) output voltage
Low-side (LO) output voltage
Logic “1” input voltage of RCT
Logic “0” input voltage of RCT
Timing resistor value of RCT
Timing capacitor value of RCT
Ambient temperature
GND
VDD
VDD
V
GND
V
(3/4 VDD)+1
V
VIL
(3/5 VDD)-1
+125
V
RT
2
kΩ
pF
°C
CT
100
-40
TA
© 2008 Fairchild Semiconductor Corporation
FAN7387 Rev. 1.0.0
www.fairchildsemi.com
6
Electrical Characteristics
VBIAS (VDD, VB -VS)=14.0V, CL=1nF, RT=50k and CT=330pF and TA=25°C, unless otherwise specified.
Symbol
Parameter
Conditions
Min.
Typ.
Max. Unit
Low-Side Supply Characteristics (VDD
)
VDD supply under-voltage positive going
threshold
VDDUV+
VDDUV-
VDD Increasing
9.5
7.5
11.0
9.0
12.5
10.5
V
V
VDD supply under-voltage negative going
threshold
VDD Decreasing
VDDUVH VDD supply under-voltage lockout hysteresis
2
V
V
VCL
IQDD
IST
Supply clamping voltage
IDD=10mA
RDT=100k
VDD=9V
14.8
15.4
220
50
Low-side quiescent supply current
Start-up supply current
500
130
10
μA
μA
μA
mA
ILK
Offset supply leakage current
Low-side dynamic operating supply current
VB=VS=600V
IPDD
0.8
High-Side Supply Characteristics (VB-VS)
VBS supply under-voltage negative going
threshold
VBSUV+
VB -VS Increasing
VB -VS Decreasing
7.7
7.1
9.2
8.6
10.7
10.1
V
V
VBS supply under-voltage negative going
threshold
VBSUV-
VBSUVH VBS supply under-voltage lockout hysteresis
0.6
50
V
IQBS
IPBS
High-side quiescent supply current
130
800
μA
μA
High-side dynamic operating supply current
400
Oscillator Characteristics
fosc1
fosc2
D
Oscillation frequency 1
RT=50k, CT=330pF
RT=1k, CT=1nF
Running Mode
Running Mode
Running Mode
Running Mode
Running Mode
RDT=100k
18
20
250
22
kHz
Oscillation frequency 2
Duty cycle
210
47.5
290
49.0
%
V
V
V
V
VRCT+
VRCT-
VIH
Upper threshold voltage of RCT
Lower threshold voltage of RCT
Logic “1” input voltage of RCT
Logic “0” input voltage of RCT
Dead time
VDD
VDD/4
3/4VDD
VIL
3/5VDD
700
DT
500
300
600
400
ns
DTMIN
Minimum dead time
VDT/SD=VDD
500
Output Characteristics
(3)
IO+
Output high, short-circuit pulse current
PW<=10µs
PW=10µs
350
650
mA
mA
(3)
IO-
VS
Note:
Output low, short-circuit pulse current
Allowable negative VS pin voltage for input
signal (VRCT) propagation to HO
-9.8
-7.0
V
3. These parameters, although guaranteed, is not 100% tested in production.
Continued on the following page...
© 2008 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN7387 Rev. 1.0.0
7
Electrical Characteristics (Continued)
VBIAS (VDD, VB -VS)=14.0V, CL=1nF, RT=50k and CT=330pF and TA=25°C, unless otherwise specified.
Symbol
Parameter
Condition
Min. Typ. Max. Unit
Output Characteristics
VDD=VBS=14V, VDT/SD=VDD
,
tON
Turn-on propagation time
Turn-off propagation time
550
160
ns
ns
VRCT=4V~VDD, fOSC=20kHz
VDD=VBS=14V, VDT/SD=VDD
RCT=4V~VDD, fOSC=20kHz
,
tOFF
V
tR
tF
Turn on rising time
Turn off falling time
CL=1000pF
CL=1000pF
50
30
120
70
ns
ns
Protection Characteristics
SD+
SD+
ISD
Shutdown “1” input voltage
2.7
V
V
Shutdown “0” input voltage
Shutdown Current
1
VSD/DT=0 After Running Mode
250
180
μA
ns
TSD
Shutdown Propagation Delay
© 2008 Fairchild Semiconductor Corporation
FAN7387 Rev. 1.0.0
www.fairchildsemi.com
8
Switching Definitions
CT
RCT
LO
VB
RCT
1
8
7
6
5
0.1µF
10µF
VDD
+14V
2
RDT
10µF
100nF
DT/SD
GND
VS
3
4
HO
470nF
RT
DT
LO
1000pF
1000pF
HO
FAN7387 Ver1.0
Figure 7. Test Circuit for Self-oscillation Method
Figure 8. Basic Operating Waveforms of
Self-oscillation
50%
DT/SD
VB
PWM+DC offset
RCT
VDD
1
2
3
4
8
7
6
5
0.1µF
10µF
+14V
TSD
RDT
DT/SD
VS
+14V
10µF 0.1µF
470nF
GND
90%
HO
HO or LO
LO
1000pF 1000pF
Figure 10. Test Circuit for Forced-oscillation Method
Using External Signal
Figure 9. Shutdown Delay Definition
RCT
50%
50%
tON
tR
tOFF
TF
90%
90%
90%
HO
LO
50%
50%
10%
TSD
10%
DT
50%
DT/ SD
50%
Figure 11. Basic Operation Waveforms of Forced-oscillation Method Using External Signal
© 2008 Fairchild Semiconductor Corporation
FAN7387 Rev. 1.0.0
www.fairchildsemi.com
9
Typical Characteristics
200
150
100
50
12.5
12.0
11.5
11.0
10.5
10.0
9.5
0
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Temperature [°C]
Temperature [°C]
Figure 12. Start-Up Current vs. Temp.
Figure 13. VDD UVLO+ vs. Temp.
10.5
10.0
9.6
9.2
8.8
8.4
8.0
7.6
7.2
10.0
9.5
9.0
8.5
8.0
7.5
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Temperature [°C]
Temperature [°C]
Figure 14. VDD UVLO- vs. Temp.
Figure 15. VBS UVLO+ vs. Temp.
10.0
9.6
9.2
8.8
8.4
8.0
7.6
7.2
16.0
15.8
15.6
15.4
15.2
15.0
14.8
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Temperature [°C]
Temperature [°C]
Figure 16. VBS UVLO- vs. Temp.
Figure 17. VCL vs. Temp.
© 2008 Fairchild Semiconductor Corporation
FAN7387 Rev. 1.0.0
www.fairchildsemi.com
10
Typical Characteristics (Continued)
2.5
2.0
1.5
1.0
0.5
0.0
500
400
300
200
100
0
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Temperature [°C]
Temperature [°C]
Figure 18. IPDD vs. Temp.
Figure 19. IQDD vs. Temp.
3.0
2.5
2.0
1.5
1.0
0.5
0.0
500
400
300
200
100
0
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Temperature [°C]
Temperature [°C]
Figure 20. ISD vs. Temp.
Figure 21. VSD+ vs. Temp.
3.0
23
22
21
20
19
18
17
2.5
2.0
1.5
1.0
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Temperature [°C]
Temperature [°C]
Figure 22. VSD- vs. Temp.
Figure 23. Operating Frequency 1 vs. Temp.
© 2008 Fairchild Semiconductor Corporation
FAN7387 Rev. 1.0.0
www.fairchildsemi.com
11
Typical Characteristics (Continued)
280
270
260
250
240
230
220
210
500
475
450
425
400
375
350
325
300
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Temperature [°C]
Temperature [°C]
Figure 24. Operating Frequency 2 vs. Temp.
Figure 25. Minimum DT vs. Temp.
50
40
30
20
10
0
52
51
50
49
48
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Temperature [°C]
Temperature [°C]
Figure 26. Dead Time Mismatch vs. Temp.
Figure 27. High-side Duty Ratio vs. Temp.
52
51
50
49
48
-40
-20
0
20
40
60
80
100
120
Temperature [°C]
Figure 28. Frequency vs. RT
Figure 29. Low-side Duty Ratio vs. Temp
© 2008 Fairchild Semiconductor Corporation
FAN7387 Rev. 1.0.0
www.fairchildsemi.com
12
Typical Application Informations
1. UVLO (Under-Voltage Lockout) Function
FAN7387 has a UVLO circuit for a low-side and high-
side block. When VDD reaches to the VDDUV+, the UVLO
RCT
LO
t
circuit is released and the FAN7387 operates normally.
At UVLO condition, the FAN7387 has a low supply
current of less than 130µA. Once UVLO is released,
FAN7387 operates normally until VDD goes below
VDDUV-, the UVLO hysteresis.
FAN7387 also has a high-side gate driver. The supply for
the high-side driver is applied between VB and VS. To
Tfix
Tfix
prevent malfunction at low supply voltage between VB
and VS, FAN7387 provides an additional UVLO circuit. If
VB-VS is under VBSUV+, the driver holds LOW state to
turn off the high-side switch. Once the voltage of VB-VS
is higher than VBSUVH after VB-VS exceeds VBSUV-, the
operation of driver resumes.
HO
DT
DT
T
Figure 31. Typical Waveforms of RCT, LO, and HO
2. Oscillator
The running frequency is determined by an external
timing resistor (RT) and timing capacitor (CT). The
(2)
t ꢂ 1.38 ꢄ RT ꢄ CT
charge time of capacitor CT from 1/4 VDD to VDD
The running frequency of IC is determined by 1/T and is
approximately given as:
determines the running frequency of LO and HO gate
driver output. Figure 30 shows connection configuration.
1
T
1
VDD
RCT
VB
(3)
frunning
ꢂ
ꢂ
1
2
3
4
8
7
6
5
2ꢀt ꢅ T ꢁ
fix
CT
VDD
HO
DT/SD
GND
VS
LO
where t is the discharging time of the RCT voltage and
and Tfix is constant value about 450ns of IC.
RT
FAN7387 Rev1.0
3. Programming Dead Time Control / Shutdown
A multi-function pin controls dead time using an external
resistor (RDT) and protects abnormal condition using an
Figure 30. Typical Connection Method
external switch. This pin should be connected to an
external capacitor to maintain stable operation.
Figure 31 shows the typical waveforms of RCT, LO, and
HO. From the circuit analysis, the discharging time of
RCT, t, is given by Equation 1:
If the voltage of DT/SD is decreased under 1V by an
external switch, such as the TR or MOSFET, the
FAN7387 enters shutdown mode. In this mode, the
FAN7387 doesn’t have any output signal.
‐ t
(1)
VRCT ꢀtꢁ ꢂ VDD ꢃ Inꢀ
ꢁ
RT ꢄ CT
From Equation 1, it is possible to calculate discharging
time, t, from VDD to 1/4 VDD by substituting VRCT(t) with
1/4 VDD
.
© 2008 Fairchild Semiconductor Corporation
FAN7387 Rev. 1.0.0
www.fairchildsemi.com
13
VB
HO
RCT
1
2
3
4
8
7
6
5
VDD
+14V
RDT
Cbp
DT/SD
VS
LO
GND
External
Signal
Rev. 1.0
Figure 32. External Shutdown Circuit
4. Gate Driver Operation
The FAN7387 has a two operating modes. One is the
self-oscillation mode by using external timing resistor
(RT) and external timing capacitor (CT) and the other is
the forced oscillation mode by external PWM signal
comes from U-com and the other devices.
Figure 33 shows how to operate IC by using external
PWM circuit with additional resistors (R1 and R2)
because of internal limitation of IC. The input signal
range from an external circuit must by within 3/5 VDD and
3/4 VDD. The external signal produce the HO and LO
output and HO signal is to in-phase with the external
input signal.
VDD
R1
RCT
VB
1
2
3
4
8
7
6
5
VDD
DT/SD
GND
R2
HO
RDT
C
VS
LO
PWM
GND
FAN7387 Rev1.0
Figure 33. Gate Driver Using External PWM Signal
© 2008 Fairchild Semiconductor Corporation
FAN7387 Rev. 1.0.0
www.fairchildsemi.com
14
Package Dimensions
.400 10.15
.373 9.46
A
[
]
.036 [0.9 TYP]
(.092) [Ø2.337]
PIN #1
(.032) [R0.813]
PIN #1
.250±.005 [6.35±0.13]
B
TOP VIEW
OPTION 1
TOP VIEW
OPTION 2
.070 1.78
.310±.010 [7.87±0.25]
.045
[ ]
1.14
.130±.005 [3.3±0.13]
.210 MAX
[5.33]
7° TYP
7° TYP
C
.015 MIN
[0.38]
.021 0.53
.015 0.37
.300
[7.62]
[
]
.140 3.55
.125 3.17
[
]
.001[.025]
C
.100
[2.54]
.430 MAX
[10.92]
.060 MAX
[1.52]
NOTES:
A. CONFORMS TO JEDEC REGISTRATION MS-001,
VARIATIONS BA
B. CONTROLING DIMENSIONS ARE IN INCHES
+.005
-.000
+0.127
-0.000
.010
0.254
[
]
REFERENCE DIMENSIONS ARE IN MILLIMETERS
C. DOES NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED
.010 INCHES OR 0.25MM.
D. DOES NOT INCLUDE DAMBAR PROTRUSIONS.
DAMBAR PROTRUSIONS SHALL NOT EXCEED
.010 INCHES OR 0.25MM.
E. DIMENSIONING AND TOLERANCING
PER ASME Y14.5M-1994.
N08EREVG
Figure 34. 8-Lead Dual Inline Package (DIP)
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in
any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor
representative to verify or obtain the most recent revision. Package specifications do not expand the terms of
Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
© 2008 Fairchild Semiconductor Corporation
FAN7387 Rev. 1.0.0
www.fairchildsemi.com
15
Package Dimensions
5.00
4.80
A
0.65
3.81
8
5
B
1.75
6.20
5.80
4.00
3.80
5.60
1
4
PIN ONE
INDICATOR
1.27
1.27
(0.33)
M
0.25
C B A
LAND PATTERN RECOMM ENDATION
SEE DETAIL A
0.25
0.10
0.25
0.19
C
1.75 MAX
0.10
C
0.51
0.33
OPTION A - BEVEL EDGE
0.50
0.25
x 45°
R0.10
R0.10
GAGE PLANE
OPTION B - NO BEVEL EDGE
0.36
NOTES: UNLESS OTHERW ISE SPECIFIED
8°
0°
0.90
A) THIS PACKAGE CONFORM S TO JEDEC
M S-012, VARIATION AA, ISSUE C,
B) ALL DIM ENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
FLASH OR BURRS.
SEATING PLANE
(1.04)
0.406
D) LANDPATTERN STANDARD: SOIC127P600X175-8M .
E) DRAW ING FILENAM E: M08AREV13
DETAIL A
SCALE: 2:1
Figure 35. 8-Lead Small Outline Package (SOP)
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in
any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor
representative to verify or obtain the most recent revision. Package specifications do not expand the terms of
Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
© 2008 Fairchild Semiconductor Corporation
FAN7387 Rev. 1.0.0
www.fairchildsemi.com
16
© 2008 Fairchild Semiconductor Corporation
FAN7387 Rev. 1.0.0
17
相关型号：
©2020 ICPDF网 联系我们和版权申明