FAN80037 [FAIRCHILD]
CD Motor Driver, 7 Channel, PQFP48, 14 X 14 MM, HEAT SINK, QFP-48;
| 型号： | FAN80037 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | CD Motor Driver, 7 Channel, PQFP48, 14 X 14 MM, HEAT SINK, QFP-48 驱动 CD 接口集成电路 |
| 文件： | 总21页 (文件大小：396K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
www.fairchildsemi.com
FAN8037 (KA3037)
7-CH Motor Drive IC
Features
Description
• 4-CH balanced transformerless (BTL) driver
• 3-CH (forward - reverse) control DC motor driver
• Operating supply voltage (4.5 V ~ 13.2 V)
• Built-in thermal shut down circuit (TSD)
• Built-in all channel mute circuit
The FAN8037 is a monolithic integrated circuit suitable for
a 7-ch motor driver which drives the tracking actuator, focus
actuator, sled motor, tray motor, changer motor, panel motor
and, spindle motor of the CDP/CAR-CD systems.
• Built-in power save mode circuit
• Built-in stand by mode circuit
• Built-in variable regulator
48-QFPH-1414
Typical Application
• Compact disk player (Tray, Changer)
• Video compact disk player (Tray, Changer)
• Car compact disk player (Tray, Changer)
• Mixing with compact disk player and mini disk player (Tray, Changer, Panel)
Rev. 1.0.0
©2000 Fairchild Semiconductor Corporation
FAN8037 (KA3037)
Pin Assignments
48
47
46
45
44
43
42
41
40
39
38
37
IN2+
36
35
34
32
32
31
DO2−
1
2
3
4
5
6
IN2−
OUT2
IN3+
PGND1
DO3+
DO3−
IN3−
DO4+
OUT3
DO4−
FAN8037
7
30
29
28
27
26
25
IN4+
IN4−
DO5+
DO5−
8
OUT4
PGND2
9
CTL1
DO6+
10
11
12
FWD1
REV1
DO6−
DO7+
13
14
15
16
17
18
19
20
21
22
23
24
2
FAN8037 (KA3037)
Pin Definitions
Pin Number
Pin Name
I/O
I
Pin Function Descrition
1
IN2+
IN2−
CH2 op-amp input (+)
CH2 op-amp inut (−)
CH2 op-amp output
CH3 op-amp input (+)
CH3 op-amp input (−)
CH3 op-amp output
CH4 op-amp input (+)
CH4 op-amp input (−)
CH4 op-amp output
2
I
3
OUT2
IN3+
O
I
4
5
IN3−
I
6
OUT3
IN4+
O
I
7
8
IN4−
I
9
OUT4
CTL1
FWD1
REV1
CTL2
FWD2
REV2
SGND
FWD3
REV3
CTL3
SB
O
I
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
CH5 motor speed control
CH5 forward input
I
I
CH5 reverse input
I
CH6 motor speed control
CH6 forward input
I
I
CH6 reverse input
-
Signal groung
I
CH7 forward input
I
CH7 reverse input
I
CH7 motor speed control
Stand by
I
PS
I
Power save
MUTE
PVCC2
DO7−
DO7+
DO6−
DO6+
PGND2
DO5−
DO5+
DO4−
DO4+
I
All mute
-
Power supply voltage (For CH5, CH6, CH7)
CH7 drive ouptut (−)
CH7 drive output (+)
CH6 drive output (−)
CH6 drive output (+)
Power ground2 (FOR CH5, CH6, CH7)
CH5 drive output (−)
CH5 drive output (+)
CH4 drive output (−)
CH4 drive output (+)
O
O
O
O
-
O
O
O
O
3
FAN8037 (KA3037)
Pin Definitions (Continued)
Pin Number
Pin Name
DO3−
DO3+
PGND1
DO2−
DO2+
DO1−
DO1+
PVCC1
REGOX
REGX
RESX
VREF
SVCC
IN1+
I/O
O
O
-
Pin Function Descrition
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
CH3 drive output (−)
CH3 drive output (+)
Power ground 1 (FOR CH1, CH2, CH3, CH4)
CH2 drive output (−)
O
O
O
O
-
CH2 drive output (+)
CH1 drive output (−)
CH1 drive output (+)
Power supply voltage (FOR CH1, CH2, CH3, CH4)
Regulator feedback input
Regulator output
I
O
I
Regulator reset input
I
Bias voltage input
-
Signal supply voltage
I
CH1 op-amp input (+)
IN1−
I
CH1 op-amp input (−)
OUT1
O
CH1 op-amp output
4
FAN8037 (KA3037)
Internal Block Diagram
OUT1
48
IN1−
IN1+ SVCC VREF RESX
REGX REGOX PVCC1 DO1+ DO1− DO2+
47
46
45
44
43
42
41
40
39
38
37
+
1
2
−
36 DO2−
IN2+
−
+
PGND1
DO3+
35
34
IN2−
−
−
+
−
+
+
3
4
OUT2
IN3+
IN3−
+
+
+
33 DO3−
−
−
−
5
6
32
31
DO4+
−
−
+
+
+
−
DO4−
OUT3
+
+
+
−
−
−
IN4+
IN4−
7
DO5+
30
D
D
D
+
M
S
S
W
C
DO5−
8
9
29
28
−
+
−
+
−
PGND2
OUT4
M
S
C
S
W
D
D
DO6+
27
26
CTL1 10
M
S
C
S
W
DO6−
11
12
FWD1
REV1
D
STAND BY
ALL MUTE
T.S.D
25
DO7+
POWER SAVE
13
14
15
16
17
FWD3
18
REV3
19
CTL3
20
SB
21
22
23
24
CTL1 FWD2 REV2 SGND
PS
MUTE PVCC2 DO7−
Notes:
1. SW = Logic switch
2. MSC = Motor speed control
3. D = Output driver
5
FAN8037 (KA3037)
Equivalent Circuits
Description
Pin No.
Internal circuit
Input
OPIN (+)
OPIN (−)
46,47,1,2
4,5,7,8
SVCC
SVCC
SVCC
0.05k
0.05k
46 1
2
8
47
5
4
7
Input
48,3,6,9
opout
SVCC
SVCC
48 3
6 9
CTL
10,13,19
SVCC
SVCC
0.05k
1k
10
13 19
Logic drive
FWD input
REV input
11,12,
14,15,
17,18
SVCC
11
12
30k
0.05k
14 15
17 18
30k
6
FAN8037 (KA3037)
Equivalent Circuits (Continued)
Description
Pin No.
Internal circuit
Power save
Standby
20,21
SVCC
SVCC
50k
0.05k
20
21
Mute
22
SVCC
SVCC
0.05k
50k
22
Logic
drive
output
24, 25
26, 27
29,30
SVCC
PVCC2
30k
24 25
1k
26 27
29 30
25k
4-CH
drive
output
31, 32
33, 34
36, 37
38, 39
SVCC
PVCC1
31 32
33 34
36 37
38 39
20k
20k
25k
7
FAN8037 (KA3037)
Equivalent Circuits (Continued)
Description
Pin No.
Internal circuit
Ref
44
SVCC
SVCC
20k
20k
1k
1k
0.05k
44
RESX
43
SVCC
SVCC
50k
0.05k
43
50k
REG0X
41
SVCC
SVCC
0.05k
41
1k
REGX
42
SVCC
0.5k
SVCC
0.05k
60k
42
25k
8
FAN8037 (KA3037)
Absolute Maximum Ratings ( Ta=25 C)
°
Parameter
Symbol
SVCC
Value
Unit
V
Maximum Supply Voltage
18
MAX
PVCC1
18
V
PVCC2
18
V
Power Dissipation
P
D
3note
W
°C
°C
A
Operating Temperature
Storge Temperature
Maximum Output Current
T
−35 ~ +85
−55 ~ +150
1
OPR
T
STG
I
OMAX
Notes:
1. When mounted on 70mm × 70mm × 1.6mm PCB
2. Power dissipation reduces 24mW/°C for using above T = 25°C
A
3. Do not exceed P and SOA
D
Pd (mW)
3,000
2,000
1,000
0
0
25
50
75
100
125
150
175
Ambient temperature, Ta [°C]
Recommended Operating Conditions ( Ta=25 C)
°
Parameter
Symbol
SVCC
Min.
4.5
Typ.
Max.
13.2
Unit
V
Operating Supply Voltage
-
-
-
PVCC1
PVCC2
4.5
SVCC
SVCC
V
4.5
V
9
FAN8037 (KA3037)
Electrical Characteristics
(SV = PV
CC
= PV
= 8V, T = 25°C, unless otherwise specified)
CC2 A
CC1
Parameter
Symbol
Conditions
Under no-load
Min.
Typ.
Max. Units
Quiescent circuit current
Power save on current
Stand by on voltage
Stand by off voltage
Power save on voltage
Power save off voltage
All mute on voltage
I
15
-
25
1
-
35
2
mA
mA
V
CC
I
Pin21=GND
PS
V
Pin20=Variation
Pin20=Variation
Pin21=Variation
Pin21=Variation
Pin22=Variation
Pin22=Variation
-
0.5
-
SBON
V
2
-
-
V
SBOFF
V
-
0.5
-
V
PSON
V
2
-
-
V
PSOFF
V
MON
-
0.5
-
V
All mute off voltage
V
2
-
V
MOFF
DRIVER PART (R =8 )
Ω
L
Output offset voltage
V
V =2.5V
IN
−80
-
6.5
11.5
12
2
+80
mV
V
OO
Maximum output voltage 1
Maximum output voltage 2
Closed-loop voltage gain
Slew rate
V
V
V
=PV
CC
=PV
CC
=PV
=PV
=8V, R =8Ω
5.5
-
OM1
OM2
CC1
CC1
CC2
L
V
=13V, R =24Ω 10.5
-
13.5
-
V
CC2
L
A
V =0.1Vrms
IN
10.5
dB
V/µs
VF
SR
Square, Vout=4Vp-p,f=120kHz
-
INPUT OPAMP PART
Input offset voltage
Input bias current
V
-
-
−30
-
-
+30
mV
nA
V
OF
I
-
7.2
-
300
B
High level output voltage
Low level output voltage
Output sink current
Output source current
Open loop voltage gain
Slew rate
V
R =Open
7.7
0.2
4
-
OH
L
V
R =Open
0.5
V
OL
L
I
R =50Ω
2
-
-
-
-
mA
mA
dB
V/µs
SINK
L
I
R =50Ω
2
4
SOURCE
L
G
V =−75dB
-
70
2.5
VO
IN
SR
Square, Vout=2Vp-p, f=120kHz
-
10
FAN8037 (KA3037)
Electrical Characteristics (Continued)
(SV = PV
CC
= PV
= 8V, T = 25°C, unless otherwise specified)
CC2 A
CC1
Parameter
Symbol
Conditions
Min.
Typ.
Max. Units
TRAY, CHANGER,PANEL DRIVE PART (R =45 )
Ω
L
Input high level voltage
Input low level voltage
Output voltage 1
V
-
-
2
-
-
-
-
0.5
-
V
V
V
V
V
IH
V
IL
V
V
V
V
V
V
=8V, V
=3V, R =8Ω
-
5
6
9
O1
O2
O3
CC
CC
CC
CTL
CTL
L
Output voltage 2
=8V, V
=3V, R =45Ω
-
-
L
Output voltage 3
=13V, V
CTL
=4.5V,
-
-
R =45Ω
L
Output load regulation
Output offset voltage 1
Output offset voltage 2
VARIABLE REGULATOR PART
Load regulation
∆V
V
=3V, I =100mA → 400mA
CTL
-
300
700
+40
+40
mV
mV
mV
RL
OO1
OO2
L
V
V
V =5V, 5V
IN
−40
−40
-
-
V =0V, 0V
IN
∆V
∆V
I =0 → 200mA
L
−40
−20
4.75
3.135
-
0
0
+10
+30
5.25
3.465
0.5
V
mV
V
RL
Line regulation
I =200mA, V =6V → 9V
L CC
CC
Regulator output voltage 1
Regulator output voltage 2
Regulator reset on voltage
Regulator reset off voltage
V
V
I =100mA
L
5.0
3.3
-
REG1
REG2
I =100mA
L
V
Reson
Resoff
Pin43=Varivation
Pin43=Varivation
V
2
-
-
V
11
FAN8037 (KA3037)
Application Information
1. THERMAL SHUTDOWN
SVCC
• When the chip temperature reaches to 175°C, then the TSD circuit is
activated.
• This shut down the bias current of the output drivers, and all the
output drivers are in cut-off state. Thus the chip temperature begin to
decrease.
I
REF
Output driver
bias
R1
Q0
R2
• when the chip temperature falls to 150°C, the TSD circuit is
deactivated and the output drivers are normally operated.
• The TSD circuit has the hysteresis temperature of 25°C.
Hysteresis
Ihys
R3
2. ALL MUTE FUNCTION
• When the pin22 is high, the TR Q1 is turned on and Q2 is off, so the
bias circuit is enabled. On the other hand, when the pin22 is Low
(GND) , the TR Q1 is turned off and Q2 is on, so the bias circuit is
disabled.
Bias blocks
(4-Ch BTL
and 3-Ch logic
loading)
SVCC
• That is, this function will cause all the output drivers to be in mute
state.
Q2
22
• Truth table is as follows;
Q1
Pin#22
HIGH
LOW
FAN8037
MUTE-OFF
MUTE-ON
3. POWER SAVE FUNCTION
• When the pin21 is high, the TR Q3 is turned on and Q4 is off, so the
bias circuit is enabled. On the other hand, when the pin21 is Low
(GND) , the TR Q3 is turned off and Q4 is on, so the bias circuit is
disabled.
SVCC
Main Bias
(except for
variable reg.)
• That is, this function will cause all the circuit blocks of the chip except
for the variable regulator to be in the off state. thus the low power
quiescent state is established
Q4
21
Q3
• Truth table is as follows;
Pin#21
HIGH
LOW
FAN8037
POWER SAVE OFF
POWER SAVE ON
12
FAN8037 (KA3037)
4. STANDBY FUNCTION
• When the pin20 is high, the TR Q5 is turned on and Q6 is off, so the
bias circuit is enabled. On the other hand, when the pin20 is Low
(GND) , the TR Q5 is turned off and Q6 is on, so the bias circuit is
disabled.
• That is, this function will cause the output drivers of the 4-CH BTL
part(Focus, Tracking, Spindle, Sled) to be in off state.
• Truth table is as follows
SVCC
Bias block
(4-CH BTL
output driver)
Q6
20
Q5
Pin#20
HIGH
LOW
KA3037
STANDBY OFF
STANDBY ON
5. REGULATOR & RESET FUNCTION
The regulator and reset circuits are illustrated in the figure 1.
• The external circuit is composed of the PNP transistor(KSB772), capacitor(about 33µF) and 2 feedback resistors.
• The capacitor is used as a ripple eliminator and should have good temperature characteristics.
• The regulator output voltage is decided as follows.
V
= (1+R1/R2) × 2.5
REG
• When the voltage of the pin 43 (Vreset) is high, the regulator circuit operates normally. If the voltage of pin 43 is low, the
regulator circuit is disabled .
SVCC
KSB772
V
REG
Vreset
43
33µF
R1
R2
42
41
40
−
2.5V
+
FAN8037
Figure 1. Regulator circuit
13
FAN8037 (KA3037)
6. FOCUS, TRACKING ACTUATOR, SPINDLE, SLED MOTOR DRIVE PART
R2
R1
−
7
8
OPin+
OPin-
1
2
4
5
46
47
Vin
39
34 32
+
DOP
DON
37
+
−
R1
Vp
R2
M
R2
+
R2
3
9
6
48
38 36 33 31
−
44
R1
Vref
R2
PVCC1
Dp
60k
+
Vp
−
62k
Qp
• The voltage, Vref is the reference voltage given by the external bias voltage of the pin 44.
• The input signal (Vin) throughpins46,1,4 and7is amplified onetime and then fed to the output stage.
(assume that input opamp was used as a buffer)
• The total closed loop voltage gain is as follows
=
+
Vref ∆V
Vin
=
+
DOP Vp 2∆V
=
– ∆
DON Vp 2 V
=
–
=
Vout
Gain
DOP DON 4∆V
Vout
=
------------ =
=
20log4 12dB
20log
∆V
• If you want to change the total closed loop voltage gain, you must use the input opamp as an amplifier
• The output stage is the balanced transformerless (BTL) driver.
• The bias voltage Vp is expressed as ;
62k
-------------------------
+ VcesatQp
= (
– –
) ×
PVCC1 VDp VcesatQp
Vp
+
60k 62k
+
VcesatQp
–
+
PVCC1 VDp VcesatQp
--------------------------------------------------------------------------
- - - - - - - - - -
(1)
=
1.97
14
FAN8037 (KA3037)
7. TRAY, CHANGER,PANEL MOTOR DRIVE PART
out 1
29
out 2
25
M
24
27
30
26
D
D
LEVEL SHIFT
M.S.C
6.5V
V(out1,out2)
CTL1,2,3
13 19
10
S.W
0
3.25V
V
CTL
IN
IN
FWD
14
REV
11
12
17
15 18
• Rotational direction control
The forward and reverse rotational direction is controlled by FWD (pin 11,14, 17) and REV (pin 12,15,18) and the input
conditions are as follows.
INPUT
OUTPUT
FWD
REV
H
OUT 1
OUT 2
State
Brake
H
H
L
Vp
H
L
Vp
L
L
Forward
H
H
-
Reverse
L
L
-
Hign impedance
• Where Vp(Power referencd voltage) is approximately about 3.75V at PVCC2=8V ) acording to equation (1).
• Where out1 pins are pins24,26,29 and out2 pins are pins25,27,30
• Motor speed control (When SVCC=PVCC2=8V)
- The almost maximum torque is obtained when the pins (10,13 and 19 (CTL1, 2, 3)) are open.
- If the voltage of the pins (10,13 and 19 (CTL1, 2, 3)) are 0V, the motor will not operate.
- When the control voltage of the pins 10,13 and 19 (CTL1, 2, 3) are between 0 and 3.25V, the differential output
voltage(V(out1,out2)) is about two times of control voltage. Hence, the control to the differential output gain is two.
- When the control voltage is greater than 3.25V, the output voltage is saturated at the 6.5V because of the output swing
limitation.
15
FAN8037 (KA3037)
8. BOOTSTRAPPED OPERATION
• Our IC has two kinds of power supplies, the power supply , SVCC is for
predrivers and the other circuit blocks(SVCC), and PVCC1 and PVCC2 is
for the power transistors.
• When SVCC=PVCCn (n=1,2), no bootstapped operation occurs. Thus the
single-ended maximum output voltage is about to
SVCC
Q3
PVCC
– (
+
)
SVCC VcesatQ3 Vbe1
SVCC – 1V
Q1
• If larger output swing is requied, use the bootstrap function. When
the bootsrap function is operated.
• In the mode, the single-ended maximum output voltage is about to
SVCC PVCCn 1V
>
+
Vout
; hence wide output dynamic
–
–
PVCCn VcesatQ1 PVCCn 0.5
range can be obtained.
Q2
PreDriver
(PD)
Power TRs
16
FAN8037 (KA3037)
Test Circuits
V
CC
50Ω
1
2
R
2
22µF
+
I
L
VREF
2.5V
+
+
1000µF
100µF
R
1
OP IN (+)
OP IN (-)
RIPPLE
R
L1
OP OUT
R
L2
48
47
46
45
44
43
42
41
40
39
38
37
IN2+
DO2-
36
PGND2 35
DO3+
1
OP IN (+)
OP IN (-)
2
3
4
5
6
IN2-
OP OUT
34
DO3− 33
OUT2
IN3+
R
R
L3
L4
OP IN (+)
OP IN (-)
DO4+
32
31
IN3−
OP OUT
OUT3
DO4−
FAN8037
IN4+
7
8
30
DO5+
OP IN (+)
OP IN (-)
R
L5
L6
IN4−
DO5− 29
I
I
I
OP OUT
L
L
L
9
28
OUT4
PGND1
DO6+
10
27
26
25
CTL1
CTL1
R
DO6−
FWD1
11
12
IN1A
IN1B
DO7+
REV1
I
L
13
14
15
16
17
18
19
20
21
22
23
24
R
L7
I
L
I
L
CTL2 IN2A IN2B
IN3A IN3B
CTL3
OP-AMP PART
OPIN(+)
OPOUT
OPIN(−)
A
B
D
1
2
3
1
2
3
V
OUT
50Ω
V
PULSE
V
A
V
B
C
V
CC
1
2
17
FAN8037 (KA3037)
Typical Application Circuits 1
[Voltage control mode]
V
CC
REGOUT
R
2
+
22µF
R
1
FOCUS TRACKING
48 47 46 45 44 43
42 41 40 39 38 37
IN2+
1
2
3
4
36
35
34
DO2−
IN2-
PGND2
DO3+
DO3−
DO4+
DO4−
OUT2
IN3+
IN3−
OUT3
M
SLED
33
32
31
5
6
M
SPINDLE
FAN8037
7
30
DO5+
IN4+
M
M
TRAY
IN4−
DO5− 29
8
9
28
OUT4
CTL1
PGND2
27
10
DO6+
CHANGER
PANEL
DO6−
26
25
11 FWD1
DO7+
12
REV1
13 14 15 16 17 18
19 20 21 22 23 24
M
ALL MUTE
POWER SAVE
FOCUS, TRACKING, SLED
SPINDLE MUTE
PANEL
INPUT
Where TY is tray motor.
CG is changer motor
PL is panel motor
VREF
FOCUS TRACKING SLED SPINDLE
TY CG PL TRAY CHANGER
CONTROL INPUT INPUT
INPUT
INPUT INPUT INPUT
[SERVO PRE AMP]
[CONTROLLER]
Notes:
Radiation pin is connected to the internal GND of the package.
Connect the pin to the external GND.
18
FAN8037 (KA3037)
Typical Application Circuits 2
[Differential PWM control mode ]
V
CC
REGOUT
R
2
+
22µF
R
1
FOCUS TRACKING
48 47 46 45 44 43
42 41 40 39 38 37
IN2+
1
2
3
4
36
35
34
DO2−
IN2-
PGND2
DO3+
DO3−
DO4+
DO4−
OUT2
IN3+
IN3−
OUT3
M
SLED
33
32
31
5
6
M
SPINDLE
FAN8037
7
30
DO5+
IN4+
M
M
TRAY
IN4−
DO5− 29
8
9
28
OUT4
CTL1
PGND2
27
10
DO6+
CHANGER
PANEL
DO6−
26
25
11 FWD1
DO7+
12
REV1
13 14 15 16 17 18
19 20 21 22 23 24
M
ALL MUTE
POWER SAVE
FOCUS, TRACKING, SLED
SPINDLE MUTE
Where TY is tray motor.
CG is changer motor
PL is panel motor
VREF
FOCUS TRACKING SLED SPINDLE
TY CG PL TRAY CHANGER PANEL
INPUT
INPUT INPUT INPUT
CONTROL INPUT
INPUT INPUT
[SERVO PRE AMP]
[CONTROLLER]
Notes:
Radiation pin is connected to the internal GND of the package.
Connect the pin to the external GND
19
FAN8037 (KA3037)
Ordering Information
Device
Package
Operating Temperature
FAN80037
48-QFPH-1414
−35°C ~ +85°C
20
FAN8037 (KA3037)
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, and (c) whose failure to
perform when properly used in accordance with
instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
12/28/99 0.0m 001
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1999 Fairchild Semiconductor Corporation
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