FDMA291P [FAIRCHILD]
Single P-Channel 1.8V Specified PowerTrench MOSFET; 单P沟道1.8V指定的PowerTrench MOSFET型号: | FDMA291P |
厂家: | FAIRCHILD SEMICONDUCTOR |
描述: | Single P-Channel 1.8V Specified PowerTrench MOSFET |
文件: | 总6页 (文件大小:125K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
May 2006
FDMA291P
Single P-Channel 1.8V Specified PowerTrench® MOSFET
General Description
Features
This device is designed specifically for battery charge
or load switching in cellular handset and other ultra-
portable applications. It features a MOSFET with low
on-state resistance.
• –6.6 A, –20V. rDS(ON) = 42 mΩ @ VGS = –4.5V
rDS(ON) = 58 mΩ @ VGS = –2.5V
rDS(ON) = 98 mΩ @ VGS = –1.8V
• Low profile – 0.8 mm maximum – in the new package
MicroFET 2x2 mm
The MicroFET 2x2 package offers exceptional thermal
performance for its physical size and is well suited to
linear mode applications.
Pin 1
Bottom Drain Contact
Drain
Source
D
D
G
1
2
3
D
D
S
6
5
4
MicroFET 2x2
Absolute Maximum Ratings TA=25oC unless otherwise noted
Symbol
VDS
Parameter
Drain-Source Voltage
Ratings
Units
V
–20
VGS
Gate-Source Voltage
V
A
±8
Drain Current – Continuous
– Pulsed
(Note 1a)
–6.6
ID
–24
W
Power Dissipation for Single Operation
(Note 1a)
(Note 1b)
2.4
PD
0.9
TJ, TSTG
Operating and Storage Junction Temperature Range
–55 to +150
°C
Thermal Characteristics
°C/W
Thermal Resistance, Junction-to-Ambient
(Note 1a)
(Note 1b)
52
RθJA
Thermal Resistance, Junction-to-Ambient
145
RθJA
Package Marking and Ordering Information
Device Marking
Device
Reel Size
Tape width
Quantity
291
FDMA291P
7’’
8mm
3000 units
FDMA291P Rev B (W)
©2006 Fairchild Semiconductor Corporation
Electrical Characteristics
TA = 25°C unless otherwise noted
Symbol
Parameter
Test Conditions
Min Typ Max Units
Off Characteristics
BVDSS
Drain–Source Breakdown Voltage
–20
V
VGS = 0 V,
ID = –250 µA
∆BVDSS
∆TJ
Breakdown Voltage Temperature
Coefficient
ID = –250 µA, Referenced to 25°C
mV/°C
–12
IDSS
Zero Gate Voltage Drain Current
Gate–Body Leakage
VDS = –16 V, VGS = 0 V
–1
µA
IGSS
VGS = ± 8 V,
VDS = 0 V
±100
nA
On Characteristics
(Note 2)
VGS(th)
Gate Threshold Voltage
–0.4 –0.7 –1.0
3
V
VDS = VGS
,
ID = –250 µA
∆VGS(th)
∆TJ
Gate Threshold Voltage
Temperature Coefficient
ID = –250 µA, Referenced to 25°C
mV/°C
rDS(on)
Static Drain–Source
On–Resistance
VGS = –4.5 V, ID = –6.6 A
VGS = –2.5 V, ID = –5.1 A
VGS = –1.8 V, ID = –3.9 A
36
51
79
49
42
58
98
64
mΩ
V
GS= –4.5 V, ID = –6.6 A, TJ=125°C
gFS
Forward Transconductance
VDS = –5 V, ID = –6.6 A
16
S
Dynamic Characteristics
Ciss
Coss
Crss
Input Capacitance
1000
190
pF
pF
pF
V
DS = –10 V, V GS = 0 V,
Output Capacitance
f = 1.0 MHz
Reverse Transfer Capacitance
100
Switching Characteristics (Note 2)
VDD = –10 V, ID = –1 A,
GS = –4.5 V, RGEN = 6 Ω
td(on)
tr
td(off)
tf
Turn–On Delay Time
Turn–On Rise Time
Turn–Off Delay Time
Turn–Off Fall Time
Total Gate Charge
Gate–Source Charge
Gate–Drain Charge
13
9
23
18
68
40
14
ns
ns
V
42
25
10
2
ns
ns
VDS = –10 V, ID = –6.6 A,
VGS = –4.5 V
Qg
Qgs
Qgd
nC
nC
nC
3
Drain–Source Diode Characteristics and Maximum Ratings
IS
Maximum Continuous Drain–Source Diode Forward Current
–2
A
V
VSD
Drain–Source Diode Forward
Voltage
VGS = 0 V, IS = –2 A (Note 2)
–0.8 –1.2
trr
Diode Reverse Recovery Time
Diode Reverse Recovery Charge
IF = –6.6 A,
dIF/dt = 100 A/µs
20
8
ns
Qrr
nC
Notes:
1. RθJA is determined with the device mounted on a 1 in2 oz. copper pad on a 1.5 x 1.5 in. board of FR-4 material. RθJC is guaranteed by design while RθJA is
determined by the user's board design.
(a) RθJA = 52°C/W when mounted on a 1in2 pad of 2 oz copper, 1.5” x 1.5” x 0.062” thick PCB
(b) RθJA = 145°C/W when mounted on a minimum pad of 2 oz copper
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%
FDMA291P Rev B (W)
Typical Characteristics
24
2.6
2.4
2.2
2
VGS = -1.8V
VGS = -4.5V
-3.0V
-2.5V
20
16
12
8
-4.0V
-3.5V
1.8
1.6
1.4
1.2
1
-2.0V
-2.0V
-2.5V
-1.8V
-3.0V
-3.5V
-4.0V
4
-4.5V
0
0.8
0
1
2
3
4
5
150
4
0
4
8
12
16
20
24
-VDS, DRAIN-SOURCE VOLTAGE (V)
-ID, DRAIN CURRENT (A)
Figure 1. On-Region Characteristics.
Figure 2. On-Resistance Variation with
Drain Current and Gate Voltage.
0.15
1.6
1.4
1.2
1
ID = -6.6A
GS = -10V
ID = -3.3A
V
0.12
0.09
0.06
0.03
0
TA = 125oC
TA = 25oC
0.8
0.6
-50
-25
0
25
50
75
100
125
0
2
4
6
8
10
TJ, JUNCTION TEMPERATURE (oC)
-VGS, GATE TO SOURCE VOLTAGE (V)
Figure 3. On-Resistance Variation with
Temperature.
Figure 4. On-Resistance Variation with
Gate-to-Source Voltage.
24
20
16
12
8
100
VGS = 0V
VDS = -10V
10
1
TA = -55oC
125oC
25oC
0.1
TA = 125oC
0.01
0.001
0.0001
25oC
4
-55oC
0
0
1
2
3
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
-VGS, GATE TO SOURCE VOLTAGE (V)
-VSD, BODY DIODE FORWARD VOLTAGE (V)
Figure 5. Transfer Characteristics.
Figure 6. Body Diode Forward Voltage Variation
with Source Current and Temperature.
FDMA291P Rev B (W)
Typical Characteristics
1600
1200
800
400
0
10
f = 1MHz
VGS = 0 V
VDS = -5V
ID = -6.6A
-15V
8
6
4
2
0
-10V
Ciss
Coss
Crss
0
4
8
12
16
20
24
0
4
8
12
16
20
Qg, GATE CHARGE (nC)
-VDS, DRAIN TO SOURCE VOLTAGE (V)
Figure 7. Gate Charge Characteristics.
Figure 8. Capacitance Characteristics.
1000
100
10
100
80
60
40
20
0
SINGLE PULSE
RθJA = 145°C/W
T
A = 25°C
100us
1ms
10ms
100ms
1s
RDS(ON) LIMIT
1
10s
DC
0.1
VGS = -10V
SINGLE PULSE
RθJA = 145oC/W
0.01
0.001
T
A = 25oC
0.01
0.1
1
10
100
1000
0.0001
0.001
0.01
0.1
1
10
100
1000
-VDS, DRAIN-SOURCE VOLTAGE (V)
t1, TIME (sec)
Figure 9. Maximum Safe Operating Area.
Figure 10. Single Pulse Maximum Power
Dissipation.
1
D = 0.5
RθJA(t) = r(t) * RθJA
RθJA =145 °C/W
0.2
0.1
0.1
0.05
P(pk)
0.02
t1
0.01
t2
0.01
TJ - TA = P * RθJA(t)
Duty Cycle, D = t1 / t2
SINGLE PULSE
0.001
0.0001
0.001
0.01
0.1
1
10
100
1000
t1, TIME (sec)
Figure 11. Transient Thermal Response Curve.
Thermal characterization performed using the conditions described in Note 1b.
Transient thermal response will change depending on the circuit board design.
FDMA291P Rev B (W)
FDMA291P Rev B (W)
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not
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FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY
PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY
LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;
NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE
SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S WORLDWIDE TERMS AND CONDITIONS,
SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR
CORPORATION.
As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, or (c) whose failure to perform
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
result in significant injury to the user.
2. A critical component is any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Formative or In
Design
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
Preliminary
First Production
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
No Identification Needed
Obsolete
Full Production
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
Not In Production
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Rev. I19
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