FI1019MTC [FAIRCHILD]
Line Transceiver, 1 Func, 1 Driver, 1 Rcvr, PDSO14, 4.40 MM, MO-153, TSSOP-14;
| 型号： | FI1019MTC |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Line Transceiver, 1 Func, 1 Driver, 1 Rcvr, PDSO14, 4.40 MM, MO-153, TSSOP-14 驱动 光电二极管 接口集成电路 驱动器 |
| 文件： | 总8页 (文件大小：322K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Preliminary
November 2000
Revised December 2000
FI1019
3.3V LVDS High Speed Differential Driver/Receiver
(Preliminary)
General Description
Features
This driver and receiver pair are designed for high speed
interconnects utilizing Low Voltage Differential Signaling
(LVDS) technology. The driver translates LVTTL signals to
LVDS levels with a typical differential output swing of
350mV and the receiver translates LVDS signals, with a
typical differential input threshold of 100mV, into LVTTL
levels. LVDS technology provides low EMI at ultra low
power dissipation even at high frequencies. This device is
ideal for high speed clock or data transfer.
■ Greater than 400Mbs data rate
■ 3.3V power supply operation
■ 0.5ns maximum differential pulse skew
■ 2.5ns maximum propagation delay
■ Low power dissipation
■ Power OFF protection
■ 100mV receiver input sensitivity
■ Fail safe protection open-circuit, shorted and terminated
conditions
■ Meets or exceeds the TIA/EIA-644 LVDS standard
■ Flow-through pinout simplifies PCB layout
■ 14-Lead SOIC and TSSOP packages save space
Ordering Code:
Order Number Package Number
Package Description
FI1019M
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
FI1019MTC
MTC14
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Function Table
Connection Diagram
Inputs
Outputs
RI+
L
RI−
H
RE
L
RO
L
H
L
L
H
X
X
H
L
Z
Fail Safe Condition
H
DI
DE
DO+
DO−
H
L
H
H
L
H
Z
L
Pin Descriptions
H
L
X
L
Z
H
Pin Name
Description
Open−Circuit or Z
H
DI
LVTTL Data Input
H = HIGH Logic Level
Z = High Impedance
L = LOW Logic Level
Fail Safe = Open, Shorted, Terminated
X = Don’t Care
DO+
DO−
DE
Non-inverting LVDS Output
Inverting LVDS Output
Driver Enable (LVTTL, Active HIGH)
Non-Inverting LVDS Input
Inverting LVDS Input
RI+
RI−
RO
LVTTL Receiver Output
RE
VCC
GND
Receiver Enable (LVTTL, Active LOW)
Power Supply
Ground
© 2000 Fairchild Semiconductor Corporation
DS500506
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Preliminary
Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions
Supply Voltage (VCC
)
−0.5V to +4.6V
−0.5V to +6V
−0.5V to 4.7V
−0.5V to +6V
−0.5V to 4.7V
Continuous
16 mA
LVTTL DC Input Voltage (DI, DE, RE)
LVDS DC Input Voltage (RI+, RI−)
LVTTL DC Output Voltage (RO)
Supply Voltage (VCC
Input Voltage (VIN
)
3.0V to 3.6V
0 to VCC
)
Magnitude of Differential Voltage
(|VID|)
LVDS DC Output Voltage (DO+, DO−)
LVDS Driver Short Circuit Current (IOSD
LVTTL DC Output Current (IO)
100 mV to VCC
0.05V to 2.35V
−40°C to +85°C
)
Common-Mode Input Voltage (VIC
Operating Temperature (TA)
)
Storage Temperature Range (TSTG
Max Junction Temperature (TJ)
Lead Temperature (TL)
)
−65°C to +150°C
150°C
Note 1: The “Absolute Maximum Ratings”: are those values beyond which
damage to the device may occur. The databook specifications should be
met, without exception, to ensure that the system design is reliable over its
power supply, temperature and output/input loading variables. Fairchild
does not recommend operation of circuits outside databook specification.
(Soldering, 10 seconds)
260°C
≥ 2000V
≥ 200V
ESD (Human Body Model)
ESD (Machine Model)
DC Electrical Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified
Symbol Parameter Test Conditions
LVDS Differential Driver Characteristics
Min
250
Typ
Max
Units
(Note 2)
VOD
Output Differential Voltage
VOD Magnitude Change from
Differential LOW-to-HIGH
Offset Voltage
350
450
25
mV
mV
V
∆VOD
RL = 100Ω, See Figure 1
VOS
1.125
1.25
1.375
25
∆VOS
Offset Magnitude Change from
Differential LOW-to-HIGH
Disabled Output Leakage Current
Power Off Output Current
Short Circuit Output Current
mV
IOZD
IOFF
IOS
V
V
V
V
OUT = VCC or GND, DE = 0V
CC = 0V, VOUT = 0V or 3.6V
OUT = 0V, DE = VCC
±20
±20
−8
µA
µA
mA
OD = 0V, DE = VCC
±6
LVTTL Driver Characteristics
VOH
VOL
IOZ
Output HIGH Voltage
I
OH = −100 µA, RE = 0V,
See Figure 6 and Table 1
OH = −8 mA, RE = 0V, VID = 400 mV
ID = 400 mV, VIC = 1.2V, see Figure 6
OL = 100 µA, RE = 0V, VID = −400 mV
See Figure 6 and Table 1
OL = −8 mA, RE = 0V, VID = −400 mV
V
CC −0.2
V
I
2.4
V
Output LOW Voltage
I
0.2
V
I
0.5
V
ID = −400 mV, VIC = 1.2V, see Figure 6
OUT = VCC or GND, RE = VCC
Disabled Output Leakage Current
V
±20
µA
LVDS Receiver Characteristics
VTH
VTL
Differential Input Threshold HIGH
See Figure 6 and Table 1
See Figure 6 and Table 1
100
mV
mV
µA
Differential Input Threshold LOW
Input Current
−100
IIN
VIN = 0V or VCC
±20
±20
II(OFF)
Power-OFF Input Current
VCC = 0V, VIN = 0V or 3.6V
µA
LVTTL Driver and Control Signals Characteristics
VIH
VIL
Input HIGH Voltage
Input LOW Voltage
Input Current
2.0
VCC
0.8
V
V
GND
IIN
V
IN = 0V or VCC
±20
±20
µA
µA
V
II(OFF)
VIK
Power-OFF Input Current
Input Clamp Voltage
VCC = 0V, VIN = 0V or 3.6V
IIK = −18 mA
−1.5
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2
Preliminary
DC Electrical Characteristics (Continued)
Device Characteristics
ICC
Power Supply Current
Driver Enabled, Driver Load: RL = 100 Ω
Receiver Disabled, No Receiver Load
Driver Enabled, Driver Load: RL = 100 Ω,
Receiver Enabled, (RI+ = 1V and RI− = 1.4V)
or (RI+ = 1.4V and RO− = 1V)
14
20
mA
mA
Driver Disabled, Receiver Enabled,
(RI+ = 1V and RI− = 1.4V) or
13.5
9
mA
(RI+ = 1.4V and RI− = 1V)
Driver Disabled, Receiver Disabled
Any LVTTL or LVDS Input
mA
pF
pF
CIN
Input Capacitance
Output Capacitance
3
5
COUT
Any LVTTL or LVDS Output
Note 2: All typical values are at TA = 25°C and with VCC = 3.3V.
AC Electrical Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified
Min
Typ
Max
Symbol
Parameter
Test Conditions
Units
(Note 3)
Driver Timing Characteristics
tPLHD
Differential Propagation Delay
LOW-to-HIGH
0.5
0.5
1.5
1.5
ns
ns
tPHLD
Differential Propagation Delay
HIGH-to-LOW
RL = 100 Ω, CL = 10 pF,
tTLHD
tTHLD
tSK(P)
tSK(PP)
tZHD
Differential Output Rise Time (20% to 80%)
Differential Output Fall Time (80% to 20%)
See Figure 2 and Figure 3
0.4
0.4
1.0
1.0
0.5
1.0
5.0
5.0
5.0
5.0
ns
ns
ns
ns
ns
ns
ns
ns
Pulse Skew |tPLH - tPHL
|
Part-to-Part Skew (Note 4)
Differential Output Enable Time from Z to HIGH
RL = 100Ω, CL = 10 pF,
tZLD
Differential Output Enable Time from Z to LOW See Figure 4 and Figure 5
Differential Output Disable Time from HIGH to Z
tHZD
tLZD
Differential Output Disable Time from LOW to Z
Receiver Timing Characteristics
tPLH
tPHL
tTLH
tTHL
tSK(P)
tSK(PP)
tZH
Propagation Delay LOW-to-HIGH
1.0
1.0
2.5
2.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Propagation Delay HIGH-to-LOW
Output Rise time (20% to 80%)
Output Fall time (80% to 20%)
|VID| = 400 mV, CL = 10 pF,
0.5
0.5
See Figure 6 and Figure 7
Pulse Skew | tPLH - tPHL
|
0.5
1.0
5.0
5.0
5.0
5.0
Part-to-Part Skew (Note 4)
LVTTL Output Enable Time from Z to HIGH
LVTTL Output Enable Time from Z to LOW
LVTTL Output Disable Time from HIGH to Z
LVTTL Output Disable Time from LOW to Z
tZL
RL = 500 Ω, CL = 10 pF,
tHZ
See Figure 8
tLZ
Note 3: All typical values are at TA = 25°C and with VCC = 5V.
Note 4: tSK(PP) is the magnitude of the difference in propagation delay times between any specified terminals of two devices switching in the same direction
(either LOW-to-HIGH or HIGH-to-LOW) when both devices operate with the same supply voltage, same temperature, and have identical test circuits.
3
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Preliminary
Note A: Input pulses have frequency = 10 MHz, tR or tF = 1 ns
Note B: CL includes all probe and jig capacitances
FIGURE 1. Differential Driver DC Test Circuit
FIGURE 2. Differential Driver Propagation Delay and
Transition Time Test Circuit
Note B: Input pulses have the frequency = 10 MHz, tR or tF = 1 ns
Note A: CL includes all probe and jig capacitances
FIGURE 4. Differential Driver Enable and
Disable Test Circuit
FIGURE 3. AC Waveforms for Differential Driver
FIGURE 5. Enable and Disable AC Waveforms
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4
Preliminary
Note A: Input pulses have frequency = 10 MHz, tR or tF = 1ns
Note B: CL includes all probe and jig capacitance
FIGURE 6. Differential Receiver Voltage Definitions and Propagation Delay and Transition Time Test Circuit
TABLE 1. Receiver Minimum and Maximum Input Threshold Test Voltages
Applied Voltages (V)
Resulting Differential
Input Voltage (mV)
VID
Resulting Common Mode
Input Voltage (V)
VIC
VIA
VIB
1.25
1.15
2.4
2.3
0.1
0
1.15
1.25
2.3
2.4
0
100
−100
100
1.2
1.2
2.35
2.35
0.05
0.05
1.2
−100
100
0.1
0.9
1.5
1.8
2.4
0
−100
600
1.5
0.9
2.4
1.8
0.6
0
−600
600
1.2
2.1
−600
600
2.1
0.3
0.6
−600
0.3
5
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Preliminary
FIGURE 7. LVDS Input to LVTTL Output AC Waveforms
Test Circuit for LVTTL Outputs
Voltage Waveforms Enable and Disable Times
FIGURE 8. LVTTL Outputs Test Circuit and AC Waveforms
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6
Preliminary
Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
Package Number M14A
7
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Preliminary
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC14
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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8
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