FIN224C [FAIRCHILD]
24-Bit Low-Power Serializer/Deserializer; 24位低功耗串行器/解串器
| 型号： | FIN224C |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | 24-Bit Low-Power Serializer/Deserializer |
| 文件： | 总9页 (文件大小：765K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
October 2009
FIN224C
24-Bit Low-Power Serializer/Deserializer
Features
Description
The FIN224C μSerDes™ is
a
low-power serializer/
Data & Control Bits
Frequency
Capability
24
20MHz
HVGA
deserializer (μSerDes™) that can help minimize the cost
and power of transferring wide signal paths. Through the
use of serialization, the number of signals transferred from
one point to another can be significantly reduced. Typical
reduction is 5:1 for unidirectional paths. Through the use of
differential signaling, shielding and EMI filters can also be
minimized, further reducing the cost of serialization.
Interface
Microcontroller / RGB
I86 & m68
µController Usage
Dynamic Current
Standby Current
Core Voltage (VDDA/S
17mA at 10Mhz
10µA
)
2.5V to 3.3V
I/O Voltage (VDDP
ESD
Package
Ordering Information
)
1.65V to 3.6V
15KV (IEC)
MLP-40 (6 x 6mm)
FIN224CMLX, MLP-40
The differential signaling is also important for providing a
noise-insensitive signal that can withstand radio and
electrical noise sources. Major reduction in power
consumption allows minimal impact on battery life in mobile
applications. It is possible to use a single Phase-Locked Loop
(PLL) for most applications, including bi-directional operation.
Related Resources
For samples and questions, please contact:
Applications
interface@fairchildsemi.com.
Slider, Folder, and Clamshell Mobile Handsets
GSM and CDMA Phones
Typical Application
Simple Interface
Built-in voltage
translation
Serializer
Deserializer
70-130
Ohms
+
-
+
-
2
2
Main
Baseband
Display
+
-
+
-
Internal
Termination
Figure 1. Mobile Phone Example
© 2009 Fairchild Semiconductor Corporation
FIN224C • Rev. 1.0.9
www.fairchildsemi.com
Pin Configuration
Pin Name
STROBE
CKREF
CKP
Description
LVCMOS Strobe Signal for Latching Data into the Serializer (On Rising Edge)
LVCMOS Clock Input and PLL Reference
LVCMOS Word Clock Output
DP[24:1]
/DIRO
LVCMOS Data I/O
LVCMOS Control Output Inversion of DIRI
S1, S2
DIRI
LVCMOS Select Pins, Controls the Mode of Operation, see Table 1
0
1
Deserializer
Serializer
LVCMOS Control, Selects Serializer or Deserializer Mode
Serial Data I/O
DSO+ / DSI-
DSO- / DSI+
CKSI+, CKSI-
CKSO+, CKSO-
VDDP
Serial Clock Input
Serial Clock Output
Power Supply for Parallel I/O and Internal Circuitry
Power Supply for Serial I/O
Power Supply for Core
VDDS
VDDA
GND
Ground Pins
Note:
1. 0 = VIL; 1 = VIH.
/DIRO
30
29
28
27
26
25
24
23
DP[9] 1
CKSO+
CKSO-
DP[10] 2
DP[11] 3
DP[12] 4
VDDP 5
CKP 6
DSO+ / DSI-
DSO- / DSI+
CKSI-
GND PAD
Must be Grounded
CKSI+
DP[13] 7
DP[14] 8
DIRI
22 S2
9
DP[15]
21 VDDS
DP[16] 10
Figure 2. MLP-40 Pinout (Through View)
© 2009 Fairchild Semiconductor Corporation
FIN224C • Rev. 1.0.9
www.fairchildsemi.com
2
Table 1. Serializer / Deserializer, Operation, and Reset Modes
DIRI
S1
S2
Mode of Operation
Reset Mode
X
0
0
LVCMOS Outputs = High Impedance
LVCMOS Inputs = Known State
1
0
0
1
1
0
Serializer Mode
Deserializer Mode
Application Diagrams
Serializer
FIN224C
Deserializer
FIN224C
1.8V
2.8V
2.8V
VDDP VDDS/A
CKP
2.8V
Baseband
Processor
Main Display
18-Bit RGB
VDDP VDDS/A
PCLK
CKREF
STROBE
PCLK
DP[18:1]
DP[19]
DP[20]
DP[21]
DP[24:22]
DATA[17:0]
HSYNC
VSYNC
/CS
CKSO+
CKSO-
CKSI+
CKSI-
DP[17:0]
HSYNC
VSYNC
/CS
DP[18:1]
DP[19]
DP[20]
DP[21]
DP[24:22]
DSO+/DSI-
DSO-/DSI+
DSO-/DSI+
DSO+/DSI-
RESET
CKSI+
CKSI-
CKSO+
CKSO-
S1
S2
S1
S2
Reset
DIRI
/DIRO
CKP
DIRI
/DIRO
CKREF
STROBE
GND
GND
Figure 3. 18-Bit RGB Interface Block Diagram
© 2009 Fairchild Semiconductor Corporation
FIN224C • Rev. 1.0.9
www.fairchildsemi.com
3
Serializer
FIN224C
Deserializer
FIN224C
Clock
Source
1.8V
2.8V
2.8V
VDDP VDDS/A
CKP
2.8V
Baseband
Processor
Main Display
16-Bit µController
VDDP VDDS/A
CKREF
STROBE
/WE
/WE
DP[8:1]
DP[1: 6:9]
DP[17]
DP[18]
DP[19]
DATA[7:0]
DATA[15:8]
A0
CKSO+
CKSO-
CKSI+
CKSI-
DP[7:0]
DP[15:8]
A0
DP[8:1]
DP[16:9]
DP[17]
DP[18]
DP[19]
/CS0
DSO+/DSI-
DSO-/DSI+
DSO-/DSI+
DSO+/DSI-
/CS0
/CS1
Main Display
8-Bit µController
DP[:24:20]
DP[24:20]
CKSI+
CKSI-
CKSO+
CKSO-
S1
S2
DIRI
/WE
S1
S2
DIRI
/DIRO
CKP
Reset
DATA[7:0]
A0
/CS1
/DIRO
CKREF
STROBE
GND
GND
Figure 4. Dual-Display µController Interface Block Diagram
Additional Application Information
Flex Cabling: The serial I/O information is transmitted at a high serial rate. Care must be taken implementing this serial I/O
flex cable. The following best practices should be used when developing the flex cabling or Flex PCB.
Keep all four differential serial wires the same length.
Do not allow noisy signals over or near differential serial wires. Example: No CMOS traces over differential serial wires.
Design goal of 70 to 130Ω differential characteristic impedance.
Do not place test points on differential serial wires.
Design differential serial wires a minimum of 2cm away from the antenna.
Visit Fairchild’s website at http://www.fairchildsemi.com/products/interface/userdes.html, contact your sales
representative, or contact Fairchild directly at interface@fairchildsemi.com for applications notes or flex guidelines.
© 2009 Fairchild Semiconductor Corporation
FIN224C • Rev. 1.0.9
www.fairchildsemi.com
4
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable
above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition,
extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute
maximum ratings are stress ratings only.
Symbol
Parameter
Min.
Max.
Unit
VDD
Supply Voltage
-0.5
-0.5
-65
+4.6
+4.6
+150
+150
+260
15.0
V
V
All Input/Output Voltage
Storage Temperature Range
Maximum Junction Temperature
TSTG
TJ
°C
°C
°C
TL
Lead Temperature (Soldering, 4 Seconds)
IEC 61000 Board Level
All Pins
Serial I/0, /RES, PAR/SPI to GND
2.5
8.0
ESD
kV
Human Body Model, JESD22-A114
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating
conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend
exceeding them or designing to absolute maximum ratings.
Symbol
Parameter
Min.
Max.
Unit
(1)
VDDA, VDDS
VDDP
Supply Voltage
Supply Voltage
2.5
1.65
-30
3.3
3.60
+70
V
V
TA
Operating Temperature
°C
Note:
1. VDDA and VDDS supplies must be hardwired together to the same power supply.
© 2009 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FIN224C • Rev. 1.0.9
5
Electrical Specifications
Values valid for over supply voltage and operating temperature ranges unless otherwise specified. Typical values are tested
at TA = 25°C and VDD = 2.775V.
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
DC Parallel I/O Characteristics
VIH
VIL
Input High Voltage
Input Low Voltage
0.65 x VDDP
GND
VDDP
V
V
0.35 x VDDP
VDDP = 3.3±0.30V
VOH
Output High Voltage
IOH = -2.0mA
IOH = -2.0mA
VDDP = 2.5±0.20V
VDDP = 1.8±0.18V
VDDP = 3.3±0.30V
VDDP = 2.5±0.20V
VDDP = 1.8±0.18V
0.75 x VDDP
V
VOL
Output Low Voltage
Input Current
0.25 x VDDP
V
IIN
-5
5
µA
DC Serial Characteristics
IODH Output High Source Current
IODL
-1.75
0.95
mA
mA
Output Low Source Current
CKSO, DSO = 0V to VDDS
S2 = S1 = 0V
,
,
IOZ
IIZ
Disabled Output Leakage Current
±1
±1
±5
±5
µA
CKSO, DSO = 0V to VDDS
S2 = S1 = 0V
Disabled Input Leakage Current
RTRM
Z
CKSI, DS Internal Receiver Termination Resistor
Serial Transmission Line Impedance
100
100
Ω
Ω
70
130
Power Characteristics
All DP and Control Inputs at 0V or No
CKREF, DIRI = 1
IDDA/SSER VDDA, VDDS Serializer Static Current
4.5
5
mA
mA
All DP and Control Inputs at 0V or No
CKREF, DIRI = 0
IDDA/SDES VDDA, VDDS Derializer Static Current
10MHz
CKREF = STROBE, DIRI = 1
20MHz
11
15
7
mA
mA
mA
mA
Dynamic Serializer Current
IDDSER
IDDSER = IDDA + IDDS + IDDP
10MHz
CKREF = STROBE, DIRI = 0
20MHz
Dynamic Deserializer Current
IDDDES
IDDSER = IDDA + IDDS + IDDP
10
V
DD Power-Down Current
IDD_PD = IDDA + IDDS + IDDP
AC Serializer, DIRI = 1 Specifications
IDD_PD
S1 = S2 = 0 All Inputs at GND or VDD
0.1
µA
fMAX
fREF
Maximum CKREF Frequency
2
20
20
MHz
MHz
CKREF Frequency Relative to
STROBE
1.1 x fSTROBE
tCPWH
tCPWL
tCLKT
CKREF Clock HIGH Time
0.2
0.2
0.5
0.5
T
T
CKREF Clock LOW Time
LVCMOS Input Transition Time
STROBE Pulse Width HIGH/LOW
90
ns
ns
tSPWH
(Tx4) / 26
2.5
(Tx22) / 26
tHTC
tSTC
tSTC
DP[n] Setup to STROBE
DP[n] Hold to STROBE
ns
ns
STROBE
DP[24:1]
tHTC
2.0
© 2009 Fairchild Semiconductor Corporation
FIN224C • Rev. 1.0.9
www.fairchildsemi.com
6
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
tTPLLS0
Phase Lock Loop Stabilization Time
200
µs
tTPLLD0
PLL Disable Time Loss of Clock
30
µs
AC Deserializer, DIRI = 0 Specifications
tSKEW_DS-
Allowed DS-CKS Input Signal Skew
-150
150
ps
ns
CKS
tRCOH
tRCOH
tPDV
CKP Out Low Time
CKP Out High Time
Data Valid to CKP Low
13a-3
13a+3
13a-3
8a-6
13a+13
8a+1
ns
ns
CKREF = STROBE, a = (1/f)/13
tROLH
Output Rise Time (20% to 80%)
Output Fall Time (20% to 80%)
18
18
ns
ns
tROLH
AC Enable and Disable Timing
tPLZ(HZ)
Deserializer Disable Time
25
ns
tPZL(ZH)
Deserializer Enable Time
Serializer Disable Time
Serializer Enable Time
2
µs
ns
ns
tPLZ(HZ)
25
65
tPZL(ZH)
Notes:
2. Skew is measured from either the rising or falling edge of CKSO clock to the rising or falling edge of DSO. Signals are
edge aligned. Both outputs should have identical load condtions for this test to be valid.
3. If CKREF is not equal to STROBE for the serializer, the CKP signal does not maintain a 50% duty cycle. The low time of
CKP remains 13 bit times.
© 2009 Fairchild Semiconductor Corporation
FIN224C • Rev. 1.0.9
www.fairchildsemi.com
7
Physical Dimensions
0.15
C
6.00
B
A
(0.80)
6.00
PIN #1 IDENT
6.38MIN
4.37MAX
0.15
C
4.77MIN
0.80 MAX
0.10
C
(0.20)
C
0.20MIN
X4
0.08
C
0.05
0.00
0.28 MAX
X40
0.50TYP
SEATING
PLANE
E
4.20
4.00
0.50
0.30
0.50
4.20
4.00
(DATUM B)
PIN #1 ID
(DATUM A)
0.18-0.30
0.10
0.05
C
C
A B
0.50
NOTES:
A. CONFORMS TO JEDEC REGISTRATION MO-220, VARIATION
WJJD-2 WITH EXCEPTION THAT THIS IS A SAWN VERSION..
B. DIMENSIONS ARE IN MILLIMETERS.
C. DIMENSIONS AND TOLERANCES PER ASME Y14.5M-1994.
D. LAND PATTERN PER IPC SM-782.
E. WIDTH REDUCED TO AVOID SOLDER BRIDGING.
F. DIMENSIONS ARE NOT INCLUSIVE OF BURRS, MOLD FLASH, OR
TIE BAR PROTRUSIONS.
G. DRAWING FILENAME: MKT-MLP40Arev3.
Figure 6. 40-Lead, Molded Leadless Package (MLP), Quad, JEDEC MO-220, 6mm Square
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without
notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most
recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which
covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/.
For current tape and reel specifications, visit Fairchild Semiconductor’s online packaging area: http://www.fairchildsemi.com/packaging/MLP40A.html
Ordering Information
Operating
Temperature Range
Part Number
Package
Packing Method
Eco Status
40-Lead, Molded Leadless Package (MLP),
Quad, JEDEC MO-220, 6mm Square
FIN224CMLX
-30 to +70°C
Green
Tape & Reel
For Fairchild’s definition of Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html.
© 2009 Fairchild Semiconductor Corporation
FIN224C • Rev. 1.0.9
www.fairchildsemi.com
8
© 2009 Fairchild Semiconductor Corporation
FIN224C • Rev. 1.0.9
www.fairchildsemi.com
9
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