FIN3385MTDX [FAIRCHILD]
Low-Voltage, 28-Bit, Flat-Panel Display Link Serializer / Deserializer; 低电压， 28位，平板显示器链路串行器/解串器
| 型号： | FIN3385MTDX |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Low-Voltage, 28-Bit, Flat-Panel Display Link Serializer / Deserializer |
| 文件： | 总21页 (文件大小：590K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
March 2012
FIN3385 / FIN3386
Low-Voltage, 28-Bit, Flat-Panel Display Link
Serializer / Deserializer
Features
Description
The FIN3385 and FIN3386 transform 28-bit wide parallel
Low-Voltage TTL (LVTTL) data into four serial Low
Voltage Differential Signaling (LVDS) data streams. A
phase-locked transmit clock is transmitted in parallel
with the data stream over a separate LVDS link. Every
cycle of transmit clock, 28-bits of input LVTTL data are
sampled and transmitted.
.
.
.
.
.
.
.
.
.
Operation -40°C to +85°C
Low Power Consumption
20MHz to 85MHz Shift Clock Support
±1V Common-Mode Range around 1.2V
Narrow Bus Reduces Cable Size and Cost
High Throughput (up to 2.38Gbps)
Internal PLL with No External Component
Compatible with TIA/EIA-644 Specification
56-Lead, TSSOP Package
The FIN3386 receives and converts the 4/3 serial LVDS
data streams back into 28/21 bits of LVTTL data, acting
as the deserializer.
For the FIN3385, at a transmit clock frequency of
85MHz, 28-bits of LVTTL data are transmitted at a rate
of 595Mbps per LVDS channel.
This pair solves EMI and cable size problems
associated with wide and high-speed TTL interfaces.
Ordering Information
Operating
Temperature Range
Packing
Part Number
Package
Method
FIN3385MTDX
FIN3386MTDX
56-Lead Thin-Shrink Small-Outline Package
Tape and Reel
-40 to +85°C
(TSSOP), JEDEC MO-153,6.1mm Wide
© 2003 Fairchild Semiconductor Corporation
FIN3385 / FIN3386 • Rev. 1.0.6
www.fairchildsemi.com
Block Diagrams
Figure 1. FIN3385 Transmitter Functional Diagram
Figure 2. FIN3386 Receiver Functional Diagram
© 2003 Fairchild Semiconductor Corporation
FIN3385 / FIN3386 • Rev. 1.0.6
www.fairchildsemi.com
2
Transmitter Pin Configuration
Figure 3. FIN3385 (28:4 Transmitter) Pin Assignments
Pin Definitions
Pin Names
TxIn
I/O Types
Number of Pins
Description of Signals
I
28/21
1
LVTTL Level Input
TxCLKIn
TxOut+
I
LVTTL Level Clock Input, the rising edge is for data strobe
Positive LVDS Differential Data Output
O
O
O
O
4/3
4/3
1
TxOut-
Negative LVDS Differential Data Output
Positive LVDS Differential Clock Output
Negative LVDS Differential Clock Output
TxCLKOut+
TxCLKOut-
1
Rising Edge Data Strobe: Assert HIGH (VCC
Falling Edge Data Strobe: Assert LOW (Ground)
)
R_FB
I
I
1
1
LVTTL Level Power-Down Input Assertion (LOW) puts the
outputs in High-Impedance state
/PwrDn
PLL VCC
PLL GND
LVDS VCC
LVDS GND
VCC
I
I
I
I
I
I
1
2
1
3
3
5
Power Supply Pin for PLL
Ground Pins for PLL
Power Supply Pin for LVDS Output
Ground Pins for LVDS Output
Power Supply Pins for LVTTL Input
Ground Pin for LVTTL Input
GND
© 2003 Fairchild Semiconductor Corporation
FIN3385 / FIN3386 • Rev. 1.0.6
www.fairchildsemi.com
3
Receiver Pin Configuration
Figure 4. FIN3386 (28:4 Receiver) Pin Assignments
Pin Definitions
Pin Names
RxIn
I/O Types
Number of Pins
Description of Signals
Negative LVDS Differential Data Output
Positive LVDS Differential Data Output
Negative LVDS Differential Data Input
Positive LVDS Differential Clock Input
LVTTL Level Data Output, goes HIGH for /PwrDn LOW
LVTTL Clock Output
I
I
4/3
RxIn+
4/3
RxCLKIn-
RxCLKIn+
RxOut
I
1
I
1
O
O
I
28/21
RxCLKOut-
/PwrDn
1
1
1
2
1
3
4
5
LVTTL Level Input. Refer to Table 2
Power Supply Pin for PLL
PLL VCC
PLL GND
LVDS VCC
LVDS GND
VCC
I
I
Ground Pins for PLL
I
Power Supply Pin for LVDS Input
Ground Pins for LVDS Input
I
I
Power Supply for LVTTL Output
Ground Pins for LVTTL Output
GND
I
© 2003 Fairchild Semiconductor Corporation
FIN3385 / FIN3386 • Rev. 1.0.6
www.fairchildsemi.com
4
Truth Tables
Table 1. Input / Output Truth Table
Inputs
Outputs
TxIn
Active
TxCLKIn
/PwrDn(1)
HIGH
HIGH
HIGH
HIGH
LOW
TxOut±
LOW / HIGH
LOW / HIGH
LOW
TxCLKOut±
LOW / HIGH
Don’t Care(2)
LOW / HIGH
Don’t Care(2)
High Impedance
Active
LOW / HIGH / High Impedance
Active
Active
Floating
Floating
Don’t Care
Floating
LOW
Don’t Care
High Impedance
Notes:
1. The outputs of the transmitter or receiver remain in a high-impedance state until VCC reaches 2V.
2. TxCLKOut± settles at a free-running frequency when the part is powered up, /PwrDn is HIGH, and the TxCLKIn
is a steady logic level (LOW / HIGH / High-Impedance).
Power-Up / Power-Down Operation Truth Tables
The outputs of the transmitter remain in the High-Impedance state until the power supply reaches 2V. Table 2 shows
the operation of the transmitter during power-up and power-down and operation of the /PwrDn pin.
Table 2. Transmitter Power-Up / Power-Down Operation Truth Table
PwrDn
>2V
Normal
>2V
VCC
TxIN
<2V
Don’t Care
High Impedance
Don’t Care
High Impedance
LOW
Don’t Care
High Impedance
Don’t Care
High Impedance
LOW
Active
Active
Active
Active
HIGH
TxOUT
TxCLKIn
TxCLKOut±
/PwrDn
Table 3. Receiver Power-Up / Power-Down Operation Truth Table
/PwrDn
RxIn±
Don’t Care
Don’t Care
Active
LOW/HIGH
Active
Active
Last Valid State
Note 3
Note 3
HIGH
Note 3
High
Impedance
Last Valid
State
RxOut
LOW
RxCLKIn±
RxCLKOut
Don’t Care
Don’t Care
Note 4
Note 3
Note 4
Note 3
High
Impedance
Active
Note 4
Note 4
/PwrDn
VCC
LOW
<2V
LOW
<2V
HIGH
<2V
HIGH
<2V
HIGH
<2V
HIGH
<2V
Notes:
3. If the input is terminated and un-driven (high-impedance) or shorted or open (fail-safe condition).
4. For /PwrDn or fail-safe condition, the RxCLKOut pin goes LOW for panel link devices and HIGH for channel link
devices.
5. Shorted means (± inputs are shorted to each other, or ± inputs are shorted to each other and ground or VCC, or
either ± inputs are shorted to ground or VCC) with no other current/voltage sources (noise) applied. If the VID is still
in the valid range (greater than 100mV) and VCM is in the valid range (0V to 2.4V), the input signal is still
recognized and the part responds normally.
© 2003 Fairchild Semiconductor Corporation
FIN3385 / FIN3386 • Rev. 1.0.6
www.fairchildsemi.com
5
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
Parameter
Min.
-0.3
-0.5
-0.3
Max.
+4.6
+4.6
+4.6
Unit
V
VCC
Power Supply Voltage
VID_TTL TTL/CMOS Input/Output Voltage
VIO_LVDS LVDS Input/Output Voltage
V
V
IOSD
TSTG
TJ
LVDS Output Short-Circuit Current
Storage Temperature Range
Continuous
-65
+150
+150
+260
>10.0
>6.5
°C
°C
°C
Maximum Junction Temperature
Lead Temperature, Soldering, 4 Seconds
TL
I/O to GND
All Pins
kV
V
Human Body Model, JESD22-A114 (1.5k,100pF)
Machine Model, JESD22-A115 (0, 200pF)
ESD
>400
Note:
6. Absolute maximum ratings are DC values beyond which the device may be damaged or have its useful life
impaired. The datasheet specifications should be met, without exception, to ensure that the system design is
reliable over its power supply, temperature, and output/input loading variables.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
VCC
Parameter
Min.
3.0
Max.
3.6
Unit
V
Supply Voltage
TA
Operating Temperature
-40
+85
100
°C
VCCNPP Maximum Supply Noise Voltage(7)
mVPP
Note:
7. 100mV VCC noise should be tested for frequency at least up to 2MHz. All the specifications should be met under
such noise.
© 2003 Fairchild Semiconductor Corporation
FIN3385 / FIN3386 • Rev. 1.0.6
www.fairchildsemi.com
6
Transmitter DC Electrical Characteristics
Typical values are at TA=25°C and with VCC=3.3V; minimum and maximum are at over supply voltages and operating
temperatures ranges, unless otherwise specified.
Symbol
Parameter
Condition
Min.
Typ.
Max.
Unit
Transmitter LVTTL Input Characteristics
VIH
VIL
VIK
Input HIGH Voltage
Input LOW Voltage
Input Clamp Voltage
2.0
VCC
0.8
V
V
V
GND
IIK=-18mA
-0.79
1.8
0
-1.50
10.0
VIN=0.4V to 4.6V
VIN=GND
IIN
Input Current
µA
-10
Transmitter LVDS Output Characteristics(8)
VOD
VOD
VOS
VOS
IOS
Output Differential Voltage
250
450
35
mV
mV
V
VOD Magnitude Change from Differential
LOW-to-HIGH
RL=100, Figure 5
Offset Voltage
1.125
1.250
25
1.375
Offset Magnitude Change from
Differential LOW-to-HIGH
mV
mA
µA
Short-Circuit Output Current
VOUT=0V
-3.5
±1
-5.0
±10
DO=0V to 4.6V,
/PwrDn=0V
IOZ
Disabled Output Leakage Current
Transmitter Supply Current
32.5MHz
31.0
32.0
37.0
42.0
10.0
29.0
30.0
35.0
39.0
49.5
55.0
60.5
66.0
55.0
41.8
44.0
49.5
55.0
40MHz
66MHz
85MHz
28:4 Transmitter Power Supply Current
for Worst-Case Pattern (with Load)(9)
RL=100
ICCWT
mA
µA
Figure 8
ICCPDT Powered-Down Supply Current
/PwrDn=0.8V
Figure 23(10)
32.5MHz
40MHz
66MHz
85MHz
28:4 Transmitter Supply Current for
ICCGT
mA
16 Grayscale(9)
Notes:
8. Positive current values refer to the current flowing into device and negative values refer to current flowing out of
pins. Voltages are referenced to ground unless otherwise specified (except VOD and VOD).
9. The power supply current for both transmitter and receiver can vary with the number of active I/O channels.
10. The 16-grayscale test pattern tests device power consumption for a “typical” LCD display pattern. The test
pattern approximates signal switching needed to produce groups of 16 vertical strips across the display.
© 2003 Fairchild Semiconductor Corporation
FIN3385 / FIN3386 • Rev. 1.0.6
www.fairchildsemi.com
7
Transmitter AC Electrical Characteristics
Typical values are at TA=25°C and with VCC=3.3V; minimum and maximum are at over supply voltages and operating
temperatures ranges, unless otherwise specified.
Symbol
tTCP
Parameter
Condition
Min.
11.76
0.35
Typ.
T
Max.
50.00
0.65
Unit
ns
T
Transmit Clock Period
tTCH
Transmit Clock (TxCLKIn) HIGH Time
Transmit Clock LOW Time
Figure 9
0.50
0.50
tTCL
0.35
0.65
T
(10% to 90%)
Figure 10
tCLKT
TxCLKIn Transition Time (Rising and Falling)
1.0
1.5
6.0
ns
ns
tJIT
tXIT
TxCLKIn Cycle-to-Cycle Jitter
TxIn Transition Time
3.0
6.0
LVDS Transmitter Timing Characteristics
tTLH
tTHL
Differential Output Rise Time (20% to 80%)
Differential Output Fall Time (20% to 80%)
TxIn Setup to TxCLNIn
0.75
0.75
1.50
1.50
ns
ns
ns
ns
ns
Figure 8
tSTC
tHTC
tTPDD
2.5
0
Figure 9
f=85MHz
TxIn Holds to TxCLNIn
Transmitter Power-Down Delay
Figure 14 (11)
100
6.8
(TA=25°C and
with VCC=3.3V)
Figure 13
tTCCD
Transmitter Clock Input to Clock Output Delay
2.8
5.5
ns
Transmitter Output Data Jitter (f=40MHz)(12)
tTPPB0
tTPPB1
tTPPB2
tTPPB3
tTPPB4
tTPPB5
tTPPB6
Transmitter Output Pulse Position of Bit 0
Transmitter Output Pulse Position of Bit 1
Transmitter Output Pulse Position of Bit 2
Transmitter Output Pulse Position of Bit 3
Transmitter Output Pulse Position of Bit 4
Transmitter Output Pulse Position of Bit 5
Transmitter Output Pulse Position of Bit 6
-0.25
0
0.25
ns
ns
ns
ns
ns
ns
ns
a-0.25
a
a+0.25
2a-0.25
3a-0.25
4a-0.25
5a-0.25
6a-0.25
2a
3a
4a
5a
6a
2a+0.25
3a+0.25
4a+0.25
5a+0.25
6a+0.25
Figure 20
1
a
f 7
Transmitter Output Data Jitter (f=65MHz) (12)
tTPPB0
tTPPB1
tTPPB2
tTPPB3
tTPPB4
tTPPB5
tTPPB6
Transmitter Output Pulse Position of Bit 0
Transmitter Output Pulse Position of Bit 1
Transmitter Output Pulse Position of Bit 2
Transmitter Output Pulse Position of Bit 3
Transmitter Output Pulse Position of Bit 4
Transmitter Output Pulse Position of Bit 5
Transmitter Output Pulse Position of Bit 6
-0.2
0
0.2
ns
ns
ns
ns
ns
ns
ns
a-0.2
a
a+0.2
2a-0.2
3a-0.2
4a-0.2
5a-0.2
6a-0.2
2a
3a
4a
5a
6a
2a+0.2
3a+0.2
4a+0.2
5a+0.2
6a+0.2
Figure 20
1
a
f 7
Continued on the following page…
© 2003 Fairchild Semiconductor Corporation
FIN3385 / FIN3386 • Rev. 1.0.6
www.fairchildsemi.com
8
Transmitter AC Electrical Characteristics (Continued)
Over supply voltage and operating temperature ranges, unless otherwise specified.
Symbol
Parameter
Condition
Min.
Typ.
Max.
Unit
Transmitter Output Data Jitter (f=85MHz)(12)
tTPPB0
tTPPB1
tTPPB2
tTPPB3
tTPPB4
tTPPB5
tTPPB6
Transmitter Output Pulse Position of Bit 0
Transmitter Output Pulse Position of Bit 1
Transmitter Output Pulse Position of Bit 2
Transmitter Output Pulse Position of Bit 3
Transmitter Output Pulse Position of Bit 4
Transmitter Output Pulse Position of Bit 5
Transmitter Output Pulse Position of Bit 6
-0.2
0
a
0.2
a+0.2
2a+0.2
3a+0.2
4a+0.2
5a+0.2
6a+0.2
370
ns
ns
ns
ns
ns
ns
ns
a-0.2
2a-0.2
3a-0.2
4a-0.2
5a-0.2
6a-0.2
2a
3a
4a
5a
6a
350
210
110
Figure 20
1
a
f 7
f=40MHz
f=65MHz
f=85MHz
Figure 26(12)
FIN3385 Transmitter Clock Out Jitter,
Cycle-to-Cycle, Figure 20
tJCC
230
ps
150
tTPLLS
Transmitter Phase Lock Loop Set Time(13)
10
ms
Notes:
11. Outputs of all transmitters stay in 3-STATE until power reaches 2V. Clock and data output begins to toggle 10ms
after VCC reaches 3.0V and /PwrDn pin is above 1.5V.
12. This output data pulse position works for both transmitters for TTL inputs, except the LVDS output bit mapping
difference (see Figure 18). Figure 20 shows the skew between the first data bit and clock output. A two-bit cycle
delay is guaranteed when the MSB is output from transmitter.
13. This jitter specification is based on the assumption that PLL has a reference clock with cycle-to-cycle input jitter
of less than 2ns.
© 2003 Fairchild Semiconductor Corporation
FIN3385 / FIN3386 • Rev. 1.0.6
www.fairchildsemi.com
9
Receiver DC Characteristics
Typical values are at TA=25°C and with VCC=3.3V. Minimum and maximum values are over supply voltage and
operating temperature ranges unless otherwise specified. Positive current values refer to the current flowing into
device and negative values refer to current flowing out of pins. Voltages are referenced to ground unless otherwise
specified (except VOD and VOD).
Symbol
Parameter
Condition
Min.
Typ.
Max.
Unit
LVTTL/CMOS DC Characteristics
VIH
VIL
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Input Clamp Voltage
Input Current
2.0
GND
2.7
VCC
0.8
V
V
VOH
VOL
VIK
IIN
IOH=-0.4mA
IOL=2mA
3.3
V
0.06
-0.79
0.30
-1.50
10
V
IIK=-18mA
V
VIN=0V to 4.6V
-10
A
Input/Output Power-Off
Leakage Current
VCC=0V, All LVTTL Inputs / Outputs
0V to 4.6V
IOFF
IOS
±10
A
Output Short-Circuit Current
VOUT=0V
-60
-120
m
Receiver LVDS Input Characteristics
Differential Input Threshold
HIGH
VTH
Figure 6, Table 4
Figure 6, Table 4
100
mV
Differential Input Threshold
LOW
VTL
-100
0.05
mV
V
VICM
IIN
Input Common Mode Range
Figure 6, Table 4
2.35
±10
±10
VIN=2.4V, VCC=3.6V or 0V
VIN=0V, VCC=3.6V or 0V
Input Current
A
Receiver Supply Current
4:28 Receiver Power Supply
32.5MHz
40.0MHz
66.0MHz
70
75
Current for Worst-Case Pattern
with Load(14)
114
135
60
85.0MHz
ICCWR
CL=8pF, Figure 7
mA
3:21 Receiver Power Supply
Current for Worst-Case Pattern
with Load(14)
32.5MHz
40.0MHz
66.0MHz
85.0MHz
49
53
78
90
NA
65
100
115
55
ICCPDT Powered-Down Supply Current /PwrDn=0.8V (RxOut Stays LOW)
A
© 2003 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FIN3385 / FIN3386 • Rev. 1.0.6
10
Receiver AC Characteristics
Typical values are at TA=25°C and with VCC=3.3V; minimum and maximum are at over supply voltages and operating
temperatures ranges, unless otherwise specified.
Symbol
tRCOP
tRCOL
Parameter
Receiver Clock Output (RxCLKOut) Period
RxCLKOut LOW Time
Condition
Min.
11.76
4.0
Typ.
T
Max. Unit
50.00
5.0
5.0
6.0
6.5
ns
ns
ns
ns
Figure 12
Rising Edge Strobe
f=85MHz
tRCOH
tRSRC
tRHRC
tROLH
RxCLKOut HIGH Time
4.5
RxOut Valid Prior to RxCLKOut
RxOut Valid After RxCLKOut
Output Rise Time (20% to 80%)
Output Fall Time (80% to 20%)
3.5
3.5
2.0
1.8
3.5
3.5
CL=8pF, Figure 8
ns
ns
tROHL
Receiver Clock Input to Clock Output
Delay(15)
TA=25°C, VCC=3.3V,
Figure 24
tRCCD
3.5
5.0
7.5
tRPPD
Receiver Power-Down Delay
Figure 17
1.0
1.19
2.87
4.55
6.23
7.91
9.59
11.27
µs
ns
ns
ns
ns
ns
ns
ns
ps
ms
ns
tRSPB0 Receiver Input Strobe Position of Bit 0
tRSPB1 Receiver Input Strobe Position of Bit 1
tRSPB2 Receiver Input Strobe Position of Bit 2
tRSPB3 Receiver Input Strobe Position of Bit 3
tRSPB4 Receiver Input Strobe Position of Bit 4
tRSPB5 Receiver Input Strobe Position of Bit 5
tRSPB6 Receiver Input Strobe Position of Bit 6
0.49
2.17
3.85
5.53
7.21
8.89
10.57
290
0.84
2.52
4.20
5.88
7.56
9.24
10.92
Figure 21
f=85MHz
tRSKM
tRPLLS
tRCOP
tRCOL
tRCOH
tRSRC
tRHRC
tRCOL
tRCOH
tRSRC
tRHRC
tROLH
tROHL
RxIN Skew Margin(16)
Figure 21
Figure 21
Figure 12
Receiver Phase Lock Loop Set Time
Receiver Clock Output (RxCLKOut) Period
RxCLKOut LOW Time
10
T
15
10.0
10.0
6.5
50
11.0
12.2
11.6
11.6
6.3
7.6
7.3
6.3
2.0
1.8
Figure 12
Rising Edge Strobe
f=40MHz
RxCLKOut HIGH Time
ns
RxOUT Valid Prior to RxCLKOut
RxOUT Valid After RxCLKOut
RxCLKOut LOW Time
6.0
5.0
9.0
9.0
Figure 12,
RxCLKOut HIGH Time
5.0
4.5
Rising Edge Strobe(17)
f=66MHz
ns
ns
RxOUT Valid Prior to RxCLKOut
RxOUT Valid After RxCLKOut
Output Rise Time (20% to 80%)
Output Fall Time (20% to 80%)
4.0
5.0
5.0
CL=8pF(17), Figure 12
Receiver Clock Input to Clock Output
Delay(18)
Figure 14, TA=25°C
and VCC=3.3v
tRCCD
3.5
5.0
7.5
ns
µs
tRPDD
Receiver Power-Down Delay
Figure 17
1.0
tRSPB0 Receiver Input Strobe Position of Bit 0
tRSPB1 Receiver Input Strobe Position of Bit 1
tRSPB2 Receiver Input Strobe Position of Bit 2
tRSPB3 Receiver Input Strobe Position of Bit 3
tRSPB4 Receiver Input Strobe Position of Bit 4
tRSPB5 Receiver Input Strobe Position of Bit 5
tRSPB6 Receiver Input Strobe Position of Bit 6
1.00
4.50
8.10
11.6
15.1
18.8
22.5
1.40
5.00
8.50
11.9
15.6
19.2
22.9
2.15
5.80
9.15
12.6
16.3
19.9
23.6
Figure 21, f=40MHz
ns
© 2003 Fairchild Semiconductor Corporation
FIN3385 / FIN3386 • Rev. 1.0.6
www.fairchildsemi.com
11
Receiver AC Characteristics
Typical values are at TA=25°C and with VCC=3.3V; minimum and maximum are at over supply voltages and operating
temperatures ranges, unless otherwise specified.
Symbol
Parameter
Condition
Min.
0.7
Typ.
1.1
Max. Unit
tRSPB0 Receiver Input Strobe Position of Bit 0
tRSPB1 Receiver Input Strobe Position of Bit 1
tRSPB2 Receiver Input Strobe Position of Bit 2
tRSPB3 Receiver Input Strobe Position of Bit 3
tRSPB4 Receiver Input Strobe Position of Bit 4
tRSPB5 Receiver Input Strobe Position of Bit 5
tRSPB6 Receiver Input Strobe Position of Bit 6
1.4
3.6
5.8
2.9
3.3
5.1
5.5
Figure 21, f=66MHz
7.3
7.7
8.0
ns
9.5
9.9
10.2
12.4
14.6
11.7
13.9
490
400
12.1
14.3
f=40MHz, Figure 21
f=66MHz, Figure 21
Figure 15
tRSKM
RxIn Skew Margin(19)
ps
tRPLLS
Receiver Phase Lock Loop Set Time
10.0
ms
Notes:
14. The power supply current for the receiver can vary with the number of I/O channels.
15. Total channel latency from serializer to deserializer is (t + tTCCD) where t is a clock period.
16. Receiver skew margin is defined as the valid sampling window after considering potential setup/hold time and
minimum/maximum bit position.
17. For the receiver with falling-edge strobe, the definition of setup/hold time is slightly different from the one with
rising-edge strobe. The clock reference point is the time when the clock falling edge passes through 2V. For hold
time tRHRC, the clock reference point is the time when falling edge passes through +0.8V.
18. Total channel latency from serializer to deserializer is (t + tCCD) (2•t + tRCCD) where t is the clock period.
19. Receiver skew margin is defined as the valid sampling window after considering potential setup/hold time and
minimum / maximum bit position.
© 2003 Fairchild Semiconductor Corporation
FIN3385 / FIN3386 • Rev. 1.0.6
www.fairchildsemi.com
12
Test Circuits
Figure 5. Differential LVDS Output DC Test Circuit
Notes:
A: For all input pulses, tR or tF<=1ns.
B: CL includes all probe and jig capacitance.
Figure 6. Differential Receiver Voltage Definitions, Propagation Delay, and Transition Time Test Circuit
Table 4. Receiver Minimum and Maximum Input Threshold Test Voltages
Resulting Differential
Input Voltage (mV)
Resulting Common
Mode Input Voltage (V)
Applied Voltages (V)
VIA
1.25
1.15
2.40
2.30
0.10
0
VIB
1.15
1.25
2.30
2.40
0
VID
100
-100
100
-100
100
-100
600
-600
600
-600
600
-600
VICM
1.20
1.20
2.35
2.35
0.05
0.05
1.20
1.20
2.10
2.10
0.30
0.30
0.10
0.90
1.50
1.80
2.40
0
1.50
0.90
2.40
1.80
0.60
0
0.60
© 2003 Fairchild Semiconductor Corporation
FIN3385 / FIN3386 • Rev. 1.0.6
www.fairchildsemi.com
13
AC Loadings and Waveforms
Figure 7. Worst-Case Test Pattern
Note:
20. The worst-case test pattern produces a maximum toggling of digital circuits, LVDS I/O, and LVTTL/CMOS I/O.
Depending on the valid strobe edge of the transmitter, the TxCLKIn can be rising or falling edge data strobe.
Figure 8. Transmitter LVDS Output Load and Transition Times
Figure 9. Transmitter Setup/Hold and HIGH/LOW Times (Rising-Edge Strobe)
Figure 10. Transmitter Input Clock Transition Time
Figure 11. Transmitter Outputs Channel-to-Channel Skew
© 2003 Fairchild Semiconductor Corporation
FIN3385 / FIN3386 • Rev. 1.0.6
www.fairchildsemi.com
14
AC Loadings and Waveforms (Continued)
Figure 12. Receiver Setup/Hold and HIGH/LOW Times
Note:
21. For the receiver with falling-edge strobe, the definition of setup/hold time is slightly different from the one with
rising-edge strobe. The clock reference point is the time when the clock falling edge passes through 2V. For hold
time tRHRC, the clock reference point is the time when falling edge passes through +0.8V.
Figure 13. Transmitter Clock-In to Clock-Out Delay (Rising-Edge Strobe)
Figure 14. Receiver Clock-In to Clock-Out Delay (Falling-Edge Strobe)
Figure 15. Receiver Phase-Lock-Loop Set Time
© 2003 Fairchild Semiconductor Corporation
FIN3385 / FIN3386 • Rev. 1.0.6
www.fairchildsemi.com
15
AC Loadings and Waveforms (Continued)
Figure 16. Transmitter Power-Down Delay
Figure 17. Receiver Power-Down Delay
Figure 18. 28 Parallel LVTTL Inputs Mapped to Four Serial LVDS Outputs
Note:
22. The information in this diagram shows the difference between clock out and the first data bit. A 2-bit cycle delay
is guaranteed when the MSB is output from the transmitter.
Figure 19. 21 Parallel LVTTL Inputs Mapped to Three Serial Outputs
Note:
23. This output date pulse position works for both transmitters with 21 TTL inputs, except the LVDS output bit
mapping difference. Two-bit cycle delay is guaranteed with the MSB is output from transmitter.
© 2003 Fairchild Semiconductor Corporation
FIN3385 / FIN3386 • Rev. 1.0.6
www.fairchildsemi.com
16
AC Loadings and Waveforms (Continued)
Figure 20.Transmitter Output Pulse Bit Position
Figure 21.Receiver Input Bit Position
Figure 22. Receiver LVDS Input Skew Margin
Note:
24. tRSKM is the budget for the cable skew and source clock skew plus Inter-Symbol Interference (ISI).
The minimum and maximum pulse position values are based on the bit position of each of the seven bits within
the LVDS data stream across PVT (Process, Voltage Supply, and Temperature).
© 2003 Fairchild Semiconductor Corporation
FIN3385 / FIN3386 • Rev. 1.0.6
www.fairchildsemi.com
17
AC Loadings and Waveforms (Continued)
Figure 23. Transmitter Clock Out Jitter Measurement Setup
Note:
25. Test setup considers no requirement for separation of RMS and deterministic jitter. Other hardware setups,
such as Wavecrest boxes, can be used if no M1 software is available, but the test methodology in Figure 24
should be followed.
Figure 24. Timing Diagram of Transmitter Clock Input with Jitter
Note:
26. This jitter pattern is used to test the jitter response (clock out) of the device over the power supply range with
worst jitter ±3ns (cycle-to-cycle) clock input. The specific test methodology is as follows:
27. Switching input data TxIn0 to TxIn20 at 0.5MHz and the input clock is shifted to left -3ns and to the right +3ns
when data is HIGH.
28. The ±3ns cycle-to-cycle input jitter is the static phase error between the two clock sources. Jumping between two
clock sources to simulate the worst-case of clock-edge jump (3ns) from graphical controllers. Cycle-to-cycle jitter
at TxCLKOut pin should be measured cross VCC range with 100mV noise (VCC noise frequency <2MHz).
© 2003 Fairchild Semiconductor Corporation
FIN3385 / FIN3386 • Rev. 1.0.6
www.fairchildsemi.com
18
AC Loadings and Waveforms (Continued)
Figure 25. “16-Grayscale” Test Pattern
Note:
29. The 16-grayscale test pattern tests device power consumption for a “typical” LCD display pattern. The test
pattern approximates signal switching needed to produce groups of 16 vertical strips across the display.
Figure 26. Transmitter Phase-Lock-Loop Time
© 2003 Fairchild Semiconductor Corporation
FIN3385 / FIN3386 • Rev. 1.0.6
www.fairchildsemi.com
19
Physical Dimensions
A
56
51
34
29
B
8.10
4.05
0.2
C B A
1
6
23
28
0.30
0.50
0.1 C
-C-
0.50
0.10
A
B
C
0.25
MTD56REV3
Figure 27. 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,6.1mm Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the
warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2003 Fairchild Semiconductor Corporation
FIN3385 / FIN3386 • Rev. 1.0.6
www.fairchildsemi.com
20
© 2003 Fairchild Semiconductor Corporation
FIN3385 / FIN3386 • Rev. 1.0.6
www.fairchildsemi.com
21
相关型号：
FIN424C
20-Bit Ultra-Low-Power Serializer / Deserializer for μController and RGB Displays
FAIRCHILD
FIN425CMLX
20-Bit Ultra-Low-Power Serializer / Deserializer for μController and RGB Displays
FAIRCHILD
©2020 ICPDF网 联系我们和版权申明