FL7930CMX [FAIRCHILD]
Single-Stage Flyback and Boundary-Mode PFC; 单级反激式和边界模式PFC
| 型号： | FL7930CMX |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Single-Stage Flyback and Boundary-Mode PFC |
| 文件： | 总20页 (文件大小：1304K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
March 2011
FL7930
Single-Stage Flyback and Boundary-Mode PFC
Controller for Lighting
Features
Description
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
Additional PFC-Ready Function (FL7930C Only)
The FL7930 is an active Power Factor Correction (PFC)
controller for low-to high-power lumens applications that
operate in Critical Conduction Mode (CRM). It uses a
voltage-mode PWM that compares an internal ramp
signal with the error amplifier output to generate a
MOSFET turn-off signal. Because the voltage-mode
CRM PFC controller does not need rectified AC line
voltage information, it saves the power loss of an input
voltage sensing network necessary for a current-mode
CRM PFC controller.
Input-Voltage-Absent-Detection Circuit
Maximum Switching Frequency Limitation
Internal Soft-Start with Overshoot Prevention
Internal Total Harmonic Distortion (THD) Optimizer
Precise Adjustable Output Over-Voltage Protection
Additional OVP Detection Pin (FL7930B Only)
Open-Feedback Protection and Disable Function
Zero-Current Detector
FL7930 provides over-voltage, open-feedback, over-
current, input-voltage-absent detection, and under-
voltage lockout protections. The FL7930 can be
disabled if the INV pin voltage is lower than 0.45V and
the operating current decreases to a very low level.
Using a new variable on-time control method, THD is
lower than the conventional CRM boost PFC ICs.
150µs Internal Startup Timer
MOSFET Over-Current Protection (OCP)
Under-Voltage Lockout with 3.5V Hysteresis
Low Startup and Operating Current
The FL3930B provides an additional OVP pin that can
be used to shut down the boost power stage when
output voltage exceeds OVP level due to damaged
resistors connected at the INV pin. The FL7930C
provides a PFC-ready pin can be used to trigger other
power stages when PFC output voltage reaches the
proper level (with hysteresis).
Totem-Pole Output with High State Clamp
+500/-800mA Peak Gate Drive Current
8-Pin Small Outline Package (SOP)
Applications
.
.
.
.
Ballast
General LED Lighting
Industrial, Commercial, and Residential Fixtures
Outdoor Lighting: Street, Roadway, Parking,
Construction and Ornamental LED Lighting Fixtures
Ordering Information
Operating
Temperature Range
Packing
Part Number
Top Mark
Package
Method
FL7930BM
FL7930BMX
FL7930CM
FL7930CMX
Rail
FL7930B
Tape & Reel
-40 to +125°C
8-Lead Small Outline Package (SOP)
Rail
FL7930C
Tape & Reel
© 2011 Fairchild Semiconductor Corporation
FL7930 • Rev. 1.0.0
www.fairchildsemi.com
Application Diagrams
Figure 1. Typical Boost PFC Application for FL7930B
FL7930B
1
2
3
4
8
7
6
5
INV
VCC
CF1
CF2
CHF
GATE
OVP
COMP
CS
GND
ZCD
Figure 2. Typical Application of Single-Stage Flyback Converter for FL7930B
DC OUTPUT
VCC
FL7930C
Line Filter
7
4
1
8
5
Out
VCC
CS
ZCD
AC INPUT
INV
3
2
COMP
RDY
PFC
Ready
GND
6
Figure 3. Typical Boost PFC Application for FL7930C
© 2011 Fairchild Semiconductor Corporation
FL7930 • Rev. 1.0.0
www.fairchildsemi.com
2
Internal Block Diagram
Figure 4. Functional Block Diagram for FL7930B
Figure 5. Functional Block Diagram for FL7930C
© 2011 Fairchild Semiconductor Corporation
FL7930 • Rev. 1.0.0
www.fairchildsemi.com
3
Pin Configuration
Figure 6. Pin Configurations (Top View)
Pin Definitions
Pin #
Name
Description
This pin is the inverting input of the error amplifier. The output voltage of the boost PFC
converter should be resistively divided to 2.5V.
1
INV
FL7930B: This pin is used to detect PFC output over-voltage when INV pin information is not
correct.
OVP
RDY
COMP
CS
2
FL7930C: This pin is used to detect PFC output-voltage reaching a pre-determined value.
When output voltage reaches 89% of rated output voltage, this pin is pulled HIGH, which is an
(open-drain) output type.
This pin is the output of the transconductance error amplifier. Components for the output
voltage compensation should be connected between this pin and GND.
3
4
This pin is the input of the over-current protection comparator. The MOSFET current is sensed
using a sensing resistor and the resulting voltage is applied to this pin. An internal RC filter is
included to filter switching noise.
This pin is the input of the zero-current detection block. If the voltage of this pin goes higher
than 1.5V, then goes lower than 1.4V, the MOSFET is turned on.
5
6
ZCD
GND
This pin is used for the ground potential of all the pins. For proper operation, the signal ground
and the power ground should be separated.
This pin is the gate drive output. The peak sourcing and sinking current levels are +500mA
and -800mA, respectively. For proper operation, the stray inductance in the gate driving path
must be minimized.
7
8
OUT
VCC
This is the IC supply pin. IC current and MOSFET drive current are supplied using this pin.
© 2011 Fairchild Semiconductor Corporation
FL7930 • Rev. 1.0.0
www.fairchildsemi.com
4
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
VCC
Parameter
Min.
Max.
VZ
Unit
V
Supply Voltage
IOH, IOL
ICLAMP
IDET
Peak Drive Output Current
-800
-10
+500
+10
+10
8.0
mA
mA
mA
Driver Output Clamping Diodes VO>VCC or VO<-0.3V
Detector Clamping Diodes
Error Amplifier Input, Output, OVP Input, ZCD, RDY, and OVP Pins(1)
CS Input Voltage(2)
-10
-0.3
-10
VIN
V
6
TJ
TA
Operating Junction Temperature
+150
+125
+150
2.5
°C
°C
°C
Operating Temperature Range
-40
-65
TSTG
Storage Temperature Range
Human Body Model, JESD22-A114
Charged Device Model, JESD22-C101
Electrostatic Discharge
Capability
ESD
KV
2.0
Notes:
1. When this pin is supplied by external power sources by accident, its maximum allowable current is 50mA.
2. In case of DC input, acceptable input range is -0.3V~6V: within 100ns -10V~6V is acceptable, but electrical
specifications are not guaranteed during such a short time.
Thermal Impedance
Symbol
Parameter
Min.
Max.
Unit
Thermal Resistance, Junction-to-Ambient(3)
150
°C/W
JA
Note:
3. Regarding the test environment and PCB type, please refer to JESD51-2 and JESD51-10.
© 2011 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FL7930 • Rev. 1.0.0
5
Electrical Characteristics
VCC = 14V, TA = -40°C to +125°C, unless otherwise specified.
Symbol
VCC Section
VSTART
VSTOP
Parameter
Condition
Min.
Typ.
Max.
Unit
Start Threshold Voltage
Stop Threshold Voltage
UVLO Hysteresis
VCC Increasing
VCC Decreasing
11
7.5
3.0
20
12
8.5
3.5
22
13
9.5
4.0
24
V
V
V
V
V
HYUVLO
VZ
Zener Voltage
ICC=20mA
VOP
Recommended Operating Range
13
20
Supply Current Section
ISTART Startup Supply Current
IOP Operating Supply Current
VCC=VSTART-0.2V
120
1.5
2.5
160
190
3.0
4.0
230
µA
mA
mA
µA
Output Not Switching
IDOP
Dynamic Operating Supply Current 50kHZ, CI=1nF
Operating Current at Disable VINV=0V
IOPDIS
90
Error Amplifier Section
VREF1
VREF1
VREF2
IEA,BS
IEAS,SR
IEAS,SK
VEAH
Voltage Feedback Input Threshold1 TA=25°C
2.465
2.500
0.1
2.535
10.0
V
mV
mV
µA
µA
µA
V
Line Regulation
VCC=14V~20V
(4)
Temperature Stability of VREF1
Input Bias Current
20
VINV=1V~4V
-0.5
0.5
Output Source Current
Output Sink Current
VINV=VREF -0.1V
VINV=VREF +0.1V
VINV=1V, VCS=0V
-12
12
Output Upper Clamp Voltage
6.0
0.9
90
6.5
1.0
115
7.0
1.1
140
VEAZ
Zero Duty Cycle Output Voltage
Transconductance(4)
V
gm
µmho
Maximum On-Time Section
tON,MAX1
Maximum On-Time Programming 1 TA=25°C, VZCD=1V
35.5
11.2
41.5
13.0
47.5
14.8
µs
µs
TA=25°C,
tON,MAX2
Maximum On-Time Programming 2
I
ZCD=0.469mA
Current-Sense Section
Current-Sense Input Threshold
Voltage Limit
VCS
ICS,BS
tCS,D
0.7
0.8
-0.1
350
0.9
1.0
500
V
Input Bias Current
VCS=0V~1V
-1.0
µA
ns
dV/dt=1V/100ns, from
0V to 5V
Current-Sense Delay to Output(4)
Continued on the following page…
© 2011 Fairchild Semiconductor Corporation
FL7930 • Rev. 1.0.0
www.fairchildsemi.com
6
Electrical Characteristics
VCC = 14V, TA = -40°C to +125°C, unless otherwise specified.
Symbol
Parameter
Condition
Min.
Typ. Max.
Unit
Zero-Current Detect Section
VZCD
Input Voltage Threshold(4)
1.35
0.05
5.5
0
1.50
0.10
6.2
1.65
0.15
7.5
1.00
1.0
-4
V
V
HYZCD Detect Hysteresis(4)
VCLAMPH Input High Clamp Voltage
VCLAMPL Input Low Clamp Voltage
IZCD,BS Input Bias Current
IZCD,SR Source Current Capability(4)
IZCD,SK Sink Current Capability(4)
IDET=3mA
V
IDET= -3mA
VZCD=1V~5V
TA=25°C
0.65
-0.1
V
-1.0
µA
mA
mA
TA=25°C
10
Maximum Delay From ZCD to Output
Turn-On(4)
dV/dt=-1V/100ns,
5V to 0V
tZCD,D
100
9.2
200
ns
Output Section
VOH
VOL
Output Voltage High
IO=-100mA, TA=25°C
IO=200mA, TA=25°C
CIN=1nF
11.0
1.0
50
12.8
2.5
100
100
14.5
1
V
V
Output Voltage Low
Rising Time(4)
Falling Time(4)
tRISE
tFALL
ns
ns
V
CIN=1nF
50
VO,MAX Maximum Output Voltage
VCC=20V, IO=100µA
VCC=5V, IO=100µA
11.5
13.0
VO,UVLO Output Voltage with UVLO Activated
V
Restart / Maximum Switching Frequency Limit Section
tRST
fMAX
Restart Timer Delay
Maximum Switching Frequency(4)
50
150
300
300
350
µs
250
kHz
RDY Pin (FL7930C Only)
IRDY,SK Output Sink Current
VRDY,SAT Output Saturation Voltage
IRDY,LK Output Leakage Current
Soft-Start Timer Section
1
2
4
500
1
mA
mV
µA
IRDY,SK = 2mA
320
Output High Impedance
tSS
Internal Soft-Soft(4)
3
5
7
ms
Protections
VOVP,INV OVP Threshold Voltage at INV Pin
HYOVP,INV OVP Hysteresis at INV Pin
TA=25°C
TA=25°C
2.620
0.120
2.675
0.175
2.730
0.230
V
V
OVP Threshold Voltage at OVP Pin
(FL7930B Only)
VOVP,OVP
TA=25°C
TA=25°C
2.740
2.845
0.345
2.960
V
V
OVP Hysteresis at OVP Pin
HYOVP,OVP
(FL7930B Only)
VEN
HYEN
TSD
Enable Threshold Voltage
Enable Hysteresis
Thermal Shutdown Temperature(4)
Hysteresis Temperature of TSD(4)
0.40
0.05
125
0.45
0.10
140
60
0.50
0.15
155
V
V
°C
°C
THYS
Note:
4. These parameters, although guaranteed by design, are not production tested.
© 2011 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FL7930 • Rev. 1.0.0
7
Comparison of FL6961, FL7930B, and FL7930C
Function
FL6961
FL7930B
FL7930C
Advantages
.
.
No External Circuit for Additional OVP
OVP Pin
None
Integrated
None
Reduced Power Loss and BOM Cost Due to
Additional OVP Circuit
.
.
No External Circuit for PFC Output UVLO
Reduced Power Loss and BOM Cost Due to
PFC Out UVLO Circuit
PFC Ready Pin
Frequency Limit
None
None
Integrated
.
.
.
Versatile Open-Drain Pin
Abnormal CCM Operation Prohibited
None
None
None
None
Integrated
Integrated
Integrated
Integrated
Integrated
Integrated
Integrated
Integrated
Abnormal Inductor Current Accumulation Can
Be Prohibited
.
.
Increased System Reliability with AC On-Off
Test
AC Absent
Detection
Guaranteed Stable Operation at Short Electric
Power Failure
.
.
Reduced Voltage and Current Stress at Startup
Soft-Start and
Startup without
Overshoot
Eliminates Audible Noise due to Unwanted
OVP Triggering
.
.
Can Avoid Burst Operation at Light Load and
High Input Voltage
Control Range
Compensation
Reduced Probability of Audible Noise Due to
the Burst Operation
.
.
.
No External Resistor is Needed
THD Optimizer
TSD
External
None
Internal
Internal
Stable and Reliable TSD Operation
Converter Temperature Range Limited Range
Integrated
Integrated
Comparison of FL7930B and FL7930C
Function
RDY Pin
OVP Pin
FL7930B
None
FL7930C
Integrated
None
Remark
.
User Choice for the Use of Pin #2
FL7930B : OVP
FL7930C : RDY
Integrated
Control Range
Compensation
Integrated
Integrated
© 2011 Fairchild Semiconductor Corporation
FL7930 • Rev. 1.0.0
www.fairchildsemi.com
8
Typical Performance Characteristics
Figure 7. Voltage Feedback Input Threshold 1 (VREF1
vs. TA
)
Figure 8. Start Threshold Voltage (VSTART) vs. TA
Figure 9. Stop Threshold Voltage (VSTOP) vs. TA
Figure 10. Startup Supply Current (ISTART) vs. TA
Figure 11. Operating Supply Current (IOP) vs. TA
Figure 12. Output Upper Clamp Voltage (VEAH) vs. TA
© 2011 Fairchild Semiconductor Corporation
FL7930 • Rev. 1.0.0
www.fairchildsemi.com
9
Typical Performance Characteristics
Figure 13. Zero Duty Cycle Output Voltage (VEAZ
)
Figure 14. Maximum On-Time Program 1 (tON,MAX1
vs. TA
)
vs. TA
Figure 15. Maximum On-Time Program 2 (tON,MAX2
vs. TA
)
Figure 16. Current Sense Input Threshold Voltage Limit
(VCS) vs. TA
Figure 17. Input High Clamp Voltage (VCLAMPH) vs. TA Figure 18. Input Low Clamp Voltage (VCLAMPL) vs. TA
© 2011 Fairchild Semiconductor Corporation
FL7930 • Rev. 1.0.0
www.fairchildsemi.com
10
Typical Performance Characteristics
Figure 19. Output Voltage High (VOH) vs. TA
Figure 20. Output Voltage Low (VOL) vs. TA
Figure 22. OVP Threshold at OVP Pin (VOVP,OVP) vs. TA
Figure 24. OVP Threshold Voltage (VOVP) vs. TA
Figure 21. Restart Timer Delay (tRST) vs. TA
Figure 23. Output Saturation Voltage (VRDY,SAT) vs. TA
© 2011 Fairchild Semiconductor Corporation
FL7930 • Rev. 1.0.0
www.fairchildsemi.com
11
Applications Information
1. Startup: Normally, supply voltage (VCC) of a PFC
block is fed from the additional power supply, which can
be called standby power. Without this standby power,
auxiliary winding for zero current detection can be used
as a supply source. Once the supply voltage of the PFC
block exceeds 12V, internal operation is enabled until
the voltage drops to 8.5V. If VCC exceeds VZ, 20mA
current is sinking from VCC
.
Figure 26. Circuit Around INV Pin
Figure 25. Startup Circuit
2. INV Block: Scaled-down voltage from the output is
the input for the INV pin. Many functions are embedded
based on the INV pin: transconductance amplifier,
output OVP comparator, and disable comparator.
For the output voltage control, a transconductance
amplifier is used instead of the conventional voltage
amplifier. The transconductance amplifier (voltage-
controlled current source) aids the implementation of
OVP and disable functions. The output current of the
amplifier changes according to the voltage difference of
the inverting and non-inverting input of the amplifier. To
cancel down the line input voltage effect on power factor
correction, effective control response of PFC block
should be slower than the line frequency. This conflicts
with the transient response of controller. Two-pole one-
zero type compensation may be used to meet both
requirements.
Figure 27. Timing Chart for INV Block
3. OVP Pin: Over-Voltage Protection (OVP) is
embedded by the information at the INV pin. That
information comes from the output through the voltage
dividing resistors. To scale down from high voltage to
low voltage, high resistance normally replaced with low
resistance. If the resistor of high resistance is damaged
and resistance is changed to high, INV pin information is
normal, but output voltage exceeds its rated output.
Once this occurs, output electrolytic capacitor may be
damaged. The FL3930B provides an additional OVP pin
that can be used to shut down the boost power stage
when output voltage exceeds the OVP level if the
resistors connected at the INV pin are damaged. To
prevent such a catastrophe, an additional OVP pin is
assigned to double check output voltage. The additional
OVP may be called second OVP, while INV pin OVP
can be called the first OVP. Since the two OVP
conditions are quite different, the protection recovery
modes are different.
The OVP comparator shuts down the output drive block
when the voltage of the INV pin is higher than 2.675V
with 0.175V hysteresis. The disable comparator
disables operation when the voltage of the inverting
input is lower than 0.35V with 100mV hysteresis. An
external small-signal MOSFET can be used to disable
the IC. The IC operating current decreases to reduce
power consumption if the IC is disabled. Figure 27 is the
timing chart of the internal circuit near the INV pin when
rated-PFC output voltage is assumed at 390VDC and
VCC supply voltage is 15V.
© 2011 Fairchild Semiconductor Corporation
FL7930 • Rev. 1.0.0
www.fairchildsemi.com
12
Once the first OVP triggers, switching stops immediately
and recovers switching when the output voltage is
decreased with a hysteresis. When the second OVP
triggers, switching can be recovered only when the VCC
supply voltage falls below VSTOP and builds up higher
than VSTART again and VOVP is lower than hysteresis. If
the second OVP is not used, the OVP pin must be
connected to the INV pin or to ground.
Figure 30. Two Cases of RDY Triggered LOW
5. Control Range Compensation: On time is controlled
by the output voltage compensator. When input voltage
is high and load is light, the control range becomes
narrow compared to when input voltage is low. That
control range decrease is anti-proportional to the double
square of the input voltage. Thus, at high line, unwanted
burst operation can occur at light load and audible noise
may be generated from the boost inductor or inductor at
input filter. Unlike other converters, burst operation in
PFC block is not needed because the PFC block itself is
normally disabled in Standby Mode. To reduce
unwanted burst operation at light load, internal control
range compensation is implemented and no burst
operation occurs until 5% load at high line.
Figure 28. Comparison of First and Second OVP
Recovery Modes
4. RDY Output: The FL7930C provides a PFC-ready
pin that can be used to trigger other power stages when
PFC output voltage reaches the proper level with
hysteresis. When the INV voltage is higher than 2.24V,
RDY out is triggered HIGH and lasts until the INV
voltage is lower than 2.051V. When input AC voltage is
quite high, for example 240VAC, PFC output voltage is
always higher than RDY threshold, regardless of boost
converter operation. In this case, the INV voltage is
already higher than 2.24V before PFC VCC touches
6. Zero-Current Detection: Zero-Current Detection
(ZCD) generates the turn-on signal of the MOSFET
when the boost inductor current reaches zero using an
auxiliary winding coupled with the inductor. When the
power switch turns on, negative voltage is induced at the
auxiliary winding due to the opposite winding direction
(see Equation 1) and positive voltage is induced (see
Equation 2) when the power switch turns off.
T
AUX
V
V
AC
AUX
(1)
(2)
T
VSTART. After boost converter operation stops, RDY is
IND
not pulled LOW because the INV voltage is higher than
the RDY threshold. When VCC of the PFC drops below
5V, RDY is pulled LOW even through PFC output
voltage is higher than threshold. The RDY pin output is
open-drain, so needs an external pull-up resistor to
supply the proper power source. The RDY pin output
remains floating until VCC is higher than 2V.
T
AUX
V
V
V
AUX
PFCOUT
AC
T
IND
where VAUX is the auxiliary winding voltage; TIND and
TAUX are boost inductor turns and auxiliary winding
turns, respectively; VAC is input voltage for PFC
converter; and VOUT_PFC is output voltage from the
PFC converter.
Figure 29. Two Cases of RDY Triggered HIGH
Figure 31. Circuit Near ZCD
© 2011 Fairchild Semiconductor Corporation
FL7930 • Rev. 1.0.0
www.fairchildsemi.com
13
Because auxiliary winding voltage can swing from
negative voltage to positive voltage, the internal block in
the ZCD pin has both positive and negative voltage
clamping circuits. When the auxiliary voltage is
negative, an internal circuit clamps the negative voltage
at the ZCD pin around 0.65V by sourcing current to the
serial resistor between the ZCD pin and the auxiliary
winding. When the auxiliary voltage is higher than 6.5V,
current is sinked through a resistor from the auxiliary
winding to the ZCD pin.
When no ZCD signal is available, the PFC controller
cannot turn on the MOSFET, so the controller checks
every switching off time and forces MOSFET turn on
when the off time is longer than 150μs. This is called
restart timer. The restart timer triggers MOSFET turn-on
at startup and may be used at the input voltage-zero
cross period.
150s
Figure 32. Auxiliary Voltage Depends
on MOSFET Switching
Figure 34. Restart Timer at Startup
To check the boost inductor current zero instance,
auxiliary winding voltage is used. When boost inductor
current becomes zero, there is a resonance between
boost inductor and all capacitors at MOSFET drain pin,
including COSS of the MOSFET; an external capacitor at
the D-S pin to reduce the voltage rising and falling slope
of the MOSFET; a parasitic capacitor at inductor; and so
on to improve performance. Resonated voltage is
reflected to the auxiliary winding and can be used for
detecting zero current of boost inductor and valley
position of MOSFET voltage stress. For valley detection,
a minor delay by the resistor and capacitor is needed. A
capacitor increases the noise immunity at the ZCD pin.
If ZCD voltage is higher than 1.5V, an internal ZCD
comparator output becomes HIGH and LOW when the
ZCD goes below 1.4V. At the falling edge of comparator
output, internal logic turns on the MOSFET.
Because the MOSFET turn on depends on the ZCD
input, switching frequency may increase to higher than
several megahertz due to mis-triggering or noise on the
nearby ZCD pin. If the switching frequency is higher
than needed for critical conduction mode (CRM),
operation mode shifts to continuous conduction mode
(CCM). In CCM, unlike CRM where the boost inductor
current is reset to zero at the next switch on; inductor
current builds up at every switching cycle and can be
raised to high current that exceeds the current rating of
the power switch or diode. This can seriously damage
the power switch and result in burn down. To avoid this,
maximum switching frequency limitation is embedded. If
ZCD signal is applied again within 3.3μs after the
previous rising edge of the gate signal, this signal is
ignored internally and FL7930 waits for another ZCD
signal. This slightly degrades the power factor
performance at light load and high input voltage.
Figure 35. Maximum Switching Frequency
Limit Operation
7. Control: The scaled output is compared with the
internal reference voltage and sinking or sourcing
current is generated from the COMP pin by the
transconductance amplifier. The error amplifier output is
compared with the internal sawtooth waveform to give
proper turn-on time based on the controller.
Figure 33. Auxiliary Voltage Threshold
© 2011 Fairchild Semiconductor Corporation
FL7930 • Rev. 1.0.0
www.fairchildsemi.com
14
Figure 38. Compensators Gain Curve
For the transconductance error amplifier side, gain
changes based on differential input. When the error is
large, gain is large to force the output dip or peak to
suppress quickly. When the error is small, low gain is
used to improve power factor performance.
Figure 36. Control Circuit
Unlike a conventional voltage-mode PWM controller,
FL7930 turns on the MOSFET at the falling edge of
ZCD signal. On instance is decided by the external
signal and the turn-on time lasts until the error amplifier
output (VCOMP) and sawtooth waveform meet. When
load is heavy, output voltage decreases, scaled output
decreases, COMP voltage increases to compensate low
output, turn-on time lengthens to give more inductor
turn-on time, and increased inductor current raises the
output voltage. This is how PFC negative feedback
controller regulates output.
250mho
115mho
The maximum of VCOMP is limited to 6.5V, which dictates
the maximum turn-on time, and switching stops when
VCOMP is lower than 1.0V.
Figure 39. Gain Characteristic
8. Soft-Start: When VCC reaches VSTART, an internal
reference voltage is increased like a stair step for 5ms.
As a result, VCOMP is also raised gradually and MOSFET
turn-on time increases smoothly. This reduces voltage
and current stress on the power switch during startup.
0.155 V / s
VCC
VSTART=12V
Figure 37. Turn-On Time Determination
SS
VREFEND=2.5V
VREF
5ms
The roles of PFC controller are regulating output voltage
and input current shaping to increase power factor. Duty
control based on the output voltage should be fast
enough to compensate output voltage dip or overshoot.
For the power factor, however, the control loop must not
react to the fluctuating AC input voltage. These two
requirements conflict; therefore, when designing a
feedback loop, the feedback loop should be least ten
times slower than AC line frequency. That slow
response is made by C1 at compensator. R1 makes
gain boost around operation region and C2 attenuates
gain at higher frequency. Boost gain by R1 helps raise
the response time and improves phase margin.
VINV=0.4V
gM
COMP
(VREFSS-VINV
)
gM=ISOURCE
COMP
ISOURCE
COMP
VCOMP
ISOURCE
RCOMP=VCOMP
FL7930 Rev.00
t
Figure 40. Soft-Start Sequence
© 2011 Fairchild Semiconductor Corporation
FL7930 • Rev. 1.0.0
www.fairchildsemi.com
15
9. Startup without Overshoot: Feedback control
speed of PFC is quite slow. Due to the slow response,
there is a gap between output voltage and feedback
control. That is why over-voltage protection (OVP) is
critical at the PFC controller and voltage dip caused by
fast load changes from light to heavy is diminished by a
bulk capacitor. OVP is easily triggered during startup
phase. Operation on and off by OVP at startup may
cause audible noise and can increase voltage stress at
startup, which is normally higher than in normal
operation. This operation is better when soft-start time is
very long; however, too much startup time enlarges the
output voltage building time at light load. FL7930 has
less overshoot prevention at startup. During startup, the
feedback loop is controlled by an internal proportional
gain controller. When the output voltage reaches the
rated value, it switches to an external compensator after
a
transition time of 30ms. In short, an internal
proportional gain controller eliminates overshoot at
startup and an external conventional compensator takes
over successfully afterward.
Figure 42. Input and Output Current Near Input
Voltage Peak
Figure 41. Startup with Overshoot Prevention
10. THD Optimization: Total Harmonic Distortion (THD)
is the factor that dictates how closely the input current
shape matches sinusoidal form. The turn-on time of the
PFC controller is almost constant over one AC line
period due to the extremely low feedback control
response. The turn-off time is determined by the current
decrease slope of the boost inductor made by the input
voltage and output voltage. Once inductor current
becomes zero, resonance between COSS and the boost
inductor makes oscillating waveforms at the drain pin
and auxiliary winding. By checking the auxiliary winding
voltage through the ZCD pin, the controller can check
the zero current of the boost inductor. At the same time,
a minor delay is inserted to determine the valley position
of drain voltage. The input and output voltage difference
is at its maximum at the zero-cross point of the AC input
voltage. The current decrease slope is steep near the
zero-cross region and more negative inductor current
flows during a drain voltage valley-detection time. Such
a negative inductor current cancels down the positive
current flows and input current becomes zero, called
“zero-cross distortion” in PFC.
Figure 43. Input and Output Current Near Input
Voltage Peak Zero Cross
To improve this, lengthened turn-on time near the zero-
cross region is a well-known technique, though the
method may be different from company to company and
may be proprietary. FL7930 accomplishes this by
sourcing current through the ZCD pin. Auxiliary winding
voltage becomes negative when the MOSFET turns on
and is proportional to input voltage. The negative
clamping circuit of ZCD outputs the current to maintain
the ZCD voltage at a fixed value. The sourcing current
from the ZCD is directly proportional to the input
voltage. Some portion of this current is applied to the
internal sawtooth generator, together with a fixed-
current source. Theoretically, the fixed-current source
and the capacitor at sawtooth generator decide the
maximum turn-on time when no current is sourcing at
ZCD clamp circuit and available turn-on time gets
shorter proportional to the ZCD sourcing current.
© 2011 Fairchild Semiconductor Corporation
FL7930 • Rev. 1.0.0
www.fairchildsemi.com
16
does not exist, soft-start is reset and waits until AC input
is live again. Soft-start manages the turn-on time for
smooth operation when it detects AC input is applied,
which applies less voltage and current stress on startup.
Figure 44. Circuit of THD Optimizer
Figure 46. Operation without Input Voltage
Absent Circuit
Figure 45. Effect of THD Optimizer
By THD optimizer, turn-on time over one AC line period
is proportionally changed, depending on input voltage.
Near the zero cross, lengthened turn-on time improves
THD performance.
11. Input Voltage Absent Detection: To save power
loss caused by input voltage-sensing resistors and to
optimize THD, FL7930 omits AC input voltage detection.
Therefore, no information about AC input is available
from the internal controller. In many cases, the VCC of
PFC controller is supplied by an independent power
source, like standby power. In this scheme, some
mismatch may exist. For example, when the electric
power is suddenly interrupted during two or three AC
line periods; VCC is still alive during that time, but output
voltage drops because there is no input power source.
Consequently, the control loop tries to compensate for
the output voltage drop and VCOMP reaches its
maximum. This lasts until AC input voltage is live again.
When AC input voltage is live again, high VCOMP allows
high switching current and more stress is put on the
MOSFET and diode. To protect against this, FL7930
internally checks if the input AC voltage exists. If input
Figure 47. Operation with Input Voltage
Absent Circuit
© 2011 Fairchild Semiconductor Corporation
FL7930 • Rev. 1.0.0
www.fairchildsemi.com
17
12. Current Sense: The MOSFET current is sensed
using an external sensing resistor for the over-current
protection. If the CS pin voltage is higher than 0.8V, the
.
.
.
ZCD path is recommended close to auxiliary
winding from boost inductor and to the ZCD pin. If
that is difficult, place a small capacitor (below 50pF)
to reduce noise.
over-current protection comparator generates
a
protection signal. An internal RC filter of 40kΩ and 8pF
is included to filter switching noise.
Switching current-sense path should not share with
any other path to avoid interference. Some
additional components may be needed to reduce
the noise level applied to the CS pin.
13. Gate Driver Output: FL7930 contains a single
totem-pole output stage designed for a direct drive of
the power MOSFET. The drive output is capable of up
to +500/-800mA peak current with a typical rise and fall
time of 50ns with 1nF load. The output voltage is
clamped to 13V to protect the MOSFET gate even if the
VCC voltage is higher than 13V.
A stabilizing capacitor for VCC is recommended as
close as possible to the VCC and ground pins. If it is
difficult, place the SMD capacitor as close to the
corresponding pins as possible.
14. PCB Layout
PFC block normally handles high switching current and
the voltage low-energy signal path can be affected by
the high-energy path. Cautious PCB layout is mandatory
for stable operation.
.
The gate drive path should be as short as possible.
The closed-loop that starts from the gate driver,
MOSFET gate, and MOSFET source to ground of
PFC controller is recommended as close as
possible. This is also the crossing point between
power ground and signal ground. Power ground
path from the bridge diode to the output bulk
capacitor should be short and wide. The sharing
position between power ground and signal ground
should be only at one position to avoid ground loop
noise. Signal path of PFC controller should be short
and wide for external components to contact.
.
PFC output voltage sensing resistor is normally
high to reduce current consumption. This path can
be affected by external noise. To reduce noise
possibility at the INV pin, a shorter path for output
sensing is recommended. If a shorter path is not
possible, place some dividing resistors between
PFC output and the INV pin — closer to the INV pin
is better. Relative high voltage close to the INV pin
can be helpful.
Figure 48. Recommended PCB Layout
© 2011 Fairchild Semiconductor Corporation
FL7930 • Rev. 1.0.0
www.fairchildsemi.com
18
Physical Dimensions
5.00
A
4.80
0.65
3.81
8
5
B
1.75
6.20
5.80
4.00
3.80
5.60
1
4
PIN ONE
INDICATOR
1.27
1.27
(0.33)
0.25
C B A
LAND PATTERN RECOMMENDATION
SEE DETAIL A
0.25
0.10
0.25
0.19
C
1.75 MAX
0.51
0.33
0.10 C
x 45°
OPTION A - BEVEL EDGE
0.50
0.25
R0.10
R0.10
GAGE PLANE
OPTION B - NO BEVEL EDGE
0.36
NOTES: UNLESS OTHERWISE SPECIFIED
8°
0°
0.90
0.40
A) THIS PACKAGE CONFORMS TO JEDEC
MS-012, VARIATION AA, ISSUE C,
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
FLASH OR BURRS.
SEATING PLANE
(1.04)
D) LANDPATTERN STANDARD: SOIC127P600X175-8M.
E) DRAWING FILENAME: M08AREV13
DETAIL A
SCALE: 2:1
Figure 49. 8-Lead Small Outline Package (SOP)
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the
warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2011 Fairchild Semiconductor Corporation
FL7930 • Rev. 1.0.0
www.fairchildsemi.com
19
© 2011 Fairchild Semiconductor Corporation
FL7930 • Rev. 1.0.0
www.fairchildsemi.com
20
相关型号：
©2020 ICPDF网 联系我们和版权申明