FOD0738 [FAIRCHILD]
Single/Dual Channel CMOS Optocoupler; 单/双通道CMOS光电耦合器型号: | FOD0738 |
厂家: | FAIRCHILD SEMICONDUCTOR |
描述: | Single/Dual Channel CMOS Optocoupler |
文件: | 总11页 (文件大小:540K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
April 2006
FOD0708 Single Channel CMOS Optocoupler
FOD0738 Dual Channel CMOS Optocoupler
Features
General Description
■ +5 V CMOS compatibility
The FOD0708 and FOD0738 optocouplers consist of an
AlGaAs LED optically coupled to a high speed trans-
impedance amplifier and voltage comparator. These
optocouplers utilize the latest CMOS IC technology to
achieve outstanding performance with very low power
consumption. The devices are housed in a compact
8-pin SOIC package for optimum mounting density.
■ 15 ns typical pulse width distortion
■ 30 ns max. pulse width distortion
■ 40 ns max. propagation delay skew
■ High speed: 15 MBd
■ 60 ns max. propagation delay
■ 10 kV/µs minimum common mode rejection
■ –40°C to 100°C temperature range
■ UL approved (file #E90700)
Applications
■ Line receivers
■ Pulse transformer replacement
■ Output interface to CMOS-LSTTL-TTL
■ Wide bandwidth analog coupling
Package Dimensions
0.164 (4.16)
0.144 (3.66)
Pin 1
0.202 (5.13)
0.182 (4.63)
0.019 (0.48)
0.010 (0.25)
0.006 (0.16)
0.143 (3.63)
0.123 (3.13)
0.244 (6.19)
0.224 (5.69)
0.008 (0.20)
0.003 (0.08)
0.021 (0.53)
0.011 (0.28)
0.050 (1.27)
TYP
Lead Coplanarity : 0.004 (0.10) MAX
NC
1
2
8
7
V
1
2
8
7
ANODE 1
V
V
DD
DD
TRUTH TABLE
LED
V
OUTPUT
O
ANODE
NC
1
CATHODE 1
O
O
OFF
ON
H
L
Note: A 0.1µF bypass capacitor
must be connected between
pins 5 and 8.
3
4
6
5
CATHODE
NC
V
O
3
4
6
5
CATHODE 2
ANODE 2
V
2
GND
GND
FOD0708
FOD0738
©2005 Fairchild Semiconductor Corporation
1
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FOD0708 Single Channel CMOS Optocoupler Rev. 1.0.7
Absolute Maximum Ratings T = 25°C unless otherwise noted
A
Symbol
Parameter
Min.
–40
–40
0
Max.
+125
+100
6
Units
°C
T
Storage Temperature
S
T
Ambient Operating Temperature
Supply Voltages
°C
A
V
Volts
Volts
mA
DD
V
Output Voltage
–0.5
V
+ 0.5
O
DD
I
I
Average Output Current
Average Forward Input Current
Lead Solder Temperature
Solder Reflow Temperature Profile
2
O
20
mA
F
260°C for 10 sec., 1.6 mm below seating plane
See Solder Reflow Temperature Profile Section
LED Power Dissipation
Single Channel
40 mW (derate above 95°C, 1.4 mW/°C)
Dual Channel
40 mW per channel (derate above 90°C, 1.2 mW/°C)
Detector Power Dissipation
Single Channel
85 mW (derate above 75°C, 1.8 mW/°C)
Dual Channel
65 mW per channel (derate above 90°C, 2.0 mW/°C)
Recommended Operating Conditions
Symbol
Parameter
Ambient Operating Temperature
Supply Voltages
Min.
–40
4.5
Max.
+100
5.5
Units
°C
T
A
V
Volts
mA
DD
I
Input Current (ON)
10
16
F
Electrical Characteristics (T = –40°C to +100°C) and 4.5 V ≤ V ≤ 5.5 V
A
DD
Test
Symbol
Parameter
Conditions
Min. Typ.* Max. Units Fig.
V
Input Forward Voltage
I = 12 mA
1.3
5
1.45
1.8
V
V
V
V
9
F
F
BV
Input Reverse Breakdown Voltage
Logic High Output Voltage
Logic Low Output Voltage
I
= 10 µA
R
OH
OL
R
V
V
I = 0, I = –20 µA
4.0
5.0
F
O
I = 12 mA,
0.01
0.1
F
I
= 20 µA
O
I
I
I
Input Threshold Current
(FOD0708)
(FOD0738)
I
= 20 µA
4.0
4.4
8.2
8.2
mA
mA
mA
1,5
3,7
4,8
TH
OL
Logic Low Output Supply Current (FOD0708) I = 12 mA
3.4
6.9
14.0
18.0
DDL
DDH
F
(FOD0738)
Logic High Output Supply Current (FOD0708) I = 0
3.7
7.5
11.0
15.0
F
(FOD0738)
*All typicals at T = 25°C and V = 5V unless otherwise noted.
A
DD
2
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FOD0708/FOD0738 Rev. 1.0.7
Switching Characteristics Over recommended temperature (T = –40°C to +100°C) and
A
4.5 V ≤ V ≤ 5.5 V. All typical specifications are at T = 25°C, V = +5 V.
DD
A
DD
Symbol
Parameter
Test Conditions
Min. Typ.* Max. Units
t
t
Propagation Delay Time to
Logic Low Output
I = 12 mA, C = 15 pF
CMOS Signal Levels, note 1, fig. 10
20
60
ns
PHL
F
L
Propagation Delay Time to
Logic High Output
I = 12 mA, C = 15 pF FOD0708
13
11
60
60
ns
PLH
F
L
CMOS Signal Levels,
note 1, fig. 10
FOD0738
PW
Pulse Width
100
0
ns
ns
| PWD |
Pulse Width Distortion
I = 12 mA, C = 15 pF
CMOS Signal Levels, note 2
30
40
F
L
t
t
t
Propagation Delay Skew
I = 12 mA, C = 15 pF
ns
ns
PSK
R
F
L
CMOS Signal Levels, note 3
Output Rise Time (10%–90%) I = 12 mA, C = 15 pF
12
8
F
L
CMOS Signal Levels
Output Fall Time (90%–10%) I = 12 mA, C = 15 pF
ns
F
F
L
CMOS Signal Levels
| CM |
Common Mode Transient
Immunity at Logic High
Output
V
= 1000 V, T = 25°C, I = 0 mA,
25
25
50
kV/µs
H
CM
A
F
note 4, fig. 11
| CM |
Common Mode Transient
V
= 1000 V, T = 25°C, I = 12 mA,
50
kV/µs
L
CM
A
F
Immunity at Logic Low Output note 5, fig. 11
*All typicals at T = 25°C and V = 5V unless otherwise noted.
A
DD
Isolation Characteristics (T = -40°C to +100°C Unless otherwise specified.)
A
Characteristics
Test Conditions Symbol
Min
Typ.**
Max
Unit
Input-Output Insulation
Leakage Current
(Relative humidity = 45%)
(T = 25°C, t = 5 s)
I
1.0
µA
I-O
A
(V = 3000 VDC) (Note 6)
I-O
Withstand Insulation
Test Voltage
(I ≤ 10 µA, R < 50%,
A
V
2500
V
I-O
H
ISO
RMS
T = 25°C) (t = 1 min.) (Note 6)
12
Resistance (Input to Output)
Capacitance (Input to Output)
(V = 500 V) (Note 6)
R
10
0.6
Ω
I-O
I-O
(f = 1 MHz) (Note 6)
C
pF
I-O
** All typical values are at V = 5 V, T = 25°C
CC
A
Notes:
1. Propagation delay time, high to low (t
), is measured from the 50% level on the rising edge of the input pulse to the 2.5V level
PHL
of the falling edge of the output voltage signal. Propagation delay time, low to high (t
), is measured from the 50% level on the
PLH
falling edge of the input pulse to the 2.5V level of the rising edge of the output voltage signal.
2. Pulse width distoration is defined as the absolute difference between the high to low and low to high propagation delay times,
| t
– t
|.
PHL
PLH
3. Propagation delay skew, t
, is defined as the worst case difference in t
or t
between units within the recommended
PLH
PSK
PHL
operating range of the device.
4. CM – The maximum tolerated rate of rise of the common mode voltage to ensure the output will remain in the high state,
H
(i,e., V
> 2.0V) Measured in kilovolts per microsecond (kV/µs).
OUT
5. CM – The maximum tolerated rate of fall of the common mode voltage to ensure the output will remain in the low state,
L
(i,e., V
< 0.8V). Measured in kilovolts per microsecond (kV/µs).
OUT
6. Isolation voltage, V , is an internal device dielectric breakdown rating. For this test, pins 1,2,3,4 are common, and pins 5,6,7,8
ISO
are common.
3
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FOD0708/FOD0738 Rev. 1.0.7
Typical Characteristics
Figure 1. FOD0708
Typical Input Threshold Current
vs Ambient Temperature
Figure 2. FOD0708
Typical Switching Speed vs Pulse Input Current
100
80
60
40
20
0
7
6
5
4
3
2
V
T
= 5V
DD
V
I
= 5V
DD
= 25oC
A
= 20µA
OL
t
PHL
t
PLH
PWD
5
7
9
11
13
15
-40
-20
0
20
40
60
80
100
I
- Pulse Input Current (mA)
F
T
- Ambient Temperature (oC)
A
Figure 3. FOD0708
Typical Logic Low Output Supply Current
vs Ambient Temperature
Figure 4. FOD0708
Typical Logic High Output Supply Current
vs Ambient Temperature
5.0
4.5
4.0
3.5
3.0
2.5
2.0
5.0
4.5
4.0
3.5
3.0
2.5
2.0
V
= 5V
DD
V
= 5V
DD
I
= 12mA
F
-40
-20
0
20
40
60
80
100
-40
-20
0
20
40
60
80
100
T
- Ambient Temperature (oC)
T
- Ambient Temperature (oC)
A
A
4
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FOD0708/FOD0738 Rev. 1.0.7
Typical Characteristics (Continued)
Figure 5. FOD0738
Typical Input Threshold Current
vs Ambient Temperature
7
Figure 6. FOD0738
Typical Switching Speed vs Pulse Input Current
100
80
60
40
20
0
Channel 1
Channel 2
V
I
= 5V
DD
V
T
= 5V
Channel 1
Channel 2
DD
= 20µA
= 25oC
OL
A
6
5
4
3
2
t
PHL
t
PLH
PWD
5
7
9
11
13
15
-40
-20
0
20
40
60
80
100
- Ambient Temperature (oC)
I
- Pulse Input Current (mA)
F
T
A
Figure 8. FOD0738
Figure 7. FOD0738
Typical Logic High Output Supply Current
vs Ambient Temperature
Typical Logic Low Output Supply Current
vs Ambient Temperature
8.5
8.0
7.5
7.0
6.5
6.0
5.5
8.5
8.0
7.5
7.0
6.5
6.0
5.5
V
= 5V
DD
V
= 5V
DD
I
= 12mA
F
-40
-20
0
20
40
60
80
100
-40
-20
0
20
40
60
80
100
- Ambient Temperature (oC)
T
- Ambient Temperature (oC)
T
A
A
5
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FOD0708/FOD0738 Rev. 1.0.7
Typical Characteristics (Continued)
Figure 9. Input Forward Current vs. Forward Voltage
100
10
T
= 100oC
A
1
= 85oC
T
T
= -40oC
= 0oC
T
A
A
0.1
A
T
= 25oC
A
0.01
0.001
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
V
- Forward Voltage (V)
F
6
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FOD0708/FOD0738 Rev. 1.0.7
Pulse Gen.
t = t = 5 ns
O
Pulse Gen.
IF = 12mA
50%
Vcc
Z
= 50 Ω
f
Z
r
O
= 50 Ω
t = t = 5 ns
f
r
Input
tPHL
Vcc
I
F
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
tPLH
I
Input
Monitoring
Node
Output
Monitoring
Node
F
0.1µF
Output
Monitoring
Node
Input
Monitor
Node
0.1µF
Bypass
90%
90%
R
IN
Output
2.5V CMOS
VOL
R
IN
10%
10%
tf
tr
Test Circuit for FOD0708
Test Circuit for FOD0738
Waveforms
Fig. 10 Test Circuit and Waveforms for tPLH, tPHL, tr and tf.
I
F
Dual Channel
VCC
+5V
B
A
1
8
7
6
5
+5V
1
2
3
4
8
7
6
5
IF
Output V
Monitoring
Node
O
0.1µF
bypass
2
3
4
A
V
FF
B
0.1µF
Bypass
Output
(VO)
VFF
GND
V
CM
+
–
VCM
Pulse Gen
Test Circuit for FOD0708
Pulse
Generator
ZO = 50Ω
Test Circuit for FOD0738
Peak
VCM
0V
VOH
VO
CMH
Switching Pos. (A), IF= 0
VO (Min)
VO (Max)
Switching Pos. (B), IF = 12 mA
VO
CML
VOL
Fig. 11 Test Circuit Common Mode Transient Immunity
(FOD0708 and FOD0738)
7
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FOD0708/FOD0738 Rev. 1.0.7
8-Pin Small Outline
0.024 (0.61)
0.060 (1.52)
0.275 (6.99)
0.155 (3.94)
0.050 (1.27)
8
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FOD0708/FOD0738 Rev. 1.0.7
Ordering Information
Option
No Suffix
R1
Order Entry Identifier
Description
FOD0708
FOD0708R1
FOD0708R2
Shipped in tubes (50 units per tube)
Tape and Reel (500 units per reel)
Tape and Reel (2500 units per reel)
R2
Marking Information
1
2
0708
6
V
X YY S
5
3
4
Definitions
1
2
3
Fairchild logo
Device number
VDE mark (Note: Only appears on parts ordered with VDE option –
See order entry table)
4
5
6
One digit year code, e.g., ‘5’
Two digit work week ranging from ‘01’ to ‘53’
Assembly package code
9
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FOD0708/FOD0738 Rev. 1.0.7
Carrier Tape Specification
8.0 0.10
2.0 0.05
3.50 0.20
0.30 MAX
Ø1.5 MIN
4.0 0.10
1.75 0.10
5.5 0.05
12.0 0.3
8.3 0.10
5.20 0.20
Ø1.5 0.1/-0
6.40 0.20
0.1 MAX
User Direction of Feed
Reflow Profile
300
280
260
240
220
200
180
160
140
120
100
80
260°C
>245°C = 42 Sec
Time above
183°C = 90 Sec
°C
1.822°C/Sec Ramp up rate
60
40
33 Sec
20
0
0
60
120
180
270
360
Time (s)
10
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FOD0708/FOD0738 Rev. 1.0.7
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
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DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVESTHE RIGHTTO MAKE CHANGES WITHOUTFURTHER NOTICETOANY
PRODUCTS HEREINTO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOTASSUMEANYLIABILITY
ARISING OUTOFTHEAPPLICATION OR USE OFANYPRODUCTOR CIRCUITDESCRIBED HEREIN; NEITHER DOES IT
CONVEYANYLICENSE UNDER ITS PATENTRIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILDíS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUTTHE EXPRESS WRITTENAPPROVALOF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, or (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in significant injury to the
user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Formative or
In Design
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
Preliminary
First Production
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
No Identification Needed
Obsolete
Full Production
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
Not In Production
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Rev. I18
11
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FOD0708/FOD0738 Rev. 1.0.7
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