FQD24N08_技术文档

August 2000

TM

QFET

FQD24N08 / FQU24N08

80V N-Channel MOSFET

General Description

Features

These N-Channel enhancement mode power field effect

transistors are produced using Fairchild’s proprietary,

planar stripe, DMOS technology.

This advanced technology has been especially tailored to

minimize on-state resistance, provide superior switching

performance, and withstand high energy pulse in the

avalanche and commutation mode. These devices are well

suited for low voltage applications such as automotive, high

efficiency switching for DC/DC converters, and DC motor

control.

•

19.6A, 80V, R_DS(on)= 0.06Ω @V_GS= 10 V

Low gate charge ( typical 19 nC)

Low Crss ( typical 50 pF)

Fast switching

100% avalanche tested

Improved dv/dt capability

D

!

D

"

! "

"

!

G

I-PAK

FQU Series

D-PAK

FQD Series

G

S

G

D

!

S

Absolute Maximum Ratings

T = 25°C unless otherwise noted

C

Symbol

V_DSS

Parameter

FQD24N08 / FQU24N08

Units

V

Drain-Source Voltage

80

19.6

12.4

78.4

± 25

230

I_D

- Continuous (T_C= 25°C)

- Continuous (T_C= 100°C)

- Pulsed

Drain Current

A

I_DM

(Note 1)

Drain Current

A

V_GSS

E_AS

I_AR

Gate-Source Voltage

V

(Note 2)

(Note 1)

(Note 3)

Single Pulsed Avalanche Energy

Avalanche Current

mJ

A

19.6

5.0

E_AR

dv/dt

P_D

Repetitive Avalanche Energy

Peak Diode Recovery dv/dt

Power Dissipation (T_A= 25°C) *

mJ

V/ns

W

6.5

2.5

Power Dissipation (T_C= 25°C)

50

W

- Derate above 25°C

Operating and Storage Temperature Range

0.4

W/°C

°C

T_J, T_STG

T_L

-55 to +150

Maximum lead temperature for soldering purposes,

300

°C

1/8" from case for 5 seconds

Thermal Characteristics

Symbol

Parameter

Typ

--

Max

2.5

50

Units

°C/W

R_θJC

R_θJA

Thermal Resistance, Junction-to-Case

Thermal Resistance, Junction-to-Ambient *

Thermal Resistance, Junction-to-Ambient

--

110

* When mounted on the minimum pad size recommended (PCB Mount)

Rev. A, August 2000

Electrical Characteristics

T = 25°C unless otherwise noted

C

Symbol

Parameter

Test Conditions

Min

Typ

Max

Units

Off Characteristics

BV_DSS

V_GS= 0 V, I_D= 250 µA

_D= 250 µA, Referenced to 25°C

Drain-Source Breakdown Voltage

80

--

V

∆BV_DSS

Breakdown Voltage Temperature

I

0.08

V/°C

/

∆T_JCoefficient

I_DSS

V

_DS= 80 V, V_GS= 0 V

_DS= 64 V, T_C= 125°C

--

1

µA

nA

Zero Gate Voltage Drain Current

V

10

I_GSSF

I_GSSR

V_GS= 25 V, V_DS= 0 V

V_GS= -25 V, V_DS= 0 V

Gate-Body Leakage Current, Forward

Gate-Body Leakage Current, Reverse

100

-100

On Characteristics

V_GS(th)

V_DS= V_GS, I_D= 250 µA

Gate Threshold Voltage

2.0

--

4.0

0.06

--

V

Ω

S

R_DS(on)

Static Drain-Source

On-Resistance

V_GS= 10 V, I_D= 9.8 A

0.048

11.5

g_FS

V_DS= 30 V, I_D= 9.8 A

(Note 4)

Forward Transconductance

--

Dynamic Characteristics

C_iss

C_oss

C_rss

Input Capacitance

--

580

210

50

750

270

65

pF

V

_DS= 25 V, V_GS= 0 V,

Output Capacitance

f = 1.0 MHz

Reverse Transfer Capacitance

Switching Characteristics

t_d(on)

t_r

t_d(off)

t_f

Turn-On Delay Time

Turn-On Rise Time

Turn-Off Delay Time

Turn-Off Fall Time

Total Gate Charge

Gate-Source Charge

Gate-Drain Charge

--

10

105

30

220

70

80

25

--

ns

V_DD= 40 V, I_D= 24 A,

R_G= 25 Ω

ns

(Note 4, 5)

35

ns

Q_g

19

nC

V_DS= 64 V, I_D= 24 A,

Q_gs

Q_gd

4.2

9.6

V_GS= 10 V

--

Drain-Source Diode Characteristics and Maximum Ratings

I_S

Maximum Continuous Drain-Source Diode Forward Current

--

19.6

78.4

1.5

--

A

I_SM

V_SD

t_rr

Maximum Pulsed Drain-Source Diode Forward Current

V_GS= 0 V, I_S= 19.6 A

_GS= 0 V, I_S= 24 A,

dI_F/ dt = 100 A/µs

Drain-Source Diode Forward Voltage

Reverse Recovery Time

--

V

63

130

ns

nC

(Note 4)

Q_rr

Reverse Recovery Charge

--

Notes:

1. Repetitive Rating : Pulse width limited by maximum junction temperature

2. L = 0.82mH, I = 19.6A, V = 25V, R = 25 Ω, Starting T = 25°C

AS

DD

G

J

3. I ≤ 24A, di/dt ≤ 300A/µs, V ≤ BV Starting T = 25°C

SD

DD

DSS, J

4. Pulse Test : Pulse width ≤ 300µs, Duty cycle ≤ 2%

5. Essentially independent of operating temperature

Rev. A, August 2000

Typical Characteristics

V_GS

Top :

15.0 V

10.0 V

8.0 V

7.0 V

6.0 V

5.5 V

5.0 V

10¹

Bottom : 4.5 V

℃

150

℃

25

10⁰

℃

-55

※

Notes :

※

Notes :

μ

1. V_DS= 30V

2. 250 s Pulse Test

1. 250 s Pulse Test

2. T_C= 25

μ

℃

-1

10

-1

10

10⁰

10¹

2

4

6

8

10

V_GS, Gate-Source Voltage [V]

V_DS, Drain-Source Voltage [V]

Figure 1. On-Region Characteristics

Figure 2. Transfer Characteristics

0.20

0.16

0.12

0.08

0.04

0.00

10¹

V_GS= 10V

V_GS= 20V

10⁰

℃

25

150

※

Notes :

1. V_GS= 0V

※

℃

Note : T = 25

J

μ

2. 250 s Pulse Test

-1

10

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

0

20

40

60

80

100

I_D, Drain Current [A]

V_SD, Source-Drain voltage [V]

Figure 3. On-Resistance Variation vs.

Drain Current and Gate Voltage

Figure 4. Body Diode Forward Voltage

Variation vs. Source Current

and Temperature

1600

1400

1200

1000

800

600

400

200

0

12

10

8

C

_iss= C_gs+ C_gd(C_ds= shorted)

_oss= C_ds+ C_gd

_rss= C_gd

V_DS= 40V

V_DS= 64V

C_oss

C

iss

※

Notes :

1. V_GS= 0 V

2. f = 1 MHz

6

C

rss

4

2

※

Note : I_D= 24A

0

-1

10

10⁰

10¹

0

2

4

6

8

10

12

14

16

18

20

Q_G, Total Gate Charge [nC]

V_DS, Drain-Source Voltage [V]

Figure 5. Capacitance Characteristics

Figure 6. Gate Charge Characteristics

Rev. A, August 2000

Typical Characteristics (Continued)

3.0

2.5

2.0

1.5

1.0

0.5

0.0

1.2

1.1

1.0

※

Notes :

0.9

0.8

1. V_GS= 0 V

※ Notes :

1. V_GS= 10 V

2. I_D= 9.8 A

μ

A

2. I_D= 250

-100

-50

0

50

100

150

200

-100

-50

0

50

100

150

200

T_J, Junction Temperature [^oC]

T, Junction Temperature [^oC]

J

Figure 7. Breakdown Voltage Variation

vs. Temperature

Figure 8. On-Resistance Variation

vs. Temperature

20

16

12

8

Operation in This Area

is Limited by R _DS(on)

10²

10 µs

100 µs

1 ms

10¹

10⁰

10 ms

DC

※

Notes :

4

1. T_C= 25 ^o

2. T_J= 150 ^o

C

3. Single Pulse

-1

0

25

10

10⁰

10¹

10²

50

75

100

125

150

℃

T_C, Case Temperature [

]

V_DS, Drain-Source Voltage [V]

Figure 9. Maximum Safe Operating Area

Figure 10. Maximum Drain Current

vs. Case Temperature

D = 0 .5

1 0 ⁰

※

N o te s

1 . Z _θ_{J C}(t)

2 . D u ty F a c to r, D = t₁/t₂

:

0 .2

℃

/W M a x.

=

2 .5

0 .1

3 . T _{J M}

-

T _C

=

P _D

* Z _θ_{J C}(t)

M

0 .0 5

1 0 ^-1

0 .0 2

0 .0 1

P_DM

t₁

s in g le p u ls e

t₂

1 0 ^-2

1 0 ^-5

1 0 ^-4

1 0 ^-3

1 0 ^-2

1 0 ^-1

1 0 ⁰

1 0 ¹

t₁, S q u a re W a ve P u ls e D u ra tio n [s e c ]

Figure 11. Transient Thermal Response Curve

Rev. A, August 2000

Gate Charge Test Circuit & Waveform

V_GS

Same Type

50KΩ

as DUT

Q_g

12V

200nF

10V

300nF

V_DS

V_GS

Q_gs

Q_gd

DUT

3mA

Charge

Resistive Switching Test Circuit & Waveforms

R_L

V_DS

90%

V_DS

V_DD

V_GS

R_G

10%

V_GS

DUT

10V

t_d(on)

t_r

t_d(off)

t_f

t _on

t _off

Unclamped Inductive Switching Test Circuit & Waveforms

BV_DSS

--------------------

BV_DSS- V_DD

L

1

2

----

E_AS

=

L I_AS

V_DS

I _D

BV_DSS

I_AS

R_G

V_DD

I_D(t)

V_DD

V_DS(t)

DUT

10V

t _p

Time

Rev. A, August 2000

Peak Diode Recovery dv/dt Test Circuit & Waveforms

+

DUT

V_DS

_

I _SD

L

Driver

R_G

Same Type

as DUT

V_DD

V_GS

• dv/dt controlled by R_G

• I_SDcontrolled by pulse period

Gate Pulse Width

--------------------------

V_GS

D =

Gate Pulse Period

10V

( Driver )

I_FM, Body Diode Forward Current

I _SD

di/dt

( DUT )

I_RM

Body Diode Reverse Current

Body Diode Recovery dv/dt

V_SD

V_DS

( DUT )

V_DD

Body Diode

Forward Voltage Drop

Rev. A, August 2000

Package Dimensions

DPAK

6.60 ±0.20

5.34 ±0.30

2.30 ±0.10

0.50 ±0.10

(0.50)

(4.34)

(0.50)

MAX0.96

0.76 ±0.10

0.50 ±0.10

1.02 ±0.20

2.30 ±0.20

2.30TYP

[2.30±0.20]

6.60 ±0.20

(5.34)

(5.04)

(1.50)

(2XR0.25)

0.76 ±0.10

Rev. A, August 2000

Package Dimensions ^(Continued)

IPAK

2.30 ±0.20

0.50 ±0.10

6.60 ±0.20

5.34 ±0.20

(0.50)

(4.34)

(0.50)

MAX0.96

0.76 ±0.10

0.50 ±0.10

2.30TYP

[2.30±0.20]

Rev. A, August 2000

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intended to be an exhaustive list of all such trademarks.

VCX™

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Quiet Series™

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ISOPLANAR™

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OPTOLOGIC™

OPTOPLANAR™

POP™

2

FACT™

FACT Quiet Series™

®

FAST

PowerTrench

DISCLAIMER

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PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY

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As used herein:

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which, (a) are intended for surgical implant into the body,

or (b) support or sustain life, or (c) whose failure to perform

when properly used in accordance with instructions for use

provided in the labeling, can be reasonably expected to

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2. A critical component is any component of a life support

device or system whose failure to perform can be

reasonably expected to cause the failure of the life support

device or system, or to affect its safety or effectiveness.

PRODUCT STATUS DEFINITIONS

Definition of Terms

Datasheet Identification

Product Status

Definition

Advance Information

Formative or In

Design

This datasheet contains the design specifications for

product development. Specifications may change in

any manner without notice.

Preliminary

First Production

This datasheet contains preliminary data, and

supplementary data will be published at a later date.

Fairchild Semiconductor reserves the right to make

changes at any time without notice in order to improve

design.

No Identification Needed

Obsolete

Full Production

This datasheet contains final specifications. Fairchild

Semiconductor reserves the right to make changes at

any time without notice in order to improve design.

Not In Production

This datasheet contains specifications on a product

that has been discontinued by Fairchild semiconductor.

The datasheet is printed for reference information only.

Rev. F1


型号：	FQD24N08
厂家：	FAIRCHILD SEMICONDUCTOR
描述：	80V N-Channel MOSFET 80V N沟道MOSFET
文件：	总9页 (文件大小：709K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

FQD24N08 [FAIRCHILD]

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