FSB50660SF [FAIRCHILD]
Motion SPMR 5 SuperFETR Series;
| 型号： | FSB50660SF |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Motion SPMR 5 SuperFETR Series 电动机控制 |
| 文件： | 总11页 (文件大小：866K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
April 2014
FSB50660SF, FSB50660SFT
Motion SPM® 5 SuperFET® Series
Features
• UL Certified No. E209204 (UL1557)
Related Source
• RD-402 - Reference Design for Motion SPM 5 Super-
• 600 V RDS(on) = 700 mMax SuperFET MOSFET 3-
Phase Inverter with Gate Drivers and Protection
FET Series
• Built-in Bootstrap Diodes Simplify PCB Layout
• AN-9082 - Motion SPM5 Series Thermal Performance
by Contact Pressure
• Separate Open-Source Pins from Low-Side MOS-
FETS for Three-Phase Current-Sensing
• AN-9080 - User’s Guide for Motion SPM 5 Series V2
• Active-HIGH Interface, Works with 3.3 / 5 V Logic,
Schmitt-trigger Input
General Description
The FSB50660SF/SFT is an advanced Motion SPM®
• Optimized for Low Electromagnetic Interference
5
module providing a fully-featured, high-performance
inverter output stage for AC Induction, BLDC and PMSM
motors such as refrigerators, fans and pumps. These
modules integrate optimized gate drive of the built-in
MOSFETs(SuperFET® technology) with to minimize EMI
and losses, while also providing multiple on-module
protection features including under-voltage lockouts and
• HVIC Temperature-Sensing Built-in for Temperature
Monitoring
• HVIC for Gate Driving and Under-Voltage Protection
• Isolation Rating: 1500 Vrms / 1 min.
• RoHS Compliant
thermal
HVIC requires only
monitoring.
The
built-in
high-speed
Applications
a
single supply voltage and
translates the incoming logic-level gate inputs to the
high-voltage, high-current drive signals required to
properly drive the module's internal MOSFETs.
Separate open-source MOSFET terminals are available
for each phase to support the widest variety of control
algorithms.
• 3-Phase Inverter Driver for Small Power AC Motor
Drives
FSB50660SF
FSB50660SFT
Package Marking & Ordering Information
Device
Package
Packing Type
Quantity
Device Marking
50660SF
FSB50660SF
SPM5P-023
SPM5N-023
Rail
Rail
15
15
FSB50660SFT
50660SFT
©2012 Fairchild Semiconductor Corporation
FSB50660SF, FSB50660SFT Rev. C6
1
www.fairchildsemi.com
Absolute Maximum Ratings
Inverter Part (each MOSFET unless otherwise specified.)
Symbol
VDSS
Parameter
Conditions
Rating
600
Unit
V
Drain-Source Voltage of Each MOSFET
*ID 25
*ID 80
*IDP
Each MOSFET Drain Current, Continuous TC = 25°C
Each MOSFET Drain Current, Continuous TC = 80°C
3.1
A
2.3
A
Each MOSFET Drain Current, Peak
Each MOSFET Drain Current, Rms
Maximum Power Dissipation
TC = 25°C, PW < 100 s
8.1
A
*IDRMS
*PD
TC = 80°C, FPWM < 20 kHz
TC = 25°C, For Each MOSFET
1.6
Arms
W
14.2
Control Part (each HVIC unless otherwise specified.)
Symbol
VCC
Parameter
Conditions
Rating
Unit
Control Supply Voltage
Applied Between VCC and COM
Applied Between VB and VS
Applied Between IN and COM
20
20
V
V
V
VBS
High-side Bias Voltage
Input Signal Voltage
VIN
-0.3 ~ VCC + 0.3
Bootstrap Diode Part (each bootstrap diode unless otherwise specified.)
Symbol
Parameter
Conditions
Rating
Unit
VRRMB
Maximum Repetitive Reverse Voltage
V
A
A
600
0.5
* IFB
Forward Current
TC = 25°C
* IFPB
Forward Current (Peak)
TC = 25°C, Under 1ms Pulse Width
1.5
Thermal Resistance
Symbol
Parameter
Conditions
Rating
Unit
Each MOSFET under Inverter Oper-
ating Condition (1st Note 1)
Junction to Case Thermal Resistance
°C/W
RJC
8.8
Total System
Symbol
Parameter
Conditions
Rating
-40 ~ 150
-40 ~ 125
Unit
°C
TJ
Operating Junction Temperature
Storage Temperature
TSTG
°C
60 Hz, Sinusoidal, 1 Minute, Con-
nect Pins to Heat Sink Plate
VISO
Isolation Voltage
1500
Vrms
1st Notes:
1. For the measurement point of case temperature T , please refer to Figure 4.
C
2. Marking “ * “ is calculation value or design factor.
©2012 Fairchild Semiconductor Corporation
FSB50660SF, FSB50660SFT Rev. C6
2
www.fairchildsemi.com
Pin descriptions
Pin Number
Pin Name
Pin Description
1
2
COM
VB(U)
VCC(U)
IN(UH)
IN(UL)
N.C
IC Common Supply Ground
Bias Voltage for U-Phase High-Side MOSFET Driving
Bias Voltage for U-Phase IC and Low-Side MOSFET Driving
Signal Input for U-Phase High-Side
3
4
5
Signal Input for U-Phase Low-Side
6
No Connection
7
VB(V)
VCC(V)
IN(VH)
IN(VL)
VTS
Bias Voltage for V-Phase High Side MOSFET Driving
Bias Voltage for V-Phase IC and Low Side MOSFET Driving
Signal Input for V-Phase High-Side
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
Signal Input for V-Phase Low-Side
Output for HVIC Temperature Sensing
VB(W)
VCC(W)
IN(WH)
IN(WL)
N.C
Bias Voltage for W-Phase High-Side MOSFET Driving
Bias Voltage for W-Phase IC and Low-Side MOSFET Driving
Signal Input for W-Phase High-Side
Signal Input for W-Phase Low-Side
No Connection
P
Positive DC-Link Input
U, VS(U)
NU
Output for U-Phase & Bias Voltage Ground for High-Side MOSFET Driving
Negative DC-Link Input for U-Phase
NV
Negative DC-Link Input for V-Phase
V, VS(V)
NW
Output for V-Phase & Bias Voltage Ground for High-Side MOSFET Driving
Negative DC-Link Input for W-Phase
W, VS(W)
Output for W Phase & Bias Voltage Ground for High-Side MOSFET Driving
(1) COM
(2) VB(U)
(3) VCC(U)
(4) IN (UH)
(5) IN (UL)
(17) P
VCC
HIN
VB
HO
VS
LO
(18) U, VS(U)
LIN
COM
(6) N.C
(19) NU
(20) NV
(7) VB(V)
(8) VCC(V)
(9) IN (VH)
(10) IN (VL)
VCC
HIN
LIN
VB
HO
VS
LO
(21) V, VS(V)
COM
VTS
(11) VTS
(12) V B(W)
(13) VCC(W)
(14) IN (WH)
(15) IN (WL)
VCC
HIN
VB
HO
VS
LO
(22) NW
(23) W, VS(W)
LIN
COM
(16)
N.C
Figure 1. Pin Configuration and Internal Block Diagram (Bottom View)
1st Notes:
®
3. Source terminal of each low-side MOSFET is not connected to supply ground or bias voltage ground inside Motion SPM 5 product. External connections should be made as
indicated in Figure 3.
©2012 Fairchild Semiconductor Corporation
FSB50660SF, FSB50660SFT Rev. C6
3
www.fairchildsemi.com
Electrical Characteristics (TJ = 25°C, VCC = VBS = 15 V unless otherwise specified.)
Inverter Part (each MOSFET unless otherwise specified.)
Symbol
Parameter
Conditions
Min Typ Max Unit
Drain - Source
Breakdown Voltage
BVDSS
V
V
V
V
IN = 0 V, ID = 1 mA (2nd Note 1)
600
-
-
V
mA
m
V
Zero Gate Voltage
Drain Current
IDSS
RDS(on)
VSD
IN = 0 V, VDS = 600 V
-
-
-
-
600
-
1
Static Drain - Source
Turn-On Resistance
CC = VBS = 15 V, VIN = 5 V, ID = 1.5 A
CC = VBS = 15 V, VIN = 0 V, ID = -1.5 A
700
1.1
Drain - Source Diode
Forward Voltage
tON
tOFF
trr
-
-
-
-
-
950
820
120
130
5
-
-
-
-
-
ns
ns
ns
J
J
VPN = 300 V, VCC = VBS = 15 V, ID = 1.5 A
IN = 0 V 5 V, Inductive Load L = 3 mH
High- and Low-Side MOSFET Switching
V
Switching Times
EON
EOFF
(2nd Note 2)
V
PN = 400 V, VCC = VBS = 15 V, ID = IDP, VDS = BVDSS,
Reverse Bias Safe Oper-
ating Area
RBSOA
TJ = 150°C
Full Square
High- and Low-Side MOSFET Switching (2nd Note 3)
Control Part (each HVIC unless otherwise specified.)
Symbol
Parameter
Conditions
Min Typ Max Unit
V
V
CC = 15 V,
IN = 0 V
IQCC
Quiescent VCC Current
Applied Between VCC and COM
-
-
-
-
200
100
A
A
V
V
BS = 15 V,
IN = 0 V
Applied Between VB(U) - U,
IQBS
Quiescent VBS Current
V
B(V) - V, VB(W) - W
UVCCD
UVCCR
UVBSD
UVBSR
V
CC Under-Voltage Protection Detection Level
7.4
8.0
7.4
8.0
8.0
8.9
8.0
8.9
9.4
9.8
9.4
9.8
V
V
V
V
Low-Side Under-Voltage
Protection (Figure 8)
VCC Under-Voltage Protection Reset Level
BS Under-Voltage Protection Detection Level
VBS Under-Voltage Protection Reset Level
V
High-Side Under-Voltage
Protection (Figure 9)
HVIC Temperature Sens-
ing Voltage Output
VTS
mV
V
CC = 15 V, THVIC = 25°C (2nd Note 4)
600
790
980
VIH
VIL
ON Threshold Voltage
OFF Threshold Voltage
Logic HIGH Level
Logic LOW Level
-
-
-
2.9
-
V
V
Applied between IN and COM
0.8
Bootstrap Diode Part (each bootstrap diode unless otherwise specified.)
Symbol
VFB
Parameter
Conditions
IF = 0.1 A, TC = 25°C (2nd Note 5)
IF = 0.1 A, TC = 25°C
Min Typ Max Unit
Forward Voltage
Reverse Recovery Time
-
-
2.5
80
-
-
V
trrB
ns
2nd Notes:
®
1. BV
is the absolute maximum voltage rating between drain and source terminal of each MOSFET inside Motion SPM 5 product. V should be sufficiently less than this
PN
DSS
value considering the effect of the stray inductance so that V should not exceed BV
in any case.
PN
DSS
2. t and t
include the propagation delay of the internal drive IC. Listed values are measured at the laboratory test condition, and they can be different according to the field
OFF
ON
applications due to the effect of different printed circuit boards and wirings. Please see Figure 6 for the switching time definition with the switching test circuit of Figure 7.
3. The peak current and voltage of each MOSFET during the switching operation should be included in the Safe Operating Area (SOA). Please see Figure 7 for the RBSOA test
circuit that is same as the switching test circuit.
4. V is only for sensing-temperature of module and cannot shutdown MOSFETs automatically.
ts
5. Built-in bootstrap diode includes around 15Ωresistance characteristic. Please refer to Figure 2.
©2012 Fairchild Semiconductor Corporation
FSB50660SF, FSB50660SFT Rev. C6
4
www.fairchildsemi.com
Recommended Operating Condition
Symbol
VPN
Parameter
Conditions
Min.
-
Typ. Max.
Unit
Supply Voltage
Applied Between P and N
300
15.0
15.0
-
400
16.5
16.5
VCC
0.6
V
V
V
V
V
VCC
Control Supply Voltage
High-Side Bias Voltage
Applied Between VCC and COM
Applied Between VB and VS
13.5
13.5
3.0
0
VBS
VIN(ON) Input ON Threshold Voltage
VIN(OFF) Input OFF Threshold Voltage
Applied Between IN and COM
-
Blanking Time for Preventing
Arm-Short
tdead
V
CC = VBS = 13.5 ~ 16.5 V, TJ 150°C
1.0
-
-
-
-
s
fPWM
PWM Switching Frequency
TJ 150°C
20
kHz
Built-in Bootstrap Diode VF-IF Characteristic
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
VF [V]
Tc=25°C
Figure 2. Built-in Bootstrap Diode Characteristics (Typical)
©2012 Fairchild Semiconductor Corporation
FSB50660SF, FSB50660SFT Rev. C6
5
www.fairchildsemi.com
These values depend on PWM control algorithm
* Example Circuit : V phase
C
1
+15 V
VDC
P
V
HIN
0
LIN
0
Output
Note
VCC
HIN
LIN
VB
HO
VS
LO
Inverter
Output
Z
Both FRFET Off
Low side FRFET On
High side FRFET On
Shoot through
R
5
0
1
0
VDC
1
0
C3
C5
COM
VTS
1
1
Forbidden
Z
R
3
N
Open Open
Same as (0,0)
C4
One Leg Diagram of Motion SPM® 5 Product
C2
10 F
*
Example of Bootstrap Param: ters
C = C2 = 1 F Ceramic Capacitor
1
Figure 3. Recommended MCU Interface and Bootstrap Circuit with Parameters
3rd Notes:
1. Parameters for bootstrap circuit elements are dependent on PWM algorithm. For 15 kHz of switching frequency, typical example of parameters is shown above.
2. RC-coupling (R and C ) and C at each input of Motion SPM 5 product and MCU (Indicated as Dotted Lines) may be used to prevent improper signal due to surge-noise.
5
5
4
3. Bold lines should be short and thick in PCB pattern to have small stray inductance of circuit, which results in the reduction of surge-voltage. Bypass capacitors such as C , C
1
2
and C should have good high-frequency characteristics to absorb high-frequency ripple-current.
3
Figure 4. Case Temperature Measurement
3rd Notes:
4. Attach the thermocouple on top of the heat-sink of SPM 5 package (between SPM 5 package and heatsink if applied) to get the correct temperature measurement.
3.5
3.0
2.5
2.0
1.5
1.0
0.5
20
40
60
80
100
120
140
160
THVIC [oC]
Figure 5. Temperature Profile of VTS (Typical)
©2012 Fairchild Semiconductor Corporation
FSB50660SF, FSB50660SFT Rev. C6
6
www.fairchildsemi.com
VIN
VIN
Irr
120% of ID
100% of ID
VDS
ID
10% of ID
ID
VDS
tON
trr
tOFF
(a) Turn-on
(b) Turn-off
Figure 6. Switching Time Definitions
CBS
VCC
ID
VCC
HIN
LIN
VB
HO
VS
LO
L
VDC
+
VDS
-
COM
VTS
One Leg Diagram of Motion SPM® 5 Product
Figure 7. Switching and RBSOA (Single-pulse) Test Circuit (Low-side)
Input Signal
UV Protection
RESET
DETECTION
RESET
Status
UVCCR
Low-side Supply, VCC
UVCCD
MOSFET Current
Figure 8. Under-Voltage Protection (Low-Side)
Input Signal
UV Protection
Status
RESET
DETECTION
RESET
UVBSR
High-side Supply, VBS
UVBSD
MOSFET Current
Figure 9. Under-Voltage Protection (High-Side)
©2012 Fairchild Semiconductor Corporation
FSB50660SF, FSB50660SFT Rev. C6
7
www.fairchildsemi.com
C1
(1) COM
(2)VB(U)
(17)P
(3)VCC(U)
VCC
HIN
VB
HO
VS
LO
R5
(4)IN
(UH)
(18)U,VS(U)
(5)IN
(UL)
VDC
C3
LIN
C5
C2
COM
(6)N.C
(7)VB(V)
(8)VCC(V)
(19)NU
(20)NV
VCC
HIN
LIN
VB
HO
VS
LO
(9)IN
(VH)
(21)V,VS(V)
(10) IN
(VL)
M
COM
VTS
(11)VTS
(12)VB(W)
(13)VCC(W)
(22)NW
VCC
HIN
VB
HO
VS
LO
(14) IN
(WH)
(23)W,VS(W)
(15) IN
(WL)
LIN
COM
(16)N.C
C4
R4
For current-sensing and protection
15 V
Supply
C6
R3
Figure 10. Example of Application Circuit
4th Notes:
1. About pin position, refer to Figure 1.
®
2. RC-coupling (R and C , R and C ) and C at each input of Motion SPM 5 product and MCU are useful to prevent improper input signal caused by surge-noise.
5
5
4
6
4
3. The voltage-drop across R affects the low-side switching performance and the bootstrap characteristics since it is placed between COM and the source terminal of the low-
3
side MOSFET. For this reason, the voltage-drop across R should be less than 1 V in the steady-state.
3
4. Ground-wires and output terminals, should be thick and short in order to avoid surge-voltage and malfunction of HVIC.
5. All the filter capacitors should be connected close to Motion SPM 5 product, and they should have good characteristics for rejecting high-frequency ripple current.
©2012 Fairchild Semiconductor Corporation
FSB50660SF, FSB50660SFT Rev. C6
8
www.fairchildsemi.com
Detailed Package Outline Drawings (FSB50660SF)
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or data on the drawing and contact a FairchildSemiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide therm and conditions,
specifically the the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/dwg/MO/MOD23DC.pdf
©2012 Fairchild Semiconductor Corporation
FSB50660SF, FSB50660SFT Rev. C6
9
www.fairchildsemi.com
Detailed Package Outline Drawings (FSB50660SFT)
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or data on the drawing and contact a FairchildSemiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide therm and conditions,
specifically the the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/dwg/MO/MOD23DF.pdf
©2012 Fairchild Semiconductor Corporation
FSB50660SF, FSB50660SFT Rev. C6
10
www.fairchildsemi.com
©2012 Fairchild Semiconductor Corporation
FSB50660SF, FSB50660SFT Rev. C6
11
www.fairchildsemi.com
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