GTLP36T612 [FAIRCHILD]
36-Bit LVTTL/GTLP Universal Bus Transceiver; 36位LVTTL / GTLP通用总线收发器
| 型号： | GTLP36T612 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | 36-Bit LVTTL/GTLP Universal Bus Transceiver |
| 文件： | 总8页 (文件大小：81K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
September 2001
Revised July 2002
GTLP36T612
36-Bit LVTTL/GTLP Universal Bus Transceiver
General Description
Features
The GTLP36T612 is an 36-bit universal bus transceiver
which provides LVTTL to GTLP signal level translation. It
allows for transparent, latched and clocked modes of data
transfer. The device provides a high speed interface for
cards operating at LVTTL logic levels and a backplane
operating at GTLP logic levels. High speed backplane
operation is a direct result of GTLP’s reduced output swing
(< 1V), reduced input threshold levels and output edge rate
control. The edge rate control minimizes bus settling time.
GTLP is a Fairchild Semiconductor derivative of the Gun-
ning Transistor logic (GTL) JEDEC standard JESD8-3.
■ Bidirectional interface between GTLP and LVTTL logic
levels
■ Designed with edge rate control circuitry to reduce out-
put noise on the GTLP port
■ Partitioned as two 18-Bit transceivers with individual
latch timing and output control
■ VREF pin provides external supply reference voltage for
receiver threshold adjustibility
■ Special PVT compensation circuitry to provide consis-
tent performance over variations of process, supply volt-
age and temperature
Fairchild’s GTLP has internal edge-rate control and is Pro-
cess, Voltage, and Temperature (PVT) compensated. Its
function is similar to BTL or GTL but with different output
levels and receiver thresholds. GTLP output LOW level is
less than 0.5V, the output HIGH is 1.5V and the receiver
threshold is 1.0V.
■ TTL compatible driver and control inputs
■ Designed using Fairchild advanced BiCMOS technology
■ Bushold data inputs on A port to eliminate the need for
external pull-up resistors for unused inputs
■ Power up/down and power off high impedance for live
insertion
■ Open drain on GTLP to support wired-or connection
■ Flow through pinout optimizes PCB layout
■ D-type flip-flop, latch and transparent data paths
■ A Port source/sink −24mA/+24mA
■ B Port sink +50mA
■ For more information see AN-5026,
Using BGA Packages
Ordering Code:
Order Number
Package Number
Package Description
GTLP36T612G
(Note 1)(Note 2)
BGA114A
114-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
Note 1: Ordering code “G” indicates Trays.
Note 2: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
© 2002 Fairchild Semiconductor Corporation
DS500590
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Truth Table
Pin Descriptions
(Note 3)
Pin Names
Description
Inputs
CEAB OEAB LEAB CLKAB A
Output
Mode
OEAB
OEBA
CEAB
CEBA
LEAB
LEBA
VREF
A-to-B Output Enable
(Active LOW) (LVTTL Level)
B
Z
B-to-A Output Enable
(Active LOW) (LVTTL Level)
X
L
L
X
X
L
L
H
L
L
L
L
L
L
X
L
X
H
L
X
X
X
L
Latched
storage
B
0 (Note 4)
A-to-B Clock/LE Enable
(Active LOW) (LVTTL Level)
L
B0 (Note 5) of A data
B-to-A Clock/LE Enable
(Active LOW) (LVTTL Level)
H
H
L
X
X
↑
L
H
L
Transparent
H
L
A-to-B Latch Enable
(Transparent HIGH) (LVTTL Level)
Clocked
storage
L
↑
H
H
B-to-A Latch Enable
(Transparent HIGH) (LVTTL Level)
of A data
GTLP Input Threshold
Reference Voltage
H
L
L
X
X
B0 (Note 5) Clock inhibit
Note 3: A-to-B data flow is shown. B-to-A data flow is similar but uses
OEBA, LEBA, CLKBA, and CEBA.
CLKAB
CLKBA
A1–A18
A-to-B Clock (LVTTL Level)
B-to-A Clock (LVTTL Level)
Note 4: Output level before the indicated steady state input conditions were
established, provided that CLKAB was HIGH before LEAB went LOW.
Note 5: Output level before the indicated steady-state input conditions
were established.
A-to-B Data Inputs or
B-to-A 3-STATE Outputs
B1–B18
B-to-A Data Inputs or
A-to-B Open Drain Outputs
FBGA Pin Assignments
Connection Diagram
Number in front of each pin indicates word.
Pin Assignment for FBGA
1
2
3
4
5
6
A
B
C
D
E
F
1A2
1A4
1A6
1A8
1A10
1A12
1A1 1OEAB 1CLKAB 1B2
1B1
1B3
1B5
1B7
1B9
1B11
1A3 1LEAB 1CEAB
1B4
1B6
1A5
1A7
1A9
1A11
VCC
GND
GND
GND
VCC
VCC
GND
GND
GND
VREF
1B8
1B10
1B12
G
H
J
1A14 1A13
1B14 1B13
1A16 1A15 1OEBA 1CEBA 1B16 1B15
1A18 1A17 1LEBA 1CLKBA 1B18 1B17
K
L
2A2
2A4
2A1 2OEAB 2CLKAB 2B2
2B1
2B3
2B5
2B7
2B9
2B11
M
N
P
R
T
2A3 2LEAB 2CEAB
2B4
2B6
2A6
2A5
2A7
2A9
2A11
VCC
GND
GND
GND
VCC
VCC
GND
GND
GND
VREF
2A8
2B8
2A10
2A12
2B10
2B12
U
V
W
2A14 2A13
2B14 2B13
2A16 2A15 2OEBA 2CEBA 2B16 2B15
2A18 2A17 2LEBA 2CLKBA 2B18 2B17
(Top Thru View)
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2
Functional Description
The GTLP36T612 is an 36-bit registered transceiver containing D-type flip-flop, latch and transparent modes of operation
for the data path. Data flow in each direction is controlled by the clock enables (CEAB and CEBA), latch enables (LEAB
and LEBA), clock (CLKAB and CLKBA) and output enables (OEAB and OEBA). The clock enables (CEAB and CEBA) and
the output enables (OEAB and OEBA) control the 18 bits of data for the A-to-B and B-to-A directions respectively.
For A-to-B data flow, when CEAB is LOW, the device operates on the LOW-to-HIGH transition of CLKAB for the flip-flop
and on the HIGH-to-LOW transition of LEAB for the latch path. That is, if CEAB is LOW and LEAB is LOW the A data is
latched regardless as to the state of CLKAB (HIGH or LOW) and if LEAB is HIGH the device is in transparent mode. When
OEAB is LOW the outputs are active. When OEAB is HIGH the outputs are HIGH impedance. The data flow of B-to-A is
similar except that CEBA, OEBA, LEBA, and CLKBA are used.
Logic Diagram
3
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Absolute Maximum Ratings(Note 6)
Recommended Operating
Conditions (Note 8)
Supply Voltage (VCC
)
−0.5V to +4.6V
−0.5V to +4.6V
DC Input Voltage (VI)
DC Output Voltage (VO)
Outputs 3-STATE
Supply Voltage VCC/VCCQ
3.15V to 3.45V
Bus Termination Voltage (VTT
)
−0.5V to +4.6V
GTLP
1.47V to 1.53V
0.98V to 1.02V
Outputs Active (Note 7)
DC Output Sink Current into
A Port IOL
−0.5V to VCC + 0.5V
VREF
Input Voltage (VI)
on A Port and Control Pins
on B Port
48 mA
−48 mA
100 mA
−50 mA
0.0V to 3.45V
0.0V to 3.45V
DC Output Source Current from
A Port IOH
HIGH Level Output Current (IOH
A Port
)
DC Output Sink Current into
B Port in the LOW State, IOL
−24 mA
LOW Level Output Current (IOL
)
DC Input Diode Current (IIK
)
A Port
+24 mA
+50 mA
VI < 0V
B Port
DC Output Diode Current (IOK
)
Operating Temperature (TA)
−40°C to +85°C
Note 6: Absolute Maximum continuous ratings are those values beyond
which damage to the device may occur. Exposure to these conditions or
conditions beyond those indicated may adversely affect device reliability.
Functional operation under absolute maximum rated conditions in not
implied.
V
V
O < 0V
−50 mA
+50 mA
O > VCC
ESD Performance
>2000V
Storage Temperature (TSTG
)
−65°C to +150°C
Note 7: IO Absolute Maximum Rating must be observed.
Note 8: Unused inputs must be held HIGH or LOW.
DC Electrical Characteristics
Over Recommended Operating Free-Air Temperature Range, V
= 1.0V (unless otherwise noted).
REF
Min
Typ
Max
Symbol
Test Conditions
Units
(Note 9)
VIH
VIL
B Port
V
REF +0.05
2.0
VTT
V
V
Others
B Port
0.0
V
REF − 0.05
Others
0.8
VREF
VIK
GTLP (Note 10)
1.0
V
V
VCC = 3.15V
II = −18 mA
−1.2
VOH
A Port
VCC, VCCQ = Min to Max (Note 11)
I
OH = −100 µA
OH = −8 mA
VCC –0.2
2.4
VCC = 3.15V
I
V
V
IOH = -24mA
2.0
VOL
A Port
B Port
VCC, VCCQ = Min to Max (Note 11)
IOL = 100 µA
IOL = 24mA
IOL = 40 mA
IOL = 50 mA
0.2
0.5
0.40
0.55
±5
V
CC = 3.15V
CC = 3.15V
V
V
II
Control Pins
A Port
V
CC = Min to Max (Note 11)
CC = 3.45V
VI = 3.45V or 0V
VI = 0V
µA
µA
V
−10
10
VI = 3.45
B Port
V
CC = 3.45V
VI = VCC
5
µA
µA
µA
VI = 0
−5
IOFF
A Port and Control Pins
A Port
VCC = 0
VI or VO = 0 to 3.45V
VI = 0.8V
30
II(hold)
VCC = 3.15V
75
VI = 2.0V
−75
10
5
IOZH
A Port
VCC = 3.45V
VCC = 3.45V
VCC = 3.45V
V
V
V
V
O = 3.45
O = 3.45V
O = 0V
µA
µA
B Port
IOZL
A Port
−10
−5
80
80
90
B Port
O = 0V
ICC
A or B Ports
Outputs HIGH
Outputs LOW
60
60
60
(VCC/VCCQ
)
I
O = 0
mA
VI = VCC or GND
Outputs Disabled
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4
DC Electrical Characteristics (Continued)
Min
Typ
Max
Symbol
Test Conditions
Units
(Note 9)
∆ICC
A Port and
Control Pins
Control Pins
A Port
V
CC = 3.45V,
One Input at 2.7V
2
mA
(Note 12)
Ci
A or Control Inputs at VCC or GND
VI = VCC or 0
VI = VCC or 0
VI = VCC or 0
6
7.5
9.0
pF
B Port
Note 9: All typical values are at VCC = 3.3V, VCCQ = 3.3V, and TA = 25°C.
Note 10: GTLP VREF and VTT are specified to 2% tolerance since signal integrity and noise margin can be significantly degraded if these supplies are noisy.
In addition, VTT and Rterm can be adjusted beyond the recommended operating conditions to accommodate backplane impedances other than 50Ω, but
must remain within the boundaries of the DC Absolute Maximum ratings. Similarly VREF can be adjusted to optimize noise margin.
Note 11: For conditions shown as Min or Max, use the appropriate value specified under recommended operating conditions.
Note 12: This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
AC Operating Requirements
Over recommended ranges of supply voltage and operating free-air temperature, V
= 1.0V (unless otherwise noted).
REF
Test Conditions
Symbol
Min
175
3.0
3.0
1.1
3.0
1.1
2.7
Max
Unit
fMAX
Maximum Clock Frequency
Pulse Duration
MHz
tWIDTH
LEAB or LEBA HIGH
ns
CLKAB or CLKBA HIGH or LOW
A before CLKAB↑
tSU
Setup Time
B before CLKBA↑
A before LEAB
ns
B before LEBA
CEAB before CLKAB↑
1.2
CEBA before CLKBA↑
A after CLKAB↑
B after CLKBA↑
A after LEAB
1.4
0.0
0.0
0.8
0.0
tHOLD
Hold Time
ns
B after LEBA
CEAB after CLKAB↑
CEBA after CLKBA↑
1.0
1.9
5
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AC Electrical Characteristics
Over recommended range of supply voltage and operating free-air temperature, VREF = 1.0V (unless otherwise noted).
C
L = 30 pF for B Port and CL = 50 pF for A Port.
From
To
(Output)
B
Min
Typ
(Note 13)
4.1
Max
Symbol
(Input)
Unit
ns
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
A
2.1
1.0
2.2
1.0
2.2
1.0
6.3
4.4
6.3
4.2
6.5
4.4
2.7
LEAB
CLKAB
B
B
4.2
ns
2.4
4.4
ns
2.5
tPLH
tPHL
tRISE
tFALL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
OEAB
B
2.0
1.0
3.8
2.6
3.1
2.1
3.8
3.8
2.2
2.4
2.4
2.6
5.6
4.3
ns
ns
ns
ns
ns
Transition Time, B Outputs (20% to 80%)
Transition Time, B Outputs (20% to 80%)
B
A
A
A
1.8
1.8
0.3
0.4
0.5
0.6
5.8
5.8
4.6
4.6
4.6
4.6
LEBA
CLKBA
tPZH, tPZL
tPHZ, tPLZ
OEBA
A
0.3
0.3
2.7
2.5
5.2
5.2
ns
Note 13: All typical values are at VCC = 3.3V, and TA = 25°C.
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6
Test Circuits and Timing Waveforms
Test Circuit for A Outputs
Test Circuit for B Outputs
Test
S
tPLH/tPHL Open
tPLZ/tPZL 6V
Note B: For B Port, CL = 30 pF is used for worst case.
tPHZ/tPZH GND
Note A: CL includes probes and Jig capacitance.
Voltage Waveform - Propagation Delay Times
Voltage Waveform - Setup and Hold Times
Voltage Waveform - Pulse Width
Voltage Waveform - Enable and Disable times
Output Waveform 1 is for an output with internal conditions such that the
output is LOW except when disabled by the control output.
Output Waveform 2 is for an output with internal conditions such that the
output is HIGH except when disabled by the control output.
Input and Measure Conditions
A or LVTTL
Pins
B or GTLP
Pins
VinHIGH
VinLOW
VM
3.0
0.0
1.5
1.5
0.0
1.0
N/A
N/A
VX
V
V
OL + 0.3V
OH − 0.3V
VY
All input pulses have the following characteristics: Frequency = 10MHz, tRISE = tFALL = 2 ns (10% to 90%), ZO = 50Ω.
The outputs are measured one at a time with one transition per measurement.
7
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Physical Dimensions inches (millimeters) unless otherwise noted
114-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
Package Number BGA114A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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8
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