MM74C373N [FAIRCHILD]
3-STATE Octal D-Type Latch . 3-STATE Octal D-Type Flip-Flop; 三态八路D型锁存器。三态八路D型触发器
| 型号： | MM74C373N |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | 3-STATE Octal D-Type Latch . 3-STATE Octal D-Type Flip-Flop |
| 文件： | 总11页 (文件大小：115K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
October 1987
Revised January 1999
MM74C373 • MM74C374
3-STATE Octal D-Type Latch •
3-STATE Octal D-Type Flip-Flop
Both the MM74C373 and the MM74C374 are being assem-
bled in 20-pin dual-in-line packages with 0.300” pin cen-
ters.
General Description
The MM74C373 and MM74C374 are integrated, comple-
mentary MOS (CMOS), 8-bit storage elements with 3-
STATE outputs. These outputs have been specially
designed to drive high capacitive loads, such as one might
find when driving a bus, and to have a fan out of 1 when
driving standard TTL. When a high logic level is applied to
the OUTPUT DISABLE input, all outputs go to a high
impedance state, regardless of what signals are present at
the other inputs and the state of the storage elements.
Features
■ Wide supply voltage range: 3V to 15V
■ High noise immunity: 0.45 VCC (typ.)
■ Low power consumption
■ TTL compatibility:
Fan out of 1driving standard TTL
■ Bus driving capability
The MM74C373 is an 8-bit latch. When LATCH ENABLE is
high, the Q outputs will follow the D inputs. When LATCH
ENABLE goes low, data at the D inputs, which meets the
set-up and hold time requirements, will be retained at the
outputs until LATCH ENABLE returns high again.
■ 3-STATE outputs
■ Eight storage elements in one package
■ Single CLOCK/LATCH ENABLE and OUTPUT DIS-
ABLE control inputs
The MM74C374 is an 8-bit, D-type, positive-edge triggered
flip-flop. Data at the D inputs, meeting the set-up and hold
time requirements, is transferred to the Q outputs on posi-
tive-going transitions of the CLOCK input.
■ 20-pin dual-in-line package with 0.300” centers takes
half the board space of a 24-pin package
Ordering Code:
Order Number Package Number
Package Description
MM74C373M
MM74C373N
MM74C374M
MM74C374N
M20B
N20A
M20B
N20A
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
© 1999 Fairchild Semiconductor Corporation
DS005906.prf
www.fairchildsemi.com
Connection Diagrams
Pin Assignments for DIP and SOIC
MM74C373
MM74C374
Top View
Top View
Truth Tables
MM74C373
MM74C374
Output
LATCH
D
Q
Output
Clock
D
Q
Disable
ENABLE
Disable
L
L
H
H
L
H
L
H
L
L
L
L
L
H
H
L
H
L
L
X
X
Q
L
H
X
X
X
X
Q
H
X
Hi-Z
Q
Hi-Z
L = LOW logic level
H = HIGH logic level
X = Irrelevant
= LOW-to-HIGH logic level transition
Q = Preexisting output level
Hi-Z = High impedance output state
www.fairchildsemi.com
2
Block Diagrams
MM74C373 (1 of 8 Latches)
MM74C374 (1 of 8 Flip-Flops)
3
www.fairchildsemi.com
Operating VCC Range
Absolute Maximum VCC
Lead Temperature (TL)
(Soldering, 10 seconds)
3V to 15V
18V
Absolute Maximum Ratings(Note 1)
Voltage at Any Pin
−0.3V to VCC + 0.3V
Operating Temperature Range (TA)
MM74C373
260°C
−40°C to +85°C
−65°C to +150°C
Storage Temperature Range (TS)
Power Dissipation
Note 1: “Absolute Maximum Ratings” are those values beyond which the
safety of the device cannot be guaranteed. Except for “Operating Tempera-
ture Range” they are not meant to imply that the devices should be oper-
ated at these limits. The table of “Electrical Characteristics” provides
conditions for actual device operation.
Dual-In-Line
700 mW
500 mW
Small Outline
DC Electrical Characteristics
Min/Max limits apply across temperature range unless otherwise noted
Symbol
Parameter
Conditions
Min
Typ
Max
Units
CMOS TO CMOS
V
V
V
V
Logical “1” Input Voltage
Logical “0” Input Voltage
Logical “1” Output Voltage
Logical “0” Output Voltage
V
V
V
V
V
V
V
V
V
V
V
V
V
= 5V
3.5
8.0
V
V
IN(1)
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
= 10V
= 5V
1.5
2.0
V
IN(0)
= 10V
V
= 5V, I = −10 µA
4.5
9.0
V
OUT(1)
OUT(0)
O
= 10V, I = −10 µA
V
O
= 5V, I = 10 µA
0.5
1.0
1.0
V
O
= 10V, I = 10 µA
V
O
I
I
I
Logical “1” Input Current
Logical “0” Input Current
3-STATE Leakage Current
= 15V, V = 15V
0.005
−0.005
0.005
−0.005
0.05
µA
µA
µA
µA
µA
IN(1)
IN(0)
OZ
IN
= 15V, V = 0V
−1.0
−1.0
IN
= 15V, V = 15V
1.0
O
= 15V, V = 0V
O
I
Supply Current
= 15V
300
CC
CMOS/LPTTL INTERFACE
V
V
V
Logical “1” Input Voltage
Logical “0” Input Voltage
Logical “1” Output Voltage
V
V
V
V
V
= 4.75V
= 4.75V
V
V
− 1.5
V
V
V
V
V
IN(1)
CC
CC
CC
CC
CC
CC
0.8
0.4
IN(0)
= 4.75V, I = −360 µA
− 0.4
OUT(1)
O
CC
= 4.75V, I = −1.6 mA
2.4
O
V
Logical “0” Output Voltage
= 4.75V, I = 1.6 mA
O
OUT(0)
OUTPUT DRIVE (Short Circuit Current)
I
I
I
I
Output Source Current
V
= 5V, V = 0V
OUT
−12
−24
6
−24
−48
12
mA
mA
mA
mA
SOURCE
SOURCE
SINK
CC
T
= 25°C (Note 2)
A
Output Source Current
V
= 10V, V
= 0V
OUT
CC
T
= 25°C (Note 2)
A
Output Sink Current
(N-Channel)
V
= 5V, V
= V
CC
OUT CC
T
= 25°C (Note 2)
A
Output Sink Current
(N-Channel)
V
= 10V, V
= V
CC
24
48
SINK
CC
OUT
T
= 25°C (Note 2)
A
Note 2: These are peak output current capabilities. Continuous output current is rated at 12 mA max.
www.fairchildsemi.com
4
AC Electrical Characteristics (Note 3)
MM74C373, TA = 25°C, CL = 50 pF, t = t = 20 ns, unless otherwise noted
r
f
Symbol
, t
Parameter
Propagation Delay,
Conditions
Min
Typ
Max
Units
t
t
V
V
V
V
= 5V, C = 50 pF
165
70
330
140
390
170
ns
ns
ns
ns
pd0 pd1
CC
L
= 10V, C = 50 pF
LATCH ENABLE to Output
CC
L
= 5V, C = 150 pF
195
85
CC
CC
L
= 10V, C = 150 pF
L
, t
Propagation Delay Data
In to Output
pd0 pd1
LATCH ENABLE = V
CC
V
V
V
V
= 5V, C = 50 pF
155
70
310
140
370
170
ns
ns
ns
ns
CC
CC
L
= 10V, C = 50 pF
L
= 5V, C = 150 pF
185
85
CC
L
= 10V, C = 150 pF
CC
L
t
f
t
Minimum Set-Up Time Data In
to CLOCK/LATCH ENABLE
t
= 0 ns
HOLD
SET-UP
MAX
V
= 5V
70
35
140
70
ns
ns
CC
CC
V
= 10V
Maximum LATCH ENABLE
Frequency
V
V
V
= 5V
= 10V
5V
3.5
4.5
6.7
9.0
75
MHz
MHz
ns
CC
CC
CC
150
110
PWH
Minimum LATCH ENABLE
Pulse Width
V
V
= 10V
= 5V
55
ns
CC
t , t
NA
µs
r
f
CC
Maximum LATCH ENABLE
Rise and Fall Time
V
= 10V
NA
µs
CC
t
t
t
, t
Propagation Delay OUTPUT
DISABLE to High Impedance
State (from a Logic Level)
Propagation Delay OUTPUT
DISABLE to Logic Level
(from High Impedance State)
Transition Time
R
= 10k, C = 5 pF
1H 0H
L
L
V
V
= 5V
105
60
210
120
ns
ns
CC
CC
= 10V
, t
R
= 10k, C = 50 pF
H1 H0
L
L
V
V
V
V
V
V
= 5V
105
45
210
90
ns
ns
ns
ns
ns
ns
pF
CC
CC
CC
CC
CC
CC
= 10V
, t
= 5V, C = 50 pF
65
130
70
THL TLH
L
= 10V, C = 50 pF
35
L
= 5V, C = 150 pF
110
70
220
140
10
L
= 10V, C = 150 pF
L
C
C
Input Capacitance
Input Capacitance
7.5
LE
LE Input (Note 4)
OUTPUT DISABLE
Input (Note 4)
7.5
10
pF
OD
C
C
Input Capacitance
Output Capacitance
Any Other Input (Note 4)
High Impedance
5
7.5
15
pF
pF
IN
10
OUT
State (Note 4)
C
Power Dissipation Capacitance
Per Package (Note 5)
200
pF
PD
Note 3: AC Parameters are guaranteed by DC correlated testing.
Note 4: Capacitance is guaranteed by periodic testing.
Note 5: C determines the no load AC power consumption of any CMOS device. For complete explanation see Family Characteristics Application Note
PD
AN-90.
5
www.fairchildsemi.com
AC Electrical Characteristics (Note 6)
MM74C374, TA = 25°C, CL = 50 pF, t = t = 20 ns, unless otherwise noted
r
f
Symbol
Parameter
Propagation Delay,
CLOCK to Output
Conditions
= 5V, C = 50 pF
Min
Typ
Max
Units
t
t
, t
V
V
V
V
150
65
300
130
360
160
ns
ns
ns
ns
pd0 pd1
CC
CC
CC
CC
L
= 10V, C = 50 pF
L
= 5V, C = 150 pF
180
80
L
= 10V, C = 150 pF
L
Minimum Set-Up Time Data In
to CLOCK/LATCH ENABLE
t
= 0 ns
SET-UP
HOLD
V
= 5V
70
140
ns
CC
V
V
V
V
V
= 10V
35
70
50
7.0
10
70
ns
ns
CC
CC
CC
CC
CC
t
f
t
, t
Minimum CLOCK Pulse Width
Maximum CLOCK Frequency
= 5V
140
100
PWH PWL
= 10V
= 5V
ns
3.5
5
MHz
MHz
MAX
= 10V
, t
Propagation Delay OUTPUT
DISABLE to High Impedance
State (from a Logic Level)
Propagation Delay OUTPUT
DISABLE to Logic Level
(from High Impedance State)
Transition Time
R
= 10k, C = 50 pF
1H 0H
L
L
V
V
= 5V
105
60
210
120
ns
ns
CC
CC
= 10V
t
t
, t
R
= 10k, C = 50 pF
H1 H0
L
L
V
V
V
V
V
V
V
V
= 5V
105
45
210
90
ns
ns
ns
ns
ns
ns
µs
µs
pF
pF
CC
CC
CC
CC
CC
CC
CC
CC
= 10V
, t
= 5V, C = 50 pF
65
130
70
THL TLH
L
= 10V, C = 50 pF
35
L
= 5V, C = 150 pF
110
70
220
140
L
= 10V, C = 150 pF
L
t , t
Maximum CLOCK Rise
and Fall Time
= 5V
15
5
>2000
>2000
7.5
r
f
= 10V
C
C
Input Capacitance
Input Capacitance
CLOCK Input (Note 7)
OUTPUT DISABLE
Input (Note 7)
10
10
CLK
7.5
OD
C
C
Input Capacitance
Output Capacitance
Any Other Input (Note 7)
High Impedance
5
7.5
15
pF
pF
IN
10
OUT
State (Note 7)
C
Power Dissipation Capacitance
Per Package (Note 8)
250
pF
PD
Note 6: AC Parameters are guaranteed by DC correlated testing.
Note 7: Capacitance is guaranteed by periodic testing.
Note 8: C determines the no load AC power consumption of any CMOS device. For complete explanation see Family Characteristics Application Note
PD
AN-90.
www.fairchildsemi.com
6
Typical Performance Characteristics
MM74C373
Propagation Delay, LATCH ENABLE to Output vs
Load Capacitance
MM74C373, MM74C374
Change in Propagation Delay
per pF of Load Capacitance
(∆tPD/pF) vs Power Supply Voltage
MM74C373
Propagation Delay, Data In to Output
vs Load Capacitance
MM74C373, MM74C374
Output Sink Current vs VOUT
MM74C373
Propagation Delay, CLOCK to Output
vs Load Capacitance
MM74C373, MM74C374
Source Current vs VCC − VOUT
7
www.fairchildsemi.com
Typical Applications
Data Bus Interfacing Element
Simple, Latching, Octal, LED Indicator
Driver with Blanking for Use as Data Display,
Bus Monitor, µP Front Panel Display, Etc.
3-STATE Test Circuits and Switching Time Waveforms
t1H, tH1
t0H, tH0
t1H, CL = 5 pF
t0H, CL = 5 pF
tH1, CL = 50 pF
tH0, CL = 50 pF
www.fairchildsemi.com
8
Switching Time Waveforms
MM74C373
Output Disable = GND
MM74C374
Output Disable = GND
9
www.fairchildsemi.com
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013. 0.300” Wide
Package Number M20B
www.fairchildsemi.com
10
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Package Number N20A
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
相关型号：
MM74C373N_NL
Bus Driver, CMOS Series, 1-Func, 8-Bit, True Output, CMOS, PDIP20, 0.300 INCH, LEAD FREE, PLASTIC, MS-001, DIP-20
FAIRCHILD
MM74C373WM
Bus Driver, CMOS Series, 1-Func, 8-Bit, True Output, CMOS, PDSO20, PLASTIC, SO-20
FAIRCHILD
MM74C373WMX
Bus Driver, CMOS Series, 1-Func, 8-Bit, True Output, CMOS, PDSO20, PLASTIC, SO-20
FAIRCHILD
©2020 ICPDF网 联系我们和版权申明