MM74C74N [FAIRCHILD]
Dual D-Type Flip-Flop; 双D型触发器
| 型号： | MM74C74N |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Dual D-Type Flip-Flop |
| 文件： | 总7页 (文件大小：72K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
October 1987
Revised January 1999
MM74C74
Dual D-Type Flip-Flop
■ High noise immunity: 0.45 VCC (typ.)
General Description
■ Low power: 50 nW (typ.)
The MM74C74 dual D-type flip-flop is a monolithic comple-
mentary MOS (CMOS) integrated circuit constructed with
N- and P-channel enhancement transistors. Each flip-flop
has independent data, preset, clear and clock inputs and Q
and Q outputs. The logic level present at the data input is
transferred to the output during the positive going transition
of the clock pulse. Preset or clear is independent of the
clock and accomplished by a low level at the preset or clear
input.
■ Medium speed operation: 10 MHz (typ.) with 10V
supply
Applications
•
•
•
•
•
•
•
•
Automotive
Data terminals
Instrumentation
Medical electronics
Alarm system
Features
■ Supply voltage range: 3V to 15V
■ Tenth power TTL compatible: Drive 2 LPT2L loads
Industrial electronics
Remote metering
Computers
Ordering Code:
Order Number Package Number
Package Description
MM74C74M
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
MM74C74N
N14A
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Truth Table
Pin Assignments for DIP and SOIC
Preset
Clear
Qn
Q n
0
0
1
1
0
1
0
1
0
1
0
0
0
1
Qn (Note 1) Qn (Note 1)
Note 1: No change in output from previous state.
Note: A logic “0” on clear sets Q to logic “0”.
A logic “0” on preset sets Q to logic “1”.
Top View
© 1999 Fairchild Semiconductor Corporation
DS005885.prf
www.fairchildsemi.com
Logic Diagram
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2
Absolute Maximum Ratings(Note 2)
Voltage at Any Pin (Note 2)
Operating Temperature Range
Storage Temperature Range
Power Dissipation
−0.3V to VCC +0.3V
−40°C to +85°C
−65°C to +150°C
Dual-In-Line
700 mW
500 mW
Note 2: “Absolute Maximum Ratings” are those values beyond which the
safety of the device cannot be guaranteed. Except for “Operating Tempera-
ture Range” they are not meant to imply that the devices should be oper-
ated at these limits. The table of “Electrical Characteristics” provides
conditions for actual device operation.
Small Outline
Lead Temperature
(Soldering, 10 seconds)
Operating VCC Range
VCC (Max)
260°C
3V to 15V
18V
DC Electrical Characteristics
Min/Max limits apply across temperature range unless otherwise noted
Symbol
Parameter
Conditions
Min
Typ
Max
Units
CMOS TO CMOS
V
V
V
V
Logical “1” Input Voltage
Logical “0” Input Voltage
Logical “1” Output Voltage
Logical “0” Output Voltage
V
V
V
V
V
V
V
V
V
V
V
= 5V
3.5
80
V
V
IN(1)
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
= 10V
= 5V
1.5
2.0
V
IN(0)
= 10V
= 5V
V
4.5
9.0
V
OUT(1)
OUT(0)
= 10V
= 5V
V
0.5
1.0
1.0
V
= 10V
= 15V
= 15V
= 15V
V
I
I
I
Logical “1” Input Current
Logical “0” Input Current
Supply Current
µA
µA
µA
IN(1)
IN(0)
CC
−1.0
0.05
60
CMOS/LPTTL INTERFACE
V
V
V
V
Logical “1” Input Voltage
Logical “0” Input Voltage
Logical “1” Output Voltage
Logical “0” Output Voltage
V
V
V
V
= 4.75V
= 4.75V
V
−1.5
IN(1)
CC
CC
CC
CC
CC
0.8
0.4
V
V
V
IN(0)
= 4.75V, I = −360 µA
2.4
OUT(1)
OUT(0)
D
= 4.75V, I = 360 µA
D
OUTPUT DRIVE (See Family Characteristics Data Sheet)
I
I
I
I
Output Source Current
Output Source Current
Output Sink Current
Output Sink Current
V
= 5V, V
IN(0)
= 0V
= 0V
−1.75
−8.0
1.75
8.0
mA
mA
mA
mA
SOURCE
SOURCE
SINK
CC
T
= 25°C, V
OUT
A
V
= 10V, V
= 0V
= 0V
CC
IN(0)
OUT
T
= 25°C, V
A
V
= 5V, V
= 5V
CC
IN(1)
T
= 25°C, V
= V
A
OUT CC
V
= 10V, V
= 10V
SINK
CC
IN(1)
OUT
T
= 25°C, V
= V
A
CC
3
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AC Electrical Characteristics (Note 3)
T
A = 25°C, C = 50 pF, unless otherwise noted
L
Symbol
Parameter
Input Capacitance
Propagation Delay Time to a
Logical “0” t or Logical “1”
Conditions
Any Input (Note 4)
Min
Typ
Max
Units
C
5.0
180
70
pF
ns
ns
IN
t
V
= 5V
300
pd
CC
CC
V
= 10V
110
pd0
t
from Clock to Q or Q
pd1
t
t
t
t
t
t
Propagation Delay Time to a
Logical “0” from Preset or Clear
Propagation Delay Time to a
Logical “1” from Preset or Clear
Time Prior to Clock Pulse that
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
= 5V
180
70
300
110
400
150
ns
ns
pd
pd
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
= 10V
= 5V
250
100
50
ns
= 10V
= 5V
ns
, t
100
40
ns
S0 S1
Data Must be Present t
= 10V
= 5V
20
ns
SETUP
, t
Time after Clock Pulse that
Data Must be Held
−20
−8.0
100
40
0
ns
H0 H1
= 10V
= 5V
0
ns
Minimum Clock Pulse
250
100
160
70
ns
PW1
PW2
Width (t = t
)
= 10V
= 5V
ns
WL WH
Minimum Preset and
Clear Pulse Width
100
40
ns
= 10V
= 5V
ns
t , t
Maximum Clock Rise
and Fall Time
15.0
5.0
µs
r
f
= 10V
= 5V
µs
f
Maximum Clock Frequency
2.0
5.0
3.5
8.0
40
MHz
MHz
pF
MAX
= 10V
C
Power Dissipation Capacitance
(Note 5)
PD
Note 3: AC Parameters are guaranteed by DC correlated testing.
Note 4: Capacitance is guaranteed by periodic testing.
Note 5: C determines the no load AC power consumption of any CMOS device. For complete explanation see Family Characteristics Application Note—
PD
AN-90.
Typical Applications
Ripple Counter (Divide by 2n)
74C Compatibility
Guaranteed Noise Margin as a Function of VCC
Shift Register
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4
Switching Time Waveform
CMOS to CMOS
t
= t = 20 ns
f
r
AC Test Circuit
5
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Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow
Package Number M14A
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6
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Package Number N14A
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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