MM74C927N [FAIRCHILD]
4-Digit Counters with Multiplexed; 4位计数器与复用型号: | MM74C927N |
厂家: | FAIRCHILD SEMICONDUCTOR |
描述: | 4-Digit Counters with Multiplexed |
文件: | 总9页 (文件大小:100K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
October 1987
Revised January 1999
MM74C925 • MM74C926 • MM74C927 • MM74C928
4-Digit Counters with Multiplexed
7-Segment Output Drivers
back LOW only when the counter is reset. Thus, this is a
3½-digit counter.
General Description
The MM74C925, MM74C926, MM74C927 and MM74C928
CMOS counters consist of a 4-digit counter, an internal out-
put latch, NPN output sourcing drivers for a 7-segment dis-
play, and an internal multiplexing circuitry with four
multiplexing outputs. The multiplexing circuit has its own
free-running oscillator, and requires no external clock. The
counters advance on negative edge of clock. A HIGH sig-
nal on the Reset input will reset the counter to zero, and
reset the carry-out LOW. A LOW signal on the Latch
Enable input will latch the number in the counters into the
internal output latches. A HIGH signal on Display Select
input will select the number in the counter to be displayed;
a LOW level signal on the Display Select will select the
number in the output latch to be displayed.
Features
■ Wide supply voltage range: 3V to 6V
■ Guaranteed noise margin: 1V
■ High noise immunity: 0.45 VCC (typ.)
■ High segment sourcing current: 40 mA
@ VCC − 1.6V, VCC = 5V
■ Internal multiplexing circuitry
Design Considerations
Segment resistors are desirable to minimize power dissipa-
tion and chip heating. The DS75492 serves as a good digit
driver when it is desired to drive bright displays. When
using this driver with a 5V supply at room temperature, the
display can be driven without segment resistors to full illu-
mination. The user must use caution in this mode however,
to prevent overheating of the device by using too high a
supply voltage or by operating at high ambient tempera-
tures.
The MM74C925 is a 4-decade counter and has Latch
Enable, Clock and Reset inputs.
The MM74C926 is like the MM74C925 except that it has a
display select and a carry-out used for cascading counters.
The carry-out signal goes HIGH at 6000, goes back LOW
at 0000.
The MM74C927 is like the MM74C926 except the second
most significant digit divides by 6 rather than 10. Thus, if
the clock input frequency is 10 Hz, the display would read
tenths of seconds and minutes (i.e., 9:59.9).
The input protection circuitry consists of a series resistor,
and a diode to ground. Thus input signals exceeding VCC
will not be clamped. This input signal should not be allowed
to exceed 15V.
The MM74C928 is like the MM74C926 except the most sig-
nificant digit divides by 2 rather than 10 and the carry-out is
an overflow indicator which is HIGH at 2000, and it goes
Ordering Code:
Order Number Package Number
Package Description
MM74C925N
MM74C926N
MM74C927N
MM74C928N
N16E
N18A
N18A
N18A
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
18-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
18-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
18-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
© 1999 Fairchild Semiconductor Corporation
DS005919.prf
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Connection Diagrams
Pin Assignments for DIP
Top View
MM74C925
Top View
MM74C926, MM74C927, MM74C928
Functional Description
Reset
— Asynchronous, active high
Segment Output — Current sourcing with 40 mA @VOUT
=
=
V
CC − 1.6V (typ.) Also, sink capability = 2
Display Select — High, displays output of counter
Low, displays output of latch
LTTL loads
Digit Output — Current sourcing with 1 mA @VOUT
1.75V. Also, sink capability = 2 LTTL loads
Carry-Out — 2 LTTL loads. See carry-out waveforms.
Latch Enable — High, flow through condition
Low, latch condition
Clock
—Negative edge sensitive
Logic Diagrams
MM74C925
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2
Logic Diagrams (Continued)
MM74C926
MM74C927
MM74C928
3
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Operating VCC Range
VCC
3V to 6V
6.5V
Absolute Maximum Ratings(Note 1)
Voltage at Any Output Pin
Voltage at Any Input Pin
Operating Temperature
Range (TA)
GND − 0.3V to VCC + 0.3V
GND − 0.3V to +15V
Lead Temperature
(Soldering, 10 seconds)
260°C
−40°C to +85°C
Note 1: “Absolute Maximum Ratings” are those values beyond which the
safety of the device cannot be guaranteed. Except for “Operating Tempera-
ture Range” they are not meant to imply that the devices should be oper-
ated at these limits. The Electrical Characteristics table provides conditions
for actual device operation.
Storage Temperature
Range
−65°C to +150°C
Power Dissipation (PD)
Refer to PD(MAX) vs TA Graph
DC Electrical Characteristics
Min/Max limits apply at −40°C ≤ t ≤ + 85°C, unless otherwise noted
j
Symbol
Parameter
Conditions
Min
Typ
Max
Units
CMOS TO CMOS
V
V
V
Logical “1” Input Voltage
Logical “0” Input Voltage
Logical “1” Output Voltage
(Carry-Out and Digit Output
Only)
V
V
V
= 5V
= 5V
3.5
V
V
IN(1)
CC
CC
CC
1.5
IN(0)
= 5V, I = −10 µA
OUT(1)
O
4.5
V
V
Logical “0” Output Voltage
Logical “1” Input Current
Logical “0” Input Current
Supply Current
V
V
V
V
V
= 5V, I = 10 µA
0.5
1
V
OUT(0)
IN(1)
IN(0)
CC
CC
CC
CC
CC
O
I
I
I
= 5V, V = 15V
0.005
−0.005
20
µA
µA
µA
IN
= 5V, V = 0V
−1
IN
= 5V, Outputs Open Circuit,
1000
= 0V or 5V
IN
CMOS/LPTTL INTERFACE
V
V
V
Logical “1” Input Voltage
Logical “0” Input Voltage
Logical “1” Output Voltage
(Carry-Out and Digit
V
V
V
= 4.75V
= 4.75V
= 4.75V,
V − 2
CC
V
V
IN(1)
CC
CC
CC
0.8
IN(0)
OUT(1)
I
= −360 µA
2.4
V
V
O
Output Only)
V
Logical “0” Output Voltage
V
= 4.75V, I = 360 µA
0.4
OUT(0)
CC
O
OUTPUT DRIVE
V
Output Voltage (Segment
Sourcing Output)
I
= −65 mA, V = 5V, T = 25°C
V
− 2
V
V
V
− 1.3
V
V
OUT
OUT
CC
j
CC
CC
CC
CC
I
= −40 mA, V = 5V T = 100°C
V − 1.6
CC
− 1.2
− 1.4
OUT
CC
j
T = 150°C
V
− 2
CC
V
j
R
Output Resistance (Segment
Sourcing Output)
I
= −65 mA, V = 5V, T = 25°C
20
32
40
50
0.8
Ω
ON
OUT
CC
j
I
= −40 mA, V = 5V T = 100°C
30
35
Ω
OUT
CC
j
T = 150°C
Ω
j
Output Resistance (Segment
Output) Temperature Coefficient
Output Source Current
(Digit Output)
0.6
%/°C
I
V
V
V
= 4.75V, V
= 1.75V, T = 150°C
−1
−2
−3.3
3.6
mA
mA
mA
SOURCE
CC
CC
CC
OUT
j
I
I
Output Source Current
(Carry-Out)
= 5V, V
= 5V, V
= 0V, T = 25°C
−1.75
SOURCE
SINK
OUT
OUT
j
Output Sink Current
(All Outputs)
= V , T = 25°C
1.75
CC
j
θ
Thermal Resistance
MM74C925: (Note 2)
MM74C926, MM74C927, MM74C928
Note 2: θ measured in free-air with device soldered into printed circuit board.
75
70
100
90
°C/W
°C/W
jA
jA
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4
AC Electrical Characteristics (Note 3)
TA = 25°C, CL = 50 pF, unless otherwise noted
Symbol
Parameter
Conditions
T = 25°C
Min
Typ
Max
Units
f
Maximum Clock Frequency
V
= 5V,
2
4
3
MHz
MHz
µs
MAX
CC
j
Square Wave Clock T = 100°C
1.5
j
t , t
Maximum Clock Rise or Fall Time
Reset Pulse Width
V
V
= 5V
= 5V
15
r
f
CC
CC
t
t
t
t
t
f
T = 25°C
250
320
250
320
2500
3200
0
100
125
ns
WR
j
T = 100°C
ns
j
Latch Enable Pulse Width
V
V
V
V
V
= 5V
= 5V
= 5V
= 5V
= 5V
T = 25°C
100
ns
WLE
CC
CC
CC
CC
CC
j
T = 100°C
125
ns
j
Clock to Latch Enable Set-Up Time
Latch Enable to Reset Wait Time
Reset to Latch Enable Set-Up Time
T = 25°C
1250
1600
−100
−100
160
ns
SET(CK, LE)
LR
j
T = 100°C
ns
j
T = 25°C
ns
j
T = 100°C
0
ns
j
T = 25°C
320
400
1000
5
ns
SET(R, LE)
j
T = 100°C
200
ns
j
Multiplexing Output Frequency
Input Capacitance
Hz
pF
MUX
C
Any Input (Note 4)
IN
Note 3: AC Parameters are guaranteed by DC correlated testing.
Note 4: Capacitance is guaranteed by periodic testing.
Typical Performance Characteristics
Typical Segment Current
vs Output Voltage
Maximum Power Dissipation
vs Ambient Temperature
Note: V = Voltage across digit driver
D
Typical Average Segment
Current vs Segment
Resistor Value
5
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Typical Performance Characteristics (Continued)
Segment Output Driver
Input Protection
Common Cathode LED Display
Segment Identification
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6
Switching Time Waveforms
Input Waveforms
Multiplexing Output Waveforms
T = 1/f
MUX
Carry-Out Waveforms
7
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Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Package Number N16E
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8
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
18-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Package Number N18A
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DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
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which, (a) are intended for surgical implant into the
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to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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