MM74HC126MX [FAIRCHILD]
Bus Driver, HC/UH Series, 4-Func, 1-Bit, True Output, CMOS, PDSO14, 0.150 INCH, MS-012, SOIC-14;
| 型号： | MM74HC126MX |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Bus Driver, HC/UH Series, 4-Func, 1-Bit, True Output, CMOS, PDSO14, 0.150 INCH, MS-012, SOIC-14 |
| 文件： | 总8页 (文件大小：90K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
September 1983
Revised January 2005
MM74HC125/MM74HC126
3-STATE Quad Buffers
General Description
Features
The MM74HC125 and MM74HC126 are general purpose
3-STATE high speed non-inverting buffers utilizing
advanced silicon-gate CMOS technology. They have high
drive current outputs which enable high speed operation
even when driving large bus capacitances. These circuits
possess the low power dissipation of CMOS circuitry, yet
have speeds comparable to low power Schottky TTL cir-
cuits. Both circuits are capable of driving up to 15 low
power Schottky inputs.
■ Typical propagation delay: 13 ns
■ Wide operating voltage range: 2–6V
■ Low input current: 1 µA maximum
■ Low quiescent current: 80 µA maximum (74HC)
■ Fanout of 15 LS-TTL loads
The MM74HC125 require the 3-STATE control input C to
be taken high to put the output into the high impedance
condition, whereas the MM74HC126 require the control
input to be low to put the output into high impedance.
All inputs are protected from damage due to static dis-
charge by diodes to VCC and ground.
Ordering Code:
Package
Order Number
Package Description
Number
MM74HC125M
M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
M14D Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HC125SJ
MM74HC125MTC
MM74HC125MTCX-NL
Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
MM74HC125N
N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
M14A Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
M14D Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HC126M
MM74HC126MX_NL
MM74HC126SJ
MM74HC126MTC
MM74HC126MTCX_NL MTC14 Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
MM74HC126N
N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. (Tape and Reel not available in N14A.)
Pb-Free package per JEDEC J-STD-020B.
© 2005 Fairchild Semiconductor Corporation
DS005308
www.fairchildsemi.com
Connection Diagrams
Pin Assignments for DIP, SOIC, SOP and TSSOP
Top View (MM74HC125)
Top View (MM74HC126)
Truth Tables
Inputs
Output
Inputs
Output
A
H
L
C
L
Y
H
L
A
H
L
C
H
H
L
Y
H
L
L
X
H
Z
X
Z
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2
Absolute Maximum Ratings(Note 1)
(Note 2)
Recommended Operating
Conditions
Supply Voltage (VCC
DC Input Voltage (VIN
DC Output Voltage (VOUT
Clamp Diode Current (IIK, IOK
)
−0.5 to +7.0V
−1.5 to VCC +1.5V
−0.5 to VCC +0.5V
±20 mA
Min Max Units
)
Supply Voltage (VCC
DC Input or Output Voltage
(VIN, VOUT
)
2
0
6
V
V
)
VCC
)
)
DC Output Current, per pin (IOUT
)
±35 mA
Operating Temperature Range (TA)
Input Rise or Fall Times (tr, tf)
−40 +85
°C
DC VCC or GND Current, per pin
(ICC
)
±70 mA
V
V
V
CC = 2.0V
CC = 4.5V
CC = 6.0V
1000 ns
Storage Temperature Range (TSTG
Power Dissipation (PD)
(Note 3)
)
−65°C to +150°C
500
400
ns
ns
600 mW
500 mW
Note 1: Absolute Maximum Ratings are those values beyond which dam-
age to the device may occur.
S.O. Package only
Note 2: Unless otherwise specified all voltages are referenced to ground.
Lead Temperature (TL)
(Soldering 10 seconds)
Note 3: Power Dissipation temperature derating — plastic “N” package: −
12 mW/°C from 65°C to 85°C.
260°C
DC Electrical Characteristics (Note 4)
T
A = 25°C
T
A = −40 to 85°C TA = −40 to 125°C
VCC
Symbol
Parameter
Conditions
Units
Typ
Guaranteed Limits
VIH
Minimum HIGH Level
Input Voltage
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
1.5
1.5
3.15
4.2
1.5
3.15
4.2
0.5
1.35
1.8
1.9
4.4
5.9
V
V
V
V
V
V
V
V
V
3.15
4.2
VIL
Maximum LOW Level
Input Voltage
0.5
0.5
1.35
1.8
1.35
1.8
VOH
Minimum HIGH Level
Output Voltage
V
IN = VIH or VIL
2.0
4.5
6.0
1.9
1.9
|IOUT| ≤ 20 µA
4.4
4.4
5.9
5.9
VIN = VIH or VIL
|IOUT| ≤ 6.0 mA
|IOUT| ≤ 7.8 mA
4.5V
6.0V
2.0V
4.5V
6.0V
4.2
5.7
0
3.98
5.48
0.1
3.84
5.34
0.1
3.7
5.2
0.1
0.1
0.1
V
V
V
V
V
VOL
Maximum LOW Level
Output Voltage
VIN = VIH or VIL
|IOUT| ≤ 20 µA
0
0.1
0.1
0
0.1
0.1
VIN = VIH or VIL
|IOUT| ≤ 6.0 mA
|IOUT| ≤ 7.8 mA
4.5V
6.0V
6.0V
0.2
0.2
0.26
0.26
±0.5
0.33
0.33
±5
0.4
0.4
±10
V
V
IOZ
Maximum 3-STATE Output
Leakage Current
VIN = VIH or VIL
µA
VOUT = VCC or GND
Cn = Disabled
IIN
Maximum Input Current
Maximum Quiescent
Supply Current
V
IN = VCC or GND
IN = VCC or GND
6.0V
6.0V
±0.1
±1.0
±1.0
µA
µA
ICC
V
8.0
80
160
I
OUT = 0 µA
Note 4: For a power supply of 5V ±10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when
designing with this supply. Worst case VIH and VIL occur at VCC=5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current
(IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used.
3
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AC Electrical Characteristics
V
CC = 5V, TA = 25°C, CL = 45 pF, tr = tf = 6 ns
Guaranteed
Limit
Symbol Parameter
Conditions
Typ
Units
tPHL, tPLH
Maximum
13
18
25
25
25
25
ns
Propagation Delay Time
Maximum
tPZH
R
L = 1 kΩ
13
17
18
13
ns
ns
ns
ns
Output Enable Time to HIGH Level
Maximum
tPHZ
RL = 1 kΩ
CL = 5 pF
RL = 1 kΩ
Output Disable Time from HIGH Level
Maximum
tPZL
Output Enable Time to LOW Level
Maximum
tPLZ
R
L = 1 kΩ
L = 5 pF
Output Disable Time from LOW Level
C
AC Electrical Characteristics
V
CC = 2.0V to 6.0V, CL = 50 pF, tr = tf = 6 ns (unless otherwise specified)
TA = 25°C
T
A = −40 to 85°C TA = −40 to 125°C
VCC
Symbol
Parameter
Conditions
Units
Typ
40
14
12
35
14
12
25
14
12
25
14
12
35
15
13
30
7
Guaranteed Limits
t
PHL, tPLH Maximum Propagation
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
100
20
125
25
150
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
pF
Delay Time
17
21
25
tPLH, tPHL Maximum Propagation
C
R
R
L = 150 pF
130
26
163
33
195
39
Delay Time
22
28
39
tPZH, tPZL Maximum Output
L = 1 kΩ
L = 1 kΩ
125
25
156
31
188
38
Enable Time
21
26
31
tPHZ, tPLZ Maximum Output
125
25
156
31
188
38
Disable Time
21
26
31
tPZL, tPZH Maximum Output
C
L = 150 pF
L = 1 kΩ
140
28
175
35
210
42
Enable Time
R
24
30
36
tTLH, tTHL Maximum Output
Rise and Fall Time
CL = 50 pF
60
75
90
12
15
18
6
10
13
15
CIN
Input Capacitance
5
10
10
10
COUT
CPD
Output Capacitance Outputs
Power Dissipation
15
20
20
20
(per gate)
Enabled
Disabled
Capacitance (Note 5)
45
6
pF
pF
Note 5: CPD determines the no load dynamic power consumption, PD = CPD VCC2f + ICC VCC, and the no load dynamic current consumption,
S = CPD VCC f + ICC
I
.
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4
Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrowy
Package Number M14A
5
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M14D
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6
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC14
7
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package Number N14A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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8
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