SG5841SZ-F116 [FAIRCHILD]
Switching Regulator/Controller;
| 型号： | SG5841SZ-F116 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Switching Regulator/Controller |
| 文件： | 总15页 (文件大小：453K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
October 2008
SG5841J — Highly Integrated Green-Mode PWM
Controller
Features
Description
The highly integrated SG5841/J series of PWM
controllers provides several features to enhance the
performance of flyback converters.
Green-Mode PWM Controller
Low Startup Current : 14µA
Low Operating Current: 4mA
To minimize standby power consumption, a proprietary
green-mode function provides off-time modulation to
continuously decrease the switching frequency at light-
load conditions. This green-mode function enables the
power supply to meet international power conservation
requirements. To further reduce power consumption,
SG5841/J is manufactured using the BiCMOS process.
This allows a low startup current, around 14µA, and an
operating current of only 4mA. As a result, a large
startup resistance can be used.
Programmable PWM Frequency with Hopping
Peak-Current-Mode Control
Cycle-by-Cycle Current Limiting
Synchronized Slope Compensation
Leading-Edge Blanking (LEB)
Constant Output Power Limit
Totem Pole Output with Soft Driving
VDD Over-Voltage Clamping
The built-in synchronized slope compensation achieves
stable peak-current-mode control. The proprietary
internal sawtooth power-limiter ensures a constant
output power limit over a wide range of AC input
Programmable Over-Temperature Protection (OTP)
Internal Open-Loop Protection
voltages, from 90VAC to 264VAC
.
SG5841/J provides many protections. In addition to
cycle-by-cycle current limiting, the internal open-loop
protection circuit ensures safety should an open-loop or
output-short-circuit failure occur. PWM output is
disabled until VDD drops below the UVLO lower limit,
then the controller restarts. An external NTC thermistor
can be applied for over-temperature protection.
VDD Under-Voltage Lockout (UVLO)
GATE Output Maximum Voltage Clamp:18V
Applications
General-purpose, switch-mode, power supplies and
flyback power converters, including:
SG5841/J is available in an 8-pin DIP or SOP package.
Power Adapters
Open-Frame SMPS
Ordering Information
Ambient Operating Frequency
Temperature Range Hopping
Eco
Status
Part Number
Package
SG5841JSZ
SG5841JSY
SG5841JDZ
SG5841SZ
SG5841SY
SG5841DZ
-20 to +85°C
-20 to +85°C
-20 to +85°C
-20 to +85°C
-20 to +85°C
-20 to +85°C
Yes
Yes
Yes
No
RoHS
Green
RoHS
RoHS
Green
RoHS
8-Pin Small Outline Package (SOP)
8-Pin Small Outline Package (SOP)
8-Pin Dual Inline Package (DIP)
8-Pin Small Outline Package (SOP)
8-Pin Small Outline Package (SOP)
8-Pin Dual Inline Package (DIP)
No
No
For Fairchild’s definition of “green” Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html.
© 2006 Fairchild Semiconductor Corporation
SG5841J • Rev. 1.3.4
www.fairchildsemi.com
Typical Application
Figure 1. Application Diagram
Block Diagram
Figure 2. Block Diagram
© 2006 Fairchild Semiconductor Corporation
SG5841J • Rev. 1.3.4
www.fairchildsemi.com
2
Marking Information
H: J = with Frequency Hopping
Null = without Frequency Hopping
T: D = DIP, S = SOP
SG5841HTP
P:Z = Lead Free
XXXX XXXXYWW
Null = regular package
XXXXXXXX : Wafer Lot
: Week
Y: Year; WW
marking for SG5841JSZ (pb-free)
marking for SG5841JDZ (pb-free)
marking for SG5841SZ (pb-free)
marking for SG5841DZ (pb-free)
V: Assembly Location
F: Fairchild Logo
Z:Plant Code
X:1 Digit Year Code
ZXYTT
5841/J
TPM
Y:1 Digit Week Code
TT:2 Digit Die Run Code
T: Package Type (D:DIP, S:SOP)
P:Y = Green Package
M:Manufacturing Flow Code
marking for SG5841JSY (green-compound)
marking for SG5841SY (green-compound)
Figure 3. Top Mark
© 2006 Fairchild Semiconductor Corporation
SG5841J • Rev. 1.3.4
www.fairchildsemi.com
3
Pin Configuration
GND
FB
GATE
VDD
VIN
RI
SENSE
RT
Figure 4. Pin Configuration
Pin Definitions
Pin # Name Function
Description
1
GND
Ground
Ground.
The signal from the external compensation circuit is fed into this pin. The PWM
duty cycle is determined in response to the signal from this pin and the current-
sense signal from pin 6. If FB voltage exceeds the threshold, the internal
protection circuit disables PWM output after a predetermined delay time.
2
FB
Feedback
For startup, this pin is pulled HIGH to the rectified line input via a resistor. Since
3
4
VIN
RI
Startup Input the startup current requirement is very small, a large startup resistance is used to
minimize power loss.
A resistor connected from the RI to GND provides a constant current source. This
determines the center PWM frequency. Increasing the resistance reduces PWM
Setting
Reference
frequency. Using a 26KΩ resistor results in a 65KHz center PWM frequency.
For over-temperature protection. An external NTC thermistor is connected from
Temperature this pin to the GND pin. The impedance of the NTC decreases at high
5
RT
Detection
temperatures. Once the voltage of the RT pin drops below a fixed limit, PWM
output is disabled.
Current
Sense
Current sense. The sensed voltage is used for peak-current-mode control and
cycle-by-cycle current limiting.
6
7
8
SENSE
VDD
Power
Supply
Power supply. If VDD exceeds a threshold, the internal protection circuit disables
PWM output.
The totem-pole output driver for the power MOSFET, which is internally clamped
below 18V.
GATE Driver Output
© 2006 Fairchild Semiconductor Corporation
SG5841J • Rev. 1.3.4
www.fairchildsemi.com
4
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device
reliability. The absolute maximum ratings are stress ratings only. All voltage values, except differential voltages, are
given with respect to GND pin.
Symbol
VDD
Parameter
Min.
Max.
30
Unit
V
Supply Voltage
Input Terminal
VIN
30
V
VFB
Input Voltage to FB Pin
Input Voltage to SENSE Pin
Input Voltage to RT Pin
Input Voltage to RI Pin
-0.3
-0.3
-0.3
-0.3
7.0
V
VSENSE
VRT
7.0
V
7.0
V
VRI
7.0
V
DIP
800
400
82.5
141
59.7
80.8
+125
+150
PD
Power Dissipation (TA < 50°C )
mW
°C/W
°C/W
SOP
DIP
ΘJA
ΘJC
Thermal Resistance (Junction-to-Air)
Thermal Resistance (Junction-to-Case)
SOP
DIP
SOP
TJ
Operating Junction Temperature
Storage Temperature Range
-40
-55
°C
°C
TSTG
Lead Temperature (Wave Soldering or Infrared,
10 Seconds)
TL
260
°C
Human Body Model, JESD22-A114
Charged Device Model, JESD22-C101
3
kV
V
ESD
250
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
Parameter
Min.
Max.
Unit
TA
Operating Ambient Temperatures
-20
+85
°C
© 2006 Fairchild Semiconductor Corporation
SG5841J • Rev. 1.3.4
www.fairchildsemi.com
5
Electrical Characteristics
VDD = 15V, TA = 25°C, unless otherwise noted.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
VDD Section
VDD-OP
VDD-ON
Continuously Operating Voltage
Start Threshold Voltage
24.7
17
V
V
15
9
16
10
14
VDD-OFF Minimum Operating Voltage
11
V
IDD-ST
IDD-OP
Startup Current
VDD=VDD-ON–0.16V
30
µA
VDD=15V, RI=26KΩ,
Operating Supply Current
4
5
mA
V
GATE=OPEN
VDD-CLAMP VDD Over-Voltage-Clamping Level
28
50
29
VDD Over-Voltage-Clamping
tD-VDDCLAMP
RI=26KΩ
100
200
µs
Debounce Time
RI Section
RINOR
RIMAX
RIMIN
RI Operating Range
15.5
36.0
KΩ
KΩ
KΩ
Maximum RI Value for Protection
Minimum RI Value for Protection
230
10
Oscillator Section
Center Frequency RI=26KΩ
62
65
68
Normal
fOSC
PWM
Frequency
KHz
RI=26KΩ
(SG5841J only)
Hopping Range
±3.7
±4.2
±4.7
RI=26KΩ
(SG5841J only)
tHOP
fOSC-G
fDV
Hopping Period
3.9
18
4.4
22
4.9
25
5
ms
KHz
%
Green-Mode Frequency
RI=26KΩ
Frequency Variation vs. VDD
Deviation
VDD=11.5V to 24.7V
Frequency Variation vs.
Temperature Deviation
5
fDT
%
TA=-20 to +85°C
Feedback Input Section
FB Input to Current Comparator
Attenuation
AV
1/3.75
1/3.20
1/2.75
7
V/V
ZFB
Input Impedance
4
5
KΩ
V
VFB-OPEN FB Output High Voltage
FB pin open
6
VFB-OLP
FB Open-Loop Trigger Level
4.2
4.5
4.8
32
V
Delay Time of FB Pin Open-Loop
Protection
tD-OLP
RI=26KΩ
26
29
ms
VFB-N
VFB-G
Green-Mode Entry FB Voltage
Green-Mode Ending FB Voltage
RI=26KΩ
RI=26KΩ
1.9
2.1
2.3
V
V
VFB-N-0.5
f
OSC
-GREEN
OSC
f
Figure 5. PWM Frequency
© 2006 Fairchild Semiconductor Corporation
SG5841J • Rev. 1.3.4
www.fairchildsemi.com
6
Electrical Characteristics (Continued)
VDD = 15V, TA = 25°C, unless otherwise noted.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
Current-Sense Section
ZSENSE Input Impedance
12
KΩ
Current Limit Flatten
VSTHFL
0.85
0.90
0.95
V
Threshold Voltage
Current Limit Valley
VSTHVA
VSTHFL–VSTHVA
0.22
150
270
V
Threshold Voltage
Propagation Delay to
GATE Output
tPD
RI=26KΩ
RI=26KΩ
200
350
ns
ns
Leading-Edge Blanking
Time
tLEB
200
60
GATE Section
DCYMAX Maximum Duty Cycle
VGATE-L Output Voltage Low
VGATE-H Output Voltage High
65
70
%
V
VDD=15V, IO=50mA
VDD=12.5V, IO=50mA
VDD=15V, CL=1nF
VDD=15V, CL=1nF
VDD=15V, GATE=6V
1.5
7.5
150
30
V
tr
tf
Rising Time
250
50
350
90
ns
ns
mA
Falling Time
IO
Peak Output Current
230
VGATE- Gate Output Clamping
VDD=24.7V
18
19
V
Voltage
CLAMP
RT Section
IRT
Output Current of RT Pin
RI=26KΩ
92
100
0.620
108
µA
V
Trigger Voltage for Over-
Temperature Protection
VRTTH
0.585
0.655
VRT-RLS OTP Release Voltage
VRTTH +0.03
100
V
Over-Temperature
tD-OTP
RI=26KΩ
60
140
µs
Debounce
© 2006 Fairchild Semiconductor Corporation
SG5841J • Rev. 1.3.4
www.fairchildsemi.com
7
Typical Performance Characteristics
30
26
22
18
14
10
5.0
4.5
4.0
3.5
3.0
2.5
-40 -25 -10
5
20
35
50
65
80
95 110 125
-40 -25 -10
5
20
35
50
65
80
95 110 125
Temperature (°C)
Temperature (°C)
Figure 6. Startup Current (IDD-ST) vs. Temperature
Figure 7. Operating Supply Current (IDD-OP
)
vs. Temperature
15
12
9
17.0
16.5
16.0
15.5
15.0
6
3
0
11
13
15
17
19
21
23
25
27
29
-40 -25 -10
5
20
35
50
65
80
95 110 125
Temperature (°C)
V
Voltage (V)
DD
Figure 8. Operating Current (IDD-OP
)
Figure 9. Start Threshold Voltage (VDD-ON
)
vs. VDD Voltage
vs. Temperature
11.0
10.5
10.0
9.5
68
67
66
65
64
63
62
9.0
-40 -25 -10
5
20
35
50
65
80
95 110 125
-40 -25 -10
5
20
35
50
65
80
95 110 125
Temperature (°C)
Temperature (°C)
Figure 10. Minimum Operating Voltage (VDD-ON
)
Figure 11. PWM Frequency (fOSC
)
vs. Temperature
vs. Temperature
© 2006 Fairchild Semiconductor Corporation
SG5841J • Rev. 1.3.4
www.fairchildsemi.com
8
Typical Performance Characteristics (Continued)
70
68
66
64
62
60
-40 -25 -10
5
20
35
50
65
80
95
110 125
Temperature (°C)
Figure 12. Maximum Duty Cycle (DCYMAX) vs. Temperature
0.66
0.65
0.64
0.63
0.62
0.61
0.60
0.59
0.58
-40 -25 -10
5
20
35
50
65
80
95
110 125
Temperature (°C)
Figure 13. Trigger Voltage for Over-Temperature Protection VRTTH vs. Temperature
108
104
100
96
92
-40 -25 -10
5
20
35
50
65
80
95 110 125
Temperature (°C)
Figure 14. Output Current of RT Pin (IRT) vs. Temperature
© 2006 Fairchild Semiconductor Corporation
SG5841J • Rev. 1.3.4
www.fairchildsemi.com
9
Functional Description
Startup Current
Leading-Edge Blanking (LEB)
Typical startup current is only 14µA, which allows a
high-resistance and low-wattage startup resistor to
minimize power loss. For an AC/DC adapter with
universal input range, a 1.5MΩ, 0.25W startup resistor
and a 10µF/25V VDD hold-up capacitor are enough for
this application.
Each time the power MOSFET is switched on, a turn-on
spike occurs at the sense-resistor. To avoid premature
termination of the switching pulse, a leading-edge
blanking time is built in. During this blanking period, the
current-limit comparator is disabled and cannot switch
off the gate drive.
Under-Voltage Lockout (UVLO)
Operating Current
The turn-on and turn-off thresholds are fixed internally
at 16V and 10V. During startup, the hold-up capacitor
must be charged to 16V through the startup resistor to
enable the IC. The hold-up capacitor continues to
supply VDD before the energy can be delivered from
auxiliary winding of the main transformer. VDD must not
drop below 10V during this startup process. This UVLO
hysteresis window ensures that hold-up capacitor is
adequate to supply VDD during startup.
Operating current is around 4mA. The low operating
current enables better efficiency and reduces the
requirement of VDD hold-up capacitance.
Green-Mode Operation
The proprietary green-mode function provides off-time
modulation to continuously decrease the PWM
frequency under light-load conditions. To avoid acoustic
noise problems, the minimum PWM frequency is set
above 22KHz. Green mode dramatically reduces power
consumption under light-load and zero-load conditions.
Power supplies using a SG5841/J controller can meet
restrictive international regulations regarding standby
power consumption.
Gate Output / Soft Driving
The SG5841/J BiCMOS output stage is a fast totem-
pole gate driver. Cross conduction has been avoided to
minimize heat dissipation, increase efficiency, and
enhance reliability. The output driver is clamped by an
internal 18V Zener diode to protect power MOSFET
transistors against undesirable gate over-voltage. A soft
driving waveform is implemented to minimize EMI.
Oscillator Operation
A resistor connected from the RI pin to the GND pin
generates a constant current source for the SG5841/J
controller. This current is used to determine the center
PWM frequency. Increasing the resistance reduces
PWM frequency. Using a 26KΩ resistor, RI, results in a
corresponding 65KHz PWM frequency. The relationship
between RI and the switching frequency is:
Built-in Slope Compensation
The sensed voltage across the current-sense resistor is
used for peak-current-mode control and pulse-by-pulse
current limiting. Built-in slope compensation improves
stability or prevents sub-harmonic oscillation. SG5841/J
inserts a synchronized, positive-going ramp at every
switching cycle.
1690
fPWM
=
(KHz)
(1)
R (KΩ)
I
Constant Output Power Limit
When the SENSE voltage across the sense resistor,
RS, reaches the threshold voltage, around 0.85V, the
output GATE drive is turned off after delay, tPD. This
The range of the PWM oscillation frequency is designed
as 47KHz ~ 109KHz.
SG5841J also integrates a frequency hopping function
internally. The frequency variation ranges from around
62KHz to 68KHz for a center frequency of 65KHz. The
frequency-hopping function helps reduce EMI emission
of a power supply with minimum line filters.
delay introduces additional current, proportional to tPD
•
VIN / LP. The delay is nearly constant, regardless of the
input voltage VIN. Higher input voltage results in larger
additional current and the output power limit is higher
than under low-input line voltage. To compensate this
variation for a wide AC input range, a sawtooth power-
limiter (saw limiter) is designed to solve the unequal
power-limit problem. The saw limiter is designed as a
positive ramp signal (Vlimit_ramp) and fed to the inverting
input of the OCP comparator. This results in a lower
current limit at high-line inputs than at low-line inputs.
Current Sensing / PWM Current Limiting
Peak-current-mode control is utilized in to regulate
output voltage and provide pulse-by-pulse current
limiting. The switch current is detected by a sense
resistor into the SENSE pin. The PWM duty cycle is
determined by this current-sense signal and the
feedback voltage. When the voltage on the SENSE pin
reaches around VCOMP = (VFB–1.0)/3.2, a switch cycle is
terminated immediately. VCOMP is internally clamped to a
variable voltage around 0.85V for output power limit.
VDD Over-Voltage Clamping
VDD over-voltage clamping prevents damage due to
abnormal conditions. If VDD voltage is over the VDD over-
voltage clamping voltage (VDD-CLAMP) and lasts for tD-
VDDCLAMP, the PWM pulses are disabled until the VDD
drops below the VDD over-voltage clamping voltage.
© 2006 Fairchild Semiconductor Corporation
SG5841J • Rev. 1.3.4
www.fairchildsemi.com
10
Thermal Protection
When VDD goes below the turn-off threshold (e.g. 10V)
the controller totally shuts down. VDD is charged up to
the turn-on threshold voltage of 16V through the startup
resistor until PWM output is restarted. This protection
remains activated as long as the overloading condition
persists. This prevents the power supply from
overheating due to overloading conditions.
An NTC thermistor RNTC in series with a resistor RA can
be connected from the RT pin to ground. A constant
current IRT is output from pin RT. The voltage on the RT
pin can be expressed as VRT = IRT × (RNTC + RA), in
which IRT = 2 x (1.3V / RI). At high ambient temperature,
RNTC is smaller, such that VRT decreases. When VRT is
less than 0.62V, the PWM is completely turned off.
Noise Immunity
Limited Power Control
Noise on the current-sense or control signal may cause
significant pulse-width jitter, particularly in the
continuous-conduction mode. Slope compensation
helps alleviate this problem. Good placement and
layout practices should be followed. Avoiding long PCB
traces and component leads, locating compensation
and filter components near SG5841/J, and increasing
power MOS gate resistance improve performance.
The FB voltage increases every time the output of the
power supply is shorted or overloaded. If the FB voltage
remains higher than a built-in threshold for longer than
t
D-OLP, PWM output is turned off. As PWM output is
turned off, the supply voltage VDD begins decreasing.
tD-OLP (ms) = 1.115 × R (KΩ)
(2)
I
© 2006 Fairchild Semiconductor Corporation
SG5841J • Rev. 1.3.4
www.fairchildsemi.com
11
Reference Circuit
Q1
F1
BD1
R1
R2
CN1
1
3
1
2
3
L3
L1
L2
2
1
2
C1
C2
T1
4
1
Vo+
D1
VZ1
TR1
R5
R7
R3
C3
D2
C4
D3
+
C7
+
+C8
C6
R4
C5
R6
D4
Q2
U1
GND GATE
1
8
7
6
5
1
R12
2
3
FB
VDD
R16
VIN SENSE
4
RI
RT
R11
R9
R10
SG5841/J
C9
+
C11
R8
THER2
U2
C12
R13
R
C10
R14
U3
VO+
R15
Figure 15. Reference Circuit
Reference
BOM
Reference
BD1
Component
Component
BD 4A/600V
Q2
MOS 7A/600V
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
D1
D2
D3
D4
F1
XC 0.68µF/300V
XC 0.1µF/300V
CC 0.01µF/500V
EC 120µ/400V
YC 222p/250V
CC 1000pF/100V
EC 1000µF/25V
EC 470µF/25V
EC 10µF/50V
R1, R2
R3
R 1MΩ 1/4W
R 100KW 1/2W
R 47Ω 1/4W
R 750KΩ 1/4W
R 2KΩ 1/8W
R 0.3Ω 2W
R4
R5, R7
R6
R8
R9
R 33KΩ 1/8W
R10
R11
R12
R13
R14
R15
R16
THER2
T1
R 4.7KΩ 1/8W 1%
R 470Ω 1/8W
R 0Ω 1/8W
CC 222pF/50V
CC 470pF/50V
CC 102pF/50V (Option)
LED
R 4.7KΩ 1/8W
R 154KΩ 1/8W
R 39KΩ 1/8W
R 100Ω 1/8W
Thermistor TTC104
Transformer (600µH-PQ2620)
IC SG5841/J
Diode BYV95C
TVS P6KE16A
Diode FR103
FUSE 4A/250V
Choke (900µH)
Choke (10mH)
Inductor (2µH)
Diode 20A/100V
U1
U2
IC PC817
L1
U3
IC TL431
L2
VZ1
VZ 9G
L3
Q1
© 2006 Fairchild Semiconductor Corporation
SG5841J • Rev. 1.3.4
www.fairchildsemi.com
12
Physical Dimensions
5.00
4.80
A
0.65
3.81
8
5
B
1.75
6.20
5.80
4.00
3.80
5.60
1
4
PIN ONE
INDICATOR
1.27
1.27
(0.33)
M
0.25
C B A
LAND PATTERN RECOMMENDATION
SEE DETAIL A
0.25
0.10
0.25
0.19
C
1.75 MAX
0.10
C
0.51
0.33
OPTION A - BEVEL EDGE
0.50
0.25
x 45°
R0.10
R0.10
GAGE PLANE
OPTION B - NO BEVEL EDGE
0.36
NOTES: UNLESS OTHERWISE SPECIFIED
8°
0°
0.90
A) THIS PACKAGE CONFORMS TO JEDEC
MS-012, VARIATION AA, ISSUE C,
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
FLASH OR BURRS.
SEATING PLANE
(1.04)
0.406
D) LANDPATTERN STANDARD: SOIC127P600X175-8M.
E) DRAWING FILENAME: M08AREV13
DETAIL A
SCALE: 2:1
Figure 16. 8-Pin Small Outline Package (SOP)
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify
or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically
the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2006 Fairchild Semiconductor Corporation
SG5841J • Rev. 1.3.4
www.fairchildsemi.com
13
Physical Dimensions (Continued)
9.83
9.00
6.67
6.096
8.255
7.61
3.683
3.20
7.62
5.08 MAX
0.33 MIN
3.60
3.00
(0.56)
2.54
0.356
0.20
0.56
0.355
9.957
7.87
1.65
1.27
7.62
NOTES: UNLESS OTHERWISE SPECIFIED
A) THIS PACKAGE CONFORMS TO
JEDEC MS-001 VARIATION BA
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS ARE EXCLUSIVE OF BURRS,
MOLD FLASH, AND TIE BAR EXTRUSIONS.
D) DIMENSIONS AND TOLERANC
ASME Y14.5M-1994
ES PER
E) DRAWING FILENAME AND REVSION: MKT-N08FREV2.
Figure 17. 8-Pin Dual Inline Package (DIP)
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify
or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically
the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2006 Fairchild Semiconductor Corporation
SG5841J • Rev. 1.3.4
www.fairchildsemi.com
14
© 2006 Fairchild Semiconductor Corporation
SG5841J • Rev. 1.3.4
www.fairchildsemi.com
15
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