SG5842A_09 [FAIRCHILD]
Highly Integrated Green-Mode PWM Controller; 高度集成绿色模式PWM控制器
| 型号： | SG5842A_09 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Highly Integrated Green-Mode PWM Controller |
| 文件： | 总15页 (文件大小：567K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
December 2009
SG5842A/SG5842JA — Highly Integrated Green-Mode
PWM Controller
Features
Description
The highly integrated SG5842A/JA series of PWM
controllers provides several features to enhance the
performance of flyback converters. To minimize standby
power consumption, a proprietary green-mode function
provides off-time modulation to continuously decrease
the switching frequency at light-load conditions. To
avoid acoustic-noise problems, the minimum PWM
frequency set above 22KHz. This green-mode function
enables the power supply to meet international power
conservation requirements. To further reduce power
consumption, SG5842A/JA is manufactured using the
BiCMOS process. This allows a low startup current,
around 14µA, and an operating current of only 4mA. As
a result, a large startup resistance can be used.
Green-Mode PWM Controller
Low Startup Current: 14µA
Low Operating Current: 4mA
Programmable PWM Frequency with Hopping
(SG5842JA)
Peak-Current-Mode Control
Cycle-by-Cycle Current Limiting
Synchronized Slope Compensation
Leading-Edge Blanking (LEB)
Constant Output Power Limit
The
compensation achieves stable peak-current-mode
control. SG5842JA integrates frequency-hopping
SG5842A/JA
built-in
synchronized
slope
Totem-Pole Output with Soft Driving
VDD Over-Voltage Protection (OVP)
Programmable Over-Temperature Protection (OTP)
Internal Latch Circuit (OTP, OVP)
Internal Open-Loop Protection
a
function that helps reduce EMI emission of a power
supply with minimum line filters.
SG5842A/JA provides many protection functions. In
addition to cycle-by-cycle current limiting, the internal
open-loop protection circuit ensures safety should an
open-loop or output short-circuit failure occur. PWM
output is disabled until VDD drops below the UVLO lower
limit, then the controller starts again. As long as VDD
exceeds about 24V, the internal OVP circuit is triggered.
An external NTC thermistor can be applied for over-
temperature protection.
VDD Under-Voltage Lockout (UVLO)
GATE Output Maximum Voltage Clamp: 18V
Applications
General-purpose switch-mode power supplies and
flyback power converters, including:
SG5842A/JA is available in an 8-pin DIP or SOP
package.
Notebook Power Adapters
Open-Frame SMPS
© 2007 Fairchild Semiconductor Corporation
SG5842A/SG5842JA • Rev. 1.4.3
www.fairchildsemi.com
Ordering Information
Operating
Part Number Temperature
Range
OTP
OVP Frequency
Eco
Status
Package
Latch Latch Hopping
SG5842JASZ -40°C to +105°C RoHS
SG5842JADZ -40°C to +105°C RoHS
SG5842JASY -40°C to +105°C Green
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
8-Pin Small Outline Package (SOP)
8-Pin Dual Inline Package (DIP)
8-Pin Small Outline Package (SOP)
SG5842ASZ
-40°C to +105°C RoHS
(Preliminary)
Yes
Yes
Yes
Yes
No
No
8-Pin Small Outline Package (SOP)
8-Pin Small Outline Package (SOP)
SG5842ASY
-40°C to +105°C Green
(Preliminary)
For Fairchild’s definition of Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html.
Application Diagram
Figure 1. Application Diagram
© 2007 Fairchild Semiconductor Corporation
www.fairchildsemi.com
SG5842A/SG582JA • Rev. 1.4.3
2
Block Diagram
Figure 2. Function Block Diagram
Marking Information
H: J = with Frequency Hopping
Null = without Frequency
Hopping
T: D = DIP, S = SOP
P: Z = Lead Free
SG5842HATP
XXXXXXXXYWWV
Null = Regular Package
XXXXXXXX: Wafer Lot
Y: Year; WW: Week
V: Assembly Location
Marking for SG5842JASZ (pb-free)
Marking for SG5842JADZ (pb-free)
Marking for SG5842ASZ (pb-free)
Marking for SG5842ADZ (pb-free)
F- Fairchild Logo
Z- Plant Code
X- 1 Digit Year Code
ZXYTT
SG5842HA
TPM
Y- 1 Digit week Code
TT: 2 Digits Die Run Code
T: Package Type (S=SOP, D=DIP)
P: Y: Green Package
M: Manufacture Flow Code
Marking for SG5842JASY (green-compound)
Marking for SG5842ASY (green-compound)
Figure 3. Top Mark
© 2007 Fairchild Semiconductor Corporation
SG5842A/SG582JA • Rev. 1.4.3
www.fairchildsemi.com
3
Pin Configuration
Figure 4. Pin Configuration
Description
Pin Definitions
Pin # Name
1
GND
Ground
The signal from the external compensation circuit is fed into this pin. The PWM duty cycle is
determined in response to the signal from this pin and the current-sense signal from Pin 6. If FB
voltage exceeds the threshold, the internal protection circuit disables PWM output after a
predetermined delay time.
2
FB
For startup, this pin is pulled HIGH to the rectified line input via a resistor. Since the startup
current requirement is very small, a large startup resistance can be used to minimize power loss.
3
4
VIN
RI
A resistor connected from the RI pin to GND provides a constant current source. This determines
the center PWM frequency. Increasing the resistance reduces PWM frequency. Using a 26KΩ
resistor results in a 65KHz center PWM frequency.
For over-temperature protection. An external NTC thermistor is connected from this pin to the
GND pin. The impedance of the NTC decreases at high temperatures. Once the voltage of the
RT pin drops below a fixed limit, PWM output is latched off.
5
6
RT
Current sense. The sensed voltage is used for peak-current-mode control and cycle-by-cycle
current limiting.
SENSE
VDD
7
8
Power supply. The internal protection circuit disables PWM output if VDD is over-voltage.
GATE The totem-pole output driver for the power MOSFET, which is internally clamped below 18V.
© 2007 Fairchild Semiconductor Corporation
SG5842A/SG582JA • Rev. 1.4.3
www.fairchildsemi.com
4
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device
reliability. The absolute maximum ratings are stress ratings only.
Symbol
VVDD
VVIN
Parameter
Min.
Max.
30
Unit
Supply Voltage(1)
Input Terminal
V
V
V
V
V
V
30
VFB
Input Voltage to FB Pin
-0.3
-0.3
-0.3
-0.3
7.0
7.0
7.0
7.0
VSENSE
VRT
Input Voltage to SENSE Pin
Input Voltage to RT Pin
Input Voltage to RI Pin
VRI
DIP
800
400
82.5
141
PD
Power Dissipation (TA < 50°C )
mW
SOP
DIP
Thermal Resistance (Junction-to-Air)
ΘJA
°C/W
SOP
TJ
TSTG
TL
Operating Junction Temperature
Storage Temperature Range
-40
-55
+125
°C
°C
°C
+150
+260
Lead Temperature (Wave Soldering or Infrared, 10 Seconds)
Human Body Model,
JESD22-A114
Electrostatic Discharge Capability
Charged Device
3
1
ESD
KV
Model, JESD22-C101
Notes:
1. All voltage values, except differential voltage, are given with respect to GND pin.
2. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
Parameter
Operating Ambient Temperature
Min.
Max.
Unit
TA
-20
+85
°C
© 2007 Fairchild Semiconductor Corporation
SG5842A/SG582JA • Rev. 1.4.3
www.fairchildsemi.com
5
Electrical Characteristics
VDD=15V and TJ=TA= -40~125°C, unless otherwise noted.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
VDD Section
VDD-OP
Continuously Operating Voltage
Start Threshold Voltage
20
17.5
11.5
30
V
V
VDD-ON
15.5
9.5
16.5
10.5
14
VDD-OFF Minimum Operation Voltage
V
IDD-ST
Startup Current
VDD=VDD-ON–0.16V
µA
VDD=15V, RI=26KΩ,
GATE=OPEN
IDD-OP
Operating Supply Current
4
5
mA
V
VDD-OVP VDD Over-Voltage Protection
23.2
24.2
100
25.2
VDD Over-Voltage Protection
Debounce Time
tD-OVP
RI=26KΩ
µs
Holding Current After OVP/OTP
Latchup
IDD-H
VDD=5V
40.0
15.5
52.5
65.0
36.0
µA
RI Section
RINOR
RIMAX
RIMIN
RI Operating Range
KΩ
KΩ
KΩ
Maximum RI Value for Protection
Minimum RI Value for Protection
230
10
Oscillator Section
Center
Frequency
RI=26KΩ
62
65
68
Normal PWM
Frequency
fOSC
KHz
RI=26KΩ
SG5842JA Only
Hopping Range
±3.7
±4.2
±4.7
RI=26KΩ
SG5842JA Only
tHOP
fOSC-G
fDV
Hopping Period
3.9
18
4.4
22
4.9
25
5
ms
KHz
%
Green-Mode Minimum Frequency
RI=26KΩ
Frequency Variation vs. VDD
Deviation
VDD=11.5V to 20V
Frequency Variation vs.
Temperature Deviation
fDT
5
%
TA=-20 to 85°C
Feedback Input Section
FB Input to Current Comparator
Attenuation
AV
1/4.5
1/4.0
1/3.5
7
V/V
ZFB
Input Impedance
4
KΩ
V
VFB-OPEN Output High Voltage
FB Pin Open
5.5
5.0
50
VFB-OLP FB Open-Loop Trigger Level
5.4
62
V
tD-OLP
VFB-N
VFB-G
FB Open-Loop Protection Delay
Green-Mode Entry FB Voltage
Green-Mode Ending FB Voltage
RI=26KΩ
RI=26KΩ
RI=26KΩ
56
2.1
ms
V
1.9
2.3
VFB-N-0.5
V
Continued on the following page…
© 2007 Fairchild Semiconductor Corporation
SG5842A/SG582JA • Rev. 1.4.3
www.fairchildsemi.com
6
Electrical Characteristics (Continued)
VDD= 15V and TJ=TA= -40~125°C, unless otherwise noted.
Figure 5. VFB vs. PWM Frequency
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
Current Sense Section
ZSENSE
VSTHFL
Input Impedance
12
KΩ
Current Limit Flatten Threshold
Voltage
0.85
0.90
0.95
V
Current Limit Valley Threshold
Voltage
VSTHVA
VSTHFL–VSTHVA
0.22
V
DCYSAW Duty Cycle of SAW Limit
Maximum Duty Cycle
45
%
ns
ns
tPD
Propagation Delay to GATE Output RI=26KΩ
150
270
200
350
tLEB
Leading-Edge Blanking Time
RI=26KΩ
200
60
GATE Section
DCYMAX Maximum Duty Cycle
VGATE-L Output Voltage Low
VGATE-H Output Voltage High
65
70
%
V
VDD=15V, IO=50mA
VDD=12.5V, IO=-50mA
VDD=15V, CL=1nF
VDD=15V, CL=1nF
VDD=15V, GATE=6V
1.5
7.5
150
30
V
tr
tf
Rising Time
250
50
350
90
ns
ns
mA
Falling Time
IO
Peak Output Current
230
VGATE-
CLAMP
Gate Output Clamping Voltage
VDD=20V
18
19
V
RT Section
IRT
Output Current of RT Pin
RI=26KΩ
67
1.015
60
70
1.050
100
73
1.085
140
µA
V
Over-Temperature Protection
Threshold Voltage
VRTTH
tD-OTP
Over-Temperature Debounce
RI=26KΩ
µs
© 2007 Fairchild Semiconductor Corporation
SG5842A/SG582JA • Rev. 1.4.3
www.fairchildsemi.com
7
Performance Characteristics
30
26
22
18
14
10
5.0
4.5
4.0
3.5
3.0
2.5
-40 -25 -10
5
20
35
50
65
80
95
110 125
-40 -25 -10
5
20
35
50
65
80
95 110 125
Temperature °C
Temperature °C
Figure 6. Startup Current (IDD-ST) vs. Temperature
Figure 7. Operating Supply Current (IDD-OP
)
vs. Temperature
15
12
9
17.5
17.0
16.5
16.0
15.5
GATE=1000pF
6
3
GATE=OPEN
0
-40 -25 -10
5
20
35
50
65
80
95 110 125
12
13
14
15
16
17
18
19
20
21
22
23
24
Temperature °C
V
Voltage (V)
DD
Figure 8. Operation Current (IDD-OP) vs. VDD
Operation
Figure 9. Start Threshold (VDD-ON) vs. Temperature
68
67
66
65
64
63
62
11.5
11.0
10.5
10.0
9.5
-40 -25 -10
5
20
35
50
65
80
95 110 125
-40
-25 -10
5
20
35
50
65
80
95
110 125
Temperature °C
Temperature °C
Figure 10. Minimum Operating Voltage (VDD-OFF
vs. Temperature
)
Figure 11. PWM Frequency (fOSC) vs. Temperature
© 2007 Fairchild Semiconductor Corporation
SG5842A/SG582JA • Rev. 1.4.3
www.fairchildsemi.com
8
Performance Characteristics (Continued)
70
68
66
64
62
60
1.085
1.075
1.065
1.055
1.045
1.035
1.025
1.015
-40 -25 -10
5
20
35
50
65
80
95
110 125
-40 -25 -10
5
20
35
50
65
80
95 110 125
Temperature °C
Temperature °C
Figure 12. Maximum Duty Cycle (DCYmax
vs. Temperature
)
Figure 13. Trigger Voltage for Over-Temperature
Protection (VRTTH) vs. Temperature
73
72
71
70
69
68
67
-40 -25 -10
5
20
35
50
65
80
95 110 125
Temperature °C
Figure 14. Output Current of RT Pin (IRT) vs. Temperature
© 2007 Fairchild Semiconductor Corporation
SG5842A/SG582JA • Rev. 1.4.3
www.fairchildsemi.com
9
Functional Description
Startup Current
The typical startup current is only 14µA, which allows a
high-resistance, low-wattage startup resistor to be used to
minimize power loss. A 1.5MΩ/0.25W startup resistor and
a 10µF/25V VDD hold-up capacitor are sufficient for an
AC/DC adapter with a universal input range.
Under-Voltage Lockout (UVLO)
The turn-on/turn-off thresholds are fixed internally at
16.5V/10.5V. To enable a SG5842A/JA controller during
startup, the hold-up capacitor must first be charged to
16.5V through the startup resistor.
The hold-up capacitor continues to supply VDD before
energy can be delivered from the auxiliary winding of
the main transformer. VDD must not drop below 10.5V
during this startup process. This UVLO hysteresis
window ensures that the hold-up capacitor can
adequately supply VDD during startup.
Operating Current
The required operating current has been reduced to
4mA. This results in higher efficiency and reduces the
VDD hold-up capacitance requirement.
Green-Mode Operation
Gate Output / Soft Driving
The proprietary green-mode function provides off-time
modulation to continuously decrease the PWM
frequency under light-load conditions. To avoid acoustic
noise problems, the minimum PWM frequency is set
above 22KHz. This green-mode function dramatically
reduces power consumption under light-load and zero-
load conditions. Power supplies using this controller can
meet even the strictest international standby power
regulations.
The SG5842A/JA BiCMOS output stage is a fast totem-
pole gate driver. Cross-conduction has been avoided to
minimize heat dissipation, increase efficiency, and
enhance reliability. The output driver is clamped by an
internal 18V Zener diode to protect the power MOSFET
transistors from harmful over-voltage gate signals. A
soft-driving waveform is implemented to minimize EMI.
Slope Compensation
The sensed voltage across the current sense resistor is
used for peak-current-mode control and cycle-by-cycle
current limiting. The built-in slope compensation
function improves power supply stability and prevents
peak-current-mode control from causing sub-harmonic
oscillations. Within every switching cycle, the
SG5842A/JA controller produces a positively sloped,
synchronized ramp signal.
Oscillator Operation
A resistor connected from the RI pin to the GND pin
generates a constant current source for the controller.
This current is used to determine the center PWM
frequency. Increasing the resistance reduces PWM
frequency. Using a 26KΩ resistor, RI, results in a
corresponding 65KHz PWM frequency. The relationship
between RI and the switching frequency is:
Constant Output Power Limit
When the SENSE voltage across the sense resistor,
RS, reaches the threshold voltage, around 0.85V; the
1690
f
PWM =
(KHz)
(1)
RI (KΩ)
The range of the PWM oscillation frequency is designed
as 47KHz ~ 109KHz.
output GATE drive is turned off after a small delay, tPD
This delay introduces additional current proportional to
PD • VIN / LP. The delay is nearly constant regardless of
.
t
SG5842JA also integrates a frequency hopping function
internally. The frequency variation ranges from around
62KHz to 68KHz for a center frequency of 65KHz. The
frequency hopping function helps reduce EMI emission
of a power supply with minimum line filters.
the input voltage VIN. Higher input voltage results in a
larger additional current and the output power limit is
higher than under low input line voltage. To compensate
this variation for a wide AC input range, a sawtooth
power-limiter (saw limiter) is designed to solve the
unequal power-limit problem. The saw limiter is
designed as a positive ramp signal (VLIMIT_RAMP) fed to
the inverting input of the OCP comparator. This results
in a lower current limit at high-line inputs than at low-
line inputs.
Leading-Edge Blanking (LEB)
Each time the power MOSFET is switched on, a turn-on
spike occurs at the sense resistor. To avoid premature
termination of the switching pulse, a leading-edge
blanking time is built in. During this blanking period, the
current-limit comparator is disabled and cannot switch
off the gate drive.
VDD Over-Voltage Protection (OVP)
VDD over-voltage protection is built in to prevent
damage due to abnormal conditions. Once the VDD
voltage is over the VDD over-voltage protection voltage
(VDD-OVP) and lasts for tD-OVP, the PWM pulse is latched
off. The PWM pulses stay latched off until the power
supply is unplugged from the mains outlet.
© 2007 Fairchild Semiconductor Corporation
SG5842A/SG582JA • Rev. 1.4.3
www.fairchildsemi.com
10
Functional Description (Continued)
Limited Power Control
Thermal Protection
The FB voltage increases every time the output of the
power supply is shorted or overloaded. If the FB voltage
remains higher than a built-in threshold longer than tD-
OLP, PWM output is turned off. As PWM output is turned
off, the supply voltage VDD begins decreasing.
An external NTC thermistor can be connected from the
RT pin to ground. A fixed current, IRT, is sourced from
the RT pin. Because the impedance of the NTC
decreases at high temperatures, when the voltage of
the RT pin drops below 1.05V, PWM output is latched
off. The RT pin output current is related to the PWM
frequency programming resistor RI.
tD-OLP (ms) = 2.154 × R (KΩ)
(2)
I
When VDD goes below the turn-off threshold (eg.
10.5V), the controller is totally shut down. VDD is
charged up to the turn-on threshold voltage of 16.5V
through the startup resistor until PWM output is
restarted. This protection feature remains activated as
long as the overloading condition persists. This
prevents the power supply from overheating due to
overloading conditions.
Noise Immunity
Noise from the current sense or the control signal may
cause significant pulse width jitter, particularly in
continuous-conduction mode. Slope compensation
helps alleviate this problem. Good placement and
layout practices should be followed. Avoid long PCB
traces and component leads. Compensation and filter
components should be located near the SG5842A/JA.
Increasing the power-MOS gate resistance is advised.
Protection Latch Circuit
The built-in latch function provides a versatile protection
feature that does not require external components (see
ordering information for a detailed description). To reset
the latch circuit, disconnect the AC line voltage of the
power supply.
© 2007 Fairchild Semiconductor Corporation
SG5842A/SG582JA • Rev. 1.4.3
www.fairchildsemi.com
11
Reference Circuit
Q1
BD1
CN1
1
3
1
2
3
L3
L1
L2
2
1
2
C1
C2
T1
4
1
Vo+
D1
VZ1
R3
C3
D2
C4
D3
+
TR1
C7
+
+C8
C6
R4
C5
R6
R1
R5
D4
R2 R7
Q2
U1
GND GATE
1
2
3
4
8
7
6
5
1
R12
FB
VIN SENSE
RI RT
SG5842A/JA
VDD
R16
R11
R9
R10
C9
+
C11
R8
THER2
U2
R13
R
C10
R14
U3
VO+
R15
Figure 15. Reference Circuit
BOM
Reference
BD1
C1
Component
Reference
Component
MOS 7A/600V
R 470KΩ 1/4W
R 100KΩ 1/2W
R 47Ω 1/4W
R 2KΩ 1/8W
R 0.3Ω 2W
BD 4A/600V
Q2
R1, R2, R5, R7
R3
XC 0.68µF/300V
XC 0.1µF/300V
CC 0.01µF/500V
EC 120µ/400V
YC 222p/250V
CC 1000pF/100V
EC 1000µF/25V
EC 470µF/25V
EC 10µF/50V
CC 222pF/50V
CC 470pF/50V
LED
C2
C3
R4
C4
R6
C5
R8
C6
R9
R 33KΩ 1/8W
R 4.7KΩ 1/8W
R 470Ω 1/8W
R 0Ω 1/8W
C7
R10
R11
R12
R13
R14
R15
R16
THER2
T1
C8
C9
C10
C11
D1
R 4.7KΩ 1/8W
R 154KΩ 1/8W 1%
R 39KΩ 1/8W 1%
R 100Ωm 1/8W
D2
Diode BYV95C
TVS P6KE16A
Diode FR103
D3
Thermistor TTC104
D4
Transformer (600µH-PQ2620)
IC SG5842A/JA
IC PC817
F1
FUSE 4A/250V
Choke (900µH)
Choke (10mH)
Inductor (2µH)
Diode 20A/100V
U1
L1
U2
L2
U3
IC TL431
L3
VZ1
VZ 9G
Q1
© 2007 Fairchild Semiconductor Corporation
SG5842A/SG5842JA • Rev. 1.4.3
www.fairchildsemi.com
12
Physical Dimensions
5.00
4.80
A
0.65
3.81
8
5
B
1.75
6.20
5.80
4.00
3.80
5.60
1
4
PIN ONE
INDICATOR
1.27
1.27
(0.33)
M
0.25
C B A
LAND PATTERN RECOMMENDATION
SEE DETAIL A
0.25
0.10
0.25
0.19
C
1.75 MAX
0.10
C
0.51
0.33
OPTION A - BEVEL EDGE
0.50
0.25
x 45°
R0.10
R0.10
GAGE PLANE
OPTION B - NO BEVEL EDGE
0.36
NOTES: UNLESS OTHERWISE SPECIFIED
8°
0°
0.90
A) THIS PACKAGE CONFORMS TO JEDEC
MS-012, VARIATION AA, ISSUE C,
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
FLASH OR BURRS.
SEATING PLANE
(1.04)
0.406
D) LANDPATTERN STANDARD: SOIC127P600X175-8M.
E) DRAWING FILENAME: M08AREV13
DETAIL A
SCALE: 2:1
Figure 16. 8-Pin, Small Outline Package (SOP)
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify
or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically
the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2007 Fairchild Semiconductor Corporation
SG5842A/SG5842JA • Rev. 1.4.3
www.fairchildsemi.com
13
Physical Dimensions (Continued)
9.83
9.00
6.67
6.096
8.255
7.61
3.683
3.20
7.62
5.08 MAX
0.33 MIN
3.60
3.00
(0.56)
2.54
0.356
0.20
0.56
0.355
9.957
7.87
1.65
1.27
7.62
NOTES: UNLESS OTHERWISE SPECIFIED
A) THIS PACKAGE CONFORMS TO
JEDEC MS-001 VARIATION BA
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS ARE EXCLUSIVE OF BURRS,
MOLD FLASH, AND TIE BAR EXTRUSIONS.
D) DIMENSIONS AND TOLERANC
ASME Y14.5M-1994
ES PER
E) DRAWING FILENAME AND REVSION: MKT-N08FREV2.
Figure 17. 8-Pin, Dual Inline Package (DIP)
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify
or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically
the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2007 Fairchild Semiconductor Corporation
SG5842A/SG5842JA • Rev. 1.4.3
www.fairchildsemi.com
14
© 2007 Fairchild Semiconductor Corporation
SG5842A/SG5842JA • Rev. 1.4.3
www.fairchildsemi.com
15
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