SG5851A [FAIRCHILD]
Low-Cost, Green-Mode, PWM Controller for Flyback Converters; 低成本，绿色模式PWM控制器，用于反激式转换器
| 型号： | SG5851A |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Low-Cost, Green-Mode, PWM Controller for Flyback Converters |
| 文件： | 总12页 (文件大小：896K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
August 2008
SG5851A
Low-Cost, Green-Mode, PWM Controller for Flyback
Converters
Features
Description
This highly integrated PWM controller provides several
enhancements designed to meet the low standby-power
needs of low-power SMPS. To minimize standby power
consumption, the proprietary green-mode function
provides off-time modulation to linearly decrease the
switching frequency under light-load conditions. This
green-mode function enables the power supply to meet
power conservation requirements.
Green-Mode PWM
Supports the “Blue Angel” Standard
Low Startup Current: 9µA
Low Operating Current: 3mA
Leading-Edge Blanking
Constant Output Power Limit
Universal Input
The BiCMOS fabrication process enables reducing the
startup current to 9µA and the operating current to 3mA.
To further improve power conservation, a large startup
resistance can be used. Built-in synchronized slope
compensation ensures the stability of peak-current-
mode control. Proprietary internal compensation
provides a constant output power limit over a universal
AC input range (90VAC to 264VAC). Pulse-by-pulse
current limiting ensures safe operation even during
short circuits.
Built-in Synchronized Slope Compensation
Current Mode Operation
Cycle-by-cycle Current Limiting
Under-Voltage Lockout (UVLO)
Programmable PWM Frequency with Frequency
Hopping
To protect the external power MOSFET from being
damaged by supply over voltage, the output driver is
clamped at 17V. SG5851A controllers, available in an
SOP package, can be used to improve the performance
and reduce the production cost of power supplies.
VDD Over-Voltage Protection (Auto Restart)
Gate Output Voltage Clamped at 17V
Low Cost
Few External Components Required
Applications
Power Adaptors
Open-Frame SMPS
Ordering Information
Operating
Temperature Range
Packing
Part Number
Package
Eco Status
Method
Tape & Reel
Tube
SG5851ASY
SG5851ADY
-40°C to +105°C
8-pin Small Outline Package (SOP)
8-pin Dual in-line Package (DIP)
Green
Green
-40°C to +105°C
For Fairchild’s definition of “green” Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html.
© 2008 Fairchild Semiconductor Corporation
SG5851A • Rev. 1.0.0
www.fairchildsemi.com
Application Diagram
10µ
SG5851A
Figure 1.
Typical Application
Block Diagram
Figure 2. Function Block Diagram
© 2008 Fairchild Semiconductor Corporation
SG5851A • Rev. 1.0.0
www.fairchildsemi.com
2
Marking Information
F- Fairchild logo
Z- Plant code
X- 1 digit year code
Y- 1 digit week code
TT: 2 digits die run code
T: Package type (S=SOP, D=DIP)
P: Y: Green compound
M: Manufacture flow code
5851A
TPM
Figure 3. Marking Information
Pin Configuration
GATE
VDD SENSE
NC
8
7
6
5
1
2
3
4
GND
FB
VDD
RI
Figure 4. Pin Configuration (Top View)
Pin Definitions
Pin #
Name
GND
FB
Description
Ground
1
2
3
Feedback
VDD
Power Supply
Reference Setting. A resistor connected from the RI pin to ground generates a constant
current source used to charge an internal capacitor and determine the switching frequency.
Increasing the resistance reduces the amplitude of the current source and reduces the
switching frequency. A 95kΩ resistor, RI, results in a 13µA constant current, II, and a 70kHz
switching frequency.
4
RI
5
6
NC
No Connection
Current Sense. This pin senses the voltage across a resistor. When the voltage reaches the
internal threshold, PWM output is disabled. This activates over-current protection. This pin also
provides current amplitude information for current-mode control.
SENSE
7
8
VDD
Power Supply
GATE
Driver Output. The totem-pole output driver for driving the power MOSFET.
© 2008 Fairchild Semiconductor Corporation
SG5851A • Rev. 1.0.0
www.fairchildsemi.com
3
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device
reliability. The absolute maximum ratings are stress ratings only. All voltage values, except differential voltage, are
given with respect to GND pin. Stresses beyond those listed under “absolute maximum ratings “may cause
permanent damage to the device.
Symbol
VVDD
VFB
Parameter
Min.
Max.
30
Unit
V
DC Supply Voltage
-0.3
-0.3
7.0
V
Input Voltage to FB Pin
7.0
V
VSENSE
PD
Input Voltage to Sense Pin
300
mW
°C
Power Dissipation
+150
141
TJ
Operating Junction Temperature
Thermal Resistance (Junction-to-Air)
Storage Temperature Range
θJA
°C/W
°C
-55
+150
+260
TSTG
TL
Lead Temperature (Wave soldering, or IR 10 seconds)
°C
Electrostatic Discharge Capability,
Human Body Model, JESD22-A114
3.0
KV
V
ESD
Electrostatic Discharge Capability,
Machine Model, JESD22-A115
200
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
Parameter
Operating Ambient Temperature
Min.
Typ.
Max.
Unit
TA
-40
+105
°C
© 2008 Fairchild Semiconductor Corporation
SG5851A • Rev. 1.0.0
www.fairchildsemi.com
4
Electrical Characteristics
VDD=15V, TA=25°C, unless otherwise noted.
Symbol
Parameter
Conditions
Min.
Typ. Max. Units
VDD Section
VDD-OP
VDD-ON
Continuous Operation Voltage
Turn-on Threshold Voltage
22
17.5
12.5
15
V
V
15.5
10.5
16.5
11.5
9
VDD-OFF Turn-off Threshold Voltage
V
IDD-ST
IDD-OP
Startup Current
µA
VDD=VDD-ON – 0.1V
VDD=15V, GATE with
1nF to GND
Operating Supply Current
3.0
3.5
26
mA
VDD-OVP VDD Over-Voltage Protection Level
tD-VDDOVP VDD Over-Voltage Protection Debounce
Feedback Input Section
Auto Restart
Auto Restart
24
25
V
100
µs
VFB-OPEN FB Output High Voltage
5
V
VFB-OL
tD-OLP
VFB-N
VFB-G
SG
FB Open-loop Trigger Level
4.3
4.6
56
4.9
3.10
100
V
ms
V
Delay Time of FB Pin Open-Loop Protection
Green-Mode Entry FB Voltage
Green-Mode Ending FB Voltage
Green-Mode Modulation Slope
2.60
40
2.85
2.2
70
V
RI=95KΩ
Hz/mV
V
1.75
VOZ-OFF FB Threshold Voltage for Zero-Duty
Current-Sense Section
ZSENSE
tPD
Input Impedance
10
40
KΩ
ns
V
Delay to Output
VDD=13.5 to 22V
55
1
100
VSTHFL
VSTHVA
tLEB
Flat Threshold Voltage for Current Limit
Valley Threshold Voltage for Current Limit
Leading-Edge Blanking Time
0.75
250
0.80
310
45
0.85
370
V
ns
%
DCYSAW Duty Cycle of SAW Limit
Maximum Duty Cycle
Oscillator Section
Center Frequency
fOSC
65
70
±4.9
3.7
22
75
RI=95KΩ
KHz
Hopping Range
tHOP
fOSC-G
fDV
Hopping Period
RI=95KΩ
ms
KHz
%
Green-Mode Frequency
Frequency Variation vs. VDD Deviation
RI=95KΩ
VDD=13.5 to 22V
0
0.2
2.0
2
Frequency Variation vs. Temperature
Deviation
fDT
TA=-20 to +85°C
%
Continued on the following page…
© 2008 Fairchild Semiconductor Corporation
SG5851A • Rev. 1.0.0
www.fairchildsemi.com
5
Electrical Characteristics
VDD=15V, TA=25°C, unless otherwise noted.
Symbol
Parameter
Conditions
Min.
70
Typ. Max. Units
Output Section
DCYMAX Maximum Duty Cycle
VGATE-L Output Voltage Low
VGATE-H Output Voltage High
75
80
%
V
VDD=15V, IO=20mA
VDD=13.5V, IO=20mA
VDD=15V, CL=1nF
VDD=15V, CL=1nF
1.5
8
V
tr
tf
Rising Time
Falling Time
120
65
ns
ns
VGATE-
CLAMP
Output Clamp Voltage
VDD=22V
16
17
18
V
Frequency
+4.9kHz
70kHz
-4.9kHz
+1.45kHz
20
No Jitter if VFB < VFB-G
kHz
-1.45kHz
FB
VFB-N
VOZ-OFF
VFB_G
Figure 5. PWM Frequency
© 2008 Fairchild Semiconductor Corporation
SG5851A • Rev. 1.0.0
www.fairchildsemi.com
6
Functional Description
SG5851A devices integrate many useful designs into
one controller for low-power, switch-mode, power
supplies. The following descriptions highlight some of
the features of the SG5851A series.
Constant Output Power Limit
When the SENSE voltage across the sense resistor,
RS, reaches the threshold voltage (~1.00V), the output
GATE drive is turned off after propagation delay, tPD
.
This propagation delay introduces an additional current
proportional to tPD•VIN/Lp. The propagation delay is
nearly constant regardless of the input line voltage VIN.
Higher input line voltages result in larger additional
currents. At high input line voltages, the output power
limit is higher than at low input line voltages.
Startup Current
The startup current is only 9µA, which allows a startup
resistor with a high resistance and a low-wattage to
supply the startup power for the controller. A 1.5MΩ,
0.25W, startup resistor and a 10µF/25V VDD hold-up
capacitor are sufficient for an AC-to-DC power adapter
with a wide input range (90VAC to 264VAC).
To compensate for this output power limit variation
across a wide AC input range, the threshold voltage is
adjusted by adding a positive ramp. This ramp signal
rises from 0.80V to 1.00V, then flattens out at 1.00V. A
smaller threshold voltage forces the output GATE drive
to terminate earlier. This reduces the total PWM turn-on
time and makes the output power equal to that of low-
line input. This proprietary internal compensation
ensures a constant output power limit for a wide AC
input voltage range (90VAC to 264VAC).
Operating Current
The operating current has been reduced to 3mA, which
results in higher efficiency and reduces the VDD hold-up
capacitance requirement.
Green-Mode Operation
The proprietary green-mode function provides off-time
modulation to linearly decrease the switching frequency
under light-load conditions. On-time is limited to provide
stronger protection against brownouts and abnormal
conditions. The feedback current, which is sampled
from the voltage feedback loop, is taken as the
reference. Once the feedback current exceeds the
threshold current, the switching frequency starts to
decrease. Green mode dramatically reduces power
consumption under light-load and zero-load conditions.
Power supplies using SG5851A meet even the strictest
regulations regarding standby power consumption.
Under-Voltage Lockout (UVLO)
The turn-on and turn-off thresholds are fixed internally
at 16.5V and 11.5V. During startup, the hold-up
capacitor must be charged to 16.5V through the startup
resistor to enable SG5851A. The hold-up capacitor
continues to supply VDD until power can be delivered
from the auxiliary winding of the main transformer. VDD
must not drop below 11.5V during the startup process.
This UVLO hysteresis window ensures that the hold-up
capacitor is adequate to supply VDD during startup.
Gate Output
Oscillator Operation
The BiCMOS output stage is a fast totem-pole gate
driver. Cross conduction has been avoided to minimize
heat dissipation, increase efficiency, and enhance
reliability. The output driver is clamped by an internal
17V Zener diode to protect power MOSFET transistors
against undesired over-voltage gate signals.
A resistor connected from the RI pin to ground
generates a constant current source used to charge an
internal capacitor. The charge time determines the
internal clock speed and the switching frequency.
Increasing the resistance reduces the amplitude of the
input current and reduces the switching frequency. A
95kΩ resistor, RI, results in a 13µA constant current, II,
and a 70kHz switching frequency. The relationship
between RI and the switching frequency is:
Built-in Slope Compensation
The sensed voltage across the current sense resistor is
used for current mode control and pulse-by-pulse
current limiting. Built-in slope compensation improves
stability and prevents sub-harmonic oscillations due to
6650
(1)
fPWM
=
(kHz)
RI(kΩ)
peak-current-mode control. The SG5851A has
a
The range of the oscillation frequency is designed to be
within 50kHz ~ 80kHz.
synchronized, positively-sloped ramp built-in at each
switching cycle. The slope of the ramp is:
0.36 × Duty
Duty(max.)
(2)
Leading-Edge Blanking (LEB)
Each time the power MOSFET is switched on, a turn-on
spike occurs at the sense-resistor. To avoid premature
termination of the switching pulse, a 310ns leading-
edge blanking time is built in. Conventional RC filtering
can therefore be omitted. During this blanking period,
the current-limit comparator is disabled and it cannot
switch off the gate driver.
Noise Immunity
Noise from the current sense or the control signal can
cause significant pulse-width jitter, particularly in
continuous-conduction mode. While slope compensation
helps alleviate these problems, further precautions should
be taken. Good placement and layout practices should be
followed. Avoiding long PCB traces and component
leads, locating compensation and filter components near
the SG5851A, and increasing power MOS gate
resistance improve performance.
© 2008 Fairchild Semiconductor Corporation
SG5851A • Rev. 1.0.0
www.fairchildsemi.com
7
Typical Performance Characteristics
14.0
12.8
11.6
10.4
9.2
17.0
16.8
16.6
16.4
16.2
16.0
8.0
-40
-25
-10
5
20
35
50
65
80
95
110
125
-40
-25
-10
5
20
35
50
65
80
95
110
110
110
125
125
125
Temperature (℃)
Temperature (℃)
Figure 6. VDD-ON vs. TA
Figure 7. VDD-OFF vs. TA
10.0
8.4
6.8
5.2
3.6
2.0
2.00
1.88
1.76
1.64
1.52
1.40
-40
-25
-10
5
20
35
50
65
80
95
110
125
-40
-25
-10
5
20
35
50
65
80
95
Temperature (℃)
Figure 8. IDD-ST vs. TA
Temperature (℃)
Figure 9. IDD-OP vs. TA
76.0
75.2
74.4
73.6
72.8
72.0
70.0
69.2
68.4
67.6
66.8
66.0
-40
-25
-10
5
20
35
50
65
80
95
110 125
-40
-25
-10
5
20
35
50
65
80
95
Temperature (℃)
Figure 10. fOSC vs. TA
Temperature (℃)
Figure 11. DCYMAX vs. TA
© 2008 Fairchild Semiconductor Corporation
SG5851A • Rev. 1.0.0
www.fairchildsemi.com
8
Typical Performance Characteristics (Continued)
3.20
3.12
3.04
2.96
2.88
2.80
2.40
2.36
2.32
2.28
2.24
2.20
-40
-25
-10
5
20
35
50
65
80
95
110
125
-40
-25
-10
5
20
35
50
65
80
95
110
125
Temperature (℃)
Temperature (℃)
Figure 12. VFB-N vs. TA
Figure 13. VFB-G vs. TA
320
308
296
284
272
260
1.90
1.86
1.82
1.78
1.74
1.70
-40
-25
-10
5
20
35
50
65
80
95
110
125
-40
-25
-10
5
20
35
50
65
80
95
110
125
Temperature (
℃
)
Temperature (℃)
Figure 14. VOZ vs. TA
Figure 15. tLEB vs. TA
© 2008 Fairchild Semiconductor Corporation
SG5851A • Rev. 1.0.0
www.fairchildsemi.com
9
Mechanical Dimensions
9.83
9.00
6.67
6.096
8.255
7.61
3.683
3.20
7.62
5.08 MAX
0.33 MIN
3.60
3.00
(0.56)
2.54
0.356
0.20
0.56
0.355
9.957
7.87
1.65
1.27
7.62
NOTES: UNLESS OTHERWISE SPECIFIED
A) THIS PACKAGE CONFORMS TO
JEDEC MS-001 VARIATION BA
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS ARE EXCLUSIVE OF BURRS,
MOLD FLASH, AND TIE BAR EXTRUSIONS.
D) DIMENSIONS AND TOLERANC
ASME Y14.5M-1994
ES PER
E) DRAWING FILENAME AND REVSION: MKT-N08FREV2.
Figure 16. 8-Lead, PDIP, JEDEC MS-001, .300 Inch Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify
or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2008 Fairchild Semiconductor Corporation
SG5851A • Rev. 1.0.0
www.fairchildsemi.com
10
Mechanical Dimensions (Continued)
5.00
4.80
A
0.65
3.81
8
5
B
1.75
6.20
5.80
4.00
3.80
5.60
1
4
PIN ONE
INDICATOR
1.27
1.27
(0.33)
M
0.25
C B A
LAND PATTERN RECOMMENDATION
SEE DETAIL A
0.25
0.10
0.25
0.19
C
1.75 MAX
0.10
C
0.51
0.33
OPTION A - BEVEL EDGE
0.50
0.25
x 45°
R0.10
R0.10
GAGE PLANE
OPTION B - NO BEVEL EDGE
0.36
NOTES: UNLESS OTHERWISE SPECIFIED
8°
0°
0.90
A) THIS PACKAGE CONFORMS TO JEDEC
MS-012, VARIATION AA, ISSUE C,
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
FLASH OR BURRS.
SEATING PLANE
(1.04)
0.406
D) LANDPATTERN STANDARD: SOIC127P600X175-8M.
E) DRAWING FILENAME: M08AREV13
DETAIL A
SCALE: 2:1
Figure 17. 8-Lead, SOIC,JEDEC MS-012, .150 Inch Narrow Body
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify
or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2008 Fairchild Semiconductor Corporation
SG5851A • Rev. 1.0.0
www.fairchildsemi.com
11
© 2008 Fairchild Semiconductor Corporation
SG5851A • Rev. 1.0.0
www.fairchildsemi.com
12
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