SG6859ATY [FAIRCHILD]
Low-Cost, Green-Mode PWM Controller for Flyback Converters; 低成本，绿色模式PWM控制器，用于反激式转换器
| 型号： | SG6859ATY |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Low-Cost, Green-Mode PWM Controller for Flyback Converters |
| 文件： | 总13页 (文件大小：502K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
March 2010
SG6859A
Low-Cost, Green-Mode PWM Controller for Flyback Converters
Features
Description
This highly integrated PWM controller provides several
enhancements designed to meet the low standby-power
needs of low-power SMPS. To minimize standby power
consumption, the proprietary green-mode function
provides off-time modulation to linearly decrease the
switching frequency under light-load conditions. This
green-mode function enables the power supply to meet
even the strictest power conservation requirements.
Green-Mode PWM
Supports the “Blue Angel” Standard
Low Startup Current: 9μA
Low Operating Current: 3mA
300mA Driving Capability
Leading-Edge Blanking
The BiCMOS fabrication process enables reducing the
startup current to 9μA and the operating current to 3mA.
To further improve power conservation, a large startup
resistance can be used. Built-in synchronized slope
compensation ensures the stability of peak current
mode control. Proprietary internal compensation
provides a constant output power limit over a universal
AC input range (90VAC to 264VAC). Pulse-by-pulse current
limiting ensures safe operation during short-circuits.
Constant Output Power Limit
Universal Input
Built-in Synchronized Slope Compensation
Current-Mode Operation
Cycle-by-cycle Current Limiting
Under-Voltage Lockout (UVLO)
Programmable PWM Frequency with Frequency
To protect the external power MOSFET from damage by
supply over voltage, the SG6859A’s output driver is
clamped at 17V. SG6859A controllers can be used to
improve the performance and reduce the production
cost of power supplies. The best choice for replacing
linear and RCC-mode power adapters, the SG6859A is
available in 8-pin DIP and 6-pin SSOT-6 packages.
Hopping
VDD Over-Voltage Protection (Auto Restart)
Gate Output Voltage Clamped at 17V
Low Cost
Few External Components Required
Small SSOT-6 Package
Applications
General-purpose switching mode power supplies and
flyback power converters, such as:
Battery chargers for cellular phones, cordless
phones, PDAs, digital cameras, and power tools
Power adapters for ink jet printers, video game
consoles, and portable audio players
Open-frame SMPS for TV/DVD standby and auxiliary
supplies, home appliances, and consumer electronics
Replacements for linear transformers and RCC SMPS
PC 5V standby power
© 2007 Fairchild Semiconductor Corporation
SG6859A • Rev. 1.0.3
www.fairchildsemi.com
Ordering Information
Part Number
SG6859ATZ
SG6859ATY
SG6859ADZ
SG6859ADY
Operating Temperature Range
Package
SSOT-6
SSOT-6
DIP-8
Packing Method
Tape & Reel
Tape & Reel
Tube
Eco Status
RoHS
-40 to +105°C
-40 to +105°C
-40 to +105°C
-40 to +105°C
Green
RoHS
DIP-8
Green
Tube
For Fairchild’s definition of Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html
Application Diagram
Figure 1. Typical Application
Internal Block Diagram
Figure 2. Functional Block Diagram
© 2007 Fairchild Semiconductor Corporation
www.fairchildsemi.com
SG6859A • Rev. 1.0.3
2
Marking Information
AAJF: SG6859A
W: Week Code
A~Z=W1~W26
A~Z=W27~W52
AAJFW
: Lead Free Package
*Marking for SG6859ATZ (Pb-free)
XXXX: AAJF=SG6859A
T : Die Run Code
. . . . : Year Code
- - - : Week Code
*Marking for SG6859ATY (Green Compound)
T: D=DIP
P: Z= Lead Free + RoHS Compatible
Null=Regular Package
XXXXXXXX: Wafer Lot
Y: Year
WW: Week
V: Assembly Location
*Marking for SG6859ADZ (Pb-free)
F- Fairchild Logo
Z- Plant Code
X- 1-Digit Year Code
Y- 1-Digit Week Code
TT: 2-Digit Die Run Code
T: Package Type (D=DIP)
P: Y: Green Package
M: Manufacture Flow Code
*Marking for SG6859ADY (Green Compound)
Figure 3. Top Mark
© 2007 Fairchild Semiconductor Corporation
SG6859A • Rev. 1.0.3
www.fairchildsemi.com
3
Pin Configurations
Figure 4. SSOT-6 Pin Configuration
Figure 5. DIP-8 Pin Configuration
Pin Definitions
DIP
Pin #
SSOT
Pin #
Name Description
GATE The totem-pole output driver for driving the power MOSFET.
1
2
3
6
5
VDD
NC
Power supply
No connection
Current sense. This pin senses the voltage across a resistor. When the voltage
reaches the internal threshold, PWM output is disabled. This activates over-current
protection. This pin also provides current amplitude information for current-mode
control.
4
4
3
SENSE
A resistor connected from the RI pin to ground generates a constant current source
used to charge an internal capacitor and determine the switching frequency.
Increasing the resistance reduces the amplitude of the current source and the
switching frequency. A 95kΩ resistor RI results in a 50μA constant current II and a
70kHz switching frequency.
5
RI
6
7
8
NC
FB
No connection
Feedback. The FB pin provides the output voltage regulation signal. It provides
feedback to the internal PWM comparator, so that the PWM comparator can control
the duty cycle.
2
1
GND
Ground
© 2007 Fairchild Semiconductor Corporation
SG6859A • Rev. 1.0.3
www.fairchildsemi.com
4
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device
reliability. The absolute maximum ratings are stress ratings only.
Symbol
VVDD
Parameter
Min.
Max.
30
Unit
V
DC Supply Voltage(1, 2)
Input Voltage to FB Pin
Input Voltage to Sense Pin
VFB
-0.3
-0.3
7.0
V
VSENSE
TJ
7.0
V
Operating Junction Temperature
150
273
113
+150
+260
3.5
°C
SSOT
DIP
°C/W
°C/W
°C
Thermal Resistance (Junction-to-Air)
ΘJA
TSTG
TL
Storage Temperature Range
-55
Lead Temperature (Wave Soldering or IR, 10 Seconds)
°C
Electrostatic Discharge Capability, Human Body Model JESD22-A114
Electrostatic Discharge Capability, Charged Device Model JESD22-C101
Electrostatic Discharge Capability, Machine Model, JESD22-A115
kV
kV
V
ESD
1.5
200
Notes:
1. All voltage values, except differential voltages, are given with respect to GND pin.
2. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
© 2007 Fairchild Semiconductor Corporation
SG6859A • Rev. 1.0.3
www.fairchildsemi.com
5
Electrical Characteristics
Unless otherwise noted, VDD=15V and TA=25°C.
Symbol
Parameter
Conditions
Min.
Typ.
Max. Units
VDD Section
VDD-OP Continuously Operation Voltage
VDD-ON Turn-on Threshold Voltage
VDD-OFF Turn-off Threshold Voltage
22
17.5
10.5
15
V
V
15.5
8.5
16.5
9.5
9
V
IDD-ST
IDD-OP
Startup Current
VDD=VDD-ON – 0.1V
μA
mA
V
Operating Supply Current
3.0
25
3.5
26
VDD=15V, CL=1nF
VDD-OVP VDD Over-Voltage Protection Level
Auto Restart
Auto Restart
24
tD-VDDOVP VDD Over-Voltage Protection Debounce
125
μs
VDD Low-Threshold Voltage to Exit
Green-off Mode
VDD-OFF
+ 1
VDD-G OFF
V
Feedback Input Section
ZFB
Input Impedance
5
kΩ
VFB-OPEN FB Output High Voltage
5
V
V
VFB-OL
tD-OLP
VFB-N
VFB-G
SG
FB Open-loop Trigger Level
4.3
4.6
56
4.9
3.10
100
Delay of FB Pin Open-loop Protection
Green-Mode Entry FB Voltage
Green-Mode Ending FB Voltage
Green-Mode Modulation Slope
ms
V
2.60
40
2.85
2.2
75
V
RI=95kΩ
Hz/mV
Current-Sense Section
ZSENSE Input Impedance
10
40
kΩ
ns
V
tPD
Delay to Output
55
1
100
VSTHFL Flat Threshold Voltage for Current Limit
VSTHVA Valley Threshold Voltage for Current Limit
0.75
270
0.80
320
40
0.85
370
V
tLEB
Leading-Edge Blanking Time
ns
%
DCYSAW Duty Cycle of SAW Limit
Oscillator Section
Center Frequency
Hopping Range
65
0
70
±4.9
3.7
75
fOSC
Frequency
RI=95kΩ
kHz
THOP
fOSC-G
fDV
Hopping Period
RI=95kΩ
ms
kHz
%
Green-Mode Frequency
RI=95kΩ
20
Frequency Variation vs. VDD Deviation
VDD=13.5 to 22V
0.02
2.00
2
Frequency Variation vs. Temperature
Deviation
fDT
TA=-20 to 85°C
%
Output Section
DCYMAX Maximum Duty Cycle
VGATE-L Output Voltage Low
VGATE-H Output Voltage High
62
8
67
72
%
V
VDD=15V, IO=20mA
VDD=13.5V, IO=20mA
VDD=15V, CL=1nF
VDD=15V, CL=1nF
1.4
V
tr
tf
Rising Time
Falling Time
150
55
ns
ns
VGATE-
CLAMP
Output Clamp Voltage
VDD=22V
16
17
18
V
© 2007 Fairchild Semiconductor Corporation
SG6859A • Rev. 1.0.3
www.fairchildsemi.com
6
Typical Performance Characteristics
17.0
16.8
16.6
16.4
16.2
16.0
13.0
12.0
11.0
10.0
9.0
8.0
-40
-25
-10
5
20
35
50
65
80
95
110 125
-40
-25
-10
5
20
35
50
65
80
95
110 125
Temperature (℃)
Temperature (℃)
Figure 6. Turn-on Threshold Voltage (VDD-ON
)
Figure 7. Turn-off Threshold Voltage (VDD-ON
)
vs. Temperature
vs. Temperature
3.0
2.5
2.0
1.5
1.0
0.5
3.5
3.3
3.1
2.9
2.7
2.5
-40
-25
-10
5
20
35
50
65
80
95
110 125
-40
-25
-10
5
20
35
50
65
80
95
110 125
Temperature (℃)
Temperature (℃)
Figure 8. Startup Current (IDD-ST) vs. Temperature
Figure 9. Operating Supply Current (IDD-OP
)
vs. Temperature
70.0
69.0
68.0
67.0
66.0
65.0
70.0
69.0
68.0
67.0
66.0
65.0
-40
-25
-10
5
20
35
50
65
80
95
110 125
-40
-25
-10
5
20
35
50
65
80
95
110 125
Temperature (℃)
Temperature (℃)
Figure 10. Center Frequency (fOSC) vs. Temperature
Figure 11. Maximum Duty Cycle (DCYMAX
)
vs. Temperature
© 2007 Fairchild Semiconductor Corporation
SG6859A • Rev. 1.0.3
www.fairchildsemi.com
7
Typical Performance Characteristics
3.2
3.0
2.8
2.6
2.4
2.2
3.0
2.8
2.6
2.4
2.2
2.0
-40
-25
-10
5
20
35
50
65
80
95
110 125
-40
-25
-10
5
20
35
50
65
80
95
110 125
Temperature (℃)
Temperature (℃)
Figure 12. Green-Mode Entry FB Voltage (VFB-N
)
Figure 13. Green-Mode Ending FB Voltage (VFB-G
vs. Temperature
)
vs. Temperature
3.5
3.0
2.5
2.0
1.5
1.0
350.0
330.0
310.0
290.0
270.0
250.0
-40
-25
-10
5
20
35
50
65
80
95
110 125
12
13
14
15
16
17
18
DD (V)
19
20
21
22
23
24
V
Temperature (℃)
Figure 14. Leading-Edge Blanking Time (tLEB
)
Figure 15. Operating Supply Current vs.
VDD Voltage
vs. Temperature
© 2007 Fairchild Semiconductor Corporation
SG6859A • Rev. 1.0.3
www.fairchildsemi.com
8
Operation Description
SG6859A devices integrate many useful designs into
one controller for low-power, switch-mode power
supplies. The following descriptions highlight some of
the features of the SG6859A series.
output GATE drive is turned off following a short
propagation delay, tPD This propagation delay
introduces an additional current proportional to
PD•VIN/LP. The propagation delay is nearly constant,
.
t
regardless of the input line voltage VIN. Higher input line
voltages result in larger additional currents. At high
input line voltages, the output power limit is higher than
at low input line voltages. To compensate for this output
power limit variation across a wide AC input range, the
threshold voltage is adjusted by adding a positive ramp.
This ramp signal rises from 0.8V to 1V, then flattens out
at 1V. A smaller threshold voltage forces the output
GATE drive to terminate earlier, which reduces the total
PWM turn-on time and makes the output power equal to
that of low line input. This proprietary internal
compensation ensures a constant output power limit for
a wide AC input voltage range (90VAC to 264VAC).
Startup Current
The startup current is only 9μA. Low startup current
allows a startup resistor with high resistance and low-
wattage to supply the startup power for the controller. A
1.5MΩ, 0.25W, startup resistor and a 10µF/25V VDD
hold-up capacitor are sufficient for an AC-to-DC power
adapter with a wide input range (100VAC to 240VAC).
Operating Current
The operating current has been reduced to 3mA. The
low operating current results in higher efficiency and
reduces the VDD hold-up capacitance requirement.
Under-Voltage Lockout (UVLO)
The turn-on and turn-off thresholds are fixed internally
at 16.5V and 9.5V. During startup, the hold-up capacitor
must be charged to 16.5V through the startup resistor to
enable the SG6859A. The hold-up capacitor continues
to supply VDD until power can be delivered from the
auxiliary winding of the main transformer. VDD must not
drop below 9.5V during this startup process. This UVLO
hysteresis window ensures that hold-up capacitor is
adequate to supply VDD during startup.
Green-Mode Operation
The proprietary green-mode function provides off-time
modulation to linearly decrease the switching frequency
under light-load conditions. On-time is limited to provide
stronger protection against brownouts and other
abnormal conditions. The feedback current, which is
sampled from the voltage feedback loop, is taken as the
reference. Once the feedback current exceeds the
threshold current, the switching frequency starts to
decrease. This green-mode function dramatically
reduces power consumption under light-load and zero-
load conditions. Power supplies using the SG6859A
can meet even the strictest regulations regarding
standby power consumption.
Gate Output
The BiCMOS output stage is a fast totem pole gate
driver. Cross conduction has been avoided to minimize
heat dissipation, increase efficiency, and enhance
reliability. The output driver is clamped by an internal
17V Zener diode to protect power MOSFET transistors
against undesired over-voltage gate signals.
Oscillator Operation
A resistor connected from the RI pin to ground
generates a constant current source used to charge an
internal capacitor. The charge time determines the
internal clock speed and the switching frequency.
Increasing the resistance reduces the amplitude of the
input current and the switching frequency. A 95kΩ RI
resistor results in a 50µA constant current, II, and a
70kHz switching frequency. The relationship between RI
and the switching frequency is:
Built-in Slope Compensation
The sensed voltage across the current-sense resistor is
used for current-mode control and pulse-by-pulse
current limiting. Built-in slope compensation improves
stability and prevents sub-harmonic oscillations due to
peak-current mode control. The SG6859A has a
synchronized, positively-sloped ramp built-in at each
switching cycle. The slope of the ramp is:
6650
RI(kΩ)
fPWM =
(kHz)
(1)
0.36 ×Duty
(2)
Duty(max.)
Leading-Edge Blanking
Each time the power MOSFET is switched on, a turn-on
spike occurs at the sense-resistor. To avoid premature
termination of the switching pulse, a 320ns leading-
edge blanking time is built in. Conventional RC filtering
can be omitted. During this blanking period, the current-
limit comparator is disabled and cannot switch off the
gate driver.
Noise Immunity
Noise from the current sense or the control signal can
cause significant pulse-width jitter, particularly in
continuous-conduction mode (CCM). While slope
compensation helps alleviate these problems, further
precautions should still be taken. Good placement and
layout practices should be followed. Avoiding long PCB
traces and component leads, locating compensation
and filter components near the SG6859A, and increasing
power MOS gate resistance improve performance.
Constant Output Power Limit
When the SENSE voltage across the sense resistor,
RS, reaches the threshold voltage (around 1V), the
© 2007 Fairchild Semiconductor Corporation
SG6859A • Rev. 1.0.3
www.fairchildsemi.com
9
Applications Information
L1
F1
1
2
L
BD1
C3
R3
R4
R1
R2
CX1
2
4
C1
C2
R5
L2
D4
T1
10
9
1,2
2
1
1
2
N
VO
R10
D1
Q1
C7
8
5
C8
D5
C9
U1
GND GATE
R7
1
2
3
6
5
4
1
7
3,4
FB
RI
VDD
GND
R15
SENSE
C6
C11
R9
R6
D2
R8
1
2
R11
C4
R13
U2
R14
C10
CY1
U3
1
R12
Figure 16. Reference Circuit
Reference
Bill of Materials (BOM)
Reference
Component
Component
BD1
BD 1A/500V
L2
10µH 6mm
CX1 (Optional)
XC 0.1μF
Q1
MOSFET 1A/600V
R 750KΩ 1206
R 47KΩ 1206
R 47Ω 1206
R 4.7Ω 1206
R 100Ω 0805
R 10Ω 1206
R 100KΩ 0805
R 10Ω 1206
R 100Ω 1/8W
R 33KΩ 0805
R 33KΩ 1/8W
R 4.7KΩ 0805
R 0Ω 0805
CY1 (Optional)
YC 1nF/400V (Y1)
CC 10nF/500V
EC 10μF/400V 105°C
CC 1nF/500V
R1,R2
R3,R4
R5
C1
C2
C3
R6
C4
EC 10μF/50V
R7
C6
CC 4.7nF 0805
CC 1nF/100V 1206
EC 470μF/10V 105°C
EC 220μF/10V 105°C
CC 2.2nF 0805
N.C.
R8
C7 (Optional)
R9
C8
R10 (Optional)
R11
R12
R13
R14
R15
T1
C9
C10
C11
D1
Diode FRI07
D2
Diode FR102
D4
Diode SB360
EE-16
D5 (Optional)
ZD 6.8V 0.5W
R 1Ω/0.5W
U1
IC SG6859A
PC817
F1
L1
U2
20mH 6•8mm
U3
TL431
© 2007 Fairchild Semiconductor Corporation
SG6859A • Rev. 1.0.3
www.fairchildsemi.com
10
Physical Dimensions
9.83
9.00
6.67
6.096
8.255
7.61
3.683
3.20
7.62
5.08 MAX
0.33 MIN
3.60
3.00
(0.56)
2.54
0.356
0.20
0.56
0.355
9.957
7.87
1.65
1.27
7.62
NOTES: UNLESS OTHERWISE SPECIFIED
A) THIS PACKAGE CONFORMS TO
JEDEC MS-001 VARIATION BA
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS ARE EXCLUSIVE OF BURRS,
MOLD FLASH, AND TIE BAR EXTRUSIONS.
D) DIMENSIONS AND TOLERANC
ASME Y14.5M-1994
ES PER
E) DRAWING FILENAME AND REVSION: MKT-N08FREV2.
Figure 17. 8-Pin, Dual Inline Package (DIP)
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify
or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically
the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2007 Fairchild Semiconductor Corporation
SG6859A • Rev. 1.0.3
www.fairchildsemi.com
11
Physical Dimensions (Continued)
Figure 18. 6-Pin, SSOT-6 Package
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify
or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically
the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2007 Fairchild Semiconductor Corporation
SG6859A • Rev. 1.0.3
www.fairchildsemi.com
12
© 2007 Fairchild Semiconductor Corporation
SG6859A • Rev. 1.0.3
www.fairchildsemi.com
13
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