SG6860SZ [FAIRCHILD]
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| 型号： | SG6860SZ |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | 暂无描述 转换器 控制器 |
| 文件： | 总11页 (文件大小：549K) |
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March 2008
SG6860
Low-Cost, Green-Mode PWM Controller for
Flyback Converters
Features
Description
This highly integrated PWM controller provides several
enhancements designed to meet the low standby-power
needs of low-power SMPS. To minimize standby power
Green-Mode PWM
Supports the “Blue Angel” Eco Standard
Low Start-up Current: 9µA
consumption,
a
proprietary green-mode function
Low Operating Current: 3mA
Leading-Edge Blanking
provides off-time modulation to linearly decrease the
switching frequency under light-load conditions. This
green-mode function enables the power supply to meet
even strict power conservation requirements.
Constant Output Power Limit
Universal Input
The BiCMOS fabrication process enables reducing the
start-up current to 9µA and the operating current to
3mA. To further improve power conservation, a large
start-up resistance can be used. Built-in synchronized
slope compensation ensures the stability of peak
current mode control. Proprietary internal compensation
provides a constant output power limit over a universal
AC input range (90VAC to 264VAC). Pulse-by-pulse
current limiting ensures safe operation even during
short-circuits.
Built-in Synchronized Slope Compensation
Current Mode Operation
Cycle-by-cycle Current Limiting
Under-Voltage Lockout (UVLO)
Programmable PWM Frequency with Frequency
Hopping
VDD Over-Voltage Protection (Latch off)
Gate Output Voltage Clamped at 17V
Low Cost
To protect the external power MOSFET from being
damaged by supply over voltage, the SG6860’s output
driver is clamped at 17V. SG6860 controllers can
improve the performance and reduce the production
cost of power supplies. The SG6860 can replace linear
and RCC-mode power adapters. It is available in 8-pin
DIP and 6-pin SOT-26 packages.
Few External Components Required
Small SOT-26 Package
Applications
Power Adaptors
Open-Frame SMPS
Ordering Information
Part Number
SG6860TZ
Operating Temperature Range
Package
Packing Method
Tape & Reel
Rail
-40°C to +85°C
-40°C to +85°C
Small SOT-26 Package
SG6860DZ
8-pin Dual in-line Package (DIP)
All packages are lead free per JEDEC: J-STD-020B standard.
© 2008 Fairchild Semiconductor Corporation
SG6860 • Rev. 1.0.1
www.fairchildsemi.com
Application Diagram
CIN
10µ
SG6860
Figure 1. Typical Application
Block Diagram
Figure 2. Function Block Diagram
© 2008 Fairchild Semiconductor Corporation
SG6860 • Rev. 1.0.1
www.fairchildsemi.com
2
Pin Configuration
Figure 3. DIP Pin Configuration (Top View)
Figure 4. SOT Pin Configuration (Top View)
Pin Definitions
Pin #
DIP
Pin #
(SOT)
Name Description
1
2
3
(6)
(5)
--
GATE
VDD
NC
Driver Output. The totem-pole output driver for driving the power MOSFET.
Power Supply.
No Connection.
Current Sense. This pin senses the voltage across a resistor. When the voltage
reaches the internal threshold, PWM output is disabled, which activates over-current
protection. This pin also provides current amplitude data for current-mode control.
4
(4)
SENSE
Reference Setting. A resistor connected from the RI pin to ground generates a
constant current source used to charge an internal capacitor and determine the
switching frequency. Increasing the resistance reduces the amplitude of the current
source and reduces the switching frequency. A 95kΩ resistor, RI, results in a 13µA
constant current, II, and a 70kHz switching frequency.
5
(3)
RI
6
7
8
--
NC
FB
No Connection.
(2)
(1)
Feedback.
GND
Ground. For ATX SMPS, it detects AC line voltage through the main transformer.
© 2008 Fairchild Semiconductor Corporation
SG6860 • Rev. 1.0.1
www.fairchildsemi.com
3
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device
reliability. The absolute maximum ratings are stress ratings only.
Symbol
VVDD
VFB
Parameter
Min.
Max.
30
Unit
V
DC Supply Voltage
-0.3
-0.3
7.0
V
Input Voltage to FB Pin
7.0
V
VSENSE
PD
Input Voltage to Sense Pin
Power Dissipation
300
mW
°C
+150
208.4
82.5
+150
TJ
Operating Junction Temperature
SOT
DIP
°C/W
°C/W
°C
θJA
Thermal Resistance (Junction-to-Air)
-55
TSTG
TL
Storage Temperature Range
+260
3.5
Lead Temperature (Wave Soldering or IR, 10 seconds)
Electrostatic Discharge Capability, Human Body Model
Electrostatic Discharge Capability, Machine Model
°C
KV
V
ESD
200
Notes:
1. All voltage values, except differential voltage, are given with respect to GND pin.
2. Stresses beyond those listed under “absolute maximum ratings“ may cause permanent damage to the device.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
Parameter
Operating Ambient Temperature
Min.
Typ.
Max.
Unit
TA
-40
+85
°C
© 2008 Fairchild Semiconductor Corporation
SG6860 • Rev. 1.0.1
www.fairchildsemi.com
4
Electrical Characteristics
VDD =15V, TA= 25°C, unless noted operating specs.
Symbol
Parameter
Conditions
Min.
Typ. Max. Units
VDD Section
VDD-OP
VDD-ON
Continuous Operation Voltage
Turn-on Threshold Voltage
22
17.5
10.5
15
V
V
15.5
8.5
16.5
9.5
9
VDD-OFF Turn-off Threshold Voltage
V
IDD-ST
IDD-OP
Start-up Current
µA
V
DD=VDD-ON – 0.1V
VDD=15V, GATE with
1nF to GND
Operating Supply Current
3.0
3.5
26
mA
VDD-OVP VDD Over-voltage Protection Level
Latch off
Latch off
VDD=5V
24
40
25
120
50
V
tD-VDDOVP VDD Over-voltage Protection Debounce
µs
µA
IDD-H
Feedback Input Section
ZFB Input Impedance
VFB-OPEN FB Output High Voltage
Holding Current after OVP Latch-off
60
5
KΩ
5
V
V
VFB-OL
tD-OLP
VFB-N
VFB-G
SG
FB Open-loop Trigger Level
4.7
54
Delay Time of FB Pin Open-loop Protection
Green-Mode Entry FB Voltage
Green-Mode Ending FB Voltage
Green-Mode Modulation Slope
ms
V
2.60
40
2.85
2.2
75
3.10
100
V
RI=95KΩ
Hz/mV
Current-Sense Section
ZSENSE
tPD
Input Impedance
10
40
KΩ
ns
V
Delay to Output
55
1
100
VSTHFL
VSTHVA
tLEB
Flat Threshold Voltage for Current Limit
Valley Threshold Voltage for Current Limit
Leading-Edge Blanking Time
0.65
250
0.70
300
40
0.75
350
V
ns
%
DCYSAW Duty Cycle of SAW Limit
Maximum Duty Cycle
Oscillator Section
Center Frequency
fOSC
65
0
70
±4.9
3.7
75
RI=95KΩ
KHz
Hopping Range
tHOP
fOSC-G
fDV
Hopping Period
RI=95KΩ
ms
KHz
%
Green-Mode Frequency
Frequency Variation vs. VDD Deviation
RI=95KΩ
20
VDD=13.5 to 22V
0.02
2.00
2
Frequency Variation vs. Temperature
Deviation
fDT
TA=-20 to 85°C
%
Output Section
DCYMAX Maximum Duty Cycle
VGATE-L Output Voltage Low
VGATE-H Output Voltage High
70
8
75
80
%
V
VDD=15V, IO=20mA
VDD=13.5V, IO=20mA
VDD=15V, CL=1nF
VDD=15V, CL=1nF
1.5
V
tr
tf
Rising Time
Falling Time
135
35
ns
ns
VGATE-
CLAMP
Output Clamp Voltage
VDD=22V
16
17
18
V
© 2008 Fairchild Semiconductor Corporation
SG6860 • Rev. 1.0.1
www.fairchildsemi.com
5
Typical Performance Characteristics
9.6
9.4
9.2
9.0
8.8
8.6
17.0
16.9
16.8
16.7
16.6
16.5
-40 -25 -10
5
20 35 50 65 80 95 110 125
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (
Temperature (
)
℃
)
℃
Figure 5. VDD-ON vs. TA
Figure 6. VDD-OFF vs. TA
3.5
15.0
13.0
11.0
9.0
3.3
3.1
2.9
2.7
2.5
7.0
5.0
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (
-40 -25 -10
5
20 35 50 65 80 95 110 125
)
℃
Temperature (
)
℃
Figure 7. IDD-ST vs. TA
Figure 8. IDD-OP vs. TA
75.0
74.6
74.2
73.8
73.4
73.0
67.0
66.8
66.6
66.4
66.2
66.0
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (
)
℃
)
℃
Figure 9. fOSC vs. TA
Figure 10. DCYMAX vs. TA
© 2008 Fairchild Semiconductor Corporation
SG6860 • Rev. 1.0.1
www.fairchildsemi.com
6
Typical Performance Characteristics (Continued)
3.00
2.96
2.92
2.88
2.84
2.80
2.30
2.26
2.22
2.18
2.14
2.10
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (
)
℃
)
℃
Figure 11. VFB-N vs. TA
Figure 12. VFB-G vs. TA
400
360
320
280
240
200
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (
)
℃
Figure 13. tLEB vs. TA
© 2008 Fairchild Semiconductor Corporation
SG6860 • Rev. 1.0.1
www.fairchildsemi.com
7
Functional Description
SG6860 integrates many useful designs into one
controller for low-power switch-mode power supplies.
The following descriptions highlight some of the
features of the SG6860 series.
Constant Output Power Limit
When the SENSE voltage across the sense resistor,
RS, reaches the threshold voltage (~1.00V), the output
GATE drive is turned off after propagation delay, tPD
.
This propagation delay introduces an additional current
proportional to tPD•VIN/Lp. The propagation delay is
nearly constant, regardless of the input line voltage VIN.
Higher input line voltages result in larger additional
currents. At high input line voltages, the output power
limit is higher than at low input line voltages.
Start-up Current
The start-up current is only 9µA, which allows a start-
up resistor with high resistance and low-wattage to
supply the start-up power for the controller. A 1.5MΩ,
0.25W, start-up resistor and a 10µF/25V VDD hold-up
capacitor are sufficient for an AC-to-DC power adapter
To compensate for this output power limit variation
across a wide AC input range, the threshold voltage is
adjusted by adding a positive ramp. This ramp signal
rises from 0.70V to 1.00V, then flattens out at 1.00V. A
smaller threshold voltage forces the output GATE drive
to terminate earlier. This reduces the total PWM turn-
on time and makes the output power equal to that of
low line input. This proprietary internal compensation
ensures a constant output power limit for a wide AC
input voltage range (90VAC to 264VAC).
with a wide input range of 90VAC to 264VAC
.
Operating Current
The operating current has been reduced to 3mA, which
results in higher efficiency and reduces the VDD hold-up
capacitance requirement.
Green-Mode Operation
The proprietary green-mode function provides off-time
modulation to linearly decrease the switching
frequency under light-load conditions. On-time is
limited to provide stronger protection against
brownouts and abnormal conditions. The feedback
current, which is sampled from the voltage feedback
loop, is taken as the reference. Once the feedback
current exceeds the threshold current, the switching
frequency starts to decrease. This green-mode
function dramatically reduces power consumption
under light-load and zero-load conditions. Power
supplies using the SG6860 can meet even strict
regulations regarding standby power consumption.
Under-Voltage Lockout (UVLO)
The turn-on and turn-off thresholds are fixed internally
at 16.5V and 9.5V. During start-up, the hold-up
capacitor must be charged to 16.5V through the start-
up resistor to enable SG6860. The hold-up capacitor
continues to supply VDD until power can be delivered
from the auxiliary winding of the main transformer. VDD
must not drop below 9.5V during the start-up process.
This UVLO hysteresis window ensures that the hold-up
capacitor is adequate to supply VDD during start-up.
Gate Output
The SG6860 BiCMOS output stage is a fast totem pole
gate driver. Cross conduction has been avoided to
minimize heat dissipation, increase efficiency, and
enhance reliability. The output driver is clamped by an
internal 17V Zener diode to protect power MOSFET
transistors against undesired over-voltage gate signals.
Oscillator Operation
A resistor connected from the RI pin to ground
generates a constant current source used to charge an
internal capacitor. The charge time determines the
internal clock speed and the switching frequency.
Increasing the resistance reduces the amplitude of the
input current and reduces the switching frequency. A
95kΩ resistor, RI, results in a 13µA constant current, II,
and a 70kHz switching frequency. The relationship
between RI and the switching frequency is:
Built-in Slope Compensation
The sensed voltage across the current sense resistor
is used for current mode control and pulse-by-pulse
current limiting. Built-in slope compensation improves
stability and prevents sub-harmonic oscillations due to
peak current mode control. The SG6860 has a
synchronized, positively-sloped ramp built-in at each
switching cycle. The slope of the ramp is:
(1)
6650
fPWM
=
(kHz)
RI (kΩ)
The range of the oscillation frequency is designed to
be within 50kHz ~ 100kHz.
(2)
0.36 × Duty
Duty(max.)
Leading-Edge Blanking
Noise Immunity
Each time the power MOSFET is switched on, a turn-
on spike occurs at the sense-resistor. To avoid
premature termination of the switching pulse, a 300ns
leading-edge blanking time is built in. Conventional RC
filtering can therefore be omitted. During this blanking
period, the current-limit comparator is disabled and
cannot switch off the gate driver.
Noise from the current sense or the control signal can
cause significant pulse-width jitter, particularly in
continuous-conduction mode. While slope compensation
helps alleviate these problems, further precautions
should be taken. Good placement and layout practices
should be followed. Avoiding long PCB traces and
component leads, locating compensation and filter
components near the SG6860, and increasing power
MOS gate resistance improve performance.
© 2008 Fairchild Semiconductor Corporation
SG6860 • Rev. 1.0.0
www.fairchildsemi.com
8
Mechanical Dimensions
D
Detail A
b
6
4
3
c
1
e
e1
θ
1
L
θ
L1
θ
1
Detail A
Figure 14. 6-SOTIC
Dimensions
Millimeter
Typ.
Inch
Typ.
Symbol
Min.
A
A1
Max.
1.45
0.15
1.30
0.50
0.22
Min.
Max.
0.057
0.006
0.051
0.020
0.009
A2
b
c
0.76
0.30
0.08
1.03
0.030
0.011
0.003
0.041
D
E
E1
e
e1
L
L1
L2
R1
R2
θ˚
θ1˚
2.90
2.80
1.60
0.95
1.90
0.45
0.60
0.25
0.114
0.110
0.063
0.037
0.075
0.018
0.024
0.010
0.30
0.60
0.020
0.024
0.10
0.10
0˚
0.004
0.004
0˚
0.25
8˚
15˚
0.010
8˚
15˚
4˚
10˚
4˚
10˚
5˚
5˚
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify
or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
© 2008 Fairchild Semiconductor Corporation
SG6860 • Rev. 1.0.0
www.fairchildsemi.com
9
Mechanical Dimensions (Continued)
D
Θ
8
5
e
B
E
1
4
L
b1
b
e
Figure 15. 8-DIPIC
Dimensions
Millimeter
Typ.
Inch
Typ.
Symbol
Min.
Max.
Min.
Max.
A
A1
A2
b
b1
D
E
E1
e
5.334
0.210
0.381
3.175
0.015
0.125
3.302
1.524
0.457
9.271
7.620
6.350
2.540
3.302
9.017
7˚
3.429
0.130
0.060
0.018
0.365
0.300
0.250
0.100
0.130
0.355
7˚
0.135
9.017
6.223
10.160
6.477
0.355
0.245
0.400
0.255
L
eB
θ˚
2.921
8.509
0˚
3.810
9.525
15˚
0.115
0.335
0˚
0.150
0.375
15˚
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify
or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
© 2008 Fairchild Semiconductor Corporation
SG6860 • Rev. 1.0.1
www.fairchildsemi.com
10
© 2008 Fairchild Semiconductor Corporation
SG6860 • Rev. 1.0.1
www.fairchildsemi.com
11
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