SPT9689AIP [FAIRCHILD]
DUAL ULTRAFAST VOLTAGE COMPARATOR; 双超快型电压比较器
| 型号： | SPT9689AIP |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | DUAL ULTRAFAST VOLTAGE COMPARATOR |
| 文件： | 总8页 (文件大小：78K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SPT9689
DUAL ULTRAFAST VOLTAGE COMPARATOR
TECHNICAL DATA
FEBRUARY 20, 2001
FEATURES
APPLICATIONS
• 650 ps propagation delay
• 100 ps propagation delay variation
• 70 dB CMRR
• Low feedthrough and crosstalk
• Differential latch control
• ECL compatible
• Automated test equipment
• High-speed instrumentation
• Window comparators
• High-speed timing
• Line receivers
• High-speed triggers
• Threshold detection
• Peak detection
GENERAL DESCRIPTION
The SPT9689 is a Subnanosecond monolithic dual com- ECL-compatible complementary digital outputs are ca-
parator. The propagation delay variation is less than pable of driving 50 Ω terminated transmission lines and
100 ps from 5 to 50 mV input overdrive voltage. The input providing 30 mA output drive.The SPT9689 is pin compat-
slew rate is 10 V/ns. The device utilizes a high precision ible with the SPT9687. It is available in 20-lead PLCC and
differential input stage with a common-mode range of 20-contact LCC packages over the industrial temperature
–2.5 V to +4.0 V.
range. The SPT9689 is also available in die form.
BLOCK DIAGRAM
INVERTING
NONINVERTING
INPUT
INPUT
+
LATCH ENABLE
LATCH ENABLE
A
Q OUTPUT
Q OUTPUT
VEE
VCC
GNDB
GNDA
Q OUTPUT
Q OUTPUT
B
LATCH ENABLE
LATCH ENABLE
+
INVERTING
INPUT
NONINVERTING
INPUT
ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)1 25 °C
Supply Voltages
Output
Output Current ................................................... 30 mA
Positive Supply Voltage (VCC to GND).... –0.5 to +6.0 V
Negative Supply Voltage (VEE to GND) .. –6.0 to +0.5 V
Ground Voltage Differential .................... –0.5 to +0.5 V
Temperature
Operating Temperature, ambient............ –40 to +85 °C
junction ..................... +150 °C
Input Voltages
Input Common Mode Voltage ................. –4.0 to +5.0 V
Differential Input Voltage ........................ –3.0 to +3.0 V
Input Voltage, Latch Controls .................... VEE to 0.5 V
Lead Temperature, (soldering 60 seconds) ..... +300 °C
Storage Temperature............................ –65 to +150 °C
Note: 1. Operation at any Absolute Maximum Rating is not implied.See
Electrical Specifications for proper nominal applied conditions
in typical applications.
ELECTRICAL SPECIFICATIONS
T A = +25 °C, VCC = +5.0 V, VEE =–5.20 V, RL = 50 Ohm to –2 V, unless otherwise specified.
TEST
CONDITIONS
TEST
LEVEL
SPT9689A
MIN TYP MAX
SPT9689B
MIN TYP MAX
PARAMETERS
UNITS
DC CHARACTERISTICS
Input Offset Voltage
Input Offset Voltage
VIN, CM=0, RS=0 Ohms1
VIN, CM=0, RS=0 Ohms1
TMIN<TA<TMAX
I
–10 ±3.0
10
15
–25
–30
±12
25
30
mV
IV
V
–15 ±4.5
±15
40
mV
µV/°C
Offset Voltage Tempco
10
Input Bias Current
Input Bias Current
Input Offset Current
Input Offset Current
I
IV
I
IV
±8
±12
±1.0 ±3.0
±2.0 ±5.0
±25
±38
±8
±12
±2.0
±4.0
±25
±38
±5.0
±7.0
µA
µA
µA
µA
TMIN<TA<TMAX
TMIN<TA<TMAX
Positive Supply Current
Negative Supply Current
Dual
Dual
I
I
18
40
30
55
18
40
35
60
mA
mA
Positive Supply Voltage, VCC
Negative Supply Voltage, VEE
IV
IV
4.75
5.0 5.25
4.75
5.0
5.25
V
V
–4.95 –5.2 –5.45 –4.95 –5.2 –5.45
Input Common Mode Range
V
–2.5
+4.0
–2.5
+4.0
V
Latch Enable
Common Mode Range
Open Loop Gain
Differential Input Resistance
Input Capacitance
Power Supply Sensitivity
IV
V
V
V
V
V
–2.0
0
–2.0
0
V
66
500
0.6
70
66
500
0.6
70
dB
kΩ
pF
dB
dB
Common Mode Rejection Ratio VCM=–2.5 to +4.0
70
70
Power Dissipation
Power Dissipation
Dual, Without Load
Dual, With Load
I
I
350
400
425
550
350
400
475
550
mW
mW
Output High Level
Output Low Level
ECL 50 Ohms to –2 V
ECL 50 Ohms to –2 V
I
I
–1.00
–1.95
–.81 –1.00
–1.54 –1.95
–.81
–1.54
V
V
AC CHARACTERISTICS
Propagation Delay
20 mV O.D.
IV
650
850
750
950
ps
Latch Set-up Time
Latch to Output Delay
Latch Pulse Width
Latch Hold Time
V
V
V
V
150
500
500
0
300
600
150
500
500
0
300
600
ps
ps
ps
ps
250 mV O.D.
Rise Time
Fall Time
20% to 80%
20% to 80%
V
V
180
80
180
80
ps
ps
Slew Rate
Bandwidth
1RS = Source impedance
V
V
10
900
10
900
V/ns
MHz
–3 dB
SPT9689
2
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LEVEL TEST PROCEDURE
TEST LEVEL CODES
All electrical characteristics are subject to the
following conditions:
I
100% production tested at the specified temperature.
II
100% production tested at TA = +25 °C, and sample tested at the
specified temperatures.
All parameters having min/max specifications
are guaranteed. The Test Level column indi-
cates the specific device testing actually per-
formed during production and Quality Assur-
ance inspection. Any blank section in the data
column indicates that the specification is not
tested at the specified condition.
III
IV
QA sample tested only at the specified temperatures.
Parameter is guaranteed (but not tested) by design and characteri-
zation data.
V
Parameter is a typical value for information purposes only.
VI
100% production tested at TA = +25 °C. Parameter is guaranteed
over specified temperature range.
falling edge for the comparator to accept data. After tH, the
output ignores the input status until the latch is strobed
again. A minimum latch pulse width of tpL is needed for
strobe operation, and the output transitions occur after a
TIMING INFORMATION
The timing diagram for the comparator is shown in figure
1. If LE is high and LE low in the SPT9689, the comparator
tracks the input difference voltage. When LE is driven low
and LE high, the comparator outputs are latched into their
existing logic states.
time of tpLOH or tpLOL
.
The set-up and hold times are a measure of the time
required for an input signal to propagate through the first
stage of the comparator to reach the latching circuitry.
Input signals occurring before tS will be detected and held;
those occurring after tH will not be detected. Changes
between tS and tH may not be detected.
The leading edge of the input signal (which consists of a
20 mV overdrive voltage) changes the comparator output
after a time of tpdL or tpdH (Q or Q). The input signal must
be maintained for a time tS (set-up time) before the LE fall-
ing edge and LE rising edge and held for time tH after the
Figure 1 – Timing Diagram
Latch Enable
50%
Latch Enable
tH
t
pL
t
S
Differential
Input Voltage
V ± V
REF OS
V
OD
t
t
pLOH
pdL
Output Q
Output Q
50%
50%
t
t
pdH
pLOL
V
+=100 mV (p-p), V =20 mV
IN OD
SPT9689
3
2/20/01
SWITCHING TERMS (Refer to figure 1)
tpLOL LATCH ENABLE TO OUTPUT LOW DELAY – the
propagation delay measured from the 50% point of
the Latch Enable signal LOW to HIGH transition to
the 50% point of an output HIGH to LOW transition
tpdH INPUT TO OUTPUT HIGH DELAY – the propaga-
tion delay measured from the time the input signal
crosses the reference (± the input offset voltage) to
the 50% point of an output LOW to HIGH transition tH
MINIMUM HOLD TIME – the minimum time after the
negative transition of the Latch Enable signal that
the input signal must remain unchanged in order to
be acquired and held at the outputs
tpdL INPUT TO OUTPUT LOW DELAY – the propagation
delay measured from the time the input signal
crosses the reference (± the input offset voltage) to
the 50% point of an output HIGH to LOW transition tpL MINIMUM LATCH ENABLE PULSE WIDTH – the
minimum time that the Latch Enable signal must be
HIGH in order to acquire an input signal change
t
pLOH LATCH ENABLE TO OUTPUT HIGH DELAY – the
propagation delay measured from the 50% point of
the Latch Enable signal LOW to HIGH transition to tS
the 50% point of an output LOW to HIGH transition
MINIMUM SET-UP TIME – the minimum time before
the negative transition of the Latch Enable signal
that an input signal change must be present in order
to be acquired and held at the outputs
VOD VOLTAGE OVERDRIVE – the difference between
the differential input and reference input voltages
GENERAL INFORMATION
The negative common mode voltage is –2.5 V. The posi-
tive common mode voltage is +4.0 V.
The SPT9689 is an ultrahigh-speed dual voltage com-
parator. It offers tight absolute characteristics. The device
has differential analog inputs and complementary logic
outputs compatible with ECL systems.The output stage is
adequate for driving terminated 50 ohm transmission
lines.
The dual comparators share the same VCC and VEE con-
nections but have separate grounds for each comparator
to achieve high crosstalk rejection.
The SPT9689 has a complementary latch enable control
for each comparator. Both should be driven by standard
ECL logic levels.
Figure 2 – Internal Function Diagram
Q
V
V
+
IN
PRE
AMP
ECL
OUT
LATCH
IN
Q
REF
1
REF
2
CLK
BUF
V
V
GND
LE
LE
EE
CC
SPT9689
4
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TYPICAL PERFORMANCE CHARACTERISTICS
PROPAGATION DELAY VS OVERDRIVE VOLTAGE
RISE AND FALL OF OUTPUTS VS TIME CROSSOVER
800
.90
1.10
1.30
750
700
650
600
1.50
1.70
1.90
550
500
400
500
600
700
TIME (ps)
800
900
0
20
40
60
80
100
OVERDRIVE (mV)
RISE TIME VS TEMPERATURE
FALL TIME VS TEMPERATURE
260
280
240
200
220
180
140
160
100
60
120
80
50
0
+50
+100
+150
-50
0
+50
+100
+150
TEMPERATURE (°C)
TEMPERATURE (°C)
HYSTERESIS VS
DLATCH
INPUT BIAS CURRENT VS COMMON MODE VOLTAGE
11
20
16
12
9
T=-55 °C
7
T=+25 °C
5
8
4
T=+125 °C
3
1
0
0
10
20
30
40
50
3.0
2.0
1.0
0.0
+1.0
+2.0
+3.0
+4.0
+5.0
D
LATCH = V V (mV)
COMMON MODE VOLTAGE (V)
LE LE
SPT9689
5
2/20/01
TYPICAL INTERFACE CIRCUIT
to decrease parasitic feedback. If the output board traces
are longer than approximately half an inch, microstripline
techniques must be employed to prevent ringing on the
output waveform. Also, the microstriplines must be termi-
nated at the far end with the characteristic impedance of
the line to prevent reflections. Both supply voltage pins
should be decoupled with high-frequency capacitors as
close to the device as possible. All ground pins and no
connects should be soldered to a common ground plane
The typical interface circuit using the comparator is shown
in figure 3. Although it needs few external components
and is easy to apply, there are several conditions that
should be noted to achieve optimal performance.The very
high operating speeds of the comparator require careful
layout, decoupling of supplies, and proper design of trans-
mission lines.
Since the SPT9689 comparator is a very high-frequency to further improve noise immunity. If using the SPT9689
and high-gain device, certain layout rules must be fol- as a single comparator, the outputs of the inactive com-
lowed to avoid oscillations. The comparator should be parator can be grounded, left open, or terminated with
soldered to the board with component lead lengths kept 50 ohms to –2 V. All outputs on the active comparator,
as short as possible. A ground plane should be used while whether used or unused, should have identical termina-
the input impedance to the part is kept as low as possible tions to minimize ground current switching transients.
Figure 4 – SPT9689 Typical Interface Circuit
with Hysteresis
Figure 3 – SPT9689 Typical Interface Circuit
+5.0 V
2 V
+5.0 V
0 to 200 W
100 W
1.3 V
ECL
10 µF
0.1 µF
100 pF
10 µF
0.1 µF
100 pF
+V
+V
CC
CC
V
V
IN
+
IN
+
LE
LE
LE
LE
Q Output
Q Output
Q Output
Q Output
GND
GND
V
EE
V
REF
V
V
EE
REF
R
R
L
L
50 W
50
W
100 pF
0.1 µF
100 pF
0.1 µF
10 µF
R
L
R
L
50 W
100 pF
100 pF
10 µF
0.1 µF
50
W
0.1 µF
10 µF
10 µF
10
F
10 µF
5.2 V
2 V
5.2 V
2 V
NOTES:
NOTES:
Denotes ground plane.
Ferrite bead. Fair Rite Part # 2643001501.
All resistors are chip type 1%.
Denotes ground plane.
Ferrite bead. Fair Rite Part # 2643001501.
All resistors are chip type 1%.
0.1 µF and 100 pF capacitors are chip type mounted as close
to the pins as possible.
0.1 µF and 100 pF capacitors are chip type mounted
as close to the pins as possible.
10 µF tant capacitors have lead lengths <0.25" long.
Represents line termination.
10 µF tant capacitors have lead lengths <0.25" long.
Represents line termination.
SPT9689
6
2/20/01
PACKAGE OUTLINES
20-Contact Leadless Chip Carrier (LCC)
A
H
INCHES
MILLIMETERS
MIN MAX
SYMBOL
MIN
MAX
A
B
C
D
E
F
.040 typ
.050 typ
1.02 typ
1.27 typ
G
0.045
0.345
0.054
0.055
0.360
0.066
1.14
8.76
1.37
1.40
9.14
1.68
Bottom
View
Pin 1
B
C
.020 typ
0.51 typ
G
H
0.022
0.028
0.075
0.56
0.71
1.91
F
D
E
20-Lead Plastic Leadless Chip Carrier (PLCC)
A
G
INCHES
MILLIMETERS
MIN MAX
SYMBOL
MIN
MAX
B
A
B
C
D
E
F
G
H
I
J
K
L
M
N
O
.045 typ
.045 typ
1.14 typ
1.14 typ
Pin 1
N
0.350
0.385
0.350
0.385
0.042
0.165
0.085
0.025
0.015
0.026
0.013
0.356
0.395
0.356
0.395
0.056
0.180
0.110
0.040
0.025
0.032
0.021
0.050
0.330
8.89
9.78
8.89
9.78
1.07
4.19
2.16
0.64
0.38
0.66
0.33
9.04
10.03
9.04
10.03
1.42
4.57
2.79
1.02
0.64
0.81
0.53
1.27
8.38
TOP
VIEW
M
O
E
F
L
K
C
D
J
I
H
Pin 1
0.290
7.37
BOTTOM
VIEW
SPT9689
7
2/20/01
PIN ASSIGNMENTS
PIN FUNCTIONS
NAME
QA
FUNCTION
QA
3
QA N/C QB QB
20 19
Output A
2
1
QA
Inverted Output A
Ground A
GNDA
LEA
LEA
VEE
GNDA
LEA
4
5
6
7
8
18 GNDB
Latch Enable A
LEB
N/C
17
16
Inverted Latch Enable A
Negative Supply Voltage
Inverting Input A
Noninverting Input A
Noninverting Input B
Inverting Input B
Positive Supply Voltage
Latch Enabled B
Inverted Latch Enable B
Ground B
TOP VIEW
N/C
LEA
–INA
+INA
+INB
–INB
VCC
LEB
LEB
GNDB
QB
15 LEB
14
VEE
VCC
9
10 11 12 13
INA +INA
+INB INB
N/C
LCC/PLCC
Output B
QB
Inverted Output B
ORDERING INFORMATION
PART
NUMBER
INPUT
TEMPERATURE
RANGE
PACKAGE
TYPE
OFFSET
10 mV
25 mV
10 mV
25 mV
SPT9689AIC
SPT9689BIC
SPT9689AIP
SPT9689BIP
SPT9689ACU
SPT9689BCU
–40 to +85 °C
–40 to +85 °C
–40 to +85 °C
–40 to +85 °C
+25 °C
20C LCC
20C LCC
20L PLCC
20L PLCC
Die*
+25 °C
Die*
*Please see the die specification for guaranteed electrical performance.
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO
IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR
USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR
THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS
WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems which, (a) are
intended for surgical implant into the body, or (b) support or sustain life,
and whose failure to perform, when properly used in accordance with
instructions for use provided in the labeling, can be reasonably
expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or
system whose failure to perform can be reasonably expected to cause
the failure of the life support device or system, or to affect its safety or
effectiveness.
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© Copyright 2002 Fairchild Semiconductor Corporation
SPT9689
8
2/20/01
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