SPT9689BIJ [FAIRCHILD]
Comparator, 2 Func, 30000uV Offset-Max, CDIP16, SIDE BRAZED, DIP-16;
| 型号： | SPT9689BIJ |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Comparator, 2 Func, 30000uV Offset-Max, CDIP16, SIDE BRAZED, DIP-16 放大器 CD |
| 文件： | 总8页 (文件大小：85K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SPT9689
DUAL ULTRAFAST VOLTAGE COMPARATOR
FEATURES
APPLICATIONS
• 650 ps Propagation Delay
• 100 ps Propagation Delay Variation
• 70 dB CMRR
• Low Feedthrough and Crosstalk
• Differential Latch Control
• ECL Compatible
• Automated Test Equipment
• High Speed Instrumentation
• Window Comparators
• High Speed Timing
• Line Receivers
• High Speed Triggers
• Threshold Detection
• Peak Detection
ECL-compatible complimentary digital outputs are capable
of driving 50 Ω terminated transmission lines and providing
GENERAL DESCRIPTION
The SPT9689 is a Subnanosecond monolithic dual com-
parator. The propagation delay variation is less than 100 ps
from 5 to 50 mV input overdrive voltage. The input slew rate
is 10 V/ns. The device utilizes a high precision differential
input stage with a common-mode range of -2.5 V to +4.0 V.
30 mA output drive. The SPT9689 is pin compatible with the
SPT9687. It is available in 16-lead sidebrazed DIP, 20-lead
PLCC and 20-contact LCC packages over the industrial
temperature range. The SPT9689 is also available in die
form.
BLOCK DIAGRAM
INVERTING
INPUT
NONINVERTING
INPUT
-
+
LATCH ENABLE
LATCH ENABLE
A
Q OUTPUT
Q OUTPUT
V
EE
V
GND
B
CC
GND
A
Q OUTPUT
Q OUTPUT
B
LATCH ENABLE
LATCH ENABLE
+
-
INVERTING
INPUT
NONINVERTING
INPUT
Signal Processing Technologies, Inc.
4755 Forge Road, Colorado Springs, Colorado 80907, USA
Phone: (719) 528-2300 FAX: (719) 528-2370 Website: http://www.spt.com E-Mail: sales@spt.com
ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)1 25 °C
Supply Voltages
Positive Supply Voltage (V
Output
Output Current ...................................................... 30 mA
to GND) .... -0.5 to +6.0 V
CC
Negative Supply Voltage (V to GND) ... -6.0 to +0.5 V
Ground Voltage Differential ...................... -0.5 to +0.5 V
EE
Temperature
Operating Temperature,ambient ...............-40 to +85 °C
junction........................ +150 °C
Input Voltages
Input Common Mode Voltage................... -4.0 to +5.0 V
Differential Input Voltage .......................... -3.0 to +3.0 V
Lead Temperature, (soldering 60 seconds) ...... +300 °C
Storage Temperature ..............................-65 to +150 °C
Input Voltage, Latch Controls ..................... V to 0.5 V
EE
Note: 1. Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for proper nominal
applied conditions in typical applications.
ELECTRICAL SPECIFICATIONS
T
= +25 °C V
= +5.0 V, V =-5.20 V, RL = 50 Ohm to -2 V, unless otherwise specified.
CC EE
A
TEST
CONDITIONS
TEST
LEVEL
SPT9689A
TYP
SPT9689B
TYP
PARAMETERS
MIN
-10
-15
MAX
10
MIN
-25
-30
MAX UNITS
DC CHARACTERISTICS
Input Offset Voltage
Input Offset Voltage
1
1
V
V
=0, R =0 Ohms
I
±3.0
±12
25 mV
IN, CM
S
=0, R =0 Ohms
IN, CM
S
T
<T <T
IV
V
I
±4.5
10
15
±15
40
30 mV
µV/°C
MIN
A
MAX
Offset Voltage Tempco
Input Bias Current
±8
±25
±38
±3.0
±5.0
30
±8
±25 µA
±38 µA
±5.0 µA
±7.0 µA
35 mA
60 mA
Input Bias Current
T
T
<T <T
IV
I
±12
±1.0
±2.0
18
±12
±2.0
±4.0
18
MIN
MIN
A
MAX
MAX
Input Offset Current
Input Offset Current
Positive Supply Current
Negative Supply Current
Positive Supply Voltage, V
<T <T
IV
I
A
Dual
Dual
I
40
55
40
IV
IV
V
4.75
-4.95
-2.5
5.0
-5.2
5.25
-5.45
+4.0
4.75
-4.95
-2.5
5.0
-5.2
5.25
-5.45
+4.0
V
V
V
CC
Negative Supply Voltage, V
EE
Input Common Mode Range
Latch Enable
Common Mode Range
Open Loop Gain
IV
V
V
V
V
V
V
I
-2.0
0
-2.0
0
V
66
500
2.0
0.6
70
66
500
2.0
0.6
70
dB
kΩ
pF
pF
dB
dB
Differential Input Resistance
Input Capacitance
Cerdip Package
LCC Package
Input Capacitance
Power Supply Sensitivity
Common Mode Rejection Ratio Vcmv=-2.5 to +4.0
70
70
Power Dissipation
Power Dissipation
Output High Level
Output Low Level
AC CHARACTERISTICS
Propagation Delay
Latch Set-up Time
Latch to Output Delay
Latch Pulse Width
Latch Hold Time
Rise Time
Dual, Without Load
Dual, With Load
350
400
425
550
350
400
475 mW
550 mW
I
ECL 50 Ohms to -2 V
ECL 50 Ohms to -2 V
I
-1.00
-1.95
-.81
-1.00
-1.95
-.81
V
V
I
-1.54
-1.54
20 mV O.D.
IV
V
V
V
V
V
V
V
V
650
150
500
500
0
850
300
600
750
150
500
500
0
950 ps
300 ps
600 ps
ps
250 mV O.D.
ps
20% to 80%
20% to 80%
180
80
180
80
ps
Fall Time
ps
Slew Rate
10
10
V/ns
Bandwidth
1
-3 dB
900
900
MHz
R = Source impedance.
S
SPT9689
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TEST LEVEL
TEST PROCEDURE
TEST LEVEL CODES
All electrical characteristics are subject to the
following conditions:
I
100% production tested at the specified temperature.
II
100% production tested at T =25 °C, and sample
A
tested at the specified temperatures.
All parameters having min/max specifications
are guaranteed. The Test Level column indi-
cates the specific device testing actually per-
formed during production and Quality Assur-
ance inspection. Any blank section in the data
column indicates that the specification is not
tested at the specified condition.
III
QA sample tested only at the specified temperatures.
IV
Parameter is guaranteed (but not tested) by design
and characterization data.
V
Parameter is a typical value for information purposes
only.
VI
100% production tested at T = 25 °C. Parameter is
A
guaranteed over specified temperature range.
The leading edge of the input signal (which consists of a
20 mV overdrive voltage) changes the comparator output
TIMING INFORMATION
after a time of t
or t
(Q or ). The input signal must be
Q
pdH
s
pdL
The timing diagram for the comparator is shown in figure 1.
If LE is high and low in the SPT9689, the comparator
maintained for a time t (set-up time) before the LE falling
LE
tracks the input difference voltage. When LE is driven low
and high, the comparator outputs are latched into their
edge and
rising edge and held for time t after the falling
H
LE
edge for the comparator to accept data. After t , the output
ignores the input status until the latch is strobed again. A
minimum latch pulse width of t is needed for strobe
H
LE
existing logic states.
pL
operation, and the output transitions occur after a time of
t
or t
.
pLOH
pLOL
Figure 1 - Timing Diagram
Latch Enable
Latch Enable
50%
tH
tpL
tS
Differential
Input Voltage
V
± V
OS
REF
50%
50%
V
OD
tpLOH
t pdL
Output Q
Output Q
tpdH
tpLOL
V
+=100 mV (p-p), V
=20 mV
OD
IN
The set-up and hold times are a measure of the time required for an input signal to propagate through the
first stage of the comparator to reach the latching circuitry. Input signals occurring before t will be detected
s
and held; those occurring after t will not be detected. Changes between t and t may not be detected.
H
s
H
SPT9689
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SWITCHING TERMS (Refer to figure 1)
t
t
LATCH ENABLE TO OUTPUT LOW DELAY - The
propagationdelaymeasuredfromthe50%pointofthe
Latch Enable signal LOW to HIGH transition to the
50% point of an output HIGH to LOW transition
pLOL
H
t
t
t
INPUT TO OUTPUT HIGH DELAY - The propagation
delaymeasured fromthetimetheinputsignalcrosses
the reference (± the input offset voltage) to the 50%
point of an output LOW to HIGH transition
pdH
MINIMUM HOLD TIME - The minimum time after the
negative transition of the Latch Enable signal that the
input signal must remain unchanged in order to be
acquired and held at the outputs
INPUT TO OUTPUT LOW DELAY - The propagation
delay measured from the time the input signal crosses
the reference (± the input offset voltage) to the 50%
point of an output HIGH to LOW transition
pdL
t
t
MINIMUM LATCH ENABLE PULSE WIDTH - The
minimum time that the Latch Enable signal must be
HIGH in order to acquire an input signal change
pL
S
LATCH ENABLE TO OUTPUT HIGH DELAY - The
propagationdelaymeasuredfromthe50%pointofthe
Latch Enable signal LOW to HIGH transition to 50%
point of an output LOW to HIGH transition
pLOH
MINIMUM SET-UP TIME - The minimum time before
the negative transition of the Latch Enable signal that
an input signal change must be present in order to be
acquired and held at the outputs
V
VOLTAGE OVERDRIVE - The difference between the
differential input and reference input voltages.
OD
GENERAL INFORMATION
The SPT9689 is an ultrahigh speed dual voltage compara-
tor. It offers tight absolute characteristics. The device has
differential analog inputs and complementary logic outputs
compatiblewithECLsystems. Theoutputstageisadequate
for driving terminated 50 ohm transmission lines.
The negative common mode voltage is -2.5 V. The
positive common mode voltage is +4.0 V.
ThedualcomparatorssharethesameV andV connec-
CC
EE
tions but have separate grounds for each comparator to
achieve high crosstalk rejection.
The SPT9689 has a complementary latch enable control for
each comparator. Both should be driven by standard ECL
logic levels.
Figure 2 - Internal Function Diagram
Q
V
V
+
–
IN
IN
PRE
AMP
ECL
OUT
LATCH
Q
REF
1
REF
2
CLK
BUF
V
V
GND
LE
LE
EE
CC
SPT9689
SPT
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7/17/00
TYPICAL PERFORMANCE CHARACTERISTICS
PROPAGATION DELAY VS OVERDRIVE VOLTAGE
RISE AND FALL OF OUTPUTS VS TIME CROSSOVER
800
-.90
750
700
-1.10
-1.30
650
600
-1.50
-1.70
550
500
0
20
40
60
80
100
-1.90
OVERDRIVE (mV)
400
500
600
TIME (ps)
700
800
900
FALL TIME VS TEMPERATURE
RISE TIME VS TEMPERATURE
260
280
220
180
240
200
)
s
p
(
E
M
I
T
S
I
R
140
160
100
60
120
80
-50
0
+50
+100
+150
-50
0
+50
+100
+150
TEMPERATURE (°C)
TEMPERATURE (°C)
INPUT BIAS CURRENT VS COMMON MODE VOLTAGE
HYSTERESIS VS
∆LATCH
20
11
9
16
12
T=-55 °C
7
T=+25 °C
5
8
4
T=+125 °C
3
1
0
0
10
20
30
40
50
-3.0
-2.0
-1.0
0.0
+1.0
+2.0
+3.0
+4.0
+5.0
∆
LATCH = V
-V (mV)
LE LE
COMMON MODE VOLTAGE (V)
SPT9689
SPT
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ance to the part is kept as low as possible to decrease
parasitic feedback. If the output board traces are longer than
approximately half an inch, microstripline techniques must
be employed to prevent ringing on the output waveform.
Also, the microstriplines must be terminated at the far end
with the characteristic impedance of the line to prevent
reflections. Both supply voltage pins should be decoupled
with high frequency capacitors as close to the device as
possible. All ground pins and no connects should be sol-
dered to a common ground plane to further improve noise
immunity. If using the SPT9689 as a single comparator, the
outputs of the inactive comparator can be grounded, left
open or terminated with 50 Ohms to -2 V. All outputs on the
active comparator, whether used or unused, should have
identical terminations to minimize ground current switching
transients.
TYPICAL INTERFACE CIRCUIT
The typical interface circuit using the comparator is shown in
figure 3. Although it needs few external components and is
easy to apply, there are several conditions that should be
noted to achieve optimal performance. The very high oper-
ating speeds of the comparator require careful layout, de-
coupling of supplies, and proper design of transmission
lines.
Since the SPT9689 comparator is a very high frequency and
high gain device, certain layout rules must be followed to
avoid oscillations. Thecomparatorshouldbesolderedtothe
board with component lead lengths kept as short as pos-
sible. A ground plane should be used while the input imped-
Figure 3 - SPT9689 Typical Interface Circuit
Figure 4 - SPT9689 Typical Interface Circuit
With Hysteresis
+5.0 V
-2 V
+5.0 V
0 to 200 Ω
100 Ω
ECL
10 µF
-1.3 V
10 µF
0.1 µF
100 pF
0.1 µF
100 pF
+V
CC
+V
CC
V
V
IN
+
LE
+
IN
LE
LE
LE
Q Output
Q Output
Q Output
GND
GND
Q Output
V
V
EE
V
EE
REF
V
REF
R
50 Ω
L
R
L
100 pF
0.1 µF
10 µF
50 Ω
100 pF
100 pF
0.1 µF
10 µF
R
L
R
L
100 pF
50 Ω
0.1 µF
10 µF
0.1 µF
50 Ω
10 µF
10 µF
10 µF
-5.2 V
-2 V
-5.2 V
-2 V
NOTES:
NOTES:
Denotes ground plane.
Ferrite bead. Fair Rite Part # 2643001501.
All resistors are chip type 1%.
Denotes ground plane.
Ferrite bead. Fair Rite Part # 2643001501.
All resistors are chip type 1%.
0.1 µF and 100 pF capacitors are chip type mounted
as close to the pins as possible.
0.1 µF and 100 pF capacitors are chip type mounted as close
to the pins as possible.
10 µF tant capacitors have lead lengths <0.25" long.
Represents line termination.
10 µF tant capacitors have lead lengths <0.25" long.
Represents line termination.
SPT9689
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PACKAGE OUTLINES
16-Lead Sidebrazed DIP
INCHES
MILLIMETERS
MIN MAX
2.29
16
1
H
SYMBOL
MIN
MAX
0.090
0.021
A
B
C
D
E
F
G
H
I
0.070
0.015
0.100 typ
0.049
—
1.78
0.38
2.54 typ
1.24
—
0.53
I
0.059
—
1.50
—
J
G
—
—
—
—
0.792
0.287
0.009
0.290
0.808
0.303
0.012
0.310
20.12
7.29
0.23
7.37
20.52
7.70
0.30
7.87
A
E
J
F
C
B
D
20-Contact Leadless Chip Carrier (LCC)
A
H
INCHES
MIN
MILLIMETERS
MIN MAX
SYMBOL
MAX
G
A
B
C
D
E
F
.040 typ
.050 typ
0.055
1.02 typ
1.27 typ
1.40
Bottom
View
Pin 1
0.045
0.345
0.054
1.14
B
0.360
8.76
1.37
9.14
0.066
1.68
.020 typ
0.028
0.51 typ
0.71
C
F
G
H
0.022
0.56
D
0.075
1.91
E
20-Lead Plastic Leadless Chip Carrier (PLCC)
A
G
INCHES
MIN
MILLIMETERS
MIN MAX
B
SYMBOL
MAX
Pin 1
N
A
B
C
D
E
F
G
H
I
.045 typ
1.14 typ
TOP
VIEW
M
O
F
0.350
0.356
0.395
0.356
0.395
0.056
0.180
0.110
0.040
0.025
0.032
0.021
0.050
0.330
8.89
9.04
10.03
9.04
10.03
1.42
4.57
2.79
1.02
0.64
0.81
0.53
1.27
8.38
E
0.385
0.350
0.385
0.042
0.165
0.085
0.025
0.015
0.026
0.013
9.78
8.89
9.78
1.07
4.19
2.16
0.64
0.38
0.66
0.33
L
K
C
D
J
I
H
J
Pin 1
K
L
BOTTOM
VIEW
M
N
O
0.290
7.37
SPT9689
SPT
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7/17/00
PIN ASSIGNMENTS
PIN FUNCTIONS
NAME
FUNCTION
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
QA
QA
QB
QB
Q
Output A
A
A
Inverted Output A
Q
GND
A
Ground A
GNDA
LEA
GNDB
LEB
LE
Latch Enable A
Inverted Latch Enable A
A
LE
A
LEA
VEE
LEB
VCC
-INB
+INB
V
Negative Supply Voltage
Inverting Input A
EE
-IN
A
-INA
+INA
+IN
+IN
Noninverting Input A
Noninverting Input B
Inverting Input B
A
B
-IN
B
DIP
V
Positive Supply Voltage
Latch Enabled B
CC
LE
QA
3
QA N/C QB QB
B
2
1
20 19
Inverted Latch Enable B
LE
B
GND
Ground B
B
GNDA
LEA
4
18 GNDB
Q
Output B
B
B
LEB
N/C
5
6
7
8
17
16
Inverted Output B
Q
TOP VIEW
N/C
LEA
15 LEB
14
VEE
VCC
9
10 11 12 13
-INA +INA
+INB -INB
N/C
LCC/PLCC
ORDERING INFORMATION
PART
NUMBER
INPUT
OFFSET
TEMPERATURE
RANGE
PACKAGE
TYPE
SPT9689AIJ
SPT9689BIJ
SPT9689AIC
SPT9689BIC
SPT9689AIP
SPT9689BIP
SPT9689ACU
SPT9689BCU
10 mV
25 mV
10 mV
25 mV
10 mV
25 mV
-40 to +85 °C
-40 to +85 °C
-40 to +85 °C
-40 to +85 °C
-40 to +85 °C
-40 to +85 °C
+25 °C
16L Sidebrazed DIP
16L Sidebrazed DIP
20C LCC
20C LCC
20L PLCC
20L PLCC
Die*
+25 °C
Die*
*Please see the die specification for guaranteed electrical performance.
Signal Processing Technologies, Inc. reserves the right to change products and specifications without notice. Permission is hereby
expressly granted to copy this literature for informational purposes only. Copying this material for any other use is strictly prohibited.
WARNING-LIFESUPPORTAPPLICATIONSPOLICY-SPTproductsshouldnotbeusedwithinLifeSupportSystemswithout thespecific
written consent of SPT. A Life Support System is a product or system intended to support or sustain life which, if it fails, can be reasonably
expected to result in significant personal injury or death.
Signal Processing Technologies believes that ultrasonic cleaning of its products may damage the wire bonding, leading to device
failure. It is therefore not recommended, and exposure of a device to such a process will void the product warranty.
SPT9689
SPT
8
7/17/00
相关型号：
SPT9693SCJ
Comparator, 2 Func, 25000uV Offset-Max, 0.45ns Response Time, CDIP20, SIDE BRAZED, CERAMIC, DIP-20
FAIRCHILD
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