USB1T1103_06 [FAIRCHILD]

Universal Serial Bus Peripheral Transceiver with Voltage Regulator; 通用串行总线外设收发器,稳压器
USB1T1103_06
型号: USB1T1103_06
厂家: FAIRCHILD SEMICONDUCTOR    FAIRCHILD SEMICONDUCTOR
描述:

Universal Serial Bus Peripheral Transceiver with Voltage Regulator
通用串行总线外设收发器,稳压器

稳压器
文件: 总16页 (文件大小:1038K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
July 2006  
USB1T1103  
Universal Serial Bus Peripheral Transceiver  
with Voltage Regulator  
Features  
Description  
Complies with Universal Serial Bus Specification 2.0  
Integrated 5V to 3.3V voltage regulator for powering  
VBus  
This chip provides a USB Transceiver functionality with a  
voltage regulator that is compliant to USB Specification  
Rev 2.0. this integrated 5V to 3.3V regulator allows inter-  
facing of USB Application specific devices with supply  
voltages ranging from 1.65V to 3.6V with the physical  
layer of Universal Serial Bus. It is capable of operating at  
12Mbits/s (full speed) data rates and hence is fully com-  
pliant to USB Specification Rev 2.0. The Vbusmon termi-  
nal allows for monitoring the Vbus line.  
Utilizes digital inputs and outputs to transmit and  
receive USB cable data  
Supports full speed (12Mbits/s) data rates  
Ideal for portable electronic devices  
MLP technology package (16 terminal) with HBCC  
footprint  
The USB1T1103 also provides exceptional ESD protec-  
tion with 15kV contact HBM on D+,D- terminals  
15kV contact HBM ESD protection on bus terminals  
Supports disable mode and is functionally equivalent  
to Philips ISP1102  
Applications  
PDA  
PC Peripherals  
Cellular Phones  
MP3 Players  
Digital Still Camera  
Information Appliance  
Ordering Information  
Part Number Package Product code Pb-Free  
Package Description  
Packing  
Method  
Number  
Top Mark  
USB1T1103MPX  
MLP14D  
$Y&Z&2&T  
USB1103  
Yes  
Yes  
14-Terminal Molded Leadless Package  
(MLP), 2.5mm Square  
3K Units  
on Tape  
and Reel  
USB1T1103MHX  
MLP16HB  
$Y&Z&2&T  
USB1103  
16-Terminal Molded Leadless Package  
(MHBCC), JEDEC MO-217,3mm  
Square  
3K Units  
on Tape  
and Reel  
Pb-Free package per JEDEC J-STD-020B.  
© 2005 Fairchild Semiconductor Corporation  
USB1T1103 Rev. 1.0.2  
www.fairchildsemi.com  
Typical Application  
Figure 1. Logic Diagram  
Connection Diagrams  
Figure 2. MLP16 GND Exposed Diepad  
(Bottom View)  
Figure 3. MLP14 GND Exposed Diepad  
(Bottom View)  
© 2005 Fairchild Semiconductor Corporation  
www.fairchildsemi.com  
USB1T1103 Rev. 1.0.2  
2
Terminal Descriptions  
Terminal  
Terminal  
Number  
I/O  
Terminal Description  
Name  
MLP14 MLP16  
1
2
3
1
2
3
OE  
I
Output Enable:  
Active LOW enables the transceiver to transmit data on the bus. When not active the transceiver is in  
the receive mode (CMOS level is relative to V  
)
CCIO  
RCV  
O
Receive Data Output:  
Non-inverted CMOS level output for USB differential Input (CMOS output level is relative to V  
).  
CCIO  
Driven LOW when SUSPN is HIGH; RCV output is stable and preserved during SE0 condition.  
V /V  
I/O  
Single-ended D+ receiver output V (CMOS level relative to V ):  
p
po  
P
CCIO  
Used for external detection of SE0, error conditions, speed of connected device; Terminal also acts  
as drive data input V (see Table 1 and Table 2).  
po  
Output drive is 4 mA buffer.  
4
5
4
5
V /V  
I/O  
I
Single-ended D- receiver output V (CMOS level relative to V  
Used for external detection of SE0, error conditions, speed of connected device; Terminal also acts  
):  
CCIO  
m
mo  
m
as drive data input V (see Table 1 and Table 2).  
mo  
Output drive is 4 mA buffer.  
SUSPND  
NC  
Suspend:  
Enables a low power state (CMOS level is relative to V  
). While the  
CCIO  
SUSPND terminal is active (HIGH) it will drive the RCV terminal to logic “0” state.  
6
6
7
No Connect  
V
Supply Voltage for digital I/O terminals (1.65V to 3.6V):  
CCIO  
When not connected the D+ and D- terminals are in 3-STATE. This supply bus is totally independent  
of V (5V) and V  
(3.3V), and must never exceed the V  
(3.3) voltage. For V  
discon-  
CC  
REG  
REG  
CCIO  
nected the O+/O- terminals are HIGH Impedance and the V (3.3V) is turned off.  
PU  
7
8
Vbusmon  
D+, D-  
O
Vbus monitor output (CMOS level relative to V  
When Vbus > 4.1V then Vbusmon = HIGH and when Vbus < 3.6V then  
Vbusmon = LOW. If SUSPND = HIGH then Vbusmon is pulled HIGH.  
):  
CCIO  
9, 8  
10, 9  
AI/O Data +, Data -:  
Differential data bus conforming to the USB standard. Terminals are HIGH Impedance for bus pow-  
ered mode when Vbus < 3.6V. For ByPass Mode then HIGH Impedance when V  
minimum.  
/ Vbus < V  
REG  
REG  
10  
11  
11  
12  
13  
NC  
NC  
No Connect  
No Connect  
V
(3.3V)  
Internal Regulator Option:  
REG  
Regulated supply output voltage (3.0V to 3.6V) during 5V operation;  
decoupling capacitor of at least 0.1 µF is required.  
Regulator ByPass Option:  
Used as supply voltage input for 3.3V operation.  
12  
13  
14  
15  
V
(5.0V)  
(3.3V)  
Internal Regulator Option:  
Used as supply voltage input (4.0V to 5.5V); can be connected directly to USB line Vbus.  
Regulator ByPass Option:  
CC  
Connected to V  
(3.3V)  
REG  
V
Pull-up Supply Voltage (3.3V ± 10%):  
PU  
Connect an external 1.5kΩ resistor on D+ (FS data rate);  
Terminal function is controlled by Config input terminal:  
Config = LOW - V (3.3V) is floating (HIGH Impedance) for zero pull-up current.  
PU  
Config = HIGH - V (3.3V) = 3.3V; internally connected to V  
(3.3V).  
PU  
REG  
V
is OFF in disable mode.  
PU  
14  
16  
Config  
GND  
I
USB connect or disconnect software control input.  
Configures 3.3V to external 1.5kΩ resistor on D+ when HIGH.  
Exposed  
Diepad  
Exposed  
Diepad  
GND GND supply down bonded to exposed diepad to be connected to the PCB GND.  
© 2005 Fairchild Semiconductor Corporation  
USB1T1103 Rev. 1.0.2  
www.fairchildsemi.com  
3
Functional Description  
The USB1T1103 transceiver is designed to convert  
CMOS data into USB differential bus signal levels and to  
convert USB differential bus signal to CMOS data.  
nals rather than discrete input and output terminals.  
Table 1 describes the specific terminal functionality  
selection. Table 2 and Table 3 describe the specific Truth  
Tables for Driver and Receiver operating functions.  
To minimize EMI and noise the outputs are edge rate  
controlled with the rise and fall times controlled and  
defined for full speed data rates only (12Mbits/s). The  
rise, fall times are balanced between the differential ter-  
minals to minimize skew.  
The USB1T1103 also has the capability of various power  
supply configurations, including a disable mode for  
VCCIO disconnected, to support mixed voltage supply  
applications (see Table 4) and Section 2.1 for detailed  
descriptions.  
The USB1T1103 differs from earlier USB Transceiver in  
that the Vp/Vm and Vpo/Vmo terminals are now I/O termi-  
Functional Tables  
Table 1. Function Select  
V /V  
V /V  
m
SUSPND  
OE  
D+, D-  
RCV  
Function  
p
po  
mo  
Vmo Input Normal Driving  
(Differential Receiver Active)  
L
L
Driving &  
Receiving  
Active  
Vpo Input  
L
H
L
Receiving (1)  
Active  
Inactive(2)  
Vp Output  
Vpo Input  
Vm Output Receiving  
H
Driving  
Vmo Input Driving during Suspend  
(Differential Receiver Inactive)  
H
H
3 STATE(1)  
Inactive(2)  
Vp Output  
Vm Output Low Power State  
Notes:  
1. Signal levels is function of connection and/or pull-up/pull-down resistors.  
2. For SUSPND = HIGH mode the differential receiver is inactive and the output RCV is forced LOW. The out-of-suspend signaling  
(K) is detected via the single-ended receivers of the Vp/Vpo and Vm/Vmo terminals.  
Table 2. Driver Function (OE = L) using Differential Input Interface  
V /V  
V /V  
Data (D+ / D-)  
m
mo  
p
po  
L
L
L
H
L
SE0 (3)  
Differential Logic 1  
Differential Logic 0  
Illegal State  
H
H
H
Notes:  
3. SE0 = Single Ended Zero  
Table 3. Receiver Function (OE = H)  
V /V  
V /V  
D+, D-  
RCV  
p
po  
m
mo  
Differential Logic 1  
Differential Logic 0  
SE0  
H
L
H
L
L
L
H
L
X
Notes:  
4. X = Don't Care  
5. RCV(0) denotes the signal level on output RCV just prior to the SE0 or SE1 event. This level is stable during the SE0 or SE1  
event period.  
© 2005 Fairchild Semiconductor Corporation  
USB1T1103 Rev. 1.0.2  
www.fairchildsemi.com  
4
Power Supply Configurations and Options  
The three modes of power supply operation are:  
external signals up to 3.6V to share the D+ and D- bus  
lines. Internally the circuitry limits leakage from D+ and  
D- terminals (maximum 10µA) and VCCIO such that  
device is in low power (suspended) state. Terminals  
Vbusmon and RCV are forced LOW as an indication of  
this mode with Vbusmon being ignored during this state.  
Normal Mode: Regulated Output and Regulator Bypass  
1. Regulated Output: VCCIO is connected and VCC(5.0)  
is connected to 5V (4.0V to 5.5V) and the internal  
voltage regulator then produces 3.3V for the USB  
connections.  
Disable Mode: VCCIO is not connected. VCC is con-  
nected, or VCC and VREG are connected. 0V to 3.3V in  
this mode D+ and D- are 3-STATE and VPU is HIGH  
Impedance (switch is turned off). The USB1T1103 allows  
external signals up to 3.6V to share the D+ and D- bus  
lines. Internally the circuitry limits leakage from D+ and  
D- pins (maximum 10µ A).  
2. Internal Regulator Bypass Mode: VCCIO is con-  
nected and both VCC(5.0) and VREG(3.3) are con-  
nected to a 3.3V source (3.0V to 3.6V).  
In both cases, for normal mode, the VCCIO is an indepen-  
dent voltage source (1.65V to 3.6V) that is a function of  
the external circuit configuration.  
A summary of the Supply Configurations is described in  
Table 4.  
Sharing Mode: VCCIO is only supply connected. VCC  
and VREG are not connected. In this mode, the D+ and  
D- terminals are 3-STATE and the USB1T1103 allows  
Table 4. Power Supply Configuration Options  
Normal  
Normal  
Terminals  
Disable  
Sharing  
(Regulated Output) (Regulator Bypass)  
VCC (5V)  
Connected  
to 5V source  
Not Connected  
or <3.6V  
Connected to  
5V Source  
Connected to  
REG (3.3V)  
V
[Max Drop of 0.3V]  
(2.7V to 3.6V)  
V
REG (3.3V)  
VCCIO  
3.3V, 300µA  
Regulated Output  
Not Connected  
3.3V, 300µA  
Regulated Output  
Connected to 3.3V Source  
0.5V  
1.65V to 3.6V Source  
3-STATE (off)  
1.65V to 3.6V Source  
1.65V to 3.6V Source  
VPU (3.3V)  
3-STATE (off)  
3.3V Available if  
Config = HIGH  
3.3V Available if  
Config = HIGH  
D =, D-  
3-STATE (off)  
Invalid [I]  
Invalid [I]  
Invalid [I]  
Hi-Z  
3-STATE  
Function of  
Mode Set Up  
Function of  
Mode Set Up  
Vp/Vpo, Vm/Vmo  
RCV  
L
L
Function of  
Mode Set Up  
Function of  
Mode Set Up  
Function of  
Mode Set Up  
Function of  
Mode Set Up  
Vbusmon  
L
Function of  
Mode Set Up  
Function of  
Mode Set Up  
OE, SUSPND, Config  
Hi-Z  
Function of  
Function of  
Mode Set Up  
Mode Set Up  
Notes:  
6. Invalid [I] I/O are to be 3-STATE, outputs to be LOW.  
© 2005 Fairchild Semiconductor Corporation  
USB1T1103 Rev. 1.0.2  
www.fairchildsemi.com  
5
Human Body Model  
ESD Protection  
Figure 3 shows the schematic representation of the  
Human Body Model ESD event. Figure 4 is the ideal  
waveform representation of the Human Body Model.  
ESD Performance of the USB1T1103  
HBM D+/D-: 15.0kV  
HBM, all other terminals (Mil-Std 883E): 6.5kV  
IEC 61000-4-2, IEC 60749-26 and IEC 60749-27  
ESD Protection: D+/D- Terminals  
The IEC 61000-4-2 standard covers ESD testing and  
performance of finished equipment and evaluates the  
equipment in its entirety for ESD immunity. Fairchild  
Semiconductor has evaluated this device using the  
IEC 6100-4-2 representative system model depicted in  
Figure 5. Under the additional standards set forth by the  
IEC, this device is also compliant with IEC 60749-26  
(HBM) and IEC 60749-27 (MM).  
Since the differential terminals of a USB transceiver may  
be subjected to extreme ESD voltages, additional immu-  
nity has been included in the D+ and D- terminals with-  
out compromising performance. The USB1T1103  
differential terminals have ESD protection to the follow-  
ing limits:  
15kV using the contact Human Body Model  
Additional ESD Test Conditions  
8kV using the Contact Discharge method as specified  
in IEC 61000-4-2  
For additional information regarding our product test  
methodologies and performance levels, please contact  
Fairchild Semiconductor.  
Figure 3. Human Body ESD Test Model  
Figure 4. HBM Current Waveform  
Figure 5. IEC 61000-4-2 ESD Test Model  
© 2005 Fairchild Semiconductor Corporation  
USB1T1103 Rev. 1.0.2  
www.fairchildsemi.com  
6
Absolute Maximum Ratings  
The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The  
device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are  
not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table defines the condi-  
tions for actual device operation.  
Symbol  
VCC (5V)  
VCCIO  
ILU  
Parameter  
Min.  
-0.5  
-0.5  
Max.  
+6.0  
Unit  
V
Supply Voltage  
I/O Supply Voltage  
+4.6  
V
Latch-up Current, VI = -1.8V to +5.4V  
DC Input Current, VI<0  
DC Input Voltage(4)  
150  
mA  
mA  
V
IIK  
-18  
VI  
-0.5  
-0.5  
VCCIO +0.5  
±18  
IOK  
DC Output Diode Current, VO >VCC or VO <0  
DC Output Voltage(5)  
mA  
V
VO  
VCCIO+0.5  
Output Source or Sink Current, VO + 0 to VCC  
Current for D+,D- Terminals  
Current for RCV, VM/VP  
DC VCC or GND Current  
ESD Immunity Voltage  
Contact HBM  
IO  
±12  
±12  
mA  
mA  
mA  
ICC, GND  
I
±100  
VESD  
Terminals D+,D-, ILI < 1µA  
All other Terminals ILI < 1µA  
Storage Temperature  
±15  
±6.5  
+125  
kV  
kV  
C
TSTG  
-40  
Power Dissipation  
PTOT  
Notes:  
ICC (5V)  
48  
9
mW  
mW  
ICCIO  
7. IO Absolute Maximumun Rating must be observed.  
8. Per ESD Methodology described on page 6.  
Recommended Operation Conditions  
Symbol  
VCC  
Parameter  
Min.  
4.0  
1.65  
0
Max.  
5.5  
Unit  
V
Supply Voltage  
I/O DC Voltage  
VCC10  
VI  
3.6  
V
DC Input Voltage Range  
VCCIO +5.5  
3.6  
V
VAI/O  
TA  
DC Input Range for AI/O, Terminal D+ and D-  
Operating Ambient Temperature  
0
V
-40  
+85  
°C  
© 2005 Fairchild Semiconductor Corporation  
USB1T1103 Rev. 1.0.2  
www.fairchildsemi.com  
7
DC Electrical Characteristics  
Supply Terminals  
Over recommended range of supply voltage and operating free air temperature (unless otherwise noted).  
VCC (5V) = 4.0V to 5.5V or VREG (3.3V) = 3.0V to 3.6V, VCCIO = 1.65V to 3.6V.  
Limits  
Symbol  
Parameter  
Conditions  
-40ºC to +85ºC  
Units  
Min. Typ. Max.  
VREG (3.3V) Regulated Supply Output  
Internal Regulator Option; ILOAD 300 µA  
3.0(9)(10)  
3.3  
3.6  
8.0  
2.0  
V
Operating Supply Current  
(VCC5.0)  
Transmitting and Receiving at 12 Mbits/s;  
CLOAD = 50 pF (D+, D-)  
ICC  
4.0(11)  
1.0(11)  
mA  
mA  
ICCIO  
I/O Operating Supply Current  
Supply Current during  
Transmitting and Receiving at 12 Mbits/s  
IDLE: VD + 2.7V, VD - 0.3V;  
SE0: VD + 0.3V, VD - 0.3V  
IDLE, SUSPND or SE0  
VCCIO = 0V  
ICC (IDLE)  
300(12)  
20.0  
µA  
µA  
µA  
FS IDLE and SE0 (VCC5.0)  
ICCIO (STATIC) I/O Static Supply Current  
ICC(DISABLE) Disable Supply Current  
25.0  
VCC Connected  
ICC(SUSPND) Suspend Supply Current  
USB1T1103  
SUSPND = HIGH  
25.0(12)  
OE = HIGH  
µA  
Vm = Vp = OPEN  
ICCIO(SHAR-  
I/O Sharing Mode Supply Current VCC (5V) Not Connected  
20.0  
10.0  
µA  
µA  
ING)  
Sharing Mode Load Current on  
D+/D- Terminals  
VCC (5V) Not Connected  
ID+ (SHARING)  
ID +/-  
Config = LOW; V= 3.6V  
VCCIO Not Connected or 0V  
Config = VD ± = 3.6V LOW or HIGH  
ID+(DISABLE) Disable Mode Load Current on  
10.0  
3.6  
µA  
V
ID+/-  
D+/D- Terminals  
VCCTH  
VCC Threshold Detection Voltage 1.65V VCCIO 3.6V  
Supply Lost  
Supply Present  
4.1  
1.4  
VCCHYS  
VCC Threshold Detection  
Hysteresis Voltage  
VCCIO = 1.8V  
70.0  
mV  
VCCIO Threshold Detection Volt-  
age  
VCCIOTH  
2.7V VREG 3.6V  
V
Supply Lost  
0.5  
0.8  
Supply Present  
VREG = 3.3V  
VCCIOHYS VCCIO Threshold Detection  
Hysteresis Voltage  
450  
mV  
VREGTH  
Regulated Supply Threshold  
Detection Voltage  
1.65V VCCIO VREG  
2.7V VREG 3.6V  
Supply Lost  
V
Supply Present  
VCCIO = 1.8V  
2.4(14)  
(15)  
VREGHYS  
Regulated Supply Threshold  
Detection Hysteresis Voltage  
450  
mV  
Notes:  
9. ILOAD includes the pull-up resistor current via terminal VPU  
10. The minimum voltage in Suspend mode is 2.7V.  
11. Not tested in production, value based on characterization.  
12. Excludes any current from load and VPU current to the 1.5kΩ resistor.  
13. Includes current between Vpu and the 1.5k internal pull-up resistor.  
14. When VCCIO < 2.7V, minimum value for VREGTH = 2.0V for supply present condition.  
15. DC electrical measurements should be taken with unused inputs and I/O pins connected to a valid logic level. This applies for all  
modes of device operation defined in the Functional Tables on Page 4.  
© 2005 Fairchild Semiconductor Corporation  
USB1T1103 Rev. 1.0.2  
www.fairchildsemi.com  
8
DC Electrical Characteristics  
Digital Terminals – excludes D+, D- Terminals  
Over recommended range of supply voltage and operating free air temperature (unless otherwise noted).  
VCCIO = 1.65V to 3.6V.  
Limits  
Symbol  
Parameter  
Conditions  
-40C° to +85°C Units  
Min.  
Max.  
Input Levels  
VIL  
LOW Level Input Voltage  
0.3*VCCIO  
V
V
VIH  
HIGH Level Input Voltage  
LOW Level Output Voltage  
HIGH Level Output Voltage  
0.6*VCCIO  
Output Levels  
VOL  
IOL = 2 mA  
OL = 100 =µA  
IOH = 2 mA  
OH = 100 =µA  
0.4  
V
V
I
0.15  
0.4  
VOH  
VCCIO -  
0.15  
I
VCCIO-  
Leakage Current  
ILI  
Input Leakage Current  
Input Capacitance  
VCCIO = 1.65V to 3.6V  
Terminal to GND  
±1.0(16)  
10.0  
µA  
pF  
Capacitance  
CIN, CI/O  
Notes:  
16. If VCCIO VREG, leakage current is higher than specified.  
DC Electrical Characteristics  
Analog I/O Terminals – D+, D- Terminals  
Over recommended range of supply voltage and operating free air temperature (unless otherwise noted).  
VCC = 4.0V to 5.5V or VREG = 3.0V to 3.6V.  
Limits  
Symbol  
Parameter  
Conditions  
-40°C to +85°C  
Units  
Min. Typ. Max.  
Input Levels – Differential Receiver  
VDI  
Differential Input Sensitivity  
Differential Common Mode Voltage  
| VI(D+) - VI(D-)  
|
0.2  
V
V
VCM  
0.8  
2.5  
0.8  
0.7  
Input Levels – Single-ended Receiver  
VIL  
LOW Level Input Voltage  
HIGH Level Input Voltage  
Hysteresis Voltage  
V
V
V
VIH  
2.0  
VHYS  
0.30  
Output Levels  
VOL  
LOW Level Output Voltage  
HIGH Level Output Voltage(17)  
RL = 1.5kΩ to 3.6V  
RL = 15kΩ to GND  
0.3  
3.6  
V
V
VOH  
2.8  
Leakage Current  
IOFF  
Input Leakage Current Off State  
CAPACITANCE  
±1.0  
20.0  
µA  
pF  
CI/O  
I/O Capacitance  
Terminal to GND  
Resistance  
© 2005 Fairchild Semiconductor Corporation  
USB1T1103 Rev. 1.0.2  
www.fairchildsemi.com  
9
Limits  
-40°C to +85°C  
Min. Typ. Max.  
41.0  
Symbol  
Parameter  
Conditions  
Units  
ZDRV  
Driver Output Impedance(18)  
34.0  
44.0  
Ω
ZIN  
Driver Input Impedance  
Switch Resistance  
Termination Voltage(19)(20)  
10.0  
MΩ  
Ω
RSW  
10.0  
3.6  
VTERM  
Notes:  
RPU Upstream Port  
3.0  
V
17. If VOH minimum = VREG - 0.2V.  
18. Includes external resistors of 27Ω on both D+ and D- terminals.  
19. This voltage is available at terminal VPU and VREG  
.
20. Minimum voltage is 2.7V in the suspend mode.  
AC Electrical Characteristics  
A I/O Terminals Full Speed  
Over recommended range of supply voltage and operating free air temperature (unless otherwise noted).  
VCC = 4.0V to 5.5V or VREG = 3.0V to 3.6V, VCCIO = 1.65V to 3.6V, CL = 50 pF; RL = 1.5K on D+ to VPU  
.
Limits  
Symbol  
Parameter  
Conditions  
-40°C to +85°C  
Min. Typ. Max.  
Unit  
Driver Characteristics  
tR  
Output Rise Time  
CL = 50 - 125 pF  
4.0  
20.0  
10% to 90%  
Figure 8, 12  
ns  
tF  
Output Fall Time  
4.0  
20.0  
tF/ tR Excludes First Transition  
from Idle State  
tRFM  
Rise/Fall Time Match  
90.0  
111.1  
%
V
Excludes First Transition from  
Idle State see Waveform  
VCRS  
Output Signal Crossover Voltage (21)  
1.3  
2.0  
Driver Timing  
tPLH  
Propagation Delay  
(Vp/Vpo, Vm/Vmo to D+/D-)  
Driver Disable Delay  
(OE to D+/D-)  
Figures 9,12  
Figures 11,12  
Figures 11,13  
18.0  
15.0  
15.0  
ns  
ns  
ns  
tPHL  
tPHZ  
tPLZ  
tPZH  
Driver Enable Delay  
(OE to D+/D-)  
tPZL  
Receiver Timing  
tPLH  
Propagation Delay (Diff)  
Figures 10,14  
Figures 10,14  
15.0  
18.0  
ns  
ns  
tPHL  
(D+/D- to Rev)  
tPLH  
Single-Ended Receiver Propagation Delay  
tPHL  
(D+/D- to Vp/ Vpo, Vm/Vmo)  
NOTES:  
21. Not production tested; limits guaranteed by design.  
© 2005 Fairchild Semiconductor Corporation  
USB1T1103 Rev. 1.0.2  
www.fairchildsemi.com  
10  
Typical Application Configurations  
Figure 6. Upstream Connection in Bypass Mode with Differential Outputs  
Figure 7. Downstream Connection in Normal Mode with Differential Outputs  
© 2005 Fairchild Semiconductor Corporation  
www.fairchildsemi.com  
USB1T1103 Rev. 1.0.2  
11  
AC Waveforms  
Figure 8. Rise and Fall Times  
Figure 10. D+/D- to R , V /V and V /V  
m
CV po  
p
mo  
Figure 11. OE to D+/D-  
Figure 9. V , V to D+/D-  
po  
mo  
Test Circuits and Waveforms  
Figure 14. Load for V /V , V V and RCV  
m
mo  
p/ po  
CL = 50 pF Full Speed Propagation Delays  
CL = -125 pF Edge Rates only  
Figure 12. Load for D+/D-  
V = 0 for tPZH, tPHZ  
V = VREG for tPZL  
Figure 13. Load for Enable and Disable Times  
© 2005 Fairchild Semiconductor Corporation  
USB1T1103 Rev. 1.0.2  
www.fairchildsemi.com  
12  
Tape and Reel Specification  
Tape Format for MHBCC and MLP  
Cover Tape  
Status  
Sealed  
Package Designator  
Tape Section  
Number Cavities  
Cavity Status  
Leader (Start End)  
Carrier  
125 (typ)  
2500/3000  
75 (typ)  
Empty  
Filled  
MHX/MPX  
Sealed  
Trailer (Hub End)  
Empty  
Sealed  
TAPE DIMENSIONS  
Dimensions are in inches (millimeters) unless otherwise specified.  
REEL DIMENSIONS  
Dimensions are in inches (millimeters) unless otherwise specified.  
Tape Size  
A
B
C
D
N
W1  
W2  
13.0  
330  
0.059  
(1.50)  
0.512  
(13.00)  
0.795  
(20.20)  
7.008  
(178)  
0.488  
(12.4)  
0.724  
(18.4)  
12 mm  
© 2005 Fairchild Semiconductor Corporation  
USB1T1103 Rev. 1.0.2  
www.fairchildsemi.com  
13  
Physical Dimensions  
Dimensions are in inches (millimeters) unless otherwise noted.  
Figure 15. Pb-Free 14-Terminal Molded Leadless Package (MLP), 2.5mm Square  
© 2005 Fairchild Semiconductor Corporation  
USB1T1103 Rev. 1.0.2  
www.fairchildsemi.com  
14  
Physical Dimensions  
Dimensions are in inches (millimeters) unless otherwise noted.  
Figure 16. Pb-Free 16-Terminal Molded Leadless Package (MHBCC), JEDEC MO-217, 3mm Square  
© 2005 Fairchild Semiconductor Corporation  
USB1T1103 Rev. 1.0.2  
www.fairchildsemi.com  
15  
© 2005 Fairchild Semiconductor Corporation  
USBIT1103 Rev.1.0.2  
www.fairchildsemi.com  
16  

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