FM8P59BP_技术文档

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FM8P59

EPROM/ROM-Based 8-Bit Microcontroller

Devices Included in this Data Sheet:

‧ FM8P59AE : 28-pin EPROM device

‧ FM8P59BE : 32-pin EPROM device

‧ FM8P59A : 28-pin Mask ROM device

‧ FM8P59B : 32-pin Mask ROM device

FEATURES

‧ Only 47 single word instructions

‧ All instructions are single cycle except for program branches which are two-cycle

‧ 13-bit wide instructions

‧ All ROM/EPROM area GOTO/FGOTO instruction

‧ All ROM/EPROM area subroutine CALL/FCALL instruction

‧ 8-bit wide data path

‧ 5-level deep hardware stack

‧ 4K x 13 bits on chip EPROM/ROM

‧ 144 x 8 bits on chip general purpose registers (SRAM)

‧ Operating speed: DC-20 MHz clock input

DC-100 ns instruction cycle

‧ Direct, indirect addressing modes for data accessing

‧ 8-bit real time clock/counter (Timer0) with 8-bit programmable prescaler

‧ Internal Power-on Reset (POR)

‧ Built-in Low Voltage Detector (LVD) for Brown-out Reset (BOR)

‧ Power-up Reset Timer (PWRT) and Oscillator Start-up Timer(OST)

‧ On chip Watchdog Timer (WDT) with internal oscillator for reliable operation and soft-ware watch-dog

enable/disable control

‧ Three I/O ports IOA, IOB and IOC with independent direction control

‧ 16 soft-ware control pull-high pins: Port B/Port C

‧ 8 soft-ware control pull-down pins:IOA0~A3/IOB0~B3

‧ 2 soft-ware control open-drain pins: IOC6/IOC7

‧ One internal interrupt source: Timer0 overflow; Two external interrupt source: INT0 pin, INT1 pin

‧ Wake-up from SLEEP by Port B/IOC4/IOC5 input falling

‧ Power saving SLEEP mode

‧ Programmable Code Protection

‧ Selectable oscillator options:

- ERC: External Resistor/Capacitor Oscillator

- XT: Crystal/Resonator Oscillator

- HF: High Frequency Crystal/Resonator Oscillator

- LF: Low Frequency Crystal Oscillator

‧ Wide-operating voltage range:

- EPROM : 2.3V to 5.5V

- ROM : 2.3V to 5.5V

This datasheet contains new product information. Feeling Technology reserves the rights to modify the product specification without notice.

No liability is assumed as a result of the use of this product. No rights under any patent accompany the sales of the product.

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GENERAL DESCRIPTION

FM8P59

The FM8P59 series is a family of low-cost, high speed, high noise immunity, EPROM/ROM-based 8-bit CMOS

microcontrollers. It employs a RISC architecture with only 47 instructions. All instructions are single cycle except

for program branches which take two cycles. The easy to use and easy to remember instruction set reduces

development time significantly.

The FM8P59 series consists of Power-on Reset (POR), Brown-out Reset (BOR), Power-up Reset Timer (PWRT),

Oscillator Start-up Timer(OST), Watchdog Timer, EPROM/ROM, SRAM, tri-state I/O port, I/O

pull-high/open-drain/pull-down control, Power saving SLEEP mode, real time programmable clock/counter,

Interrupt, Wake-up from SLEEP mode, and Code Protection for EPROM products. There are four oscillator

configurations to choose from, including the power-saving LP (Low Power) oscillator and cost saving RC oscillator.

The FM8P59 series address 4K×13 of program memory.

The FM8P59 series can directly or indirectly address its register files and data memory. All special function

registers including the program counter are mapped in the data memory.

BLOCK DIAGRAM

5-level

STACK

Oscillator

Circuit

SRAM

FSR

Watchdog

Timer

Program

Counter

PORTA

PORTB

EPROM

/ ROM

Instruction

Decoder

ALU

Interrupt

Control

Timer0

Accumulator

PORTC

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P.2/FM8P59

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PIN CONNECTION

FM8P59

PDIP, SOP

SSOP

T0CKI

Vdd

1

2

3

4

5

6

7

8

9

28 RSTB

27 OSCI

26 OSCO

25 IOC7

24 IOC6

23 IOC5

22 IOC4

21 IOC3

20 IOC2

19 IOC1

18 IOC0

17 IOB7

16 IOB6

15 IOB5

Vss

T0CKI

Vdd

RSTB

OSCI

OSCO

IOC7

IOC6

IOC5

IOC4

IOC3

IOC2

IOC1

IOC0

IOB7

IOB6

IOB5

1

28

27

26

25

24

23

22

21

20

19

18

17

16

15

2

NC

3

Vss

INT1

4

INT1

IOA0

IOA1

IOA2

IOA3

IOA0

5

IOA1

6

IOA2

7

FM8P59A

FM8P59AE

FM8P59A

FM8P59AE

IOA3

8

IOB0/INT0

IOB1

9

IOB0/INT0 10

IOB1 11

10

11

12

13

14

IOB2

IOB2 12

IOB3

IOB3 13

IOB4

IOB4 14

Vss

PDIP, SOP

1

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

IOA5

IOA4

T0CKI

Vdd

IOA6

IOA7

RSTB

OSCI

OSCO

IOC7

IOC6

IOC5

IOC4

IOC3

IOC2

IOC1

IOC0

IOB7

IOB6

IOB5

2

3

4

5

NC

6

Vss

7

INT1

8

IOA0

IOA1

IOA2

IOA3

IOB0/INT0

IOB1

IOB2

IOB3

IOB4

FM8P59B

FM8P59BE

9

10

11

12

13

14

15

16

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PIN DESCRIPTIONS

FM8P59

FM8P59A/FM8P59AE

Name

I/O

I/O IOA0 ~ IOA3 as bi-direction I/O port

Description

IOA0 ~ IOA3

IOB0/INT0

IOB1 ~ IOB7

IOC0 ~ IOC7

INT1

I/O Bi-direction I/O pin with system wake-up function / External interrupt input 0

I/O Bi-direction I/O port with system wake-up function

I/O Bi-direction I/O port

I

External interrupt input 1 triggered by falling edge

Clock input to Timer0. Must be tied to Vss or Vdd, if not in use, to reduce current

consumption

T0CKI

RSTB

OSCI

System clear (RESET) input. This pin is an active low RESET to the device.

X’tal type: Oscillator crystal input

RC type: Clock input of RC oscillator

X’tal type: Oscillator crystal output.

RC mode: Outputs with 1/4 the frequency of OSCI to denotes the instruction cycle rate

Positive supply

OSCO

O

Vdd

Vss

-

Ground

Legend: I=input, O=output, I/O=input/output

FM8P59B/FM8P59BE

Name

I/O

Description

IOA0 ~ IOA7

IOB0/INT0

IOB1 ~ IOB7

IOC0 ~ IOC7

INT1

I/O Bi-direction I/O port

I/O Bi-direction I/O pin with system wake-up function / External interrupt input 0

I/O Bi-direction I/O port with system wake-up function

I/O Bi-direction I/O port

I

External interrupt input 1 triggered by falling edge

Clock input to Timer0. Must be tied to Vss or Vdd, if not in use, to reduce current

consumption

T0CKI

RSTB

OSCI

System clear (RESET) input. This pin is an active low RESET to the device.

X’tal type: Oscillator crystal input

RC type: Clock input of RC oscillator

X’tal type: Oscillator crystal output.

RC mode: Outputs with 1/4 the frequency of OSCI to denotes the instruction cycle rate

Positive supply

OSCO

O

Vdd

Vss

-

Ground

Legend: I=input, O=output, I/O=input/output

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1.0 MEMORY ORGANIZATION

FM8P59

FM8P59 series memory is organized into program memory and data memory.

1.1 Program Memory Organization

The FM8P59 series have an 12-bit Program Counter capable of addressing a 4K×13 program memory space.

The RESET vector for the FM8P59 series is at FFFh.

The H/W interrupt vector is at 008h. And the S/W interrupt vector is at 002h.

FM8P59 series has program memory size greater than 1K words, but the CALL and GOTO instructions only have a

10-bit address range. This 10-bit address range allows a branch within a 1K program memory page size. To allow

CALL and GOTO instructions to address the entire 4K program memory address range for FM8P59 series, there is

another two bits to specify the program memory page. This paging bit comes from the PCHBUF<3:2> bits. When

doing a CALL or GOTO instruction, the user must ensure that page bit PCHBUF<3:2> are programmed so that the

desired program memory page is addressed. When one of the return instructions is executed, the entire 12-bit PC is

POPed from the stack. Therefore, manipulation of the PCHBUF <3:2> is not required for the return instructions.

User can use “PAGE” instruction to change memory page and maintains the program memory page. Otherwise,

user can use “FCALL(far call)/FGOTO(far goto)” instructions to program user's code.

FIGURE 1.1: Program Memory Map and STACK

PC<11:0>

Stack 1

Stack 2

Stack 3

Stack 4

Stack 5

FFFh

Reset Vector

:

008h H/W Interrupt Vector

002h S/W Interrupt Vector

000h

FM8P59 Series

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FM8P59

1.2 Data Memory Organization

Data memory is composed of Special Function Registers and General Purpose Registers.

The General Purpose Registers are accessed either directly or indirectly through the FSR register.

The Special Function Registers are registers used by the CPU and peripheral functions to control the

operation of the device.

In FM8P59 series, the data memory is partitioned into four banks. Switching between these banks requires the RP1

and RP0 bits in the FSR register to be configured for the desired bank. User can use “BANK” instruction to change

the data memory bank.

TABLE 1.1: Registers File Map for FM8P59 Series

FSR<7:6>

Address

Description

0 0

Bank 0

0 1

Bank 1

1 0

1 1

Bank 3

Bank 2

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

INDF

TMR0

PCL

N/A

OPTION

STATUS

FSR

PORTA

PORTB

PORTC

PCON

05h

06h

07h

IOSTA

IOSTB

IOSTC

WUCON

PCHBUF

PDCON

BPHCON

CPHCON

INTEN

Memory back to address in Bank 0

INTFLAG

10h

|

1Fh

General

Purpose

Registers

20h

|

3Fh

General

Purpose

Registers

General

Purpose

Registers

General

Purpose

Registers

General

Purpose

Registers

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FM8P59

TABLE 1.2: The Registers Controlled by OPTION or IOST Instructions

Address

N/A (w)

05h (w)

06h (w)

07h (w)

Name

OPTION

IOSTA

IOSTB

IOSTC

B7

-

B6

B5

B4

B3

B2

B1

B0

INTEDG

T0CS

T0SE

PSA

PS2

PS1

PS0

Port A I/O Control Register

Port B I/O Control Register

Port C I/O Control Register

TABLE 1.3: Operational Registers Map

Address

00h (r/w)

01h (r/w)

02h (r/w)

03h (r/w)

04h (r/w)

05h (r/w)

06h (r/w)

07h (r/w)

08h (r/w)

09h (r/w)

0Ah (r/w)

0Bh (r/w)

0Ch (r/w)

0Dh (r/w)

0Eh (r/w)

0Fh (r/w)

Name

INDF

B7

B6

B5

B4

B3

B2

B1

B0

C

Uses contents of FSR to address data memory (not a physical register)

8-bit real-time clock/counter

TMR0

PCL

Low order 8 bits of PC

STATUS

FSR

GP2

RP1

GP1

RP0

IOA6

IOB6

IOC6

EIS

GP0

TO

PD

Z

DC

Indirect data memory address pointer

PORTA

PORTB

PORTC

PCON

IOA7

IOB7

IOC7

WDTE

/WUB7

-

IOA5

IOB5

IOC5

LVDTE

/WUB5

-

IOA4

IOB4

IOC4

ROC

/WUB4

-

IOA3

IOB3

IOC3

-

IOA2

IOB2

IOC2

-

IOA1

IOB1

IOC1

IOA0

IOB0

IOC0

ODC67 /WUC45

WUCON

PCHBUF

PDCON

BPHCON

CPHCON

INTEN

/WUB6

-

/WUB3

/WUB2

/WUB1

/WUB0

Upper 4 bits Buffer of PC

/PDB3

/PHB7

/PHC7

GIE

/PDB2

/PHB6

/PHC6

-

/PDB1

/PHB5

/PHC5

-

/PDB0

/PHB4

/PHC4

-

/PDA3

/PHB3

/PHC3

INT1IE

INT1IF

/PDA2

/PHB2

/PHC2

INT0IE

INT0IF

/PDA1

/PDA0

/PHB0

/PHC0

T0IE

/PHB1

/PHC1

-

INTFLAG

-

T0IF

Legend: - = unimplemented, read as ‘0’,

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2.0 FUNCTIONAL DESCRIPTIONS

FM8P59

2.1 Operational Registers

2.1.1 INDF (Indirect Addressing Register)

Address

00h (r/w)

Name

INDF

B7

B6

B5

B4

B3

B2

B1

B0

Uses contents of FSR to address data memory (not a physical register)

The INDF Register is not a physical register. Any instruction accessing the INDF register can actually access the

register pointed by FSR Register. Reading the INDF register itself indirectly (FSR=”0”) will read 00h. Writing to the

INDF register indirectly results in a no-operation (although status bits may be affected).

The bits 5-0 of FSR register are used to select up to 64 registers (address: 00h ~ 3Fh).

In FM8P59 series, the data memory is partitioned into four banks. Switching between these banks requires the RP1

and RP0 bits in the FSR register to be configured for the desired bank. The lower locations of each bank are

reserved for the Special Function Registers. Above the Special Function Registers are General Purpose Registers.

All Special Function Registers and some of General Purpose Registers from other banks are mirrored in bank 0 for

code reduction and quicker access.

Accessed

RP1:RP0

Bank

0

1

2

3

0 0

0 1

1 0

1 1

EXAMPLE 2.1: INDIRECT ADDRESSING

‧ Register file 38 contains the value 10h

‧ Register file 39 contains the value 0Ah

‧ Load the value 38 into the FSR Register

‧ A read of the INDF Register will return the value of 10h

‧ Increment the value of the FSR Register by one (@FSR=39h)

‧ A read of the INDR register now will return the value of 0Ah.

FIGURE 2.2: Direct/Indirect Addressing for FM8P59 Series

Direct Addressing

Indirect Addressing

RP1:RP0

5

from opcode

0

5 from FSR register 0

bank select

location select

0 0

0 1

1 0

1 1

00h

3Fh

location select

addressing INDF register

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FM8P59

2.1.2 TMR0 (Time Clock/Counter register)

Address

01h (r/w)

Name

TMR0

B7

B6

B5

B4

B3

B2

B1

B0

8-bit real-time clock/counter

The Timer0 is a 8-bit timer/counter. The clock source of Timer0 can come from the instruction cycle clock or by an

external clock source (T0CKI pin) defined by T0CS bit (OPTION<5>). If T0CKI pin is selected, the Timer0 is

increased by T0CKI signal rising/falling edge (selected by T0SE bit (OPTION<4>)).

The prescaler is assigned to Timer0 by clearing the PSA bit (OPTION<3>). In this case, the prescaler will be cleared

when TMR0 register is written with a value.

2.1.3 PCL (Low Bytes of Program Counter) & Stack

Address

02h (r/w)

Name

PCL

B7

B6

B5

B4

B3

B2

B1

B0

Low order 8 bits of PC

FM8P59 devices have a 12-bit wide Program Counter (PC) and five-level deep 12-bit hardware push/pop stack. The

low byte of PC is called the PCL register. This register is readable and writable. The high byte of PC is called the

PCH register. This register contains the PC<11:8> bits and is not directly readable or writable. All updates to the

PCH register go through the PCHBUF register. As a program instruction is executed, the Program Counter will

contain the address of the next program instruction to be executed. The PC value is increased by one, every

instruction cycle, unless an instruction changes the PC.

For a GOTO instruction, the PC<9:0> is provided by the GOTO instruction word. The PC<11:10> is updated from

the PCHBUF<3:2>. The PCL register is mapped to PC<7:0>, and the PCHBUF register is not updated.

For a CALL instruction, the PC<9:0> is provided by the CALL instruction word. The PC<11:10> is updated from the

PCHBUF<3:2>. The next PC will be loaded (PUSHed) onto the top of STACK. The PCL register is mapped to

PC<7:0>, and the PCHBUF register is not updated.

For a FGOTO instruction, the PC<11:0> is provided by the FGOTO instruction word. The PCL register is mapped to

PC<7:0>, the PCHBUF<3:2> bits is also updated from the FGOTO instruction word, and the PCHBUF<1:0> bits are

not updated.

For a FCALL instruction, the PC<11:0> is provided by the FCALL instruction word. The next PC will be loaded

(PUSHed) onto the top of STACK. The PCL register is mapped to PC<7:0>, the PCHBUF<3:2> bits is also updated

from the FCALL instruction word, and the PCHBUF<1:0> bits are not updated.

For a RETIA, RETFIE, or RETURN instruction, the PC are updated (POPed) from the top of STACK. The PCL

register is mapped to PC<7:0>, and the PCHBUF register is not updated.

For any instruction where the PCL is the destination (excluding TBL instruction), the PC<7:0> is provided by the

instruction word or ALU result. However, the PC<11:8> will come from the PCHBUF<3:0> bits (PCHBUF Æ PCH).

For TBL instruction, the PC<7:0> is provided by the ALU result, and the PC<9:8> are not changed. The PC<11:10>

will come from the PCH<3:2> bits.

PCHBUF register is never updated with the contents of PCH.

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FM8P59

FIGURE 2.2: Loading of PC in Different Situations

Situation 1: GOTO Instruction

PCH

11 10 9

PCL

8

7

0

PC

PCHBUF<3:2>

Opcode<9:0>

-

PCHBUF

Situation 2: CALL Instruction

STACK<11:0>

Opcode<9:0>

PCH

11 10 9

PC

8

7

PCHBUF<3:2>

-

PCHBUF

Situation 3: FGOTO Instruction

PCH

11 10 9

8

-

7

PC

Opcode<11:0>

-

PCHBUF

To PCHBUF<3:2>

Opcode<11:10>

STACK<11:0>

Situation 4: FCALL Instruction

PCH

11 10 9

PC

PCL

8

-

7

0

Opcode<11:0>

Opcode<11:10>

-

PCHBUF

To PCHBUF<3:2>

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FM8P59

Situation 5: RETIA, RETFIE, or RETURN Instruction

STACK<11:0>

PCH

PCL

11 10 9

8

-

7

0

PC

-

PCHBUF

Situation 6: Instruction with PCL as destination (except TBL instruction)

PCH

PCL

11 10 9

8

7

0

PC

ALU result<7:0>

or Opcode<7:0>

PCHBUF<3:0>

-

PCHBUF

Situation 7: TBL Instruction

PCH

PCL

11 10 9

8

7

0

PC

PCHBUF<3:2>

ALU result<7:0>

-

PCH<9:8> bits are unchanged

PCHBUF

Note: PCHBUF is used for instruction with PCL as destination, GOTO and CALL instructions.

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FM8P59

2.1.4 STATUS (Status Register)

Address

03h (r/w)

Name

B7

B6

B5

B4

B3

B2

Z

B1

B0

C

STATUS

GP2

GP1

GP0

TO

PD

DC

This register contains the arithmetic status of the ALU, the RESET status.

If the STATUS Register is the destination for an instruction that affects the Z, DC or C bits, then the write to these

three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits

are not writable. Therefore, the result of an instruction with the STATUS Register as destination may be different

than intended. For example, CLRR STATUS will clear the upper three bits and set the Z bit. This leaves the

STATUS Register as 000u u1uu (where u = unchanged).

C : Carry/borrow bit.

ADDAR, ADDIA

= 1, a carry occurred.

= 0, a carry did not occur.

SUBAR, SUBIA

= 1, a borrow did not occur.

= 0, a borrow occurred.

Note : A subtraction is executed by adding the two’s complement of the second operand. For rotate (RRR, RLR)

instructions, this bit is loaded with either the high or low order bit of the source register.

DC : Half carry/half borrow bit.

ADDAR, ADDIA

= 1, a carry from the 4th low order bit of the result occurred.

= 0, a carry from the 4th low order bit of the result did not occur.

SUBAR, SUBIA

= 1, a borrow from the 4th low order bit of the result did not occur.

= 0, a borrow from the 4th low order bit of the result occurred.

Z : Zero bit.

= 1, the result of a logic operation is zero.

= 0, the result of a logic operation is not zero.

PD : Power down flag bit.

= 1, after power-up or by the CLRWDT instruction.

= 0, by the SLEEP instruction.

TO : Time overflow flag bit.

= 1, after power-up or by the CLRWDT or SLEEP instruction.

= 0, a watch-dog time overflow occurred.

GP2:GP0 : General purpose read/write bits.

2.1.5 FSR (Indirect Data Memory Address Pointer)

Address

04h (r/w)

Name

FSR

B7

B6

B5

B4

B3

B2

B1

B0

RP1

RP0

Indirect data memory address pointer

Bit5:Bit0 : Select registers address in the indirect addressing mode. See 2.1.1 for detail description.

RP1:RP0 : These bits are used to switching the bank of four data memory banks. User can use “BANK” instruction

to change bank. See 2.1.1 for detail description.

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2.1.6 PORTA, PORTB & PORTC (Port Data Registers)

FM8P59

Address

05h (r/w)

06h (r/w)

07h (r/w)

Name

PORTA

PORTB

PORTC

B7

B6

B5

B4

B3

B2

B1

B0

IOA7

IOB7

IOC7

IOA6

IOB6

IOC6

IOA5

IOB5

IOC5

IOA4

IOB4

IOC4

IOA3

IOB3

IOC3

IOA2

IOB2

IOC2

IOA1

IOB1

IOC1

IOA0

IOB0

IOC0

Reading the port (PORTA, PORTB, PORTC register) reads the status of the pins independent of the pin’s

input/output modes. Writing to these ports will write to the port data latch.

For FM8P59A devices, PORTA is a 4-bit port data Register. In this type, only the low order 4 bits are used

(PORTA<3:0>) and bits 7-4 are unimplemented and read as ‘0’s.

For FM8P59B devides, PORTA is a 8-bit port data Register.

PORTB and PORTC are 8-bit port data registers.

2.1.7 PCON (Power Control Register)

Address

08h (r/w)

Name

PCON

B7

B6

B5

B4

B3

-

B2

-

B1

B0

WDTE

EIS

LVDTE

ROC

ODC67 /WUC45

/WUC45 : = 0, Enable the input falling wake-up function of IOC4 and IOC5 pins.

= 1, Disable the input falling wake-up function of IOC4 and IOC5 pins.

ODC67 : = 0, Disable the internal open-drain of IOC6 and IOC7 pins.

= 1, Enable the internal open-drain of IOC6 and IOC7 pins.

Bit3:Bit2 : Not used. Read as “0”s.

ROC : R-option function of IOC0 and IOC1 pins enable bit.

= 0, Disable the R-option function.

= 1, Enable the R-option function. In this case, if a 430KΩ external resister is connected/disconnected to Vss,

the status of IOC0 (IOC1) is read as “0”/”1”.

LVDTE : LVDT (low voltage detector) enable bit.

= 0, Disable LVDT.

= 1, Enable LVDT.

EIS : Define the function of IOB0/INT0 pin.

= 0, IOB0 (bi-directional I/O pin) is selected. The path of INT0 is masked.

= 1, INT0 (external interrupt pin) is selected. In this case, the I/O control bit of IOB0 must be set to “1”. The path

of Port B input change of IOB0 pin is masked by hardware, the status of INT0 pin can also be read by way

of reading PORTB.

WDTE : WDT (watch-dog timer) enable bit.

= 0, Disable WDT.

= 1, Enable WDT.

2.1.8 WUCON (Port B Input Falling Wake-up Control Register)

Address

09h (r/w)

Name

B7

B6

B5

B4

B3

B2

B1

B0

WUCON

/WUB7

/WUB6

/WUB5

/WUB4

/WUB3

/WUB2

/WUB1

/WUB0

/WUB0 : = 0, Enable the input falling wake-up function of IOB0 pin.

= 1, Disable the input falling wake-up function of IOB0 pin.

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/WUB1 : = 0, Enable the input falling wake-up function of IOB1 pin.

= 1, Disable the input falling wake-up function of IOB1 pin.

/WUB2 : = 0, Enable the input falling wake-up function of IOB2 pin.

= 1, Disable the input falling wake-up function of IOB2 pin.

/WUB3 : = 0, Enable the input falling wake-up function of IOB3 pin.

= 1, Disable the input falling wake-up function of IOB3 pin.

/WUB4 : = 0, Enable the input falling wake-up function of IOB4 pin.

= 1, Disable the input falling Wake-up function of IOB4 pin.

/WUB5 : = 0, Enable the input falling wake-up function of IOB5 pin.

= 1, Disable the input falling wake-up function of IOB5 pin.

/WUB6 : = 0, Enable the input falling wake-up function of IOB6 pin.

= 1, Disable the input falling wake-up function of IOB6 pin.

/WUB7 : = 0, Enable the input falling wake-up function of IOB7 pin.

= 1, Disable the input falling wake-up function of IOB7 pin.

2.1.9 PCHBUF (High Byte Buffer of Program Counter)

Address

Name

B7

-

B6

-

B5

-

B4

-

B3

B2

B1

B0

0Ah (r/w)

PCHBUF

Upper 4 bits Buffer of PC

PCHBUF<3:2> : Program memory page selection bits.

= 0, 0 Æ Page 0.

= 0, 1 Æ Page 1.

= 1, 0 Æ Page 2.

= 1, 1 Æ Page 3.

User can use “PAGE” instruction to change memory page and maintains the program memory page. Otherwise,

user can use “FGOTO” (far goto), or “FCALL” (far call) instructions to program user's code.

See 2.1.3 for detail description.

2.1.10 PDCON (Pull-down Control Register)

Address

Name

B7

B6

B5

B4

B3

B2

B1

B0

0Bh (r/w)

PDCON

/PDB3

/PDB2

/PDB1

/PDB0

/PDA3

/PDA2

/PDA1

/PDA0

/PDA0 : = 0, Enable the internal pull-down of IOA0 pin.

= 1, Disable the internal pull-down of IOA0 pin.

/PDA1 : = 0, Enable the internal pull-down of IOA1 pin.

= 1, Disable the internal pull-down of IOA1 pin.

/PDA2 : = 0, Enable the internal pull-down of IOA2 pin.

= 1, Disable the internal pull-down of IOA2 pin.

/PDA3 : = 0, Enable the internal pull-down of IOA3 pin.

= 1, Disable the internal pull-down of IOA3 pin.

/PDB0 : = 0, Enable the internal pull-down of IOB0 pin.

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= 1, Disable the internal pull-down of IOB0 pin.

FM8P59

/PDB1 : = 0, Enable the internal pull-down of IOB1 pin.

= 1, Disable the internal pull-down of IOB1 pin.

/PDB2 : = 0, Enable the internal pull-down of IOB2 pin.

= 1, Disable the internal pull-down of IOB2 pin.

/PDB3 : = 0, Enable the internal pull-down of IOB3 pin.

= 1, Disable the internal pull-down of IOB3 pin.

2.1.11 BPHCON (PortB Pull-high Control Register)

Address

Name

B7

B6

B5

B4

B3

B2

B1

B0

0Ch (r/w)

BPHCON

/PHB7

/PHB6

/PHB5

/PHB4

/PHB3

/PHB2

/PHB1

/PHB0

/PHB0 : = 0, Enable the internal pull-high of IOB0 pin.

= 1, Disable the internal pull-high of IOB0 pin.

/PHB1 : = 0, Enable the internal pull-high of IOB1 pin.

= 1, Disable the internal pull-high of IOB1 pin.

/PHB2 : = 0, Enable the internal pull-high of IOB2 pin.

= 1, Disable the internal pull-high of IOB2 pin.

/PHB3 : = 0, Enable the internal pull-high of IOB3 pin.

= 1, Disable the internal pull-high of IOB3 pin.

/PHB4 : = 0, Enable the internal pull-high of IOB4 pin.

= 1, Disable the internal pull-high of IOB4 pin.

/PHB5 : = 0, Enable the internal pull-high of IOB5 pin.

= 1, Disable the internal pull-high of IOB5 pin.

/PHB6 : = 0, Enable the internal pull-high of IOB6 pin.

= 1, Disable the internal pull-high of IOB6 pin.

/PHB7 : = 0, Enable the internal pull-high of IOB7 pin.

= 1, Disable the internal pull-high of IOB7 pin.

2.1.12 CPHCON (PortC Pull-high Control Register)

Address

Name

B7

B6

B5

B4

B3

B2

B1

B0

0Dh (r/w)

CPHCON

/PHC7

/PHC6

/PHC5

/PHC4

/PHC3

/PHC2

/PHC1

/PHC0

/PHC0 : = 0, Enable the internal pull-high of IOC0 pin.

= 1, Disable the internal pull-high of IOC0 pin.

/PHC1 : = 0, Enable the internal pull-high of IOC1 pin.

= 1, Disable the internal pull-high of IOC1 pin.

/PHC2 : = 0, Enable the internal pull-high of IOC2 pin.

= 1, Disable the internal pull-high of IOC2 pin.

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/PHC3 : = 0, Enable the internal pull-high of IOC3 pin.

= 1, Disable the internal pull-high of IOC3 pin.

/PHC4 : = 0, Enable the internal pull-high of IOC4 pin.

= 1, Disable the internal pull-high of IOC4 pin.

/PHC5 : = 0, Enable the internal pull-high of IOC5 pin.

= 1, Disable the internal pull-high of IOC5 pin.

/PHC6 : = 0, Enable the internal pull-high of IOC6 pin.

= 1, Disable the internal pull-high of IOC6 pin.

/PHC7 : = 0, Enable the internal pull-high of IOC7 pin.

= 1, Disable the internal pull-high of IOC7 pin.

2.1.13 INTEN (Interrupt Mask Register)

Address

Name

B7

B6

-

B5

-

B4

-

B3

B2

B1

-

B0

0Eh (r/w)

INTEN

GIE

INT1IE

INT0IE

T0IE

T0IE : Timer0 overflow interrupt enable bit.

= 0, Disable the Timer0 overflow interrupt.

= 1, Enable the Timer0 overflow interrupt.

Bit1 : Not used. Read as “0”.

INT0IE : External INT0 pin interrupt enable bit.

= 0, Disable the External INT0 pin interrupt.

= 1, Enable the External INT0 pin interrupt.

INT1IE : External INT1 pin interrupt enable bit.

= 0, Disable the External INT1 pin interrupt.

= 1, Enable the External INT1 pin interrupt.

Bit6:BIT4 : Not used. Read as “0”s.

GIE : Global interrupt enable bit.

= 0, Disable all interrupts.

= 1, Enable all un-masked interrupts.

Note : When an interrupt event occur with the GIE bit and its corresponding interrupt enable bit are all set, the

GIE bit will be cleared by hardware to disable any further interrupts. The RETFIE instruction will exit the

interrupt routine and set the GIE bit to re-enable interrupt.

2.1.14 INTFLAG (Interrupt Status Register)

Address

0Fh (r/w)

Name

B7

-

B6

-

B5

-

B4

-

B3

B2

B1

-

B0

INTFLAG

INT1IF

INT0IF

T0IF

T0IF : Timer0 overflow interrupt flag. Set when Timer0 overflows, reset by software.

Bit1 : Not used. Read as “0”.

INT0IF : External INT0 pin interrupt flag. Set by rising/falling (selected by INTEDG bit (OPTION<6>)) edge on INT0

pin, reset by software.

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INT1IF : External INT1 pin interrupt flag. Set by falling edge on INT1 pin, reset by software.

Bit7:BIT4 : Not used. Read as “0”s.

2.1.15 ACC (Accumulator)

Address

N/A (r/w)

Name

ACC

B7

B6

B5

B4

B3

B2

B1

B0

Accumulator

Accumulator is an internal data transfer, or instruction operand holding. It can not be addressed.

2.1.16 OPTION Register

Address

N/A (w)

Name

B7

-

B6

B5

B4

B3

B2

B1

B0

OPTION

INTEDG

T0CS

T0SE

PSA

PS2

PS1

PS0

Accessed by OPTION instruction.

By executing the OPTION instruction, the contents of the ACC Register will be transferred to the OPTION Register.

The OPTION Register is a 7-bit wide, write-only register which contains various control bits to configure the

Timer0/WDT prescaler, Timer0, and the external INT interrupt.

The OPTION Register are “write-only” and are set all “1”s except INTEDG bit.

PS2:PS0 : Prescaler rate select bits.

PS2:PS0

Timer0 Rate

WDT Rate

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

1:2

1:4

1:8

1:16

1:32

1:64

1:128

1:256

1:1

1:2

1:4

1:8

1:16

1:32

1:64

1:128

PSA : Prescaler assign bit.

= 1, WDT (watch-dog timer).

= 0, TMR0 (Timer0).

T0SE : TMR0 source edge select bit.

= 1, Falling edge on T0CKI pin.

= 0, Rising edge on T0CKI pin.

T0CS : TMR0 clock source select bit.

= 1, External T0CKI pin.

= 0, internal instruction clock cycle.

INTEDG : INT0 pin interrupt edge select bit.

= 1, interrupt on rising edge of INT0 pin.

= 0, interrupt on falling edge of INT0 pin.

Bit7 : Not used.

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2.1.17 IOSTA, IOSTB & IOSTC (Port I/O Control Registers)

Address

N/A (w)

Name

IOSTA

IOSTB

IOSTC

B7

B6

B5

B4

B3

B2

B1

B0

Port A I/O Control Register

Port B I/O Control Register

Port C I/O Control Register

Accessed by IOST instruction.

The Port I/O Control Registers are loaded with the contents of the ACC Register by executing the IOST R (05h~07h)

instruction. A ‘1’ from a IOST Register bit puts the corresponding output driver in hi-impedance state (input mode).

A ‘0’ enables the output buffer and puts the contents of the output data latch on the selected pins (output mode).

The IOST Registers are “write-only” and are set (output drivers disabled) upon RESET.

2.2 I/O Ports

Port A, port B and port C are bi-directional tri-state I/O ports. Port A is a 4-pin I/O port for FM8P59A, and port A is a

8-pin I/O port for FM8P59B. Port B and port C are 8-pin I/O ports.

All I/O pins (IOA<7:0>, IOB<7:0> and IOC<7:0>) have data direction control registers (IOSTA, IOSTB, IOSTC)

which can configure these pins as output or input.

IOB<7:0> and IOC<7:0> have its corresponding pull-high control bits (BPHCON and CPHCON registers) to enable

the weak internal pull-high. The weak pull-high is automatically turned off when the pin is configured as an output

pin.

IOA<3:0> and IOB<3:0> have its corresponding pull-down control bits (PDCON register) to enable the weak internal

pull-down. The weak pull-down is automatically turned off when the pin is configured as an output pin.

IOC<7:6> have its corresponding open-drain control bit (ODC67 bit (PCON<1>) ) to enable the open-drain output

when these pins are configured to be an output pin.

IOA0 and IOA1 are the R-option pins enabled by setting the ROC bit (PCON<4>). When the R-option function is

used, it is recommended that IOA0 and IOA1 are used as output pins, and read the status of IOA0 and IOA1 before

these pins are configured to be an output pin.

IOB<7:0> and IOC<5:4> also provide the input falling wake-up function. Each pin has its corresponding input falling

wake-up enable bits (WUCON register and /WUC45 bit (PCON<0>) ) to select the input falling wake-up source.

The IOB0 is also an external interrupt input signal by setting the EIS bit (PCON<6>). In this case, IOB0 input falling

wake-up function will be disabled by hardware even if it is enabled by software.

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FIGURE 2.3: Block Diagram of I/O PINs

IOA7 ~ IOA0, IOC7 ~ IOC6, IOC3 ~ IOC0 :

Data bus

D

Q

IOST

Latch

> EN

Q

IOST R

I/O PIN

D

DATA

Latch

> EN

Q

WR PORT

RD PORT

Pull-down is not shown in the figure

IOC5 ~ IOC4 :

Data bus

D

Q

IOST

Latch

> EN

Q

IOST R

I/O PIN

D

DATA

Latch

> EN

Q

WR PORT

RD PORT

Set PBCIF

WUC45

Pull-high and open-drain are not shown in the figure

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IOB0 :

Data bus

D

Q

IOST

Latch

> EN

Q

IOST R

I/O PIN

D

DATA

Latch

> EN

Q

WR PORT

RD PORT

Q

D

Set PBCIF

Latch

EN<

WUBn

EIS

INTEDG

EIS

INT0

Pull-high/pull-down and open-drain are not shown in the figure

IOB7 ~ IOB1 :

Data bus

D

Q

IOST

Latch

> EN

Q

IOST R

I/O PIN

D

DATA

Latch

> EN

Q

WR PORT

RD PORT

Q

D

Set PBCIF

Latch

EN<

WUBn

Pull-high/pull-down and open-drain are not shown in the figure

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2.3 Timer0/WDT & Prescler

FM8P59

2.3.1 Timer0

The Timer0 is a 8-bit timer/counter. The clock source of Timer0 can come from the internal clock or by an external

clock source (T0CKI pin).

2.3.1.1 Using Timer0 with an Internal Clock : Timer mode

Timer mode is selected by clearing the T0CS bit (OPTION<5>). In timer mode, the timer0 register (TMR0) will

increment every instruction cycle (without prescaler). If TMR0 register is written, the increment is inhibited for the

following two cycles.

2.3.1.2 Using Timer0 with an External Clock : Counter mode

Counter mode is selected by setting the T0CS bit (OPTON<5>). In this mode, Timer0 will increment either on every

rising or falling edge of pin T0CKl. The incrementing edge is determined by the source edge select bit T0SE

(OPTION<4>).

The external clock requirement is due to internal phase clock (Tosc) synchronization. Also, there is a delay in the

actual incrementing of Timer0 after synchronization.

When no prescaler is used, the external clock input is the same as the prescaler output. The synchronization of

T0CKI with the internal phase clocks is accomplished by sampling the prescaler output on the T2 and T4 cycles of

the internal phase clocks. Therefore, it is necessary for T0CKI to be high for at least 2 T_OSCand low for at least 2

Tosc.

When a prescaler is used, the external clock input is divided by the asynchronous prescaler. For the external clock

to meet the sampling requirement, the ripple counter must be taken into account. Therefore, it is necessary for

T0CKI to have a period of at least 4Tosc divided by the prescaler value.

2.3.2 Watchdog Timer (WDT)

The Watchdog Timer (WDT) is a free running on-chip RC oscillator which does not require any external components.

So the WDT will still run even if the clock on the OSCI and OSCO pins is turned off, such as in SLEEP mode. During

normal operation or in SLEEP mode, a WDT time-out will cause the device reset and the TO bit (STATUS<4>) will

be cleared.

The WDT can be disabled by clearing the control bit WDTE (PCON<7>) to “0”.

The WDT has a nominal time-out period of 18 ms (without prescaler). If a longer time-out period is desired, a

prescaler with a division ratio of up to 1:128 can be assigned to the WDT controlled by the OPTION register. Thus,

the longest time-out period is approxmately 2.3 seconds.

The CLRWDT instruction clears the WDT and the prescaler, if assigned to the WDT, and prevents it from timing out

and generating a device reset.

The SLEEP instruction resets the WDT and the prescaler, if assigned to the WDT. This gives the maximum SLEEP

time before a WDT Wake-up Reset.

2.3.3 Prescaler

An 8-bit counter (down counter) is available as a prescaler for the Timer0, or as a postscaler for the Watchdog Timer

(WDT). Note that the prescaler may be used by either the Timer0 module or the WDT, but not both. Thus, a

prescaler assignment for the Timer0 means that there is no prescaler for the WDT, and vice-versa.

The PSA bit (OPTION<3>) determines prescaler assignment. The PS<2:0> bits (OPTION<2:0>) determine

prescaler ratio.

When the prescaler is assigned to the Timer0 module, all instructions writing to the TMR0 register will clear the

prescaler. When it is assigned to WDT, a CLRWDT instruction will clear the prescaler along with the WDT.

The prescaler is neither readable nor writable. On a RESET, the prescaler contains all ‘1’s.

To avoid an unintended device reset, CLRWDT or CLRR TMR0 instructions must be executed when changing the

prescaler assignment from Timer0 to the WDT, and vice-versa.

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FIGURE 2.4: Block Diagram of The Timer0/WDT Prescaler

Instruction Cycle

(Fosc/4 or Fosc/2 or Fosc/1 or Fosc/8)

0

1

8

MUX

Data Bus

TMR0

Register

Sync

2 Cycles

T0CKI

1

MUX

PSA

0

Set T0IF flag

on overflow

T0SE

T0CS

0

1

0

8-Bit

Prescaler

MUX

PSA

Watchdog

Timer

WDT Time-out

MUX

PSA

PS2:PS0

2.4 Interrupts

The FM8P59 series has up to three sources of interrupt:

1. External interrupt INT0 pin.

2. External interrupt INT1 pin.

3. TMR0 overflow interrupt.

INTFLAG is the interrupt flag register that recodes the interrupt requests in the relative flags.

A global interrupt enable bit, GIE (INTEN<7>), enables (if set) all un-masked interrupts or disables (if cleared) all

interrupts. Individual interrupts can be enabled/disabled through their corresponding enable bits in INTEN register

regardless of the status of the GIE bit.

When an interrupt event occur with the GIE bit and its corresponding interrupt enable bit are all set, the GIE bit will

be cleared by hardware to disable any further interrupts, and the next instruction will be fetched from address 008h.

The interrupt flag bits must be cleared by software before re-enabling GIE bit to avoid recursive interrupts.

The RETFIE instruction exits the interrupt routine and set the GIE bit to re-enable interrupt.

The flag bit in INTFLAG register is set by interrupt event regardless of the status of its mask bit. Reading the

INTFLAG register will be the logic AND of INTFLAG and INTEN.

When an interrupt is generated by the INT instruction, the next instruction will be fetched from address 002h.

2.4.1 External INT0 Interrupt

External interrupt on INT0 pin is rising or falling edge triggered selected by INTEDG (OPTION<6>).

When a valid edge appears on the INT0 pin the flag bit INT0IF (INTFLAG<2>) is set. This interrupt can be disabled

by clearing INT0IE bit (INTEN<2>).

2.4.2 External INT1 Interrupt

External interrupt on INT1 pin is falling edge triggered.

When a falling edge appears on the INT1 pin the flag bit INT1IF (INTFLAG<3>) is set. This interrupt can be disabled

by clearing INT1IE bit (INTEN<3>).

2.4.3 Timer0 Interrupt

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An overflow (FFh Æ 00h) in the TMR0 register will set the flag bit T0IF (INTFLAG<0>). This interrupt can be

disabled by clearing T0IE bit (INTEN<0>).

2.5 Power-down Mode (SLEEP)

Power-down mode is entered by executing a SLEEP instruction.

When SLEEP instruction is executed, the PD bit (STATUS<3>) is cleared, the TO bit is set, the watchdog timer will

be cleared and keeps running, and the oscillator driver is turned off.

All I/O pins maintain the status they had before the SLEEP instruction was executed.

2.5.1 Wake-up from SLEEP Mode

The device can wake-up from SLEEP mode through one of the following events:

1. RSTB reset.

2. WDT time-out reset (if enabled).

3. PORTB/IOC4/IOC5 input falling.

External RSTB reset and WDT time-out reset will cause a device reset. The PD and TO bits can be used to

determine the cause of device reset. The PD bit is set on power-up and is cleared when SLEEP instruction is

executed. The TO bit is cleared if a WDT time-out occurred.

For the device to wake-up through an PORTB/IOC4/IOC5 input falling event, and the program will execute next PC

after wake-up. Any pin which corresponding /WUBn bit (WUCON<7:0>) or /WUC45 bit (PCON<0>) is set to “1” or

configured as output will be excluded from this function.

The system wake-up delay time is 18ms plus 128 oscillator cycle time.

2.6 Reset

FM8P59 devices may be RESET in one of the following ways:

1. Power-on Reset (POR)

2. Brown-out Reset (BOR)

3. RSTB Pin Reset

4. WDT time-out Reset

Some registers are not affected in any RESET condition. Their status is unknown on Power-on Reset and

unchanged in any other RESET. Most other registers are reset to a “reset state” on Power-on Reset, RSTB or WDT

Reset.

A Power-on RESET pulse is generated on-chip when Vdd rise is detected. To use this feature, the user merely ties

the RSTB pin to Vdd.

On-chip Low Voltage Detector (LVD) places the device into reset when Vdd is below a fixed voltage. This ensures

that the device does not continue program execution outside the valid operation Vdd range. Brown-out RESET is

typically used in AC line or heavy loads switched applications.

A RSTB or WDT Wake-up from SLEEP also results in a device RESET, and not a continuation of operation before

SLEEP.

The TO and PD bits (STATUS<4:3>) are set or cleared depending on the different reset conditions.

2.6.1 Power-up Reset Timer(PWRT)

The Power-up Reset Timer provides a nominal 18ms delay after Power-on Reset (POR), Brown-out Reset (BOR),

RSTB Reset or WDT time-out Reset. The device is kept in reset state as long as the PWRT is active.

The PWDT delay will vary from device to device due to Vdd, temperature, and process variation.

2.6.2 Oscillator Start-up Timer(OST)

The OST timer provides a 128 oscillator cycle delay (from OSCI input) after the PWRT delay (18ms) is over. This

delay ensures that the X’tal oscillator or resonator has started and stabilized. The device is kept in reset state as

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long as the OST is active.

This counter only starts incrementing after the amplitude of the OSCI signal reaches the oscillator input thresholds.

2.6.3 Reset Sequence

When Power-on Reset (POR), Brown-out Reset (BOR), RSTB Reset or WDT time-out Reset is detected, the reset

sequence is as follows:

1. The reset latch is set and the PWRT & OST are cleared.

2. When the internal POR, BOR, RSTB Reset or WDT time-out Reset pulse is finished, then the PWRT begins

counting.

3. After the PWRT time-out, the OST is activated.

4. And after the OST delay is over, the reset latch will be cleared and thus end the on-chip reset signal.

The totally system reset delay time is 18ms plus 128 oscillator cycle time.

FIGURE 2.5: Simplified Block Diagram of on-chip Reset Circuit

WDT

Time-out

WDT

Module

S

R

Q

RSTB

Vdd

Reset

Latch

Low Voltage

Detector

(LVD)

BOR

POR

CHIP RESET

Power-on

Reset

(POR)

RESET

On-Chip

RC OSC

Power-up

Reset Timer

(PWRT)

Oscillator

Start-up Timer

(OST)

OSCI

FIGURE 2.6: Time-out Sequence on Power-up (RSTB Pin Tied to Vdd)

VDD

RSTB

INTERNAL PWRB

T_PWRT

PWRT TIME-OUT

T_OST

OST TIME-OUT

INTERNAL RESET

Note: T_PWRT= 18 ms; T_OST= 128 oscillator cycle time

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FIGURE 2.7: Time-out Sequence on Power-up (RSTB Pin Not Tied to Vdd)

VDD

RSTB

INTERNAL PWRB

T_PWRT

PWRT TIME-OUT

T_OST

OST TIME-OUT

INTERNAL RESET

Note: T_PWRT= 18 ms; T_OST= 128 oscillator cycle time

TABLE 2.1: Reset Conditions for All Registers

Power-on Reset

Brown-out Reset

RSTB Reset

WDT Reset

Register

Address

ACC

N/A

xxxx xxxx

uuuu uuuu

-011 1111

OPTION

-011 1111

A: 0000 1111

B: 1111 1111

A: 0000 1111

B: 1111 1111

IOSTA

05h

IOSTB

IOSTC

06h

07h

1111 1111

xxxx xxxx

1111 1111

0001 1xxx

xxxx xxxx

---- xxxx

xxxx xxxx

1010 --00

0000 0000

---- -000

1111 1111

0--- 00-0

---- 00-0

xxxx xxxx

1111 1111

uuuu uuuu

1111 1111

000# #uuu

uuuu uuuu

---- uuuu

uuuu uuuu

1010 --00

0000 0000

---- -000

1111 1111

0--- 00-0

---- 00-0

uuuu uuuu

INDF

00h

TMR0

01h

PCL

02h

STATUS

FSR

03h

04h

PORTA

05h

PORTB

06h

PORTC

07h

PCON

08h

WUCON

PCHBUF

PDCON

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10 ~ 3Fh

BPHCON

CPHCON

INTEN

INTFLAG

General Purpose Registers

Legend: u = unchanged, x = unknown, - = unimplemented, # = refer to the following table for possible values.

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TABLE 2.2: TO /PD Status after Reset

TO

1

PD

1

RESET was caused by

Power-on Reset

1

Brown-out reset

u

RSTB Reset during normal operation

RSTB Reset during SLEEP

WDT Reset during normal operation

WDT Wake-up during SLEEP

1

0

1

0

Legend: u = unchanged

TABLE 2.3: Events Affecting TO /PD Status Bits

Event

TO

1

PD

1

Power-on

WDT Time-Out

0

u

SLEEP instruction

CLRWDT instruction

Legend: u = unchanged

1

0

1

2.7 Hexadecimal Convert to Decimal (HCD)

Decimal format is another number format for FM8P59 series. When the content of the data memory has been

assigned as decimal format, it is necessary to convert the results to decimal format after the execution of ALU

instructions. When the decimal converting operation is processing, all of the operand data (including the contents of

the data memory (RAM), accumulator (ACC), immediate data, and look-up table) should be in the decimal format, or

the results of conversion will be incorrect.

Instruction DAA can convert the ACC data from hexadecimal to decimal format after any addition operation and

restored to ACC.

The conversion operation is illustrated in example 2.2.

EXAMPLE 2.2: DAA CONVERSION

MOVIA

MOVAR 30h

MOVIA

ADDAR

90h

;Set immediate data = decimal format number “90” (ACC Å 90h)

;Load immediate data “90” to data memory address 30H

;Set immediate data = decimal format number “10” (ACC Å 10h)

;Contents of the data memory address 30H and ACC are binary-added

;the result loads to the ACC (ACC Å A0h, C Å 0)

10h

30h, 0

DAA

;Convert the content of ACC to decimal format, and restored to ACC

;The result in the ACC is “00” and the carry bit C is “1”. This represents the

;decimal number “100”

Instruction DAS can convert the ACC data from hexadecimal to decimal format after any subtraction

operation and restored to ACC.

The conversion operation is illustrated in example 2.3.

EXAMPLE 2.3: DAS CONVERSION

MOVIA

MOVAR 30h

MOVIA

SUBAR

10h

;Set immediate data = decimal format number “10” (ACC Å 10h)

;Load immediate data “10” to data memory address 30H

;Set immediate data = decimal format number “20” (ACC Å 20h)

;Contents of the data memory address 30H and ACC are binary-subtracted

;the result loads to the ACC (ACC Å F0h, C Å 0)

20h

30h, 0

DAS

;Convert the content of ACC to decimal format, and restored to ACC

;The result in the ACC is “90” and the carry bit C is “0”. This represents the

;decimal number “ -10”

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2.8 Oscillator Configurations

FM8P59

FM8P59 series can be operated in four different oscillator modes. Users can program two configuration bits

(Fosc<1:0>) to select the appropriate modes:

‧ LF: Low Frequency Crystal Oscillator

‧ XT: Crystal/Resonator Oscillator

‧ HF: High Frequency Crystal/Resonator Oscillator

‧ ERC: External Resistor/Capacitor Oscillator

In LF, XT, or HF modes, a crystal or ceramic resonator in connected to the OSCI and OSCO pins to establish

oscillation. When in LF, XT, or HF modes, the devices can have an external clock source drive the OSCI pin.

The ERC device option offers additional cost savings for timing insensitive applications. The RC oscillator

frequency is a function of the supply voltage, the resistor (Rext) and capacitor (Cext), the operating temperature,

and the process parameter.

FIGURE 2.8: HF, XT or LF Oscillator Modes (Crystal Operation or Ceramic Resonator)

FM8P59

OSCI

C1

C2

X’TAL

RS

SLEEP

RF

OSCO

Internal

Circuit

FIGURE 2.9: HF, XT or LF Oscillator Modes (External Clock Input Operation)

FM8P59

OSCI

Clock from

External System

OSCO

Open

FIGURE 2.10: ERC Oscillator Mode

Rext

FM8P59

OSCI

Internal

Circuit

Cext

OSCO

/1, /2, /4, /8

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2.9 Configurations Word

FM8P59

TABLE 2.4: Configurations Word

Name

Description

Oscillator Selection Bits

= 1, 1 Æ ERC mode (default)

= 1, 0 Æ HF mode

Fosc

= 0, 1 Æ XT mode

= 0, 0 Æ LF mode

Watchdog Timer Enable Bit

= 1, WDT enabled (default)

= 0, WDT disabled

WDTEN

Code Protection Bit

PROTECT = 1, EPROM code protection off (default)

= 0, EPROM code protection on

Low Voltage Detector Selection Bit

= 1, 1 Æ disable (default)

LVDT

= 1, 0 Æ enable, LVDT voltage = 2.0V, controlled by SLEEP

= 0, 1 Æ enable, LVDT voltage = 2.0V

= 0, 0 Æ enable, LVDT voltage = 3.6V

Instruction Period Selection Bits

= 1, 1 Æ four oscillator periods (default)

= 1, 0 Æ two oscillator periods

= 0, 1 Æ one oscillator period

OSCD

= 0, 0 Æ eight oscillator periods

Power Mode Selection Bit

PMOD

TYPE

= 1, Non-power saving (default)

= 0, Power saving

Type Selection Bit

= 1, A type (28-pin) is selected (default)

= 0, B type (32-pin) is selected

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3.0 INSTRUCTION SET

Mnemonic,

Operands

Status

Cycles

Description

Operation

Affected

BCR

BSR

R, bit Clear bit in R

R, bit Set bit in R

0 Æ R

1 Æ R

1

-

BTRSC R, bit Test bit in R, Skip if Clear

Skip if R = 0

Skip if R = 1

No operation

1/2 ⁽¹⁾

1

BTRSS

NOP

R, bit Test bit in R, Skip if Set

No Operation

00h Æ WDT,

00h Æ WDT prescaler

CLRWDT

OPTION

SLEEP

Clear Watchdog Timer

Load OPTION register

Go into power-down mode

1

TO PD

,

ACC Æ OPTION

-

00h Æ WDT,

TO PD

,

00h Æ WDT prescaler

PC<7:0> + ACC Æ PC<7:0>

PC<9:8> unchanged

TBL

Table look-up

1

C, DC, Z

PCHBUF<3:2> Æ PC<11:10>

Adjust ACC’s data format from HEX to

DEC after any addition operation

DAA

DAS

ACC(hex) Æ ACC(dec)

1

C

-

Adjust ACC’s data format from HEX to

DEC after any subtraction operation

PC + 1 Æ Top of Stack,

002h Æ PC

INT

S/W interrupt

2

-

RETURN

RETFIE

Return from subroutine

Return from interrupt, set GIE bit

Clear ACC

Top of Stack Æ PC

Top of Stack Æ PC,

1 Æ GIE

CLRA

IOST

00h Æ ACC

ACC Æ IOST register

00h Æ R

1

Z

-

R

Load IOST register

Clear R

CLRR

MOVAR

MOVR

DECR

Z

-

Move ACC to R

ACC Æ R

R, d Move R

R Æ dest

Z

R, d Decrement R

R - 1 Æ dest

R - 1 Æ dest,

Skip if result = 0

DECRSZ R, d Decrement R, Skip if 0

INCR R, d Increment R

1/2 ⁽¹⁾

1

-

Z

-

R + 1 Æ dest

R + 1 Æ dest,

Skip if result = 0

INCRSZ R, d Increment R, Skip if 0

1/2 ⁽¹⁾

ADDAR R, d Add ACC and R

R + ACC Æ dest

R - ACC Æ dest

R + ACC + C Æ dest

ACC and R Æ dest

ACC or R Æ dest

R xor ACC Æ dest

R Æ dest

1

C, DC, Z

SUBAR R, d Subtract ACC from R

ADCAR R, d Add ACC and R with Carry

SBCAR R, d Subtract ACC from R with Carry

ANDAR R, d AND ACC with R

C, DC, Z

Z

IORAR

R, d Inclusive OR ACC with R

XORAR R, d Exclusive OR ACC with R

COMR

RLR

R, d Complement R

R<7> Æ C,

R<6:0> Æ dest<7:1>,

C Æ dest<0>

R, d Rotate left f through Carry

1

C

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C Æ dest<7>,

RRR

R, d Rotate right f through Carry

R<7:1> Æ dest<6:0>,

R<0> Æ C

1

C

R<3:0> Æ dest<7:4>,

R<7:4> Æ dest<3:0>

SWAPR R, d Swap R

1

-

MOVIA

ADDIA

SUBIA

ANDIA

IORIA

I

Move Immediate to ACC

I Æ ACC

1

-

Add ACC and Immediate

Subtract ACC from Immediate

AND Immediate with ACC

OR Immediate with ACC

I + ACC Æ ACC

I - ACC Æ ACC

ACC and I Æ ACC

ACC or I Æ ACC

ACC xor I Æ ACC

C, DC, Z

Z

XORIA

Exclusive OR Immediate to ACC

I Æ ACC,

Top of Stack Æ PC

RETIA

I

Return, place Immediate in ACC

2

-

BANK

PAGE

I

Move Immediate to memory bank bits I Æ RP<1:0>

Move Immediate to program page bits I Æ PCHBUF<3:2>

PC + 1 Æ Top of Stack,

1

-

CALL

I

Call subroutine

I Æ PC<9:0>

PCHBUF<3:2> Æ PC<11:10>

I Æ PC<9:0>

PCHBUF<3:2> Æ PC<11:10>

PC + 1 Æ Top of Stack,

I Æ PC<11:0>

I<11:10> Æ PCHBUF<3:2>

I Æ PC<11:0>

2

3

-

GOTO

FCALL

FGOTO

Unconditional branch

Call subroutine

Unconditional branch

I<11:10> Æ PCHBUF<3:2>

Note: 1. 2 cycles for skip, else 1 cycle. (3 cycles if skip and followed by a 2-word instruction FCALL/FGOTO)

2. bit : Bit address within an 8-bit register R

R : Register address (00h to 3Fh)

I : Immediate data

ACC : Accumulator

d : Destination select;

=0 (store result in ACC)

=1 (store result in file register R)

dest : Destination

PC : Program Counter

PCHBUF : High Byte Buffer of Program Counter

WDT : Watchdog Timer Counter

GIE : Global interrupt enable bit

TO : Time-out bit

PD : Power-down bit

C : Carry bit

DC : Digital carry bit

Z : Zero bit

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ADCAR

Syntax:

Add ACC and R with Carry

ADCAR R, d

Operands:

0 ≤ R ≤ 63

^d∈[0,1]

Operation:

R + ACC + C Æ dest

Status Affected:

Description:

C, DC, Z

Add the contents of the ACC register and register ‘R’ with Carry. If ‘d’ is 0 the result is stored

in the ACC register. If ‘d’ is ‘1’ the result is stored back in register ‘R’.

1

Cycles:

ADDAR

Syntax:

Add ACC and R

ADDAR R, d

Operands:

0 ≤ R ≤ 63

^d∈[0,1]

Operation:

ACC + R Æ dest

Status Affected:

Description:

C, DC, Z

Add the contents of the ACC register and register ‘R’. If ‘d’ is 0 the result is stored in the ACC

register. If ‘d’ is ‘1’ the result is stored back in register ‘R’.

1

Cycles:

ADDIA

Add ACC and Immediate

Syntax:

ADDIA I

Operands:

Operation:

Status Affected:

Description:

0 ≤ I ≤ 255

ACC + I Æ ACC

C, DC, Z

Add the contents of the ACC register with the 8-bit immediate ‘I’. The result is placed in the

ACC register.

1

Cycles:

ANDAR

Syntax:

AND ACC and R

ANDAR R, d

Operands:

0 ≤ R ≤ 63

^d∈[0,1]

Operation:

ACC and R Æ dest

Status Affected:

Description:

Z

The contents of the ACC register are AND’ed with register ‘R’. If ‘d’ is 0 the result is stored in

the ACC register. If ‘d’ is ‘1’ the result is stored back in register ‘R’.

1

Cycles:

ANDIA

AND Immediate with ACC

Syntax:

ANDIA I

Operands:

Operation:

Status Affected:

Description:

0 ≤ I ≤ 255

ACC AND I Æ ACC

Z

The contents of the ACC register are AND’ed with the 8-bit immediate ‘I’. The result is placed

in the ACC register.

1

Cycles:

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BANK

Move Immediate to memory bank bits

Syntax:

BANK I

Operands:

Operation:

0 ≤ I ≤ 3

I Æ RP<1:0>

Status Affected:

Description:

Cycles:

None

The memory bank bits are loaded with the 2-bit immediate ‘I’.

1

BCR

Clear Bit in R

BCF R, b

0 ≤ R ≤ 63

⁰≤ b ≤ 7

Syntax:

Operands:

Operation:

Status Affected:

Description:

Cycles:

0 Æ R

None

Clear bit ‘b’ in register ‘R’.

1

BSR

Set Bit in R

BSR R, b

0 ≤ R ≤ 63

⁰≤ b ≤ 7

Syntax:

Operands:

Operation:

Status Affected:

Description:

Cycles:

1 Æ R

None

Set bit ‘b’ in register ‘R’.

1

BTRSC

Test Bit in R, Skip if Clear

Syntax:

BTRSC R, b

Operands:

0 ≤ R ≤ 63

⁰≤ b ≤ 7

Operation:

Skip if R = 0

Status Affected:

Description:

None

If bit ‘b’ in register ‘R’ is 0 then the next instruction is skipped.

If bit ‘b’ is 0 then next instruction fetched during the current instruction execution is discarded,

and a NOP is executed instead making this a 2-cycle instruction..

Cycles:

1/2 (3 cycles if skip and followed by a 2-word instruction FCALL/FGOTO)

BTRSS

Test Bit in R, Skip if Set

Syntax:

BTRSS R, b

Operands:

0 ≤ R ≤ 63

⁰≤ b ≤ 7

Operation:

Skip if R = 1

Status Affected:

Description:

None

If bit ‘b’ in register ‘R’ is ‘1’ then the next instruction is skipped.

If bit ‘b’ is ‘1’, then the next instruction fetched during the current instruction execution, is

discarded and a NOP is executed instead, making this a 2-cycle instruction.

1/2 (3 cycles if skip and followed by a 2-word instruction FCALL/FGOTO)

Cycles:

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CALL

Subroutine Call

CALL I

Syntax:

Operands:

Operation:

0 ≤ I ≤ 1023

PC +1 Æ Top of Stack;

I Æ PC<9:0>

PCHBUF<3:2> Æ PC<11:10>

Status Affected:

Description:

None

Subroutine call. First, return address (PC+1) is pushed onto the stack. The 10-bit immediate

address is loaded into PC bits <9:0>. CALL is a two-cycle instruction.

2

Cycles:

CLRA

Clear ACC

Syntax:

CLRA

Operands:

Operation:

None

00h Æ ACC;

1 Æ Z

Status Affected:

Description:

Cycles:

Z

The ACC register is cleared. Zero bit (Z) is set.

1

CLRR

Clear R

Syntax:

CLRR R

Operands:

Operation:

0 ≤ R ≤ 63

00h Æ R;

1 Æ Z

Status Affected:

Description:

Cycles:

Z

The contents of register ‘R’ are cleared and the Z bit is set.

1

CLRWDT

Syntax:

Clear Watchdog Timer

CLRWDT

Operands:

Operation:

None

00h Æ WDT;

00h Æ WDT prescaler (if assigned);

1 Æ TO ;

1 Æ PD

Status Affected:

Description:

TO PD

,

The CLRWDT instruction resets the WDT. It also resets the prescaler, if the prescaler is

assigned to the WDT and not Timer0. Status bits TO and PD are set.

1

Cycles:

COMR

Complement R

Syntax:

COMR R, d

Operands:

0 ≤ R ≤ 63

^d∈[0,1]

Operation:

R Æ dest

Status Affected:

Description:

Z

The contents of register ‘R’ are complemented. If ‘d’ is 0 the result is stored in the ACC

register. If ‘d’ is 1 the result is stored back in register ‘R’.

1

Cycles:

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DAA

Adjust ACC’s data format from HEX to DEC

Syntax:

DAA

Operands:

Operation:

None

ACC(hex) Æ ACC(dec)

Status Affected:

Description:

C

Convert the ACC data from hexadecimal to decimal format after any addition

operation and restored to ACC.

1

Cycles:

DAS

Adjust ACC’s data format from HEX to DEC

Syntax:

DAS

Operands:

Operation:

Status Affected:

Description:

None

ACC(hex) Æ ACC(dec)

None

Convert the ACC data from hexadecimal to decimal format after any subtraction operation

and restored to ACC.

1

Cycles:

DECR

Decrement R

Syntax:

Operands:

DECR R, d

0 ≤ R ≤ 63

^d∈[0,1]

Operation:

R - 1 Æ dest

Status Affected:

Description:

Z

Decrement register ‘R’. If ‘d’ is 0 the result is stored in the ACC register. If ‘d’ is 1 the result is

stored back in register ‘R’.

1

Cycles:

DECRSZ

Syntax:

Decrement R, Skip if 0

DECRSZ R, d

Operands:

0 ≤ R ≤ 63

^d∈[0,1]

Operation:

R - 1 Æ dest; skip if result =0

Status Affected:

Description:

None

The contents of register ‘R’ are decremented. If ‘d’ is 0 the result is placed in the ACC

register. If ‘d’ is 1 the result is placed back in register ’R’.

If the result is 0, the next instruction, which is already fetched, is discarded and a NOP is

executed instead making it a two-cycle instruction.

1/2 (3 cycles if skip and followed by a 2-word instruction FCALL/FGOTO)

Cycles:

FCALL

Subroutine Call

Syntax:

FCALL I

Operands:

Operation:

0 ≤ I ≤ 4095

PC +1 Æ Top of Stack;

I Æ PC<11:0>

I<11:10> Æ PCHBUF<3:2>

Status Affected:

Description:

None

Subroutine call. First, return address (PC+1) is pushed onto the stack. The 12-bit immediate

address is loaded into PC bits <11:0>. FCALL is a two-word (three-cycle) instruction.

3

Cycles:

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FGOTO

Unconditional Branch

FGOTO I

Syntax:

Operands:

Operation:

0 ≤ I ≤ 4095

I Æ PC<11:0>

I<11:10> Æ PCHBUF<3:2>

Status Affected:

Description:

None

FGOTO is an unconditional branch. The 12-bit immediate value is loaded into PC bits

<11:0>. FGOTO is a two-word (three-cycle) instruction.

3

Cycles:

GOTO

Unconditional Branch

Syntax:

GOTO I

Operands:

Operation:

0 ≤ I ≤ 1023

I Æ PC<9:0>

PCHBUF<3:2> Æ PC<11:10>

Status Affected:

Description:

None

GOTO is an unconditional branch. The 10-bit immediate value is loaded into PC bits <9:0>.

GOTO is a two-cycle instruction.

2

Cycles:

INCR

Increment R

Syntax:

Operands:

INCR R, d

0 ≤ R ≤ 63

^d∈[0,1]

Operation:

R + 1 Æ dest

Status Affected:

Description:

Z

The contents of register ‘R’ are incremented. If ‘d’ is 0 the result is placed in the ACC register.

If ‘d’ is 1 the result is placed back in register ‘R’.

1

Cycles:

INCRSZ

Syntax:

Increment R, Skip if 0

INCRSZ R, d

Operands:

0 ≤ R ≤ 63

^d∈[0,1]

Operation:

R + 1 Æ dest, skip if result = 0

Status Affected:

Description:

None

The contents of register ‘R’ are incremented. If ‘d’ is 0 the result is placed in the ACC register.

If ‘d’ is the result is placed back in register ‘R’.

If the result is 0, then the next instruction, which is already fetched, is discarded and a NOP is

executed instead making it a two-cycle instruction.

1/2 (3 cycles if skip and followed by a 2-word instruction FCALL/FGOTO)

Cycles:

INT

S/W Interrupt

Syntax:

Operands:

Operation:

INT

None

PC + 1 Æ Top of Stack,

002h Æ PC

Status Affected:

Description:

None

Interrupt subroutine call. First, return address (PC+1) is pushed onto the stack. The address

002h is loaded into PC bits <10:0>.

2

Cycles:

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IORAR

OR ACC with R

IORAR R, d

0 ≤ R ≤ 63

Syntax:

Operands:

^d∈[0,1]

Operation:

ACC or R Æ dest

Status Affected:

Description:

Z

Inclusive OR the ACC register with register ‘R’. If ‘d’ is 0 the result is placed in the ACC

register. If ‘d’ is 1 the result is placed back in register ‘R’.

1

Cycles:

IORIA

OR Immediate with ACC

Syntax:

IORIA I

Operands:

Operation:

Status Affected:

Description:

0 ≤ I ≤ 255

ACC or I Æ ACC

Z

The contents of the ACC register are OR’ed with the 8-bit immediate ‘I’. The result is placed

in the ACC register.

1

Cycles:

IOST

Load IOST Register

Syntax:

IOST R

Operands:

Operation:

Status Affected:

Description:

Cycles:

R = 5,6 or 7

ACC Æ IOST register R

None

IOST register ‘R’ (R= 5,6 or 7) is loaded with the contents of the ACC register.

1

MOVAR

Move ACC to R

Syntax:

MOVAR R

Operands:

Operation:

Status Affected:

Description:

Cycles:

0 ≤ R ≤ 63

ACC Æ R

None

Move data from the ACC register to register ‘R’.

1

MOVIA

Move Immediate to ACC

Syntax:

MOVIA I

Operands:

Operation:

Status Affected:

Description:

Cycles:

0 ≤ I ≤ 255

I Æ ACC

None

The 8-bit immediate ‘I’ is loaded into the ACC register. The don’t cares will assemble as 0s.

1

MOVR

Move R

Syntax:

MOVR R, d

Operands:

0 ≤ R ≤ 63

^d∈[0,1]

Operation:

R Æ dest

Status Affected:

Description:

Z

The contents of register ‘R’ is moved to destination ‘d’. If ‘d’ is 0, destination is the ACC

register. If ‘d’ is 1, the destination is file register ‘R’. ‘d’ is 1 is useful to test a file register since

status flag Z is affected.

1

Cycles:

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NOP

No Operation

NOP

Syntax:

Operands:

Operation:

None

No operation

Status Affected:

Description:

Cycles:

None

No operation.

1

OPTION

Load OPTION Register

Syntax:

OPTION

Operands:

Operation:

Status Affected:

Description:

Cycles:

None

ACC Æ OPTION

None

The content of the ACC register is loaded into the OPTION register.

1

PAGE

Move Immediate to program page bits

Syntax:

PAGE I

Operands:

Operation:

Status Affected:

Description:

Cycles:

0 ≤ I ≤ 3

I Æ PCHBUF<3:2>

None

The program page bits are loaded with the 2-bit immediate ‘I’.

1

RETFIE

Return from Interrupt, Set ‘GIE’ Bit

Syntax:

RETFIE

Operands:

Operation:

Status Affected:

Description:

None

Top of Stack Æ PC

None

The program counter is loaded from the top of the stack (the return address). The ‘GIE’ bit is

set to 1. This is a two-cycle instruction.

2

Cycles:

RETIA

Return with Immediate in ACC

Syntax:

RETIA I

Operands:

Operation:

0 ≤ I ≤ 255

I Æ ACC;

Top of Stack Æ PC

Status Affected:

Description:

None

The ACC register is loaded with the 8-bit immediate ‘I’. The program counter is loaded from

the top of the stack (the return address). This is a two-cycle instruction.

2

Cycles:

RETURN

Return from Subroutine

Syntax:

RETURN

Operands:

Operation:

Status Affected:

Description:

None

Top of Stack Æ PC

None

The program counter is loaded from the top of the stack (the return address). This is a

two-cycle instruction.

2

Cycles:

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RLR

Rotate Left f through Carry

RLR R, d

Syntax:

Operands:

0 ≤ R ≤ 63

^d∈[0,1]

Operation:

R<7> Æ C;

R<6:0> Æ dest<7:1>;

C Æ dest<0>

Status Affected:

Description:

C

The contents of register ‘R’ are rotated one bit to the left through the Carry Flag. If ‘d’ is 0 the

result is placed in the ACC register. If ‘d’ is 1 the result is stored back in register ‘R’.

1

Cycles:

RRR

Rotate Right f through Carry

Syntax:

Operands:

RRR R, d

0 ≤ R ≤ 63

^d∈[0,1]

Operation:

C Æ dest<7>;

R<7:1> Æ dest<6:0>;

R<0> Æ C

Status Affected:

Description:

C

The contents of register ‘R’ are rotated one bit to the right through the Carry Flag. If ‘d’ is 0 the

result is placed in the ACC register. If ‘d’ is 1 the result is placed back in register ‘R’.

1

Cycles:

SLEEP

Enter SLEEP Mode

SLEEP

Syntax:

Operands:

Operation:

None

00h Æ WDT;

00h Æ WDT prescaler;

1 Æ TO ;

0 Æ PD

Status Affected:

Description:

TO PD

,

Time-out status bit ( TO ) is set. The power-down status bit (PD ) is cleared. The WDT and its

prescaler are cleared.

The processor is put into SLEEP mode.

1

Cycles:

SBCAR

Syntax:

Subtract ACC from R with Carry

SBCAR R, d

Operands:

0 ≤ R ≤ 63

^d∈[0,1]

Operation:

R + ACC + C Æ dest

Status Affected:

Description:

C, DC, Z

Add the 2’s complement data of the ACC register from register ‘R’ with Carry. If ‘d’ is 0 the

result is stored in the ACC register. If ‘d’ is 1 the result is stored back in register ‘R’.

1

Cycles:

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FM8P59

SUBAR

Syntax:

Operands:

Subtract ACC from R

SUBAR R, d

0 ≤ R ≤ 63

^d∈[0,1]

Operation:

R - ACC Æ dest

Status Affected:

Description:

C, DC, Z

Subtract (2’s complement method) the ACC register from register ‘R’. If ‘d’ is 0 the result is

stored in the ACC register. If ‘d’ is 1 the result is stored back in register ‘R’.

1

Cycles:

SUBIA

Subtract ACC from Immediate

Syntax:

SUBIA I

Operands:

Operation:

Status Affected:

Description:

0 ≤ I ≤ 255

I - ACC Æ ACC

C, DC, Z

Subtract (2’s complement method) the ACC register from the 8-bit immediate ‘I’. The result is

placed in the ACC register.

1

Cycles:

SWAPR

Syntax:

Swap nibbles in R

SWAPR R, d

Operands:

0 ≤ R ≤ 63

^d∈[0,1]

Operation:

R<3:0> Æ dest<7:4>;

R<7:4> Æ dest<3:0>

Status Affected:

Description:

None

The upper and lower nibbles of register ‘R’ are exchanged. If ‘d’ is 0 the result is placed in

ACC register. If ‘d’ is 1 the result in placed in register ‘R’.

1

Cycles:

TBL

Table Look-up

Syntax:

TBL

Operands:

Operation:

None

PC<7:0> + ACC Æ PC<7:0>

PC<9:8> unchanged

PCHBUF<3:2> Æ PC<11:10>

C, DC, Z

Operate with RETIA to look-up table

1

Status Affected:

Description:

Cycles:

XORAR

Syntax:

Exclusive OR ACC with R

XORAR R, d

Operands:

0 ≤ R ≤ 63

^d∈[0,1]

Operation:

ACC xor R Æ dest

Status Affected:

Description:

Z

Exclusive OR the contents of the ACC register with register ’R’. If ‘d’ is 0 the result is stored in

the ACC register. If ‘d’ is 1 the result is stored back in register ‘R’.

1

Cycles:

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FM8P59

XORIA

Exclusive OR Immediate with ACC

XORIA I

Syntax:

Operands:

Operation:

0 ≤ I ≤ 255

ACC xor I Æ ACC

Status Affected:

Description:

Z

The contents of the ACC register are XOR’ed with the 8-bit immediate ‘I’. The result is placed

in the ACC register.

1

Cycles:

Rev0.99 Jul 20, 2005

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4.0 ABSOLUTE MAXIMUM RATINGS

FM8P59

Ambient Operating Temperature

Store Temperature

0℃ to +70℃

-65℃ to +150℃

0V to +6.0V

DC Supply Voltage (Vdd)

Input Voltage with respect to Ground (Vss)

-0.3V to (Vdd + 0.3)V

5.0 OPERATING CONDITIONS

DC Supply Voltage

+2.3V to +5.5V

Operating Temperature

0℃ to +70℃

Rev0.99 Jul 20, 2005

P.41/FM8P59

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6.0 ELECTRICAL CHARACTERISTICS

FM8P59

6.1 ELECTRICAL CHARACTERISTICS of FM8P59AE/47BE

Under Operating Conditions, at four clock instruction cycles and WDT & LVDT are disabled

Sym

F_HF

Description

Conditions

HF mode, Vdd=5V

Min.

2

Typ.

Max.

20

Unit

MHz

HF mode, Vdd=3V

XT mode, Vdd=5V

XT mode, Vdd=3V

LF mode, Vdd=5V

LF mode, Vdd=3V

ERC mode, Vdd=5V

ERC mode, Vdd=3V

I/O ports, Vdd=5V

RSTB pin, Vdd=5V

I/O ports, Vdd=5V

RSTB pin, Vdd=5V

I_OH=-5.4mA, Vdd=5V

I_OL=8.7mA, Vdd=5V

Input pin at Vss

1

5

1000

4

MHz

KHZ

MHz

F_XT

F_LF

32

DC

F_ERC

2.2

4.2

V

V_IH

Input high voltage

Input low voltage

1.1

1.0

V

V_IL

V

V_OH

V_OL

I_PH

Output high voltage

Output low voltage

Pull-high current

Pull-down current

3.8

V

0.6

V

-70

50

uA

I_PD

Input pin at Vdd

Vdd=5V

I_WDT

WDT current

Vdd=3V

3

uA

Vdd=5V

I_LVDTLVDT current

Vdd=3V

Sleep mode, Vdd=5V

Sleep mode, Vdd=3V

HF mode: 20MHz, Vdd = 5V

Vdd = 3V

uA

I_SB

Power down current

< 1

mA

uA

XT mode: 4MHz, Vdd = 5V

Vdd = 3V

I_DD

Operating current

LF mode: 32KHz, Vdd = 5V

Vdd = 3V

15

uA

ERC mode: 4MHz, Vdd = 5V

Vdd = 3V

mA

6.2 ELECTRICAL CHARACTERISTICS of FM8P59A/47B

To be defined

Rev0.99 Jul 20, 2005

P.42/FM8P59

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7.0 PACKAGE DIMENSION

FM8P59

7.1 28-PIN PDIP 600mil

D

e

B1

B

Dimension In Millimeters

Dimension In Inches

Symbols

Min

Nom

-

Max

Min

Nom

-

Max

A

A1

A2

B

-

0.38

3.81

-

5.59

-

0.220

-

0.015

0.150

-

3.94

1.52

0.46

37.08

15.24

13.84

2.54

-

4.06

0.155

0.06

0.018

1.460

0.600

0.545

0.100

-

0.160

-

B1

D

-

36.96

-

37.34

1.455

-

1.470

E

-

E1

e

13.72

-

13.97

0.540

-

0.550

-

L

3.18

16.00

0.125

0.630

eB

16.51

17.02

0.650

0.670

Rev0.99 Jul 20, 2005

P.43/FM8P59

FEELING

TECHNOLOGY

FM8P59

7.2 28-PIN Skinny PDIP 300mil

D

C

1.000

PIN 1 INDENT

e

B

B1

B2

Dimension In Millimeters

Dimension In Inches

Symbols

Min

-

Nom

Max

4.57

-

Min

-

Nom

Max

0.180

-

A

A1

A2

B

-

0.38

-

3.30

-

0.015

-

3.56

1.65

0.58

1.12

0.33

35.43

8.38

7.52

-

0.130

0.140

0.065

0.023

0.044

0.013

1.395

0.330

0.296

-

1.02

0.41

0.71

0.20

35.13

7.87

7.26

-

0.0040

0.016

0.028

0.008

1.383

0.310

0.284

-

B1

B2

C

-

0.25

35.18

8.31

7.32

2.54

-

0.010

1.385

0.327

0.288

0.100

-

D

E

E1

e

L

3.18

8.64

-

0.125

0.340

-

eB

-

9.65

-

0.380

Rev0.99 Jul 20, 2005

P.44/FM8P59

FEELING

TECHNOLOGY

FM8P59

7.3 28-PIN SOP 300mil

View “

A

D

View “

A

7^o(4x)

e

D1

B

£

L

Dimension In Millimeters

Dimension In Inches

Symbols

Min

Nom

2.488

-

Max

2.743

-

Min

-

Nom

0.098

-

Max

0.108

-

A

A1

A2

B

-

0.152

2.21

0.006

0.087

0.012

0.008

0.700

0.290

0.048

0.404

0.025

0°

2.336

0.406

0.254

17.91

7.493

1.270

10.42

-

2.464

0.508

0.304

18.42

7.62

1.321

10.57

-

0.091

0.016

0.010

0.705

0.295

0.050

0.410

-

0.097

0.020

0.012

0.725

0.300

0.052

0.416

-

0.305

0.204

17.78

7.366

1.219

10.26

0.635

0°

C

D

E

e

eB

L

θ

4°

8°

4°

8°

D1

0.356

0.508

-

0.014

0.020

-

Rev0.99 Jul 20, 2005

P.45/FM8P59

FEELING

TECHNOLOGY

FM8P59

7.4 28-PIN SSOP 209mil

D

View “

A

C

b

e

R

-H-

GAUGE PLANE

SEATING PLANE

0.10

o

£

L

View “

A

Dimension In Millimeters

Symbols

Min

-

Nom

Max

2.00

-

A

A1

A2

b

-

0.05

1.62

0.22

0.09

9.90

7.40

5.00

1.75

-

1.85

0.38

0.25

10.50

8.20

5.60

10.57

0.95

-

c

-

D

10.20

7.80

5.30

E

E1

e

0.65 BSC

0.55

10.42

0.75

-

L

R

0.09

θ^o

0^o

4^o

8^o

Rev0.99 Jul 20, 2005

P.46/FM8P59

FEELING

TECHNOLOGY

FM8P59

7.5 32-PIN PDIP 600mil

D

H

SEATING PLANE

0.018TYP.

0.100TYP.

0.050TYP.

Dimension In Inchs

Symbols

Min

-

Nom

-

Max

A

A1

A2

D

0.220

-

0.015

0.150

1.645

-

0.155

1.650

0.600BSC

0.545

0.130

0.650

7

0.160

1.660

E

E1

L

0.540

0.115

0.630

0

0.550

0.150

0.670

15

e_B

θ^o

Rev0.99 Jul 20, 2005

P.47/FM8P59

FEELING

TECHNOLOGY

FM8P59

7.6 32-PIN SOP 450mil

D

View “

A

0.016TYP.

0.05TYP.

-H-

Searing Plane

0.004MAX.

X

o

£

View “

A

L

Dimension In Inch

Symbols

Min

-

Max

0.120

0.014

0.815

0.450

0.580

0.050

10^o

A

A1

D

0.004

0.799

0.437

0.530

0.016

0^o

E

H

L

θ^o

Rev0.99 Jul 20, 2005

P.48/FM8P59

FEELING

TECHNOLOGY

8.0 ORDERING INFORMATION

FM8P59

OTP Type MCU

FM8P59AEP

FM8P59AEM

FM8P59AED

FM8P59AER

FM8P59BEP

FM8P59BED

Package Type

PDIP

Pin Count

Package Size

600 mil

28

32

Skinny PDIP

SOP

300 mil

SSOP

209 mil

PDIP

600 mil

SOP

450 mil

Mask Type MCU

FM8P59AP

FM8P59AM

FM8P59AD

FM8P59AR

FM8P59BP

FM8P59BD

Package Type

PDIP

Pin Count

Package Size

600 mil

28

32

Skinny PDIP

SOP

300 mil

SSOP

209 mil

PDIP

600 mil

SOP

450 mil

Rev0.99 Jul 20, 2005

P.49/FM8P59


型号：	FM8P59BP
厂家：	Feeling Technology
描述：	EPROM/ROM-Based 8-Bit Microcontroller 可编程只读存储器电动程控只读存储器微控制器
文件：	总49页 (文件大小：336K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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