FM8PE53B [FEELING]
OTP-Based 8-Bit Microcontroller;
| 型号： | FM8PE53B |
| 厂家： | 
Feeling Technology |
| 描述： | OTP-Based 8-Bit Microcontroller 微控制器 |
| 文件： | 总53页 (文件大小：2258K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EELING
FM8PE53B
OTP-Based 8-Bit Microconer
Devices Included in this Data Sheet:
FM8PE53B : OTP device
FEATURES
Only 42 single word instructions
All instructions are single cycle except for program branches which are two-cycle
13-bit wide instructions
All OTP area GOTO instruction
All OTP area subroutine CALL instruction
8-bit wide data path
5-level deep hardware stack
Operating speed: DC-20 MHz clock input
DC-100 ns instruction cycle
Device
Pins # I/O #
OTP (Word)
RAM (Byte)
FM8PE53B
14 12
1K
49
Direct, indirect addressing modes for data accessing
8-bit real time clock/counter (Timer0) with 8-bit programmable prescaler
Internal Power-on Reset (POR)
Built-in Low Voltage Detector (LVD) for Brown-out Reset (BOR)
Power-up Reset Timer (PWRT) and Oscillator Start-up Timer(OST)
On chip Watchdog Timer (WDT) with internal oscillator for reliable operation and soft-ware watch-dog
enable/disable control
Two I/O ports IOA and IOB with independent direction control
Soft-ware I/O pull-high/pull-down or open-drain control
One internal interrupt source: Timer0 overflow; Two external interrupt source: INT pin, Port B input change
Wake-up from SLEEP by INT pin or Port B input change
Power saving SLEEP mode
Built-in 8MHz, 4MHz, 1MHz, and 455KHz internal RC oscillator
Programmable Code Protection
Selectable oscillator options:
- ERC: External Resistor/Capacitor Oscillator
- HF: High Frequency Crystal/Resonator Oscillator
- XT: Crystal/Resonator Oscillator
- LF: Low Frequency Crystal Oscillator
- IRC: Internal Resistor/Capacitor Oscillator
- ERIC: External Resistor/Internal Capacitor Oscillator
Operating voltage range: 1.8V to 3.5V
This datasheet contains on. Feeling Technology reserves the rights to modify the product specification without notice.
No liability is assumed as a rethis product. No rights under any patent accompany the sales of the product.
Web site: http://www.feeling-teom.tw
Rev1.02.011 Aug 21, 2014
P.1/FM8PE53B
EELING
FM8PE53B
GENERAL DESCRIPTION
The FM8PE53B is a low-cost, high speed, high noise immunity, OTP-based 8-bit CMOS microcontrollers. It
employs a RISC architecture with only 42 instructions. All instructions are single cycle except for program
branches which take two cycles. The easy to use and easy to remember instruction set reduces development
time significantly.
The FM8PE53B consists of Power-on Reset (POR), Brown-out Reset (BOR), Power-up Reset Timer (PWRT),
Oscillator Start-up Timer(OST), Watchdog Timer, OTP, SRAM, tri-state I/O port, I/O pull-high/open-drain/pull-down
control, Power saving SLEEP mode, real time programmable clock/counter, Interrupt, Wake-up from SLEEP
mode, and Code Protection for OTP products. There are three oscillator configurations to choose from, including
the power-saving LF (Low Frequency) oscillator and cost saving RC oscillator.
The FM8PE53B address 1K×13 of program memory.
The FM8PE53B can directly or indirectly address its register files and data memory. All special function registers
including the program counter are mapped in the data memory.
BLOCK DIAGRAM
DATA BUS
Oscillator
Circuit
5-level
STACK
Control
Interrupt
Watchdog
Timer
Program
Counter
FSR
SRAM
PORTA
PORTB
Instruction
Decoder
ALU
OTP-ROM
Interrupt
Control
8-bit Timer0
Accumulator
Web site: http://www.feeling-techcom.tw
Rev1.02.011 Aug 21, 2014
P.2/FM8PE53B
EELING
FM8PE53B
PIN CONNECTION
PDIP, SOP
IOA0
IOB7
1
2
3
4
5
6
7
14 IOA1
13 IOA2
12 IOA3
11 VSS
IOB6
FM8PE53B
VDD
IOB5/OSCI
IOB4/OSCO
IOB3/RSTB
10 IOB0/INT
9
8
IOB1
IOB2/T0CKI
PIN DESCRIPTIONS
Name
I/O
I/O
Description
IOA0 ~ IOA3 as bi-direction I/O pin
Software controlled pull-down
IOA0 ~ IOA3
Bi-direction I/O pin with system wake-up function
IOB0/INT
IOB1
I/O Software controlled pull-high/open-drain/pull-down
External interrupt input
Bi-direction I/O pin with system wake-up function
I/O
Software controlled pull-high/open-drain/pull-down
Bi-direction I/O pin with system wake-up function
I/O Software controlled pull-high/open-drain/pull-down
External clock input to Timer0
IOB2/T0CKI
Input pin or open-drain output pin with system wake-up function
System clear (RESET) input. Active low RESET to the device. Weak pull-high
always on if configured as RSTB.
Voltage on this pin must not exceed VDD, See IOB3 diagram for detail
description.
IOB3/RSTB
IOB4/OSCO
I/O
Bi-direction I/O pin with system wake-up function (RCOUT optional in IRC/ERIC,
ERC mode)
I/O Software controlled pull-high/open-drain
Oscillator crystal output (HF, XT, LF mode)
Outputs with the instruction cycle rate (RCOUT optional in IRC/ERIC, ERC mode)
Bi-direction I/O pin with system wake-up function (IRC mode)
Software controlled pull-high/open-drain
Oscillator crystal input (HF, XT, LF mode)
IOB5/OSCI
I/O
External clock source input (ERIC, ERC mode)
Bi-direction I/O pin with system wake-up function
Software controlled pull-high/open-drain
IOB6 ~ IOB7
I/O
Vdd
Vss
-
-
Positive supply
Ground
Legend: I=input, O=output, I/O=input/output
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P.3/FM8PE53B
EELING
FM8PE53B
1.0 MEMORY ORGANIZATION
FM8PE53B memory is organized into program memory and data memory.
1.1 Program Memory Organization
The FM8PE53B has a 10-bit Program Counter capable of addressing a 1K×13 program memory space.
The RESET vector for the FM8PE53B is at 3FFh.
The H/W interrupt vector is at 008h. And the S/W interrupt vector is at 002h.
FM8PE53B supports all OTP area CALL/GOTO instructions without page.
Figure 1.1: Program Memory Map and STACK
PC<9:0>
Stack 1
Stack 2
Stack 3
Stack 4
Stack 5
3FFh
Reset Vector
:
:
008h H/W Interrupt Vector
002h S/W Interrupt Vector
000h
FM8PE53B
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EELING
FM8PE53B
1.2 Data Memory Organization
Data memory is composed of Special Function Registers and General Purpose Registers.
The General Purpose Registers are accessed either directly or indirectly through the FSR register.
The Special Function Registers are registers used by the CPU and peripheral functions to control the operation of
the device.
Table 1.1: Registers File Map for FM8PE53B
Address
00h
Description
INDF
TMR0
01h
02h
PCL
N/A
OPTION
03h
STATUS
04h
FSR
05h
PORTA
05h
06h
IOSTA
IOSTB
06h
PORTB
07h
General Purpose Register
PCON
08h
09h
WUCON
0Ah
PCHBUF
0Bh
PDCON
0Ch
0Dh
0Eh
ODCON
PHCON
INTEN
0Fh
INTFLAG
General Purpose Registers
10h ~ 3Fh
Table 1.2: The Registers Controlled by OPTION or IOST Instructions
Address
N/A (w)
05h (w)
06h (w)
Name
OPTION
IOSTA
B7
*
B6
B5
B4
B3
B2
B1
B0
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
Port A I/O Control Register
Port B I/O Control Register
IOSTB
Table 1.3: Operational Registers Map
Address
00h (r/w)
01h (r/w)
02h (r/w)
03h (r/w)
04h (r/w)
05h (r/w)
06h (r/w)
07h (r/w)
08h (r/w)
09h (r/w)
0Ah (r/w)
0Bh (r/w)
0Ch (r/w)
0Dh (r/w)
0Eh (r/w)
0Fh (r/w)
Name
INDF
B7
B6
B5
B4
B3
B2
B1
B0
C
Uses contents of FSR to address data memory (not a physical register)
8-bit real-time clock/counter
TMR0
PCL
Low order 8 bits of PC
̅̅̅̅
̅̅̅̅
PD
STATUS
FSR
RST
*
GP1
*
GP0
TO
Z
DC
Indirect data memory address pointer
PORTA
PORTB
SRAM
IOA3
IOB3
IOA2
IOB2
IOA1
IOB1
IOA0
IOB0
IOB7
IOB6
IOB5
IOB4
General Purpose Register
PCON
WDTE
WUB7
-
EIS
WUB6
-
LVDTE
WUB5
-
*
*
*
*
*
WUCON
PCHBUF
PDCON
ODCON
PHCON
INTEN
INTFLAG
WUB4
WUB3
-
WUB2
-
WUB1
WUB0
-
2 MSBs Buffer of PC
/PDB2
ODB6
/PHB6
*
/PDB1
ODB5
/PHB5
*
/PDB0
ODB4
/PHB4
*
/PDA3
/PDA2
ODB2
/PHB2
INTIE
INTIF
/PDA1
ODB1
/PHB1
PBIE
/PDA0
ODB0
/PHB0
T0IE
ODB7
/PHB7
GIE
*
-
-
-
-
-
PBIF
T0IF
Legend: - = unimplemented, read as ‘0’, * = unimplemented, read as ‘1’,
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P.5/FM8PE53B
EELING
FM8PE53B
2.0 FUNCTIONAL DESCRIPTIONS
2.1 Operational Registers
2.1.1
INDF (Indirect Addressing Register)
Address
00h (r/w)
Name
INDF
B7
B6
B5
B4
B3
B2
B1
B0
Uses contents of FSR to address data memory (not a physical register)
The INDF Register is not a physical register. Any instruction accessing the INDF register can actually access the
register pointed by FSR Register. Reading the INDF register itself indirectly (FSR=”0”) will read 00h. Writing to the
INDF register indirectly results in a no-operation (although status bits may be affected).
The bits 5-0 of FSR register are used to select up to 64 registers (address: 00h ~ 3Fh).
Example 2.1: INDIRECT ADDRESSING
Register file 38 contains the value 10h
Register file 39 contains the value 0Ah
Load the value 38 into the FSR Register
A read of the INDF Register will return the value of 10h
Increment the value of the FSR Register by one (@FSR=39h)
A read of the INDF register now will return the value of 0Ah.
Figure 2.1: Direct/Indirect Addressing
Direct Addressing
From opcode
Indirect Addressing
From FSR register 0
5
0
5
00h
location select
addressing INDF register
location select
3Fh
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EELING
FM8PE53B
2.1.2
TMR0 (Time Clock/Counter register)
Address
01h (r/w)
Name
TMR0
B7
B6
B5
B4
B3
B2
B1
B0
8-bit real-time clock/counter
The Timer0 is a 8-bit timer/counter. The clock source of Timer0 can come from the instruction cycle clock or by an
external clock source (T0CKI pin) defined by T0CS bit (OPTION<5>). If T0CKI pin is selected, the Timer0 is
increased by T0CKI signal rising/falling edge (selected by T0SE bit (OPTION<4>)).
The prescaler is assigned to Timer0 by clearing the PSA bit (OPTION<3>). In this case, the prescaler will be
cleared when TMR0 register is written with a value.
2.1.3
PCL (Low Bytes of Program Counter) & Stack
Address
02h (r/w)
Name
PCL
B7
B6
B5
B4
B3
B2
B1
B0
Low order 8 bits of PC
FM8PE53B device has a 10-bit wide Program Counter (PC) and five-level deep 10-bit hardware push/pop stack.
The low byte of PC is called the PCL register. This register is readable and writable. The high byte of PC is called
the PCH register. This register contains the PC<9:8> bits and is not directly readable or writable. All updates to
the PCH register go through the PCHBUF register. As a program instruction is executed, the Program Counter
will contain the address of the next program instruction to be executed. The PC value is increased by one, every
instruction cycle, unless an instruction changes the PC.
For a GOTO instruction, the PC<9:0> is provided by the GOTO instruction word. The PCL register is mapped to
PC<7:0>, and the PCHBUF register is not updated.
For a CALL instruction, the PC<9:0> is provided by the CALL instruction word. The next PC will be loaded
(PUSHed) onto the top of STACK. The PCL register is mapped to PC<7:0>, and the PCHBUF register is not
updated.
For a RETIA, RETFIE, or RETURN instruction, the PC are updated (POPed) from the top of STACK. The PCL
register is mapped to PC<7:0>, and the PCHBUF register is not updated.
For any instruction where the PCL is the destination, the PC<7:0> is provided by the instruction word or ALU
result. However, the PC<9:8> will come from the PCHBUF<1:0> bits (PCHBUF PCH).
PCHBUF register is never updated with the contents of PCH.
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P.7/FM8PE53B
EELING
FM8PE53B
Figure 2.2: Loading of PC in Different Situations
Situation 1: GOTO Instruction
PCH
PCL
9
8
-
7
-
0
PC
Opcode <9:0>
-
-
-
-
PCHBUF
Situation 2: CALL Instruction
STACK<9:0>
Opcode <9:0>
PCH
PCL
9
8
7
-
0
PC
-
-
-
-
-
PCHBUF
Situation 3: RETIA, RETFIE, or RETURN Instruction
PCH PCL
STACK<9:0>
9
8
7
0
PC
-
-
-
-
-
-
PCHBUF
Situation 4: Instruction with PCL as destination
PCH PCL
8
9
7
0
PC
ALU result <7:0>
Or Opcode <7:0>
PCHBUF<1:0>
-
-
-
-
-
-
PCHBUF
Note: PCHBUF is used only for instruction with PCL as destination for FM8PE53B.
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EELING
FM8PE53B
2.1.4
STATUS (Status Register)
Address
03h (r/w)
Name
B7
B6
B5
B4
B3
̅̅̅̅
PD
B2
Z
B1
B0
C
̅̅̅̅
STATUS
RST
GP1
GP0
TO
DC
This register contains the arithmetic status of the ALU, the RESET status.
If the STATUS Register is the destination for an instruction that affects the Z, DC or C bits, then the write to these
̅̅̅̅
̅̅̅̅
three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD
bits are not writable. Therefore, the result of an instruction with the STATUS Register as destination may be
different than intended. For example, CLRR STATUS will clear the upper three bits and set the Z bit. This leaves
the STATUS Register as 000u u1uu (where u = unchanged).
C : Carry/borrow bit.
ADDAR, ADDIA
= 1, Carry occurred.
= 0, No Carry occurred.
SUBAR, SUBIA
= 1, No borrow occurred.
= 0, Borrow occurred.
Note : A subtraction is executed by adding the two’s complement of the second operand. For rotate (RRR,
RLR) instructions, this bit is loaded with either the high or low order bit of the source register.
DC : Half carry/half borrow bit
ADDAR, ADDIA
= 1, Carry from the 4th low order bit of the result occurred.
= 0, No Carry from the 4th low order bit of the result occurred.
SUBAR, SUBIA
= 1, No Borrow from the 4th low order bit of the result occurred.
= 0, Borrow from the 4th low order bit of the result occurred.
Z : Zero bit.
= 1, The result of a logic operation is zero.
= 0, The result of a logic operation is not zero.
̅̅̅̅
PD : Power down flag bit.
= 1, after power-up or by the CLRWDT instruction.
= 0, by the SLEEP instruction.
̅̅̅̅
TO : Time overflow flag bit.
= 1, after power-up or by the CLRWDT or SLEEP instruction
= 0, a watch-dog time overflow occurred
GP1:GP0 : General purpose read/write bits.
RST : Bit for wake-up type.
= 1, Wake-up from SLEEP on Port B input change.
= 0, Wake-up from other reset types.
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P.9/FM8PE53B
EELING
FM8PE53B
2.1.5
FSR (Indirect Data Memory Address Pointer)
Address
04h (r/w)
Name
FSR
B7
*
B6
*
B5
B4
B3
B2
B1
B0
Indirect data memory address pointer
Bit5:Bit0 : Select registers address in the indirect addressing mode. See 2.1.1 for detail description.
Bit7:Bit6 : Not used. Read as “1”s.
2.1.6
PORTA, PORTB (Port Data Registers)
Address
Name
PORTA
PORTB
B7
B6
B5
B4
B3
B2
B1
B0
05h (r/w)
06h (r/w)
IOA3
IOB3
IOA2
IOB2
IOA1
IOB1
IOA0
IOB0
IOB7
IOB6
IOB5
IOB4
Reading the port (PORTA, PORTB register) reads the status of the pins independent of the pin’s input/output
modes. Writing to these ports will write to the port data latch.
PORTA is a 4-bit port data Register. Only the low order 4 bits are used (PORTA<3:0>). Bits 7-4 are general
purpose read/write bits.
IOA3:IOA0 : PORTA I/O pin.
= 1, Port pin is high level.
= 0, Port pin is low level.
IOB7:IOB0 : PORTB I/O pin.
= 1, Port pin is high level.
= 0, Port pin is low level.
Note: IOB3 is open-drain output only if IOSTB3 = 0. See 2.1.17 for detail description.
2.1.7
PCON (Power Control Register)
Address
08h (r/w)
Name
PCON
B7
B6
B5
B4
*
B3
*
B2
*
B1
*
B0
*
WDTE
EIS
LVDTE
Bit4:Bit0 : Not used. Read as “1”s.
LVDTE : LVDT (low voltage detector) enable bit.
= 1, Enable LVDT.
= 0, Disable LVDT.
EIS : Define the function of IOB0/INT pin.
= 1, INT (external interrupt pin) is selected. In this case, the I/O control bit of IOB0 must be set to “1”. The
path of Port B input change of IOB0 pin is masked by hardware, the status of INT pin can also be read
by way of reading PORTB.
= 0, IOB0 (bi-directional I/O pin) is selected. The path of INT is masked.
WDTE : WDT (watch-dog timer) enable bit.
= 1, Enable WDT.
= 0, Disable WDT.
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EELING
FM8PE53B
2.1.8
WUCON (Port B Input Change Interrupt/Wake-up Control Register)
Address
09h (r/w)
Name
B7
B6
B5
B4
B3
B2
B1
B0
WUCON
WUB7
WUB6
WUB5
WUB4
WUB3
WUB2
WUB1
WUB0
WUB0 : = 1, Enable the input change interrupt/wake-up function of IOB0 pin.
= 0, Disable the input change interrupt/wake-up function of IOB0 pin.
WUB1 : = 1, Enable the input change interrupt/wake-up function of IOB1 pin.
= 0, Disable the input change interrupt/wake-up function of IOB1 pin.
WUB2 : = 1, Enable the input change interrupt/wake-up function of IOB2 pin.
= 0, Disable the input change interrupt/wake-up function of IOB2 pin.
WUB3 : = 1, Enable the input change interrupt/wake-up function of IOB3 pin.
= 0, Disable the input change interrupt/wake-up function of IOB3 pin.
WUB4 : = 1, Enable the input change interrupt/wake-up function of IOB4 pin.
= 0, Disable the input change interrupt/wake-up function of IOB4 pin.
WUB5 : = 1, Enable the input change interrupt/wake-up function of IOB5 pin.
= 0, Disable the input change interrupt/wake-up function of IOB5 pin.
WUB6 : = 1, Enable the input change interrupt/wake-up function of IOB6 pin.
= 0, Disable the input change interrupt/wake-up function of IOB6 pin.
WUB7 : = 1, Enable the input change interrupt/wake-up function of IOB7 pin.
= 0, Disable the input change interrupt/wake-up function of IOB7 pin.
2.1.9
PCHBUF (High Byte Buffer of Program Counter)
Address
0Ah (r/w)
Name
B7
-
B6
-
B5
-
B4
-
B3
-
B2
-
B1
B0
PCHBUF
2 MSBs Buffer of PC
Bit1:Bit0 : See 2.1.3 for detail description.
Bit7:Bit2 : Not used. Read as “0”s.
2.1.10 PDCON (Pull-down Control Register)
Address
Name
B7
B6
B5
B4
B3
B2
B1
B0
0Bh (r/w)
PDCON
/PDB2
/PDB1
/PDB0
/PDA3
/PDA2
/PDA1
/PDA0
/PDA0 : = 1, Disable the internal pull-down of IOA0 pin.
= 0, Enable the internal pull-down of IOA0 pin.
/PDA1 : = 1, Disable the internal pull-down of IOA1 pin.
= 0, Enable the internal pull-down of IOA1 pin.
/PDA2 : = 1, Disable the internal pull-down of IOA2 pin.
= 0, Enable the internal pull-down of IOA2 pin.
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EELING
FM8PE53B
/PDA3 : = 1, Disable the internal pull-down of IOA3 pin.
= 0, Enable the internal pull-down of IOA3 pin.
/PDB0 : = 1, Disable the internal pull-down of IOB0 pin.
= 0, Enable the internal pull-down of IOB0 pin.
/PDB1 : = 1, Disable the internal pull-down of IOB1 pin.
= 0, Enable the internal pull-down of IOB1 pin.
/PDB2 : = 1, Disable the internal pull-down of IOB2 pin.
= 0, Enable the internal pull-down of IOB2 pin.
Bit7 : General purpose read/write bit.
2.1.11 ODCON (Open-drain Control Register)
Address
Name
B7
B6
B5
B4
B3
B2
B1
B0
0Ch (r/w)
ODCON
ODB7
ODB6
ODB5
ODB4
ODB2
ODB1
ODB0
ODB0 : = 1, Enable the internal open-drain of IOB0 pin.
= 0, Disable the internal open-drain of IOB0 pin.
ODB1 : = 1, Enable the internal open-drain of IOB1 pin.
= 0, Disable the internal open-drain of IOB1 pin.
ODB2 : = 1, Enable the internal open-drain of IOB2 pin.
= 0, Disable the internal open-drain of IOB2 pin.
Bit3 : General purpose read/write bit.
ODB4 : = 1, Enable the internal open-drain of IOB4 pin.
= 0, Disable the internal open-drain of IOB4 pin.
ODB5 : = 1, Enable the internal open-drain of IOB5 pin.
= 0, Disable the internal open-drain of IOB5 pin.
ODB6 : = 1, Enable the internal open-drain of IOB6 pin.
= 0, Disable the internal open-drain of IOB6 pin.
ODB7 : = 1, Enable the internal open-drain of IOB7 pin.
= 0, Disable the internal open-drain of IOB7 pin.
2.1.12 PHCON (Pull-high Control Register)
Address
Name
B7
B6
B5
B4
B3
B2
B1
B0
0Dh (r/w)
PHCON
/PHB7
/PHB6
/PHB5
/PHB4
/PHB2
/PHB1
/PHB0
/PHB0 : = 1, Disable the internal pull-high of IOB0 pin.
= 0, Enable the internal pull-high of IOB0 pin.
/PHB1 : = 1, Disable the internal pull-high of IOB1 pin.
= 0, Enable the internal pull-high of IOB1 pin.
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/PHB2 : = 1, Disable the internal pull-high of IOB2 pin.
= 0, Enable the internal pull-high of IOB2 pin.
Bit3 : General purpose read/write bit.
/PHB4 : = 1, Disable the internal pull-high of IOB4 pin.
= 0, Enable the internal pull-high of IOB4 pin.
/PHB5 : = 1, Disable the internal pull-high of IOB5 pin.
= 0, Enable the internal pull-high of IOB5 pin.
/PHB6 : = 1, Disable the internal pull-high of IOB6 pin.
= 0, Enable the internal pull-high of IOB6 pin.
/PHB7 : = 1, Disable the internal pull-high of IOB7 pin.
= 0, Enable the internal pull-high of IOB7 pin.
2.1.13 INTEN (Interrupt Mask Register)
Address
Name
B7
B6
*
B5
*
B4
*
B3
*
B2
B1
B0
0Eh (r/w)
INTEN
GIE
INTIE
PBIE
T0IE
T0IE : Timer0 overflow interrupt enable bit.
= 1, Enable the Timer0 overflow interrupt.
= 0, Disable the Timer0 overflow interrupt.
PBIE : Port B input change interrupt enable bit.
= 1, Enable the Port B input change interrupt.
= 0, Disable the Port B input change interrupt.
INTIE : External INT pin interrupt enable bit.
= 1, Enable the External INT pin interrupt.
= 0, Disable the External INT pin interrupt.
Bit6:Bit3 : Not used. Read as “1”s.
GIE : Global interrupt enable bit.
= 1, Enable all un-masked interrupts. For wake-up from SLEEP mode through an interrupt event, the device
will branch to the interrupt address (008h).
= 0, Disable all interrupts. For wake-up from SLEEP mode through an interrupt event, the device will
continue execution at the instruction after the SLEEP instruction.
Note : When an interrupt event occur with the GIE bit and its corresponding interrupt enable bit are all set,
the GIE bit will be cleared by hardware to disable any further interrupts. The RETFIE instruction will
exit the interrupt routine and set the GIE bit to re-enable interrupt.
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2.1.14 INTFLAG (Interrupt Status Register)
Address
0Fh (r/w)
Name
B7
-
B6
-
B5
-
B4
-
B3
-
B2
B1
B0
INTFLAG
INTIF
PBIF
T0IF
T0IF : Timer0 overflow interrupt flag. Set when Timer0 overflows, reset by software.
PBIF : Port B input change interrupt flag. Set when Port B input changes, reset by software.
INTIF : External INT pin interrupt flag. Set by rising/falling (selected by INTEDG bit (OPTION<6>)) edge on INT
pin, reset by software.
Bit7:Bit3 : Not used. Read as “0”s.
2.1.15 ACC (Accumulator)
Address
N/A (r/w)
Name
ACC
B7
B6
B5
B4
B3
B2
B1
B0
Accumulator
Accumulator is an internal data transfer, or instruction operand holding. It cannot be addressed.
2.1.16 OPTION Register
Address
N/A (w)
Name
B7
*
B6
B5
B4
B3
B2
B1
B0
OPTION
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
Accessed by OPTION instruction.
By executing the OPTION instruction, the contents of the ACC Register will be transferred to the OPTION
Register.
The OPTION Register is a 7-bit wide, write-only register which contains various control bits to configure the
Timer0/WDT prescaler, Timer0, and the external INT interrupt.
The OPTION Register are “write-only” and are set all “1”s except INTEDG bit.
PS2:PS0 : Prescaler rate select bits.
PS2:PS0
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Timer0 Rate
1:2
WDT Rate
1:1
1:4
1:8
1:16
1:32
1:64
1:128
1:256
1:2
1:4
1:8
1:16
1:32
1:64
1:128
PSA : Prescaler assign bit.
= 0, TMR0 (Timer0).
= 1, WDT (watch-dog timer).
T0SE : TMR0 source edge select bit.
= 0, Rising edge on T0CKI pin.
= 1, Falling edge on T0CKI pin.
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T0CS : TMR0 clock source select bit.
= 0, internal instruction clock cycle.
= 1, External T0CKI pin. Pin IOB2/T0CKI is forced to be an input even if IOST IOB2 = “0”.
INTEDG : Interrupt edge select bit.
= 0, interrupt on falling edge of INT pin.
= 1, interrupt on rising edge of INT pin.
Bit7 : Not used.
2.1.17 IOSTA & IOSTB (Port I/O Control Registers)
Address
N/A (w)
N/A (w)
Name
IOSTA
IOSTB
B7
B6
B5
B4
B3
IOSTA3 IOSTA2 IOSTA1 IOSTA0
IOSTB7 IOSTB6 IOSTB5 IOSTB4 IOSTB3 IOSTB2 IOSTB1 IOSTB0
B2
B1
B0
Accessed by IOST instruction.
The Port I/O Control Registers are loaded with the contents of the ACC Register by executing the IOST R
(05h~06h) instruction.
The IOST Registers are “write-only” and are set (output drivers disabled) upon RESET.
IOSTA3:IOSTA0 : PORTA I/O control bit.
= 1, PORTA pin configured as an input (tri-stated).
= 0, PORTA pin configured as an output.
IOSTB7:IOSTB0 : PORTB I/O control bit.
= 1, PORTB pin configured as an input (tri-stated).
= 0, PORTB pin configured as an output.
Note: 1. IOB3 is open-drain output only if IOSTB3 = 0.
2. The IOB3 open-drain function will be fixed to “Disable” by H/W if the
configuration bit IOB3OD= Disable, even if bit IOSTB3 = 0.
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2.2 I/O Ports
Port A and port B are bi-directional tri-state I/O ports. Port A is a 4-pin I/O port. Port B is a 8-pin I/O port. Please
note that IOB3 is an input or open-drain output pin.
All I/O pins have data direction control registers (IOSTA, IOSTB) which can configure these pins as output or
input. The exceptions are IOB2 which may be controlled by the T0CS bit (OPTION<5>).
IOB<7:4> and IOB<2:0> have its corresponding pull-high control bits (PHCON register) to enable the weak
internal pull-high. The weak pull-high is automatically turned off when the pin is configured as an output pin.
IOA<3:0> and IOB<2:0> have its corresponding pull-down control bits (PDCON register) to enable the weak
internal pull-down. The weak pull-down is automatically turned off when the pin is configured as an output pin.
IOB<7:4> and IOB<2:0> have its corresponding open-drain control bits (ODCON register) to enable the open-
drain output when these pins are configured to be an output pin.
IOB<7:0> also provides the input change interrupt/wake-up function. Each pin has its corresponding input change
interrupt/wake-up enable bits (WUCON) to select the input change interrupt/wake-up source.
The IOB0 is also an external interrupt input signal by setting the EIS bit (PCON<6>). In this case, IOB0 input
change interrupt/wake-up function will be disabled by hardware even if it is enabled by software.
The CONFIGURATION words can set several I/Os to alternate functions. When acting as alternate functions the
pins will read as “0” during port read.
Figure 2.3: Block Diagram of I/O Pins
IOA3 ~ IOA0:
DATA BUS
D
Q
IOST
Latch
IOST R
EN
Q
Q
I/O PIN
D
DATA
Latch
WR PORT
RD PORT
EN
Q
Pull-down is not shown in the figure
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IOB0/INT:
DATA BUS
D
Q
IOST
Latch
IOST R
EN
Q
Q
I/O PIN
D
DATA
Latch
WR PORT
EN
Q
D
RD PORT
Set PBIF
Q
Q
Latch
WUB0
EIS
EN
INT
INTEDG
EIS
Pull-high/pull-down and open-drain are not shown in the figure
IOB3:
DATA BUS
D
Q
IOST
Latch
IOST R
EN
Q
Q
I/O PIN
D
DATA
Latch
WR PORT
RD PORT
EN
Q
D
RSTBIN
Q
Q
Set PBIF
WUB3
Latch
EN
Voltage on this pin must not exceed VDD.
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IOB7 ~ IOB4, IOB2 ~ IOB1:
DATA BUS
D
Q
IOST
Latch
IOST R
EN
Q
Q
I/O PIN
D
DATA
Latch
WR PORT
RD PORT
EN
Q
D
Q
Q
Set PBIF
WUBn
Latch
EN
Pull-high/pull-down and open-drain are not shown in the figure
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2.3 Timer0/WDT & Prescler
2.3.1
Timer0
The Timer0 is a 8-bit timer/counter. The clock source of Timer0 can come from the internal clock or by an external
clock source (T0CKI pin).
2.3.1.1 Using Timer0 with an Internal Clock: Timer mode
Timer mode is selected by clearing the T0CS bit (OPTION<5>). In timer mode, the timer0 register (TMR0) will
increment every instruction cycle (without prescaler). If TMR0 register is written, the increment is inhibited for the
following two cycles.
2.3.1.2 Using Timer0 with an External Clock: Counter mode
Counter mode is selected by setting the T0CS bit (OPTON<5>). In this mode, Timer0 will increment either on
every rising or falling edge of pin T0CKl. The incrementing edge is determined by the source edge select bit
T0SE (OPTION<4>).
The external clock requirement is due to internal phase clock (TOSC) synchronization. Also, there is a delay in the
actual incrementing of Timer0 after synchronization.
When no prescaler is used, the external clock input is the same as the prescaler output. The synchronization of
T0CKI with the internal phase clocks is accomplished by sampling the prescaler output on the T2 and T4 cycles of
the internal phase clocks. Therefore, it is necessary for T0CKI to be high for at least 2 TOSC and low for at least 2
TOSC
.
When a prescaler is used, the external clock input is divided by the asynchronous prescaler. For the external
clock to meet the sampling requirement, the ripple counter must be taken into account. Therefore, it is necessary
for T0CKI to have a period of at least 4Tosc divided by the prescaler value.
2.3.2
Watchdog Timer (WDT)
The Watchdog Timer (WDT) is a free running on-chip RC oscillator which does not require any external
components. So the WDT will still run even if the clock on the OSCI and OSCO pins is turned off, such as in
SLEEP mode. During normal operation or in SLEEP mode, a WDT time-out will cause the device reset and the
̅̅̅̅
TO bit (STATUS<4>) will be cleared.
The WDT can be disabled by clearing the control bit WDTE (PCON<7>) to “0”.
The WDT has a nominal time-out period of 18ms, 4.5ms, 288ms or 72ms selected by SUT bit of configuration
word (without prescaler). If a longer time-out period is desired, a prescaler with a division ratio of up to 1:128 can
be assigned to the WDT controlled by the OPTION register. Thus, the longest time-out period is approxmately
36.8 seconds.
The CLRWDT instruction clears the WDT and the prescaler, if assigned to the WDT, and prevents it from timing
out and generating a device reset.
The SLEEP instruction resets the WDT and the prescaler, if assigned to the WDT. This gives the maximum
SLEEP time before a WDT Wake-up Reset.
2.3.3
Prescaler
An 8-bit counter (down counter) is available as a prescaler for the Timer0, or as a postscaler for the Watchdog
Timer (WDT). Note that the prescaler may be used by either the Timer0 module or the WDT, but not both. Thus,
a prescaler assignment for the Timer0 means that there is no prescaler for the WDT, and vice-versa.
The PSA bit (OPTION<3>) determines prescaler assignment. The PS<2:0> bits (OPTION<2:0>) determine
prescaler ratio.
When the prescaler is assigned to the Timer0 module, all instructions writing to the TMR0 register will clear the
prescaler. When it is assigned to WDT, a CLRWDT instruction will clear the prescaler along with the WDT.
The prescaler is neither readable nor writable. On a RESET, the prescaler contains all ‘1’s.
To avoid an unintended device reset, CLRWDT or CLRR TMR0 instructions must be executed when changing the
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prescaler assignment from Timer0 to the WDT, and vice-versa.
Figure 2.4: Block Diagram of the Timer0/WDT Prescaler
Instruction Cycle
(Fosc/2, Fosc/4, Fosc/8)
8
0
1
Data Bus
Sync
TMR0
T0SE
2 Cycles
Register
Set T0IF flag
on overflow
1
0
T0CKI (IOB2)
T0CS
PSA
0
1
8-Bit
WDT Time-out
Prescaler
1
0
Watchdog
Timer
PSA
PSA
PS2:PS0
2.4 Interrupts
The FM8PE53B has up to three sources of interrupt:
1. External interrupt INT pin.
2. TMR0 overflow interrupt.
3. Port B input change interrupt (pins IOB7:IOB0).
INTFLAG is the interrupt flag register that recodes the interrupt requests in the relative flags.
A global interrupt enable bit, GIE (INTEN<7>), enables (if set) all un-masked interrupts or disables (if cleared) all
interrupts. Individual interrupts can be enabled/disabled through their corresponding enable bits in INTEN register
regardless of the status of the GIE bit.
When an interrupt event occur with the GIE bit and its corresponding interrupt enable bit are all set, the GIE bit
will be cleared by hardware to disable any further interrupts, and the next instruction will be fetched from address
008h. The interrupt flag bits must be cleared by software before re-enabling GIE bit to avoid recursive interrupts.
The RETFIE instruction exits the interrupt routine and set the GIE bit to re-enable interrupt.
The flag bit (except PBIF bit) in INTFLAG register is set by interrupt event regardless of the status of its mask bit.
Reading the INTFLAG register will be the logic AND of INTFLAG and INTEN.
When an interrupt is generated by the INT instruction, the next instruction will be fetched from address 002h.
2.4.1
External INT Interrupt
External interrupt on INT pin is rising or falling edge triggered selected by INTEDG (OPTION<6>).
When a valid edge appears on the INT pin the flag bit INTIF (INTFLAG<2>) is set. This interrupt can be disabled
by clearing INTIE bit (INTEN<2>).
The INT pin interrupt can wake-up the system from SLEEP condition, if bit INTIE was set before going to SLEEP.
If GIE bit was set, the program will execute interrupt service routine after wake-up; or if GIE bit was cleared, the
program will execute next PC after wake-up.
2.4.2
Timer0 Interrupt
An overflow (FFh 00h) in the TMR0 register will set the flag bit T0IF (INTFLAG<0>). This interrupt can be
disabled by clearing T0IE bit (INTEN<0>).
2.4.3
Port B Input Change Interrupt
An input change on IOB<7:0> set flag bit PBIF (INTFLAG<1>). This interrupt can be disabled by clearing PBIE bit
(INTEN<1>).
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Before the port B input change interrupt is enabled, reading PORTB (any instruction accessed to PORTB,
including read/write instructions) is necessary. Any pin which corresponding WUBn bit (WUCON<7:0>) is cleared
to “0” or configured as output or IOB0 pin configured as INT pin will be excluded from this function.
The port B input change interrupt also can wake-up the system from SLEEP condition, if bit PBIE was set before
going to SLEEP. And GIE bit also decides whether or not the processor branches to the interrupt vector following
wake-up. If GIE bit was set, the program will execute interrupt service routine after wake-up; or if GIE bit was
cleared, the program will execute next PC after wake-up.
2.5 Power-down Mode (SLEEP)
Power-down mode is entered by executing a SLEEP instruction.
̅̅̅̅
̅̅̅̅
When SLEEP instruction is executed, the PD bit (STATUS<3>) is cleared, the TO bit is set, the watchdog timer
will be cleared and keeps running, and the oscillator driver is turned off.
All I/O pins maintain the status they had before the SLEEP instruction was executed.
2.5.1
Wake-up from SLEEP Mode
The device can wake-up from SLEEP mode through one of the following events:
1. RSTB reset.
2. WDT time-out reset (if enabled).
3. Interrupt from RB0/INT pin, or PORTB change interrupt.
External RSTB reset and WDT time-out reset will cause a device reset. The PD and TO bits can be used to
̅̅̅̅
̅̅̅̅
̅̅̅̅
determine the cause of device reset. The PD bit is set on power-up and is cleared when SLEEP instruction is
̅̅̅̅
executed. The TO bit is cleared if a WDT time-out occurred.
For the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be set. Wake-up
is regardless of the GIE bit. If GIE bit is cleared, the device will continue execution at the instruction after the
SLEEP instruction. If the GIE bit is set, the device will branch to the interrupt address (008h).
In HF or LF oscillation mode, the system wake-up delay time is 18/4.5/288/72ms (selected by SUT bit of
configuration word).
And in IRC/ERIC or ERC oscillation mode, the system wake-up delay time is 650us.
2.6 Reset
FM8PE53B devices may be RESET in one of the following ways:
1. Power-on Reset (POR)
2. Brown-out Reset (BOR)
3. RSTB Pin Reset
4. WDT time-out Reset
Some registers are not affected in any RESET condition. Their status is unknown on Power-on Reset and
unchanged in any other RESET. Most other registers are reset to a “reset state” on Power-on Reset, RSTB or
WDT Reset.
A Power-on RESET pulse is generated on-chip when Vdd rise is detected. To use this feature, the user merely
ties the RSTB pin to Vdd.
On-chip Low Voltage Detector (LVD) places the device into reset when Vdd is below a fixed voltage. This ensures
that the device does not continue program execution outside the valid operation Vdd range. Brown-out RESET is
typically used in AC line or heavy loads switched applications.
A RSTB or WDT Wake-up from SLEEP also results in a device RESET, and not a continuation of operation before
SLEEP.
̅̅̅̅
̅̅̅̅
The TO and PD bits (STATUS<4:3>) are set or cleared depending on the different reset conditions.
2.6.1
Power-up Reset Timer (PWRT)
The Power-up Reset Timer provides a nominal 18/4.5/288/72ms (selected by SUT bit of configuration word) (or
650us, varies based on oscillator selection and reset condition) delay after Power-on Reset (POR), Brown-out
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Reset (BOR), RSTB Reset or WDT time-out Reset. The device is kept in reset state as long as the PWRT is
active.
The PWDT delay will vary from device to device due to Vdd, temperature, and process variation.
Table 2.1: PWRT Period
Power-on Reset
Brown-out Reset
RSTB Reset
WDT time-out Reset
Oscillator Mode
ERC & IRC/ERIC 18/4.5/288/72ms or 650us
HF & XT & LF 18/4.5/288/72ms
650 us
18/4.5/288/72ms
2.6.2
Oscillator Start-up Timer (OST)
The OST timer provides a 64 oscillator cycle delay (from OSCI input) after the PWRT delay (18/4.5/288/72ms or
650us) is over. This delay ensures that the X’tal oscillator or resonator has started and stabilized. The device is
kept in reset state as long as the OST is active.
This counter only starts incrementing after the amplitude of the OSCI signal reaches the oscillator input
thresholds.
2.6.3
Reset Sequence
When Power-on Reset (POR), Brown-out Reset (BOR), RSTB Reset or WDT time-out Reset is detected, the
reset sequence is as follows:
1. The reset latch is set and the PWRT & OST are cleared.
2. When the internal POR, BOR, RSTB Reset or WDT time-out Reset pulse is finished, then the PWRT begins
counting.
3. After the PWRT time-out, the OST is activated.
4. And after the OST delay is over, the reset latch will be cleared and thus end the on-chip reset signal.
In HF, XT or LF oscillation mode, the totally system reset delay time is 18/4.5/288/72ms plus 64 oscillator cycle
time.
And in IRC/ERIC or ERC oscillation mode, the totally system reset delay time is 18/4.5/288/72ms or 650us after
Power-on Reset (POR), Brown-out Reset (BOR), or 650us after RSTB Reset or WDT time-out Reset.
Figure 2.5: Simplified Block Diagram of on-chip Reset Circuit
WDT
Time-out
WDT
Module
RSTB
Vdd
S
R
Q
Q
Reset
Latch
Low Voltage
Detector
(LVD)
BOR
CHIP RESET
Power-on
Reset
POR
(POR)
RESET
RESET
On-Chip
RC OSC
Power-up
Reset Timer
(PWRT)
Oscillator
Start-up Timer
(OST)
OSCI
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Table 2.2: Reset Conditions for All Registers
Power-on Reset
Brown-out Reset
RSTB Reset
WDT Reset
Register
Address
ACC
OPTION
N/A
N/A
xxxx xxxx
-011 1111
---- 1111
1111 1111
xxxx xxxx
xxxx xxxx
1111 1111
0001 1xxx
11xx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
101- ----
0000 0000
---- --00
1111 1111
0000 0000
1111 1111
0--- -000
---- -000
xxxx xxxx
uuuu uuuu
-011 1111
---- 1111
1111 1111
uuuu uuuu
uuuu uuuu
1111 1111
000# #uuu
11uu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
101- ----
0000 0000
---- --00
1111 1111
0000 0000
1111 1111
0--- -000
---- -000
uuuu uuuu
IOSTA
N/A
IOSTB
N/A
INDF
00h
TMR0
01h
PCL
02h
STATUS
03h
FSR
04h
PORTA
05h
PORTB
06h
General Purpose Register
PCON
07h
08h
WUCON
PCHBUF
PDCON
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10 ~ 3Fh
ODCON
PHCON
INTEN
INTFLAG
General Purpose Registers
Legend: u = unchanged, x = unknown, - = unimplemented,
# = refer to the following table for possible values.
̅̅̅̅ ̅̅̅̅
Table 2.3: RST / TO / PD Status after Reset or Wake-up
̅̅̅̅
̅̅̅̅
RST
0
TO
PD
RESET was caused by
Power-on Reset
1
1
u
1
0
0
1
1
1
u
0
1
0
0
0
Brown-out reset
0
RSTB Reset during normal operation
RSTB Reset during SLEEP
0
0
WDT Reset during normal operation
WDT Wake-up during SLEEP
Wake-up on pin change during SLEEP
0
1
Legend: u = unchanged
̅̅̅̅ ̅̅̅̅
Table 2.4: Events AffectingTO / PDStatus Bits
̅̅̅̅
̅̅̅̅
PD
Event
TO
Power-on
1
0
1
1
1
u
0
1
WDT Time-Out
SLEEP instruction
CLRWDT instruction
Legend: u = unchanged
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2.7 Hexadecimal Convert to Decimal (HCD)
Decimal format is another number format for FM8PE53B. When the content of the data memory has been
assigned as decimal format, it is necessary to convert the results to decimal format after the execution of ALU
instructions. When the decimal converting operation is processing, all of the operand data (including the contents
of the data memory (RAM), accumulator (ACC), immediate data, and look-up table) should be in the decimal
format, or the results of conversion will be incorrect.
Instruction DAA can convert the ACC data from hexadecimal to decimal format after any addition operation and
restored to ACC.
The conversion operation is illustrated in example 2.2.
Example 2.2: DAA CONVERSION
Address Code
NA
n
#include
<8PE53B.ASH>
…
n+1
n+2
n+3
n+4
MOVIA
MOVAR
MOVIA
ADDAR
0x90
;Set immediate data = decimal format number “90” (ACC 90h)
;Load immediate data “90” to data memory address 30H
;Set immediate data = decimal format number “10” (ACC 10h)
;Contents of the data memory address 30H and ACC are binary-added
;the result loads to the ACC (ACC A0h, C 0)
0x30
0x10
0x30,A
n+5
n+6
DAA
…
;Convert the content of ACC to decimal format, and restored to ACC
;The result in the ACC is “00” and the carry bit C is “1”. This represents the
;decimal number “100”
Instruction DAS can convert the ACC data from hexadecimal to decimal format after any subtraction operation
and restored to ACC.
The conversion operation is illustrated in example 2.3.
Example 2.3: DAS CONVERSION
Address Code
NA
n
#include
<8PE53B.ASH>
…
n+1
n+2
n+3
n+4
MOVIA
MOVAR
MOVIA
SUBAR
0x10
;Set immediate data = decimal format number “10” (ACC 10h)
;Load immediate data “90” to data memory address 30H
;Set immediate data = decimal format number “20” (ACC 20h)
;Contents of the data memory address 30H and ACC are binary-subtracted
;the result loads to the ACC (ACC F0h, C 0)
0x30
0x20
0x30,A
n+5
n+6
DAS
…
;Convert the content of ACC to decimal format, and restored to ACC
;The result in the ACC is “90” and the carry bit C is “0”. This represents the
;decimal number “ -10”
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EELING
FM8PE53B
2.8 Oscillator Configurations
FM8PE53B can be operated in six different oscillator modes. Users can program FOSC configuration bit to select
the appropriate modes:
ERC: External Resistor/Capacitor Oscillator
HF: High Frequency Crystal/Resonator Oscillator
XT: Crystal/Resonator Oscillator
LF: Low Frequency Crystal Oscillator
IRC: Internal Resistor/Capacitor Oscillator
ERIC: External Resistor/Internal Capacitor Oscillator
In LF, XT, or HF modes, a crystal or ceramic resonator in connected to the OSCI and OSCO pins to establish
oscillation. When in LF, XT, or HF modes, the devices can have an external clock source drive the OSCI pin.
The ERC device option offers additional cost savings for timing insensitive applications. The RC oscillator
frequency is a function of the resistor (Rext) and capacitor (Cext), the operating temperature, and the process
parameter.
The IRC/ERIC device option offers largest cost savings for timing insensitive applications. These devices offer 4
different internal RC oscillator frequency, 8 MHz, 4 MHz, 1 MHz, and 455 KHz, which is selected by configuration
bit (Fosc). Or user can change the oscillator frequency with external resistor. The ERIC oscillator frequency is a
function of the resistor (Rext), the operating temperature, and the process parameter.
Figure 2.6: HF, XT or LF Oscillator Modes (Crystal Operation or Ceramic Resonator)
FM8PE53B
C1
OSCI
SLEEP
X`TAL
RS
R1
RF
OSCO
C2
Internal
Circuit
Figure 2.7: HF, XT or LF Oscillator Modes (External Clock Input Operation)
FM8PE53B
OSCI
Clock from
External System
OSCO
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FM8PE53B
Figure 2.8: ERC Oscillator Mode (External RC Oscillator)
FM8PE53B
Rext
OSCI
Internal
Circuit
Cext
/2, /4, /8
OSCO
Figure 2.9: ERIC Oscillator Mode (External R, Internal C Oscillator)
FM8PE53B
Rext
OSCI
Internal
Circuit
Cext
(300pF~0.1uF)
C
/2, /4, /8
OSCO
The typical oscillator frequency vs. external resistor is as following table
Frequency
455KHz
1MHz
Rext @ 3V
850.6K
536.6K
179.1K
95.3K
4MHz
8MHz
16MHz
44.5K
Note: Values are provided for design reference only.
Figure 2.10: IRC Oscillator Mode (Internal R, Internal C Oscillator)
FM8PE53B
OSCI
C
Internal
Circuit
/2, /4, /8
OSCO
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FM8PE53B
2.9 Configuration Words
Table 2.5: Configuration Words
Name
Description
Oscillator Selection Bit
ERC mode (external R & C) (default)
IOB4/OSCO pin controlled by OSCOUT configuration bit
HF mode
XT mode
LF mode
4 MHz IRC mode (internal R & C)
IOB4/OSCO pin controlled by OSCOUT configuration bit
8 MHz IRC mode (internal R & C)
IOB4/OSCO pin controlled by OSCOUT configuration bit
1 MHz IRC mode (internal R & C)
IOB4/OSCO pin controlled by OSCOUT configuration bit
455 KHz IRC mode (internal R & C)
IOB4/OSCO pin controlled by OSCOUT configuration bit
ERIC mode (external R & internal C)
IOB4/OSCO pin controlled by OSCOUT configuration bit
Note: See Table 2.6 for detail description.
Low Voltage Detector Selection Bit
Enable, LVDT voltage = 3.0V (default)
Enable, LVDT voltage = 2.3V
Fosc
Enable, LVDT voltage = 2.6V
LVDT
Enable, LVDT voltage = 2.8V
Enable, LVDT voltage = 2.1V
Enable, LVDT voltage = 2.1V, Controlled by SLEEP
Enable, LVDT voltage = 1.9V
Disable
PWRT & WDT Time Period Selection Bit (The value must be a multiple of prescaler rate)
PWRT = WDT prescaler rate = 18ms (default)
PWRT = WDT prescaler rate = 4.5ms
PWRT = WDT prescaler rate = 288ms
PWRT = WDT prescaler rate = 72ms
PWRT = 650us, WDT prescaler rate = 18ms
PWRT = 650us, WDT prescaler rate = 4.5ms
PWRT = 650us, WDT prescaler rate = 288ms
PWRT = 650us, WDT prescaler rate = 72ms
IOB4/OSCO Pin Selection Bit for IRC/ERIC/ERC Mode
OSCO pin is selected (default)
SUT
OSCOUT
RSTBIN
WDTEN
IOB4 pin is selected
IOB3/RSTB Pin Selection Bit
IOB3 pin is selected (default)
RSTB pin is selected
Watchdog Timer Enable Bit
WDT enabled (default)
WDT disabled
Code Protection Bit
PROTECT OTP code protection off (default)
OTP code protection on
Instruction Period Selection Bit
Four oscillator periods (default)
Two oscillator periods
OSCD
Eight oscillator periods
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FM8PE53B
Name
Description
Power Mode Selection Bit
Non-power saving (default)
Power saving
PMOD
Read Port Control Bit for Output Pins
From registers (default)
From pins
RDPORT
I/O Pin Input Buffer Control Bit
SCHMITT With Schmitt-trigger (default)
Without Schmitt-trigger
IOB3 Pin Open-Drain Output Enable Bit
IOB3OD
Enable open-drain function (IOB3 pin is Bi-direction) (default)
Disable open-drain function (IOB3 pin is Only input)
Table 2.6: Selection of IOB5/OSCI and IOB4/OSCO Pins
Mode of oscillation
IRC
IOB5/OSCI
Force to IOB5
Force to OSCI
Force to OSCI
IOB4/OSCO
IOB4/OSCO selected by OSCOUT bit
ERC, ERIC
HF, XT, LF
IOB4/OSCO selected by OSCOUT bit
Force to OSCO
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FM8PE53B
3.0 INSTRUCTION SET
Mnemonic,
Operands
Status
Affected
Description
Operation
Cycles
BCR
R, bit Clear bit in R
R, bit Set bit in R
0 R<b>
1
1
1/2(1)
1/2(1)
1
-
-
-
-
-
BSR
1 R<b>
BTRSC
BTRSS
NOP
R, bit Test bit in R, Skip if Clear
R, bit Test bit in R, Skip if Set
No Operation
Skip if R<b> = 0
Skip if R<b> = 1
No operation
00h WDT,
00h WDT prescaler
00h WDT,
̅̅̅̅ ̅̅̅̅
CLRWDT
Clear Watchdog Timer
1
TO, PD
̅̅̅̅ ̅̅̅̅
SLEEP
OPTION
DAA
Go into power-down mode
Load OPTION register
1
1
1
TO, PD
00h WDT prescaler
ACC OPTION
-
Adjust ACC’s data format from HEX to
DEC after any addition operation
ACC(hex) ACC (dec)
C
Adjust ACC’s data format from HEX to
DEC after any subtraction operation
DAS
ACC(hex) ACC (dec)
Top of Stack PC
1
2
2
-
-
-
RETURN
RETFIE
Return from subroutine
Top of Stack PC,
1 GIE
Return from interrupt, set GIE bit
PC + 1 Top of Stack
002h PC
INT
S/W interrupt
2
-
IOST
R
Load IOST register
Clear ACC
ACC IOST register
00h ACC
00h R
1
1
1
1
1
1
-
CLRA
CLRR
MOVAR
MOVR
DECR
Z
Z
-
R
R
Clear R
Move ACC to R
ACC R
R, d Move R
R dest
Z
Z
R, d Decrement R
R - 1 dest
R - 1 dest,
Skip if result = 0
DECRSZ
INCR
R, d Decrement R, Skip if 0
R, d Increment R
1/2(1)
1
-
Z
-
R + 1 dest
R + 1 dest,
Skip if result = 0
INCRSZ
R, d Increment R, Skip if 0
1/2(1)
ADDAR
SUBAR
ADCAR
SBCAR
ANDAR
IORAR
XORAR
COMR
R, d Add ACC and R
R + ACC dest
R - ACC dest
1
1
1
1
1
1
1
1
C, DC, Z
R, d Subtract ACC from R
R, d Add ACC and R with Carry
R, d Subtract ACC from R with Carry
R, d AND ACC with R
C, DC, Z
R + ACC + C dest
C, DC, Z
̅̅̅̅̅̅̅
R + ACC + C dest
C, DC, Z
ACC and R dest
ACC or R dest
R xor ACC dest
Z
Z
Z
Z
R, d Inclusive OR ACC with R
R, d Exclusive OR ACC with R
R, d Complement R
ꢀ
R dest
R<7> C,
RLR
R, d Rotate left R through Carry
R<6:0> dest<7:1>,
C dest<0>
1
C
C dest<7>,
RRR
R, d Rotate right R through Carry
R, d Swap R
R<7:1> dest<6:0>,
R<0> C
1
1
C
-
R<3:0> dest<7:4>,
R<7:4> dest<3:0>
SWAPR
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FM8PE53B
Mnemonic,
Operands
Status
Description
Operation
Cycles
Affected
MOVIA
I
I
I
I
I
I
Move Immediate to ACC
I ACC
1
1
1
1
1
1
-
ADDIA
SUBIA
ANDIA
IORIA
Add ACC and Immediate
Subtract ACC from Immediate
AND Immediate with ACC
OR Immediate with ACC
I + ACC ACC
I - ACC ACC
ACC and I ACC
ACC or I ACC
ACC xor I ACC
C, DC, Z
C, DC, Z
Z
Z
Z
XORIA
Exclusive OR Immediate to ACC
I ACC,
RETIA
I
Return, place Immediate in ACC
2
-
Top of Stack PC
PC + 1 Top of Stack,
I PC
CALL
I
I
Call subroutine
2
2
-
-
GOTO
Unconditional branch
I PC
Note: 1. 2 cycles for skip, else 1 cycle.
2. bit :Bit address within an 8-bit register R
R :Register address (00h to 3Fh)
I :Immediate data
ACC :Accumulator
d :Destination select;
=0 (store result in ACC)
=1 (store result in file register R)
dest :Destination
PC :Program Counter
PCH :High Byte register of Program Counter
WDT :Watchdog Timer Counter
GIE :Global interrupt enable bit
̅̅̅̅
TO :Time-out bit
̅̅̅̅
PD :Power-down bit
C :Carry bit
DC :Digital carry bit
Z :Zero bit
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FM8PE53B
ADCAR
Add ACC and R with Carry
Syntax:
ADCAR R, d
Operands:
0
d
R
[0,1]
0x3F
Operation:
R + ACC + C dest
Status Affected:
Description:
C, DC, Z
Add the contents of the ACC register and register ‘R’ with Carry. If ‘d’ is 0 the result is
stored in the ACC register. If ‘d’ is ‘1’ the result is stored back in register ‘R’.
1
Cycles:
ADDAR
Syntax:
Add ACC and R
ADDAR R, d
Operands:
0
d
R
[0,1]
0x3F
Operation:
ACC + R dest
Status Affected:
Description:
C, DC, Z
Add the contents of the ACC register and register ‘R’. If ‘d’ is 0 the result is stored in the
ACC register. If ‘d’ is ‘1’ the result is stored back in register ‘R’.
1
Cycles:
ADDIA
Add ACC and Immediate
Syntax:
ADDIA I
Operands:
Operation:
Status Affected:
Description:
0
I
0xFF
ACC + I ACC
C, DC, Z
Add the contents of the ACC register with the 8-bit immediate ‘I’. The result is placed in the
ACC register.
1
Cycles:
ANDAR
Syntax:
AND ACC and R
ANDAR R, d
Operands:
0
d
R
[0,1]
0x3F
Operation:
ACC and R dest
Status Affected:
Description:
Z
The contents of the ACC register are AND’ed with register ‘R’. If ‘d’ is 0 the result is stored
in the ACC register. If ‘d’ is ‘1’ the result is stored back in register ‘R’.
1
Cycles:
ANDIA
AND Immediate with ACC
Syntax:
ANDIA I
Operands:
Operation:
Status Affected:
Description:
0
I
0xFF
ACC AND I ACC
Z
The contents of the ACC register are AND’ed with the 8-bit immediate ‘I’. The result is
placed in the ACC register.
1
Cycles:
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FM8PE53B
BCR
Clear Bit in R
Syntax:
BCR R, b
Operands:
0
0
R
b
0x3F
7
Operation:
Status Affected:
Description:
Cycles:
0 R<b>
None
Clear bit ‘b’ in register ‘R’.
1
BSR
Set Bit in R
Syntax:
Operands:
BSR R, b
0
0
R
b
0x3F
7
Operation:
Status Affected:
Description:
Cycles:
1 R<b>
None
Set bit ‘b’ in register ‘R’.
1
BTRSC
Test Bit in R, Skip if Clear
Syntax:
BTRSC R, b
Operands:
0
0
R
b
0x3F
7
Operation:
Skip if R<b> = 0
Status Affected:
Description:
None
If bit ‘b’ in register ‘R’ is 0 then the next instruction is skipped.
If bit ‘b’ is 0 then next instruction fetched during the current instruction execution is
discarded, and a NOP is executed instead making this a 2-cycle instruction.
1/2
Cycles:
BTRSS
Test Bit in R, Skip if Set
Syntax:
BTRSS R, b
Operands:
0
0
R
b
0x3F
7
Operation:
Skip if R<b> = 1
Status Affected:
Description:
None
If bit ‘b’ in register ‘R’ is ‘1’ then the next instruction is skipped.
If bit ‘b’ is ‘1’, then the next instruction fetched during the current instruction execution, is
discarded and a NOP is executed instead, making this a 2-cycle instruction.
1/2
Cycles:
CALL
Subroutine Call
Syntax:
CALL I
Operands:
Operation:
0
I
0x3FF
PC +1 Top of Stack;
I PC
Status Affected:
Description:
None
Subroutine call. First, return address (PC+1) is pushed onto the stack. The 10-bit
immediate address is loaded into PC bits <9:0>. CALL is a 2-cycle instruction.
2
Cycles:
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FM8PE53B
CLRA
Clear ACC
Syntax:
CLRA
Operands:
Operation:
None
00h ACC;
1 Z
Status Affected:
Description:
Cycles:
Z
The ACC register is cleared. Zero bit (Z) is set.
1
CLRR
Clear R
Syntax:
CLRR R
Operands:
Operation:
0
R
0x3F
00h R;
1 Z
Status Affected:
Description:
Cycles:
Z
The contents of register ‘R’ are cleared and the Z bit is set.
1
CLRWDT
Syntax:
Clear Watchdog Timer
CLRWDT
Operands:
Operation:
None
00h WDT;
00h WDT prescaler (if assigned);
̅̅̅̅
1 TO;
̅̅̅̅
1 PD
̅̅̅̅ ̅̅̅̅
Status Affected:
Description:
TO, PD
The CLRWDT instruction resets the WDT. It also resets the prescaler, if the prescaler is
̅̅̅̅
̅̅̅̅
assigned to the WDT and not Timer0. Status bits TO and PD are set.
1
Cycles:
COMR
Complement R
Syntax:
COMR R, d
Operands:
0
d
R
[0,1]
0x3F
ꢀ
Operation:
R dest
Status Affected:
Description:
Z
The contents of register ‘R’ are complemented. If ‘d’ is 0 the result is stored in the ACC
register. If ‘d’ is 1 the result is stored back in register ‘R’.
1
Cycles:
DAA
Adjust ACC’s data format from HEX to DEC
Syntax:
DAA
Operands:
Operation:
Status Affected:
Description:
None
ACC(hex) ACC(dec)
C
Convert the ACC data from hexadecimal to decimal format after any addition operation and
restored to ACC.
1
Cycles:
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FM8PE53B
DAS
Adjust ACC’s data format from HEX to DEC
Syntax:
DAS
Operands:
Operation:
Status Affected:
Description:
None
ACC(hex) ACC(dec)
None
Convert the ACC data from hexadecimal to decimal format after any subtraction operation
and restored to ACC.
1
Cycles:
DECR
Decrement R
Syntax:
Operands:
DECR R, d
0
d
R
[0,1]
0x3F
Operation:
R - 1 dest
Status Affected:
Description:
Z
Decrement of register ‘R’. If ‘d’ is 0 the result is stored in the ACC register. If ‘d’ is 1 the
result is stored back in register ‘R’.
1
Cycles:
DECRSZ
Syntax:
Decrement R, Skip if 0
DECRSZ R, d
Operands:
0
d
R
[0,1]
0x3F
Operation:
R - 1 dest; skip if result =0
Status Affected:
Description:
None
The contents of register ‘R’ are decrement. If ‘d’ is 0 the result is placed in the ACC
register. If ‘d’ is 1 the result is stored back in register ’R’.
If the result is 0, the next instruction, which is already fetched, is discarded and a NOP is
executed instead and making it a 2-cycle instruction.
1/2
Cycles:
GOTO
Unconditional Branch
Syntax:
GOTO I
Operands:
Operation:
Status Affected:
Description:
0
I
0x3FF
I PC
None
GOTO is an unconditional branch. The 10-bit immediate value is loaded into PC bits <9:0>.
GOTO is a 2-cycle instruction.
2
Cycles:
INCR
Increment R
Syntax:
Operands:
INCR R, d
0
d
R
[0,1]
0x3F
Operation:
R + 1 dest
Status Affected:
Description:
Z
The contents of register ‘R’ are increment. If ‘d’ is 0 the result is placed in the ACC register.
If ‘d’ is 1 the result is stored back in register ‘R’.
1
Cycles:
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FM8PE53B
INCRSZ
Increment R, Skip if 0
Syntax:
INCRSZ R, d
Operands:
0
d
R
[0,1]
0x3F
Operation:
R + 1 dest, skip if result = 0
Status Affected:
Description:
None
The contents of register ‘R’ are increment. If ‘d’ is 0 the result is placed in the ACC register.
If ‘d’ is the result is stored back in register ‘R’.
If the result is 0, then the next instruction, which is already fetched, is discarded and a NOP
is executed instead and making it a 2-cycle instruction.
1/2
Cycles:
INT
S/W Interrupt
Syntax:
Operands:
Operation:
INT
None
PC + 1 Top of Stack,
002h PC
Status Affected:
Description:
None
Interrupt subroutine call. First, return address (PC+1) is pushed onto the stack. The
address 002h is loaded into PC bits <9:0>.
2
Cycles:
IORAR
OR ACC with R
Syntax:
IORAR R, d
Operands:
0
d
R
[0,1]
0x3F
Operation:
ACC or R dest
Status Affected:
Description:
Z
Inclusive OR the ACC register with register ‘R’. If ‘d’ is 0 the result is placed in the ACC
register. If ‘d’ is 1 the result is placed back in register ‘R’.
1
Cycles:
IORIA
OR Immediate with ACC
Syntax:
IORIA I
Operands:
Operation:
Status Affected:
Description:
0
I
0xFF
ACC or I ACC
Z
The contents of the ACC register are OR’ed with the 8-bit immediate ‘I’. The result is
placed in the ACC register.
1
Cycles:
IOST
Load IOST Register
Syntax:
IOST R
Operands:
Operation:
Status Affected:
Description:
Cycles:
R = 0x05 or 0x06
ACC IOST register R
None
IOST register ‘R’ (R= 0x05 or 0x06) is loaded with the contents of the ACC register.
1
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FM8PE53B
MOVAR
Move ACC to R
Syntax:
MOVAR R
Operands:
Operation:
Status Affected:
Description:
Cycles:
0
R
0x3F
ACC R
None
Move data from the ACC register to register ‘R’.
1
MOVIA
Move Immediate to ACC
Syntax:
MOVIA I
Operands:
Operation:
Status Affected:
Description:
Cycles:
0
I
0xFF
I ACC
None
The 8-bit immediate ‘I’ is loaded into the ACC register. The don’t cares will assemble as 0s.
1
MOVR
Move R
Syntax:
MOVR R, d
Operands:
0
d
R
[0,1]
0x3F
Operation:
R dest
Status Affected:
Description:
Z
The contents of register ‘R’ is moved to destination ‘d’. If ‘d’ is 0, destination is the ACC
register. If ‘d’ is 1, the destination is file register ‘R’. ‘d’ is 1 is useful to test a file register
since status flag Z is affected.
1
Cycles:
NOP
No Operation
NOP
Syntax:
Operands:
Operation:
Status Affected:
Description:
Cycles:
None
No operation
None
No operation.
1
OPTION
Load OPTION Register
Syntax:
OPTION
Operands:
Operation:
Status Affected:
Description:
Cycles:
None
ACC OPTION
None
The content of the ACC register is loaded into the OPTION register.
1
RETFIE
Return from Interrupt, Set ‘GIE’ Bit
Syntax:
RETFIE
Operands:
Operation:
None
Top of Stack PC
1 GIE
Status Affected:
Description:
None
The program counter is loaded from the top of the stack (the return address). The ‘GIE’ bit
is set to 1. This is a 2-cycle instruction.
2
Cycles:
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RETIA
Return with Immediate in ACC
Syntax:
RETIA I
Operands:
Operation:
0
I
0xFF
I ACC;
Top of Stack PC
None
Status Affected:
Description:
The ACC register is loaded with the 8-bit immediate ‘I’. The program counter is loaded from
the top of the stack (the return address). This is a 2-cycle instruction.
2
Cycles:
RETURN
Return from Subroutine
Syntax:
RETURN
Operands:
Operation:
Status Affected:
Description:
None
Top of Stack PC
None
The program counter is loaded from the top of the stack (the return address). This is a two-
cycle instruction.
2
Cycles:
RLR
Rotate Left R through Carry
Syntax:
Operands:
RLR R, d
0
d
R
[0,1]
0x3F
Operation:
R<7> C;
R<6:0> dest<7:1>;
C dest<0>
Status Affected:
Description:
C
The contents of register ‘R’ are rotated left one bit to the left through the Carry Flag. If ‘d’ is
0 the result is placed in the ACC register. If ‘d’ is 1 the result is stored back in register ‘R’.
1
Cycles:
RRR
Rotate Right R through Carry
Syntax:
Operands:
RRR R, d
0
d
R
[0,1]
0x3F
Operation:
C dest<7>;
R<7:1> dest<6:0>;
R<0> C
Status Affected:
Description:
C
The contents of register ‘R’ are rotated one bit to the right through the Carry Flag. If ‘d’ is 0
the result is placed in the ACC register. If ‘d’ is 1 the result is placed back in register ‘R’.
1
Cycles:
Web site: http://www.feeling-techcom.tw
Rev1.02.011 Aug 21, 2014
P.37/FM8PE53B
EELING
FM8PE53B
SLEEP
Enter SLEEP Mode
Syntax:
SLEEP
Operands:
Operation:
None
00h WDT;
00h WDT prescaler;
̅̅̅̅
1 TO;
̅̅̅̅
0 PD
̅̅̅̅ ̅̅̅̅
Status Affected:
Description:
TO,PD
̅̅̅̅
̅̅̅̅
Time-out status bit (TO) is set. The power-down status bit (PD) is cleared. The WDT and its
prescaler cleared.
The processor is put into SLEEP mode.
1
Cycles:
SBCAR
Syntax:
Subtract ACC from R with Carry
SBCAR R, d
Operands:
0
d
R
[0,1]
̅̅̅̅̅̅̅
0x3F
Operation:
R + ACC + C dest
Status Affected:
Description:
C, DC, Z
Add the 2’s complement data of the ACC register from register ‘R’ with Carry. If ‘d’ is 0 the
result is stored in the ACC register. If ‘d’ is 1 the result is stored back in register ‘R’.
1
Cycles:
SUBAR
Syntax:
Subtract ACC from R
SUBAR R, d
Operands:
0
d
R
[0,1]
0x3F
Operation:
R - ACC dest
Status Affected:
Description:
C, DC, Z
Subtract (2’s complement method) the ACC register from register ‘R’. If ‘d’ is 0 the result is
stored in the ACC register. If ‘d’ is 1 the result is stored back in register ‘R’.
1
Cycles:
SUBIA
Subtract ACC from Immediate
Syntax:
SUBIA I
Operands:
Operation:
Status Affected:
Description:
0
I
0xFF
I - ACC ACC
C, DC, Z
Subtract (2’s complement method) the ACC register from the 8-bit immediate ‘I’. The result
is placed in the ACC register.
1
Cycles:
SWAPR
Syntax:
Swap nibbles in R
SWAPR R, d
Operands:
0
d
R
[0,1]
0x3F
Operation:
R<3:0> dest<7:4>;
R<7:4> dest<3:0>
Status Affected:
Description:
None
The upper and lower nibbles of register ‘R’ are exchanged. If ‘d’ is 0 the result is placed in
ACC register. If ‘d’ is 1 the result in placed in register ‘R’.
1
Cycles:
Web site: http://www.feeling-techcom.tw
Rev1.02.011 Aug 21, 2014
P.38/FM8PE53B
EELING
FM8PE53B
XORAR
Exclusive OR ACC with R
Syntax:
XORAR R, d
Operands:
0x3F
d0R[0,1]
Operation:
ACC xor R dest
Status Affected:
Description:
Z
Exclusive OR the contents of the ACC register with register ’R’. If ‘d’ is 0 the result is stored
in the ACC register. If ‘d’ is 1 the result is stored back in register ‘R’.
1
Cycles:
XORIA
Exclusive OR Immediate with ACC
Syntax:
XORIA I
Operands:
Operation:
Status Affected:
Description:
0
I
0xFF
ACC xor I ACC
Z
The contents of the ACC register are XOR’ed with the 8-bit immediate ‘I’. The result is
placed in the ACC register.
1
Cycles:
Web site: http://www.feeling-techcom.tw
Rev1.02.011 Aug 21, 2014
P.39/FM8PE53B
EELING
FM8PE53B
4.0 ABSOLUTE MAXIMUM RATINGS
Ambient Operating Temperature
Store Temperature
0℃ to +70℃
-65℃ to +150℃
0V to +4.0V
DC Supply Voltage (Vdd)
Input Voltage with respect to Ground (Vss)
-0.3V to (Vdd + 0.3)V
5.0 OPERATING CONDITIONS
DC Supply Voltage
+1.8V to +3.5V
Operating Temperature
0℃ to +70℃
Web site: http://www.feeling-techcom.tw
Rev1.02.011 Aug 21, 2014
P.40/FM8PE53B
EELING
FM8PE53B
6.0 ELECTRICAL CHARACTERISTICS
6.1 ELECTRICAL CHARACTERISTICS of FM8PE53B
Ta=25℃
Under Operating Conditions, at four clock instruction cycles and WDT & LVDT are disabled
Sym
FHF
FXT
FLF
Description
Conditions
Min.
4
Typ.
Max.
20
Unit
MHz
MHz
KHz
MHz
X’tal oscillation range HF mode, Vdd=3V
X’tal oscillation range XT mode, Vdd=3V
X’tal oscillation range LF mode, Vdd=3V
0.455
32
20
455
16
FERC RC oscillation range ERC mode, Vdd=3V
ERIC mode, external R, Vdd=3V
DC
DC
16
FIRC/ERIC RC oscillation range
MHz
IRC mode, internal R, Vdd=3V
With Schmitt-trigger
0.455
8
I/O ports, Vdd=3V
1.7
1.7
VDD
VDD
RSTB, T0CKI pins, Vdd=3V
Without Schmitt-trigger
I/O ports, Vdd=3V
VIH
Input high voltage
V
1.5
1.5
VDD
VDD
RSTB, T0CKI pins, Vdd=3V
With Schmitt-trigger
I/O ports, Vdd=3V
VSS
VSS
0.8
0.8
RSTB, T0CKI pins, Vdd=3V
Without Schmitt-trigger
I/O ports, Vdd=3V
VIL
Input low voltage
V
VSS
VSS
2.6
0.9
0.9
RSTB, T0CKI pins, Vdd=3V
IOH=-2.5mA, Vdd=3.3V
IOL=8.7mA, Vdd=3.3V
Input pin at Vss, Vdd=3.3V
Input pin at Vdd, Vdd=3.3V
VOH
VOL
IPH
Output high voltage
Output low voltage
Pull-high current
Pull-down current
V
0.6
-30
25
V
-10
7
-21
12
uA
uA
uA
IPD
IWDT
WDT current (18mS) Vdd=3.3V
Vdd=3V
1.2
20.2
17.5
2
TWDT WDT period (18mS)
mS
Vdd=4V
Vdd=3.3V LVDT = 2.8V
Vdd=3V LVDT = 2.6V ~ 1.8V
ILVDT
ISB
LVDT current
uA
uA
1.5
0.1
Power down current Sleep mode, Vdd=3V
0.3
HF mode, Vdd=3V, 4 clock instruction, OSCI / OSCO =20pF / 20pF
20MHz
16MHz
1.73
1.45
IDD
Operating current
mA
mA
HF mode, Vdd=3V, 2 clock instruction, OSCI / OSCO =20pF / 20pF
20MHz
16MHz
2.2
1.88
XT mode, Vdd=3V, 4 clock instruction, OSCI / OSCO =20pF / 20pF
20MHz
16MHz
8MHz
1.06
0.91
0.64
0.51
0.42
IDD
Operating current
4MHz
455KHz
Web site: http://www.feeling-techcom.tw
Rev1.02.011 Aug 21, 2014
P.41/FM8PE53B
EELING
FM8PE53B
Sym
Description
Conditions
Min.
Typ.
Max.
Unit
XT mode, Vdd=3V, 2 clock instruction, OSCI / OSCO =20pF / 20pF
20MHz
16MHz
8MHz
1.5
1.34
0.81
0.59
0.44
IDD
Operating current
mA
4MHz
455KHz
LF mode, Vdd=3V, 4 clock instruction, OSCI / OSCO =20pF / 20pF
455KHz
32KHz
300
284
IDD
IDD
IDD
Operating current
Operating current
Operating current
uA
mA
mA
LF mode, Vdd=3V, 2 clock instruction, OSCI / OSCO =20pF / 20pF
455KHz
311.5
287.5
32KHz
ERC mode, Vdd=3V, 4 clock instruction
R=1Kohm
F=16.1MHz
F=11.3MHz
3.15
1.54
C=3P
R=3.3Kohm
ERC mode, Vdd=3V, 2 clock instruction
R=1Kohm
F=16.2MHz
F=11.7MHz
3.78
2.12
C=3P
R=3.3Kohm
ERIC mode, external R, Vdd=3V, 4 clock instruction
R=95.3Kohm
R=179.1Kohm
0.81
0.56
F=8MHz
F=4MHz
ERIC mode, external R, Vdd=3V, 2 clock instruction
R=95.3Kohm
R=179.1Kohm
1.17
0.74
F=8MHz
F=4MHz
IRC mode, internal R, Vdd=3V, 4 clock instruction
F=8MHz
0.82
0.59
0.41
0.38
F=4MHz
F=1MHz
F=455KHz
IDD
Operating current
mA
IRC mode, internal R, Vdd=3V, 2 clock instruction
F=8MHz
F=4MHz
F=1MHz
F=455KHz
1.24
0.77
0.45
0.39
Web site: http://www.feeling-techcom.tw
Rev1.02.011 Aug 21, 2014
P.42/FM8PE53B
EELING
FM8PE53B
6.2 ELECTRICAL CHARACTERISTICS Charts of FM8PE53B
6.2.1
6.2.2
6.2.3
Internal 4 MHz RC vs. Supply Voltage (Ta=25℃)
3.00%
2.00%
1.00%
0.00%
4M LV
1.8 1.9
2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 4
-1.00%
-2.00%
-3.00%
Voltage
Note: Curves are for design reference only.
Internal 8 MHz RC vs. Supply Voltage (Ta=25℃)
2.50%
1.50%
0.50%
8M LV
-0.50%
-1.50%
-2.50%
-3.50%
1.8 1.9
2
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9
3
3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9
4
Voltage
Note: Curves are for design reference only.
Internal 1 MHz RC vs. Supply Voltage (Ta=25℃)
3.00%
2.00%
1.00%
0.00%
1M LV
1.8 1.9
2
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9
3
3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9
4
-1.00%
-2.00%
-3.00%
Voltage
Note: Curves are for design reference only.
Web site: http://www.feeling-techcom.tw
Rev1.02.011 Aug 21, 2014
P.43/FM8PE53B
EELING
FM8PE53B
6.2.4
Internal 455 KHz RC vs. Supply Voltage (Ta=25℃)
3.00%
2.00%
1.00%
0.00%
455K LV
1.8 1.9
2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 4
-1.00%
-2.00%
-3.00%
Voltage
Note: Curves are for design reference only.
Internal 4 MHz RC vs. Temperature
6.2.5
3.00%
2.00%
1.00%
0.00%
-40 -30 -20 -10
0
10 20 25 30 40 50 60 70 80 90 100 110 120 125
Avg-3V
-1.00%
-2.00%
-3.00%
Temperature
Note: Curves are for design reference only.
Internal 8 MHz RC vs. Temperature
6.2.6
3.00%
2.00%
1.00%
0.00%
-40 -30 -20 -10
0
10 20 25 30 40 50 60 70 80 90 100 110 120 125
Avg-3V
-1.00%
-2.00%
-3.00%
Temperature
Note: Curves are for design reference only.
Web site: http://www.feeling-techcom.tw
Rev1.02.011 Aug 21, 2014
P.44/FM8PE53B
EELING
FM8PE53B
6.2.7
6.2.8
6.2.9
Internal 1 MHz RC vs. Temperature
3.00%
2.00%
1.00%
0.00%
Avg-3V
-40 -30 -20 -10
0
10 20 25 30 40 50 60 70 80 90 100 110 120 125
-1.00%
-2.00%
-3.00%
Temperature
Note: Curves are for design reference only.
Internal 455 KHz RC vs. Temperature
3.00%
2.00%
1.00%
0.00%
Avg-3V
10 20 25 30 40 50 60 70 80 90 100 110 120 125
-40 -30 -20 -10
0
-1.00%
-2.00%
-3.00%
Temperature
Note: Curves are for design reference only.
WDT 18mS Reset time vs. Temperature
35.00
30.00
25.00
20.00
15.00
10.00
5.00
Avg-3V
0.00
-40 -30 -20 -10
0
10 20 25 30 40 50 60 70 80 90 100 110 120 125
Temperature
Note: Curves are for design reference only.
Web site: http://www.feeling-techcom.tw
Rev1.02.011 Aug 21, 2014
P.45/FM8PE53B
EELING
FM8PE53B
6.2.10 WDT 4.5mS Reset time vs. Temperature
9.00
8.00
7.00
6.00
5.00
4.00
3.00
2.00
1.00
0.00
Avg-3V
-40 -30 -20 -10
0
10 20 25 30 40 50 60 70 80 90 100 110 120 125
Temperature
Note: Curves are for design reference only.
6.2.11 WDT 72mS Reset time vs. Temperature
140.00
120.00
100.00
80.00
60.00
40.00
20.00
0.00
Avg-3V
-40 -30 -20 -10
0
10 20 25 30 40 50 60 70 80 90 100 110 120 125
Temperature
Note: Curves are for design reference only.
6.2.12 WDT 288mS Reset time vs. Temperature
600.00
500.00
400.00
300.00
200.00
100.00
0.00
Avg-3V
-40 -30 -20 -10
0
10 20 25 30 40 50 60 70 80 90 100 110 120 125
Temperature
Note: Curves are for design reference only.
Web site: http://www.feeling-techcom.tw
Rev1.02.011 Aug 21, 2014
P.46/FM8PE53B
EELING
FM8PE53B
6.2.13 WDT 18mS Reset time vs. Supply Voltage (Ta=25℃)
40.00
35.00
30.00
25.00
20.00
15.00
10.00
5.00
Avg-18mS
0.00
1.8 1.9
2
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9
Voltage
3
3
3
3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 4
Note: Curves are for design reference only.
6.2.14 WDT 4.5mS Reset time vs. Supply Voltage (Ta=25℃)
10.00
8.00
6.00
4.00
2.00
0.00
Avg-4.5mS
1.8 1.9
2
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9
Voltage
3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9
4
Note: Curves are for design reference only.
6.2.15 WDT 72mS Reset time vs. Supply Voltage (Ta=25℃)
160.00
140.00
120.00
100.00
80.00
60.00
40.00
20.00
0.00
Avg-72mS
1.8 1.9
2
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9
Voltage
3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9
4
Note: Curves are for design reference only.
Web site: http://www.feeling-techcom.tw
Rev1.02.011 Aug 21, 2014
P.47/FM8PE53B
EELING
FM8PE53B
6.2.16 WDT 288mS Reset time vs. Supply Voltage (Ta=25℃)
700.00
600.00
500.00
400.00
300.00
200.00
100.00
0.00
Avg-288mS
1.8 1.9
2
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9
Voltage
3 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 4
Note: Curves are for design reference only.
6.2.17 LVDT 2.0V vs. Temperature
3.00
2.50
2.00
1.50
1.00
0.50
0.00
Avg-2.0V
-40 -30 -20 -10
0
10 20 25 30 40 50 60 70 80 90 100 110 120 125
Temperature
Note: Curves are for design reference only.
6.2.18 LVDT 2.8V vs. Temperature
4.00
3.50
3.00
2.50
2.00
1.50
1.00
0.50
0.00
Avg-2.8V
-40 -30 -20 -10
0
10 20 25 30 40 50 60 70 80 90 100 110 120 125
Temperature
Note: Curves are for design reference only.
Web site: http://www.feeling-techcom.tw
Rev1.02.011 Aug 21, 2014
P.48/FM8PE53B
EELING
FM8PE53B
6.2.19 LVDT 1.8V vs. Temperature
2.50
2.00
1.50
1.00
0.50
0.00
Avg-1.8V
-40 -30 -20 -10
0
10 20 25 30 40 50 60 70 80 90 100 110 120 125
Temperature
Note: Curves are for design reference only.
6.2.20 LVDT 2.2V vs. Temperature
3.00
2.50
2.00
1.50
1.00
0.50
0.00
Avg-2.2V
-40 -30 -20 -10
0
10 20 25 30 40 50 60 70 80 90 100 110 120 125
Temperature
Note: Curves are for design reference only.
6.2.21 LVDT 2.4V vs. Temperature
3.50
3.00
2.50
2.00
1.50
1.00
0.50
0.00
Avg-2.4V
-40 -30 -20 -10
0
10 20 25 30 40 50 60 70 80 90 100 110 120 125
Temperature
Note: Curves are for design reference only.
Web site: http://www.feeling-techcom.tw
Rev1.02.011 Aug 21, 2014
P.49/FM8PE53B
EELING
FM8PE53B
6.2.22 LVDT 2.6V vs. Temperature
3.50
3.00
2.50
2.00
1.50
1.00
0.50
0.00
Avg-2.6V
-40 -30 -20 -10
0
10 20 25 30 40 50 60 70 80 90 100 110 120 125
Temperature
Note: Curves are for design reference only.
Web site: http://www.feeling-techcom.tw
Rev1.02.011 Aug 21, 2014
P.50/FM8PE53B
EELING
FM8PE53B
7.0 PACKAGE DIMENSION
7.1 14-PIN PDIP 300mil
D
14
8
7
1
0.100typ.
0.018typ.
0.060typ.
Dimension In Inches
Symbols
Min
-
Nom
-
Max
0.210
-
A
A1
A2
D
0.015
0.125
0.735
-
0.130
0.750
0.300 BSC.
0.250
0.130
0.355
7o
0.135
0.775
E
E1
L
0.245
0.115
0.335
0o
0.255
0.150
0.375
15o
eB
θo
Web site: http://www.feeling-techcom.tw
Rev1.02.011 Aug 21, 2014
P.51/FM8PE53B
EELING
FM8PE53B
7.2 14-PIN SOP 150mil
14
8
o
5
4
x
5
1
0
.
0
1
7
“
A
C
D
e
0.004max
B
GAUGE PLANE
SEATING PLANE
o
£
L
DETAIL : A
Dimension In Inches
Symbols
Min
Nom
0.064
-
Max
0.068
0.010
0.020
0.0098
0.344
0.157
-
A
A1
B
0.058
0.004
0.013
0.016
0.008
0.341
0.154
0.050
0.236
0.025
-
C
D
E
0.0075
0.336
0.150
-
e
H
L
θo
0.228
0.015
0o
0.244
0.050
8o
Web site: http://www.feeling-techcom.tw
Rev1.02.011 Aug 21, 2014
P.52/FM8PE53B
EELING
FM8PE53B
8.0 PACKAGE IR Re-flow Soldering Curve
250 5
10 1 sec
150 10
90 30 sec
2 ~ 5 / sec
2 ~ 5 / sec
Time
9.0 ORDERING INFORMATION
OTP Type MCU
FM8PE53BP
FM8PE53BD
Package Type
Pin Count
Package Size
300 mil
PDIP
SOP
14
14
150 mil
Web site: http://www.feeling-techcom.tw
Rev1.02.011 Aug 21, 2014
P.53/FM8PE53B
相关型号：
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