AOD4186 [FREESCALE]
N-Channel Enhancement Mode Field; N沟道增强型场
| 型号： | AOD4186 |
| 厂家： | 
Freescale |
| 描述： | N-Channel Enhancement Mode Field |
| 文件： | 总6页 (文件大小：471K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
AOD4186
N-Channel Enhancement Mode Field
Effect Transistor
General Description
The AOD4186 combines advanced trench MOSFET
technology with a low resistance package to provide
extremely low RDS(ON). This device is ideal for low voltage inverter applications.
Features
VDS (V) =40V
(VGS = 10V)
(VGS = 10V)
(VGS = 4.5V)
ID = 35A
RDS(ON) < 15mΩ
DS(ON) < 19mΩ
R
D
G
S
Absolute Maximum Ratings TA=25°C unless otherwise noted
Parameter
Symbol
Maximum
Units
VDS
Drain-Source Voltage
40
V
VGS
ID
IDM
IDSM
Gate-Source Voltage
Continuous Drain
Current G
±20
V
A
TC=25°C
35
TC=100°C
27
Pulsed Drain Current C
70
TA=25°C
TA=70°C
10
Continuous Drain
Current
Avalanche Current C
Repetitive avalanche energy L=0.1mH C
A
8
24
IAR
A
EAR
29
mJ
TC=25°C
Power Dissipation B
TC=100°C
50
PD
W
25
TA=25°C
2.5
PDSM
W
Power Dissipation A
TA=70°C
1.6
TJ, TSTG
Junction and Storage Temperature Range
-55 to 175
°C
Thermal Characteristics
Parameter
Symbol
Typ
16.7
40
Max
25
50
3
Units
°C/W
°C/W
°C/W
Maximum Junction-to-Ambient A
t ≤ 10s
RθJA
Maximum Junction-to-Ambient A D
Maximum Junction-to-Case
Steady-State
Steady-State
RθJC
2.5
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AOD4186
N-Channel Enhancement Mode Field
Effect Transistor
Electrical Characteristics (TJ=25°C unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
STATIC PARAMETERS
BVDSS
Drain-Source Breakdown Voltage
ID=250µA, VGS=0V
40
V
VDS=40V, VGS=0V
1
5
IDSS
Zero Gate Voltage Drain Current
µA
TJ=55°C
IGSS
Gate-Body leakage current
Gate Threshold Voltage
On state drain current
V
DS=0V, VGS= ±20V
VDS=VGS ID=250µA
GS=10V, VDS=5V
100
2.7
nA
V
VGS(th)
ID(ON)
1.7
2.2
V
100
A
VGS=10V, ID=20A
12.4
20
15
24
19
mΩ
mΩ
RDS(ON)
TJ=125°C
Static Drain-Source On-Resistance
VGS=4.5V, ID=15A
VDS=5V, ID=20A
IS=1A,VGS=0V
14.5
60
gFS
VSD
IS
Forward Transconductance
Diode Forward Voltage
S
V
A
0.75
1
Maximum Body-Diode Continuous Current
60
DYNAMIC PARAMETERS
Ciss
Coss
Crss
Rg
Input Capacitance
780
90
980
130
80
1200
170
110
5.7
pF
pF
pF
Ω
VGS=0V, VDS=20V, f=1MHz
Output Capacitance
Reverse Transfer Capacitance
Gate resistance
48
VGS=0V, VDS=0V, f=1MHz
1.9
3.8
SWITCHING PARAMETERS
Qg(10V)
Total Gate Charge
Total Gate Charge
Gate Source Charge
Gate Drain Charge
Turn-On DelayTime
Turn-On Rise Time
Turn-Off DelayTime
Turn-Off Fall Time
13.5
7
17
9
20
11
3
nC
nC
nC
nC
ns
Qg(4.5V)
Qgs
Qgd
tD(on)
tr
VGS=10V, VDS=20V, ID=20A
2
2.5
4.5
6
2.7
6.3
12
26
7
ns
VGS=10V, VDS=20V, RL=1.0Ω,
RGEN=3Ω
tD(off)
tf
ns
ns
trr
IF=20A, dI/dt=500A/µs
IF=20A, dI/dt=500A/µs
9
12
31
Body Diode Reverse Recovery Time
Body Diode Reverse Recovery Charge
15
38
ns
Qrr
24
nC
2
A. The value of RθJA is measured with the device mounted on 1in FR-4 board with 2oz. Copper, in a still air environment with T =25°C. The Power
A
dissipation PDSM is based on R θJA and the maximum allowed junction temperature of 150°C. The value in any given application depends on the
user's specific board design, and the maximum temperature of 175°C may be used if the PCB allows it.
B. The power dissipation PD is based on TJ(MAX)=175°C, using junction-to-case thermal resistance, and is more useful in setting the upper dissipation
limit for cases where additional heatsinking is used.
C. Repetitive rating, pulse width limited by junction temperature TJ(MAX)=175°C. Ratings are based on low frequency and duty cycles to keep initial T
J
=25°C.
D. The RθJA is the sum of the thermal impedence from junction to case RθJC and case to ambient.
E. The static characteristics in Figures 1 to 6 are obtained using <300µs pulses, duty cycle 0.5% max.
F. These curves are based on the junction-to-case thermal impedence which is measured with the device mounted to a large heatsink, assuming a
maximum junction temperature of TJ(MAX)=175°C. The SOA curve provides a single pulse rating.
G. The maximum current rating is limited by bond-wires.
2
H. These tests are performed with the device mounted on 1 in FR-4 board with 2oz. Copper, in a still air environment with T =25°C.
A
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AOD4186
N-Channel Enhancement Mode Field
Effect Transistor
TYPICAL ELECTRICAL AND THERMAL CHARACTERISTICS
80
60
40
20
0
80
60
40
20
0
6V
10V
VDS=5V
4.5V
4V
125°C
25°C
VGS=3.5V
4
0
1
2
3
4
5
6
0
1
2
3
5
VGS(Volts)
VDS (Volts)
Figure 2: Transfer Characteristics (Note E)
Fig 1: On-Region Characteristics (Note E)
20
2
18
16
14
12
10
8
1.8
1.6
1.4
1.2
1
VGS=10V
ID=20A
VGS=4.5V
VGS=10V
VGS=4.5V
ID=15A
0.8
0
25
50
75
100 125 150 175 200
0
5
10
15
20
25
30
I
D (A)
Temperature (°C)
Figure 3: On-Resistance vs. Drain Current and
Gate Voltage (Note E)
Figure 4: On-Resistance vs. Junction Temperature
(Note E)
40
35
30
25
20
15
10
1.0E+02
1.0E+01
ID=20A
1.0E+00
125°C
1.0E-01
1.0E-02
1.0E-03
1.0E-04
1.0E-05
125°C
25°C
25°C
0.0
0.2
0.4
0.6
VSD (Volts)
Figure 6: Body-Diode Characteristics (Note E)
0.8
1.0
1.2
2
4
6
8
10
V
GS (Volts)
Figure 5: On-Resistance vs. Gate-Source Voltage
(Note E)
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AOD4186
N-Channel Enhancement Mode Field
Effect Transistor
TYPICAL ELECTRICAL AND THERMAL CHARACTERISTICS
10
1500
1200
900
600
300
0
VDS=20V
ID=20A
8
Ciss
6
4
Coss
2
Crss
0
0
5
10
Qg (nC)
15
20
0
10
20
DS (Volts)
30
40
V
Figure 7: Gate-Charge Characteristics
Figure 8: Capacitance Characteristics
200
160
120
80
100.0
10.0
1.0
10µs
RDS(ON)
TJ(Max)=175°C
100µs
TC=25°C
DC
1ms
10ms
TJ(Max)=175°C
TC=25°C
40
0.1
0
0.01
0.1
1
10
100
0.0001
0.001
0.01
0.1
1
10
VDS (Volts)
Pulse Width (s)
Figure 9: Maximum Forward Biased Safe
Operating Area (Note F)
Figure 10: Single Pulse Power Rating Junction-to-
Case (Note F)
10
1
In descending order
D=0.5, 0.3, 0.1, 0.05, 0.02, 0.01, single pulse
D=Ton/T
TJ,PK=TC+PDM.ZθJC.RθJC
RθJC=3°C/W
PD
0.1
Single Pulse
Ton
T
0.01
0.00001
0.0001
0.001
0.01
Pulse Width (s)
Figure 11: Normalized Maximum Transient Thermal Impedance (Note F)
0.1
1
10
100
4/6
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AOD4186
N-Channel Enhancement Mode Field
Effect Transistor
TYPICAL ELECTRICAL AND THERMAL CHARACTERISTICS
100
60
50
40
30
20
10
0
TA=25°C
TA=100°C
TA=125°C
TA=150°C
10
0.000001
0
25
50
75
100
125
150
175
0.00001
0.0001
0.001
Time in avalanche, tA (s)
TCASE (°C)
Figure 12: Single Pulse Avalanche capability (Note
C)
Figure 13: Power De-rating (Note F)
10000
1000
100
10
60
50
40
30
20
10
0
TA=25°C
1
0.00001
0.001
0.1
10
1000
0
25
50
75
100
125
150
175
T
CASE (°C)
Pulse Width (s)
Figure 15: Single Pulse Power Rating Junction-to-
Ambient (Note H)
Figure 14: Current De-rating (Note F)
10
1
In descending order
D=0.5, 0.3, 0.1, 0.05, 0.02, 0.01, single pulse
D=Ton/T
TJ,PK=TA+PDM.ZθJA.RθJA
RθJA=50°C/W
0.1
0.01
Single Pulse
PD
Ton
T
0.001
0.00001
0.0001
0.001
0.01
0.1
1
10
100
1000
Pulse Width (s)
Figure 16: Normalized Maximum Transient Thermal Impedance (Note H)
5/6
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AOD4186
N-Channel Enhancement Mode Field
Effect Transistor
Gate Charge Test Circuit & Waveform
Vgs
Qg
10V
+
VDC
+
Qgs
Qgd
Vds
VDC
-
-
DUT
Vgs
Ig
Charge
Resistive Switching Test Circuit & Waveforms
RL
Vds
Vds
90%
10%
+
DUT
Vdd
Vgs
VDC
Rg
-
Vgs
Vgs
td(on)
t
r
td(off)
t
f
ton
toff
Unclamped Inductive Switching (UIS) Test Circuit & Waveforms
L
EAR= 1/2 LIA2R
BVDSS
Vds
Id
Vgs
Vds
+
Vgs
Vdd
I AR
VDC
Id
Rg
-
DUT
Vgs
Vgs
Diode Recovery Test Circuit & Waveforms
Q rr = - Idt
Vds +
Vds -
Ig
DUT
Vgs
trr
L
Isd
I F
Isd
Vgs
dI/dt
I RM
+
Vdd
VDC
Vdd
-
Vds
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