AOL1712 [FREESCALE]

N-Channel Enhancement Mode Field; N沟道增强型场
AOL1712
型号: AOL1712
厂家: Freescale    Freescale
描述:

N-Channel Enhancement Mode Field
N沟道增强型场

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中文:  中文翻译
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AOL1712  
N-Channel Enhancement Mode Field  
Effect Transistor  
General Description  
SRFET TM AOL1712 uses advanced trench technology with a monolithically integrated Schottky  
diode to provide excellent RDS(ON),and low gate charge. This device is suitable for use as a low side  
FET in SMPS, load switching and general purpose applications.  
Features  
VDS (V) = 30V  
ID =65A  
(VGS = 10V)  
RDS(ON) < 4.2m(VGS = 10V)  
RDS(ON) < 5.5m(VGS = 4.5V)  
Ultra SO-8TM Top View  
D
D
SRFET TM  
Soft Recovery MOSFET:  
Integrated Schottky Diode  
Bottom tab  
connected to  
drain  
G
S
S
G
Absolute Maximum Ratings TC=25°C unless otherwise noted  
Parameter  
Symbol  
Maximum  
Units  
Drain-Source Voltage  
VDS  
30  
V
Gate-Source Voltage  
VGS  
±12  
65  
V
A
TC=25°C  
Continuous Drain  
Current B, H  
Pulsed Drain Current C  
TC=100°C  
ID  
65  
80  
IDM  
TA=25°C  
TA=70°C  
16  
Continuous Drain  
Current A  
Avalanche Current C  
A
IDSM  
IAR  
12  
38  
A
Repetitive avalanche energy L=0.3mH C  
EAR  
217  
100  
50  
mJ  
TC=25°C  
Power Dissipation B  
TC=100°C  
PD  
W
TA=25°C  
2.1  
PDSM  
W
Power Dissipation A  
1.3  
TA=70°C  
Junction and Storage Temperature Range TJ, TSTG  
-55 to 175  
°C  
Thermal Characteristics  
Parameter  
Symbol  
Typ  
19.6  
50  
Max  
25  
Units  
°C/W  
°C/W  
°C/W  
Maximum Junction-to-Ambient A  
t ≤ 10s  
RθJA  
Maximum Junction-to-Ambient A  
Steady-State  
Maximum Junction-to-Case D  
60  
Steady-State  
RθJC  
1
1.5  
1/6  
www.freescale.net.cn  
AOL1712  
N-Channel Enhancement Mode Field  
Effect Transistor  
Electrical Characteristics (TJ=25°C unless otherwise noted)  
Symbol  
Parameter  
Conditions  
Min  
Typ  
Max Units  
STATIC PARAMETERS  
ID=250µA, VGS=0V  
BVDSS  
Drain-Source Breakdown Voltage  
30  
V
V
DS=30V, VGS=0V  
0.1  
mA  
20  
IDSS  
Zero Gate Voltage Drain Current  
TJ=125°C  
TJ=125°C  
V
DS=0V, VGS= ±12V  
IGSS  
Gate-Body leakage current  
Gate Threshold Voltage  
On state drain current  
±100  
2.5  
nA  
V
VGS(th)  
ID(ON)  
VDS=VGS ID=250µA  
1.4  
80  
1.8  
VGS=10V, VDS=5V  
A
V
GS=10V, ID=20A  
3.5  
5.5  
4.4  
90  
4.2  
6.6  
5.5  
RDS(ON)  
Static Drain-Source On-Resistance  
mΩ  
V
GS=4.5V, ID=20A  
VDS=5V, ID=20A  
IS=1A,VGS=0V  
Maximum Body-Diode + Schottky Diode Continuous Current H  
gFS  
VSD  
IS  
Forward Transconductance  
Diode Forward Voltage  
S
V
A
0.36  
0.5  
65  
DYNAMIC PARAMETERS  
Ciss  
Coss  
Crss  
Rg  
Input Capacitance  
3940 5120  
pF  
pF  
pF  
VGS=0V, VDS=15V, f=1MHz  
Output Capacitance  
Reverse Transfer Capacitance  
Gate resistance  
590  
255  
VGS=0V, VDS=0V, f=1MHz  
0.72  
1.1  
95  
SWITCHING PARAMETERS  
Qg(10V) Total Gate Charge  
Qg(4.5V) Total Gate Charge  
73  
35  
nC  
nC  
nC  
nC  
ns  
VGS=10V, VDS=15V, ID=20A  
Qgs  
Qgd  
tD(on)  
tr  
Gate Source Charge  
Gate Drain Charge  
Turn-On DelayTime  
Turn-On Rise Time  
Turn-Off DelayTime  
Turn-Off Fall Time  
10.4  
12.4  
9.8  
8.4  
45  
VGS=10V, VDS=15V, RL=0.75,  
RGEN=3Ω  
ns  
tD(off)  
tf  
ns  
ns  
10  
trr  
IF=20A, dI/dt=300A/µs  
IF=20A, dI/dt=300A/µs  
36  
43  
Body Diode Reverse Recovery Time  
Body Diode Reverse Recovery Charge  
ns  
Qrr  
32  
nC  
A: The value of RθJA is measured with the device in a still air environment with T A=25°C. The power dissipation PDSM and current rating IDSM are  
based on TJ(MAX)=150°C, using steady state junction-to-ambient thermal resistance.  
B. The power dissipation PD is based on TJ(MAX)=175°C, using junction-to-case thermal resistance, and is more useful in setting the upper  
dissipation limit for cases where additional heatsinking is used.  
C: Repetitive rating, pulse width limited by junction temperature T J(MAX)=175°C.  
D. The RθJA is the sum of the thermal impedence from junction to case R θJC and case to ambient.  
E. The static characteristics in Figures 1 to 6 are obtained using <300us pulses, duty cycle 0.5% max.  
F. These curves are based on the junction-to-case thermal impedence which is measured with the device mounted to a large heatsink,  
assuming a maximum junction temperature of TJ(MAX)=175°C. The SOA curve provides a single pulse rating.  
G. These tests are performed with the device mounted on 1 in 2 FR-4 board with 2oz. Copper, in a still air environment with T A=25°C.  
H. The maximum current rating is limited by bond-wires.  
* This device is guaranteed green after date code 8P11 (June 1 ST 2008)  
Rev3: July. 2008  
2/6  
www.freescale.net.cn  
AOL1712  
N-Channel Enhancement Mode Field  
Effect Transistor  
TYPICAL ELECTRICAL AND THERMAL CHARACTERISTICS  
80  
60  
40  
20  
0
100  
VDS=5V  
10V  
4.5V  
3.5V  
80  
60  
40  
20  
0
VGS=3.0V  
125°C  
25°C  
0
0.5  
1
1.5  
2
2.5  
3
1
1.5  
2
2.5  
VGS(Volts)  
Figure 2: Transfer Characteristics  
3
3.5  
4
V
DS (Volts)  
Figure 1: On-Region Characteristics  
5
1.9  
1.7  
1.5  
1.3  
1.1  
0.9  
0.7  
ID=20A  
VGS=10V  
VGS=4.5V  
4.5  
4
VGS=4.5V  
VGS=10V  
3.5  
3
0
5
10  
15  
20  
25  
30  
-40 -15 10 35  
60 85 110 135 160 185  
I
D (A)  
Temperature (°C)  
Figure 4: On-Resistance vs. Junction  
Temperature  
Figure 3: On-Resistance vs. Drain Current and  
Gate Voltage  
12  
100  
10  
ID=20A  
10  
8
125°C  
1
125°C  
25°C  
6
0.1  
25°C  
4
0.01  
0.001  
2
2
4
6
8
10  
0.0  
0.2  
0.4  
SD (Volts)  
Figure 6: Body-Diode Characteristics  
0.6  
0.8  
1.0  
V
V
GS (Volts)  
Figure 5: On-Resistance vs. Gate-Source Voltage  
3/6  
www.freescale.net.cn  
AOL1712  
N-Channel Enhancement Mode Field  
Effect Transistor  
TYPICAL ELECTRICAL AND THERMAL CHARACTERISTICS  
10  
8
6000  
VDS=15V  
ID=20A  
5000  
Ciss  
4000  
3000  
6
4
2000  
Coss  
2
Crss  
1000  
0
0
0
10  
20  
30  
40  
50  
60  
70  
80  
0
5
10  
15  
20  
25  
30  
Qg (nC)  
V
DS (Volts)  
Figure 7: Gate-Charge Characteristics  
Figure 8: Capacitance Characteristics  
100.0  
10.0  
1.0  
10000  
1000  
100  
TJ(Max)=175°C  
TC=25°C  
100µs  
1ms  
RDS(ON)  
10ms  
limited  
100ms  
DC  
TJ(Max)=175°C  
TC=25°C  
10  
0.1  
1
10  
10
0.0001  
0.001  
0.01  
0.1  
1
Pulse Width (s)  
VDS (Volts)  
Figure 10: Single Pulse Power Rating Junction-to-  
Case (Note F)  
Figure 9: Maximum Forward Biased Safe  
Operating Area (Note F)  
10  
1
In descending order  
D=0.5, 0.3, 0.1, 0.05, 0.02, 0.01, single pulse  
D=Ton/T  
TJ,PK=TC+PDM.ZθJc.RθJc  
RθJC=1.5°C/W  
PD  
0.1  
Single Pulse  
Ton  
T
0.01  
0.00001  
0.0001  
0.001  
0.01  
Pulse Width (s)  
Figure 11: Normalized Maximum Transient Thermal Impedance (Note F)  
0.1  
1
10  
100  
4/6  
www.freescale.net.cn  
AOL1712  
N-Channel Enhancement Mode Field  
Effect Transistor  
TYPICAL ELECTRICAL AND THERMAL CHARACTERISTICS  
100  
120  
100  
80  
60  
40  
20  
0
80  
TC=25°C  
60  
40  
20  
0
25  
50  
75  
100  
125  
150  
175  
1.0E-06  
1.0E-05  
Time in avalanche, tA (s)  
Figure 12: Single Pulse Avalanche capability  
1.0E-04  
1.0E-03  
TCASE (°C)  
Figure 13: Power De-rating (Note B)  
80  
60  
40  
20  
0
100  
80  
60  
40  
20  
0
TJ(Max)=150°C  
TA=25°C  
0
25  
50  
75  
TCASE (°C)  
Figure 14: Current De-rating (Note B)  
100  
125  
150  
175  
0.001  
0.01  
0.1  
1
10  
100  
1000  
Pulse Width (s)  
Figure15: Single Pulse Power Rating Junction-to-  
Ambient (Note G)  
10  
1
D=Ton/T  
In descending order  
D=0.5, 0.3, 0.1, 0.05, 0.02, 0.01, single pulse  
TJ,PK=TC+PDM.ZθJc.RθJc  
RθJA=60°C/W  
0.1  
0.01  
PD  
D=Ton/T  
Single Pulse  
TJ,PK=TA+PDM.ZθJA.RθJA  
RθJA=60°C/W  
Ton  
T
0.001  
0.00001  
0.0001  
0.001  
0.01  
0.1  
1
10  
100  
1000  
Pulse Width (s)  
Figure 16: Normalized Maximum Transient Thermal Impedance (Note G)  
5/6  
www.freescale.net.cn  
AOL1712  
N-Channel Enhancement Mode Field  
Effect Transistor  
Gate Charge Test Circuit &Waveform  
Vgs  
Qg  
10V  
+
VDC  
+
Qgs  
Qgd  
Vds  
VDC  
-
-
DUT  
Vgs  
Vds  
Ig  
Charge  
Resistive Switching Test Circuit & Waveforms  
RL  
Vds  
90%  
10%  
+
DUT  
Vdd  
Vgs  
VDC  
Rg  
-
Vgs  
Vgs  
t d(on)  
t
r
t d(off)  
t
f
t on  
toff  
Unclamped Inductive Switching (UIS) Test Circuit & Waveforms  
L
2
EAR=1/2LI  
AR  
BVDSS  
Vds  
Id  
Vds  
+
Vgs  
Vdd  
IAR  
Vgs  
VDC  
Id  
Rg  
-
DUT  
Vgs  
Vgs  
Diode RecoveryTest Circuit &Waveforms  
Qrr=- Idt  
Vds +  
Vds -  
Ig  
DUT  
Vgs  
Isd  
trr  
L
IF  
Isd  
dI/dt  
+
IRM  
Vdd  
Vgs  
VDC  
Vdd  
-
Vds  
6/6  
www.freescale.net.cn  

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