DSP56307/D [FREESCALE]
24-BIT DIGITAL SIGNAL PROCESSOR; 24位数字信号处理器型号: | DSP56307/D |
厂家: | Freescale |
描述: | 24-BIT DIGITAL SIGNAL PROCESSOR |
文件: | 总64页 (文件大小:1130K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
DSP56374
Rev. 4.2, 1/2007
Freescale Semiconductor
Data Sheet: Technical Data
DSP56374 Data Sheet
Table of Contents
1 Overview
The DSP56374 is a high-density CMOS device with
3.3 V inputs and outputs.
1
2
3
4
5
6
7
8
9
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Signal Groupings . . . . . . . . . . . . . . . . . . . . . . . . . 5
Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . 25
Power Requirements . . . . . . . . . . . . . . . . . . . . . 26
Thermal Characteristics . . . . . . . . . . . . . . . . . . . 27
DC Electrical Characteristics . . . . . . . . . . . . . . . 28
AC Electrical Characteristics. . . . . . . . . . . . . . . . 29
NOTE
This document contains information on a
new product. Specifications and
information herein are subject to change
without notice.
10 Internal Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . 29
11 External Clock Operation . . . . . . . . . . . . . . . . . . 29
12 Reset, Stop, Mode Select, and Interrupt Timing. 32
13 Serial Host Interface SPI Protocol Timing. . . . . . 35
14 Serial Host Interface (SHI) I2C Protocol Timing . 41
15 Programming the Serial Clock . . . . . . . . . . . . . . 43
16 Enhanced Serial Audio Interface Timing. . . . . . . 44
17 Timer Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
18 GPIO Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
19 JTAG Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
20 Watchdog Timer Timing . . . . . . . . . . . . . . . . . . . 53
For software or simulation models (for
example, IBIS files), contact sales or go
to www.freescale.com.
The DSP56374 supports digital audio applications
requiring sound field processing, acoustic equalization,
and other digital audio algorithms. The DSP56374 uses
the high performance, single-clock-per-cycle DSP56300
core family of programmable CMOS digital signal
processors (DSPs) combined with the audio signal
processing capability of the Freescale Semiconductor,
Inc. Symphony™ DSP family, as shown in Figure 1.
Significant architectural enhancements include a barrel
shifter, 24-bit addressing, and direct memory access
© Freescale Semiconductor, Inc., 2004, 2005, 2006, 2007. All rights reserved.
Overview
(DMA). The DSP56374 offers 150 million instructions per second (MIPS) using an internal 150 MHz
clock.
Data Sheet Conventions
This data sheet uses the following conventions:
Used to indicate a signal that is active when pulled low (For example,
the RESET pin is active when low.)
OVERBAR
“asserted” Means that a high true (active high) signal is high or that a low true
(active low) signal is low
“deasserted” Means that a high true (active high) signal is low or that a low true
(active low) signal is high
Examples:
Signal/
Symbol
Logic State
Signal State
Voltage*
PIN
PIN
PIN
PIN
True
False
True
Asserted
Deasserted
Asserted
VIL / VOL
VIH / VOH
VIH / VOH
VIL / VOL
False
Deasserted
Note: *Values for V , V , V , and V are defined by individual product specifications.
IL OL
IH
OH
DSP56374 Data Sheet, Rev. 4.2
2
Freescale Semiconductor
Features
15*
12*
3
12
5
Memory Expansion Area
Watch
dog
Timer
GPIO
ESAI_1
Interface
Triple
Timer
SHI
Interface
ESAI
Interface
X Data
RAM
Y Data
RAM
Program
RAM
6k
× 24
6k
× 24
6k
× 24
ROM
20k 24
ROM
4k 24
ROM
4k 24
×
×
×
Peripheral
Expansion Area
YAB
XAB
PAB
DAB
Address
Generation
Unit
Six Channel
DMA Unit
24-Bit
Bootstrap
ROM
DSP56300
Core
DDB
YDB
XDB
PDB
GDB
Internal
Data
Bus
Switch
Power
Mgmt.
Clock
Gen.
4
Data ALU
Program
Interrupt
Controller
Program
Decode
Controller
Program
Address
Generator
JTAG
OnCE
PLL
+ →
× 24 56 56-bit MAC
Two 56-bit Accumulators
24
56-bit Barrel Shifter
XTAL
MODA/IRQA/GPIO
MODB/IRQB/GPIO
MODC/IRQC/GPIO
MODD/IRQD/GPIO
EXTAL
RESET
PINIT/NMI
* ESAI_1 and dedicated GPIO pins are not available in the 52-pin package.
Figure 1. DSP56374 Block Diagram
2 Features
2.1 DSP56300 Modular Chassis
•
150 Million Instructions Per Second (MIPS) with a 150 MHz clock at an internal logic supply
(QVDDL) of 1.25 V
•
•
Object Code Compatible with the 56K core
Data ALU with a 24 x 24 bit multiplier-accumulator and a 56-bit barrel shifter;16 bit arithmetic
support
•
Program Control with position independent code support
DSP56374 Data Sheet, Rev. 4.2
Freescale Semiconductor
3
Features
•
•
Six-channel DMA controller
Provides a wide range of frequency multiplications (1 to 255), predivider factors (1 to 31), PLL
feedback multiplier (2 or 4), Output divide factor (1, 2, or 4) and a power-saving clock divider
i
(2 : i = 0 to 7) to reduce clock noise
•
•
•
•
Internal address tracing support and OnCE for Hardware/Software debugging
JTAG port, supporting boundary scan, compliant to IEEE 1149.1
Very low-power CMOS design, fully static design with operating frequencies down to DC
STOP and WAIT low-power standby modes
2.2 On-chip Memory Configuration
•
•
•
•
•
6Kx24 Bit Y-Data RAM and 4Kx24 Bit Y-Data ROM
6Kx24 Bit X-Data RAM and 4Kx24 Bit X-Data ROM
20Kx24 Bit Program and Bootstrap ROM including a PROM patching mechanism
6Kx24 Bit Program RAM.
Various memory switches are available. See memory table below.
Table 1. DSP56374 Memory Switch Configurations
Bit Settings
MSW0
Memory Sizes (24-bit words)
Prog
RAM
X Data
RAM
Y Data
RAM
Prog
ROM
X Data
ROM
Y Data
ROM
MSW1
MS
X
0
0
1
1
X
0
1
0
1
0
1
1
1
1
6K
2K
6K
10K
8K
6K
6K
6K
6K
4K
20K
20K
20K
20K
20K
4K
4K
4K
4K
4K
4K
4K
4K
4K
4K
4K
8K
4K
10K
4K
2.3 Peripheral Modules
•
Enhanced Serial Audio Interface (ESAI): up to 4 receiver pins and up to 6 transmitter pins, master
or slave. I S, Sony, AC97, network, and other programmable protocols.
2
•
Enhanced Serial Audio Interface I (ESAI_1): up to 4 receiver pins and up to 6 transmitter pins,
master or slave. I S, Sony, AC97, network and other programmable protocols. Note: Available in
2
the 80-pin package only.
2
•
Serial Host Interface (SHI): SPI and I C protocols, 10-word receive FIFO, support for 8, 16, and
24-bit words. Three noise reduction filter modes.
•
•
Triple Timer module (TEC)
Most pins of unused peripherals may be programmed as GPIO pins. Up to 47 pins can be
configured as GPIO on the 80 pin package and 20 pins on the 52 pin package.
DSP56374 Data Sheet, Rev. 4.2
4
Freescale Semiconductor
Documentation
•
Hardware Watchdog Timer
2.4 Packages
80-pin and 52-pin plastic LQFP packages.
3 Documentation
Table 2 lists the documents that provide a complete description of the DSP56374 and are required to design
properly with the part. Documentation is available from a local Freescale Semiconductor, Inc. (formerly
Motorola) distributor, semiconductor sales office, Literature Distribution Center, or through the Freescale
DSP home page on the Internet (the source for the latest information).
Table 2. DSP56374 Documentation
Document Name
Description
Order Number
DSP56300 Family Manual
Detailed description of the 56300-family architecture and the DSP56300FM/AD
24-bit core processor and instruction set
DSP56374 User’s Manual
Detailed description of memory, peripherals, and interfaces
DSP56374UM/D
DSP56374
DSP56374 Technical Data Sheet Electrical and timing specifications; pin and package
descriptions
DSP56374 Product Brief
Brief description of the chip
DSP56374PB/D
4 Signal Groupings
The input and output signals of the DSP56374 are organized into functional groups, which are listed in
Table 3.
The DSP56374 is operated from a 1.25 V and 3.3 V supply; however, some of the inputs can tolerate 5.0 V.
A special notice for this feature is added to the signal descriptions of those inputs.
Table 3. DSP56374 Functional Signal Groupings
Number of
Signals1
Detailed
Description
Functional Group
Power (VDD
)
11
9
Table 15
Table 5
Table 6
Table 7
Table 8
Table 9
Table 10
Table 11
Ground (GND)
Scan Pins
1
Clock and PLL
Interrupt and mode control
SHI
3
Port H2
Port H2
Port C4
Port E5
5
5
ESAI
12
12
ESAI_1
DSP56374 Data Sheet, Rev. 4.2
Freescale Semiconductor
5
Signal Groupings
Table 3. DSP56374 Functional Signal Groupings (continued)
Number of
Detailed
Description
Functional Group
Signals1
Dedicated GPIO
Port G3
15
3
Table 12
Table 13
Table 14
Timer
JTAG/OnCE Port
4
Note:
1
Pins are not 5 V. tolerant unless noted.
Port H signals are the GPIO port signals which are multiplexed with the MOD and HREQ signals.
Port G signals are the dedicated GPIO port signals.
Port C signals are the GPIO port signals which are multiplexed with the ESAI signals.
Port E signals are the GPIO port signals which are multiplexed with the ESAI_1 signals.
2
3
4
5
4.1 Power
Table 4. Power Inputs
Description
Power Name
PLLA_VDD (1) PLL Power— The voltage (3.3 V) should be well-regulated and the input should be provided with
an extremely low impedance path to the 3.3 VDD power rail. The user must provide adequate
external decoupling capacitors between PLLA_VDD and PLLA_GND. PLLA_VDD requires a filter
as shown in Figure 1 and Figure 2 below. See the DSP56374 technical data sheet for additional
details.
PLLP_VDD(1)
PLL Power— The voltage (3.3 V) should be well-regulated and the input should be provided with
an extremely low impedance path to the 3.3 VDD power rail. The user must provide adequate
external decoupling capacitors between PLLP_VDD and PLLP_GND.
PLLD_VDD (1) PLL Power— The voltage (1.25 V) should be well-regulated and the input should be provided with
an extremely low impedance path to the 1.25 VDD power rail. The user must provide adequate
external decoupling capacitors between PLLD_VDD and PLLD_GND.
CORE_VDD (4) Core Power—The voltage (1.25 V) should be well-regulated and the input should be provided with
an extremely low impedance path to the 1.25 VDD power rail. The user must provide adequate
external decoupling capacitors.
IO_VDD
(80-pin 4)
(52-pin 3)
SHI, ESAI, ESAI_1, WDT and Timer I/O Power —The voltage (3.3 V) should be well-regulated,
and the input should be provided with an extremely low impedance path to the 3.3 VDD power rail.
This is an isolated power for the SHI, ESAI, ESAI_1, WDT and Timer I/O. The user must provide
adequate external decoupling capacitors.
4.2 Ground
Table 5. Grounds
Description
Ground Name
PLLA_GND(1)
PLL Ground—The PLL ground should be provided with an extremely low-impedance path to
ground. This connection must be tied externally to all other chip ground connections. The user
must provide adequate external decoupling capacitors between PLLA_VDD and PLLA_GND.
DSP56374 Data Sheet, Rev. 4.2
6
Freescale Semiconductor
Signal Groupings
Table 5. Grounds (continued)
Description
Ground Name
PLLP_GND(1)
PLL Ground—The PLL ground should be provided with an extremely low-impedance path to
ground. This connection must be tied externally to all other chip ground connections. The user
must provide adequate external decoupling capacitors between PLLP_VDD and PLLP_GND.
PLLD_GND(1) PLL Ground—The PLL ground should be provided with an extremely low-impedance path to
ground. This connection must be tied externally to all other chip ground connections. The user
must provide adequate external decoupling capacitors between PLLD_VDD and PLLD_GND.
CORE_GND(4) Core Ground—The Core ground should be provided with an extremely low-impedance path to
ground. This connection must be tied externally to all other chip ground connections. The user
must provide adequate external decoupling capacitors.
IO_GND(2)
SHI, ESAI, ESAI_1, WDT and Timer I/O Ground—IO_GND is the ground for the SHI, ESAI,
ESAI_1, WDT and Timer I/O. This connection must be tied externally to all other chip ground
connections. The user must provide adequate external decoupling capacitors.
4.3 SCAN
Table 6. SCAN Signals
State
Signal
Type
During
Reset
Signal Description
Name
SCAN
Input
Input
SCAN—Manufacturing test pin. This pin must be connected to ground.
4.4 Clock and PLL
Table 7. Clock and PLL Signals
Signal Description
State
during
Reset
Signal
Type
Name
EXTAL
Input
Input
External Clock / Crystal Input—An external clock source must be connected
to EXTAL in order to supply the clock to the internal clock generator and PLL.
XTAL
Output Chip Driven Crystal Output—Connects the internal Crystal Oscillator output to an external
crystal. If an external clock is used, leave XTAL unconnected.
PINIT/NMI
Input
Input
PLL Initial/Nonmaskable Interrupt—During assertion of RESET, the value of
PINIT/NMI is written into the PLL Enable (PEN) bit of the PLL control register,
determining whether the PLL is enabled or disabled. After RESET
de-assertion and during normal instruction processing, the PINIT/NMI
Schmitt-trigger input is a negative-edge-triggered nonmaskable interrupt
(NMI) request internally synchronized to the internal system clock.
This pin has an internal pull up resistor.
This input is 5 V tolerant.
DSP56374 Data Sheet, Rev. 4.2
Freescale Semiconductor
7
Signal Groupings
4.5 Interrupt and Mode Control
The interrupt and mode control signals select the chip’s operating mode as it comes out of hardware reset.
After RESET is de-asserted, these inputs are hardware interrupt request lines.
Table 8. Interrupt and Mode Control
State
Signal Name
Type
during
Reset
Signal Description
MODA/IRQA
Input
MODA Mode Select A/External Interrupt Request A—MODA/IRQA is an
Input
active-low Schmitt-trigger input, internally synchronized to the DSP
clock. MODA/IRQA selects the initial chip operating mode during
hardware reset and becomes a level-sensitive or
negative-edge-triggered, maskable interrupt request input during
normal instruction processing. This pin can also be programmed as
GPIO. MODA, MODB, MODC, and MODD select one of 16 initial chip
operating modes, latched into the OMR when the RESET signal is
de-asserted. If the processor is in the stop standby state and the
MODA/IRQA pin is pulled to GND, the processor will exit the stop state.
This pin has an internal pull up resistor.
This input is 5 V tolerant.
PH0
Input, output,
or
Port H0—When the MODA/IRQA is configured as GPIO, this signal is
individually programmable as input, output, or internally disconnected.
disconnected
MODB/IRQB
Input
MODB Mode Select B/External Interrupt Request B—MODB/IRQB is an
Input
active-low Schmitt-trigger input, internally synchronized to the DSP
clock. MODB/IRQB selects the initial chip operating mode during
hardware reset and becomes a level-sensitive or
negative-edge-triggered, maskable interrupt request input during
normal instruction processing. This pin can also be programmed as
GPIO. MODA, MODB, MODC, and MODD select one of 16 initial chip
operating modes, latched into OMR when the RESET signal is
de-asserted.
This pin has an internal pull up resistor.
This input is 5 V tolerant.
PH1
Input, output,
or
Port H1—When the MODB/IRQB is configured as GPIO, this signal is
individually programmable as input, output, or internally disconnected.
disconnected
MODC/IRQC
Input
MODC Mode Select C/External Interrupt Request C—MODC/IRQC is an
Input
active-low Schmitt-trigger input, internally synchronized to the DSP
clock. MODC/IRQC selects the initial chip operating mode during
hardware reset and becomes a level-sensitive or
negative-edge-triggered, maskable interrupt request input during
normal instruction processing. This pin can also be programmed as
GPIO. MODA, MODB, MODC, and MODD select one of 16 initial chip
operating modes, latched into OMR when the RESET signal is
de-asserted.
This pin has an internal pull up resistor.
This input is 5 V tolerant.
DSP56374 Data Sheet, Rev. 4.2
8
Freescale Semiconductor
Signal Groupings
Table 8. Interrupt and Mode Control (continued)
State
Signal Name
Type
during
Reset
Signal Description
PH2
Input, output,
or
Port H2—When the MODC/IRQC is configured as GPIO, this signal is
individually programmable as input, output, or internally disconnected.
disconnected
MODD/IRQD
Input
MODD Mode Select D/External Interrupt Request D—MODD/IRQD is an
Input
active-low Schmitt-trigger input, internally synchronized to the DSP
clock. MODD/IRQD selects the initial chip operating mode during
hardware reset and becomes a level-sensitive or
negative-edge-triggered, maskable interrupt request input during
normal instruction processing. This pin can also be programmed as
GPIO. MODA, MODB, MODC, and MODD select one of 16 initial chip
operating modes, latched into OMR when the RESET signal is
de-asserted.
This pin has an internal pull up resistor.
This input is 5 V tolerant.
PH3
Input, output,
or
Port H3—When the MODD/IRQD is configured as GPIO, this signal is
individually programmable as input, output, or internally disconnected.
disconnected
RESET
Input
Input
Reset—RESET is an active-low, Schmitt-trigger input. When asserted,
the chip is placed in the Reset state and the internal phase generator is
reset. The Schmitt-trigger input allows a slowly rising input (such as a
capacitor charging) to reset the chip reliably. When the RESET signal is
de-asserted, the initial chip operating mode is latched from the MODA,
MODB, MODC, and MODD inputs. The RESET signal must be asserted
during power up. A stable EXTAL signal must be supplied while RESET
is being asserted.
This pin has an internal pull up resistor.
This input is 5 V tolerant.
4.6 Serial Host Interface
The SHI has five I/O signals that can be configured to allow the SHI to operate in either SPI or I C mode.
2
DSP56374 Data Sheet, Rev. 4.2
Freescale Semiconductor
9
Signal Groupings
Signal
Table 9. Serial Host Interface Signals
State during
Signal Type
Signal Description
Name
Reset
SCK
Input or output
Tri-stated
SPI Serial Clock—The SCK signal is an output when the SPI is configured
as a master and a Schmitt-trigger input when the SPI is configured as a
slave. When the SPI is configured as a master, the SCK signal is derived
from the internal SHI clock generator. When the SPI is configured as a
slave, the SCK signal is an input, and the clock signal from the external
master synchronizes the data transfer. The SCK signal is ignored by the SPI
if it is defined as a slave and the slave select (SS) signal is not asserted. In
both the master and slave SPI devices, data is shifted on one edge of the
SCK signal and is sampled on the opposite edge where data is stable. Edge
polarity is determined by the SPI transfer protocol.
SCL
Input or output
I2C Serial Clock—SCL carries the clock for I2C bus transactions in the I2C
mode. SCL is a Schmitt-trigger input when configured as a slave and an
open-drain output when configured as a master. SCL should be connected
to VDD through an external pull-up resistor according to the I2C
specifications.
This signal is tri-stated during hardware, software, and individual reset.
This pin has an internal pull up resistor.
This input is 5 V tolerant.
MISO
Input or output
Tri-stated
SPI Master-In-Slave-Out—When the SPI is configured as a master, MISO
is the master data input line. The MISO signal is used in conjunction with the
MOSI signal for transmitting and receiving serial data. This signal is a
Schmitt-trigger input when configured for the SPI Master mode, an output
when configured for the SPI Slave mode, and tri-stated if configured for the
SPI Slave mode when SS is de-asserted. An external pull-up resistor is not
required for SPI operation.
SDA
Input or
open-drain
output
I2C Data and Acknowledge—In I2C mode, SDA is a Schmitt-trigger input
when receiving and an open-drain output when transmitting. SDA should be
connected to VDD through a pull-up resistor. SDA carries the data for I2C
transactions. The data in SDA must be stable during the high period of SCL.
The data in SDA is only allowed to change when SCL is low. When the bus
is free, SDA is high. The SDA line is only allowed to change during the time
SCL is high in the case of start and stop events. A high-to-low transition of
the SDA line while SCL is high is a unique situation, and is defined as the
start event. A low-to-high transition of SDA while SCL is high is a unique
situation defined as the stop event.
This signal is tri-stated during hardware, software, and individual reset.
Thus, there is no need for an external pull-up in this state.
This pin has an internal pull up resistor.
This input is 5 V tolerant.
DSP56374 Data Sheet, Rev. 4.2
10
Freescale Semiconductor
Signal Groupings
Table 9. Serial Host Interface Signals (continued)
Signal
Name
State during
Signal Description
Reset
Signal Type
MOSI
Input or output
Tri-stated
SPI Master-Out-Slave-In—When the SPI is configured as a master, MOSI
is the master data output line. The MOSI signal is used in conjunction with
the MISO signal for transmitting and receiving serial data. MOSI is the slave
data input line when the SPI is configured as a slave. This signal is a
Schmitt-trigger input when configured for the SPI Slave mode.
HA0
Input
I2C Slave Address 0—This signal uses a Schmitt-trigger input when
configured for the I2C mode. When configured for I2C slave mode, the HA0
signal is used to form the slave device address. HA0 is ignored when
configured for the I2C master mode.
This signal is tri-stated during hardware, software, and individual reset.
Thus, there is no need for an external pull-up in this state.
This pin has an internal pull up resistor.
This input is 5 V tolerant.
SS
Input
Input
Ignored Input SPI Slave Select—This signal is an active low Schmitt-trigger input when
configured for the SPI mode. When configured for the SPI Slave mode, this
signal is used to enable the SPI slave for transfer. When configured for the
SPI master mode, this signal should be kept de-asserted (pulled high). If it
is asserted while configured as SPI master, a bus error condition is flagged.
If SS is de-asserted, the SHI ignores SCK clocks and keeps the MISO
output signal in the high-impedance state.
HA2
I2C Slave Address 2—This signal uses a Schmitt-trigger input when
configured for the I2C mode. When configured for the I2C Slave mode, the
HA2 signal is used to form the slave device address. HA2 is ignored in the
I2C master mode.
This pin has an internal pull up resistor.
This input is 5 V tolerant.
HREQ Input or Output
Tri-stated
Host Request—This signal is an active low Schmitt-trigger input when
configured for the master mode but an active low output when configured for
the slave mode.
When configured for the slave mode, HREQ is asserted to indicate that the
SHI is ready for the next data word transfer and de-asserted at the first clock
pulse of the new data word transfer. When configured for the master mode,
HREQ is an input. When asserted by the external slave device, it will trigger
the start of the data word transfer by the master. After finishing the data word
transfer, the master will await the next assertion of HREQ to proceed to the
next transfer. This pin can also be programmed as GPIO.
PH4
Input, output, or
disconnected
Port H4—When HREQ is configured as GPIO, this signal is individually
programmable as input, output, or internally disconnected.
This pin has an internal pull up resistor.
This input is 5 V tolerant.
DSP56374 Data Sheet, Rev. 4.2
Freescale Semiconductor
11
Signal Groupings
4.7 Enhanced Serial Audio Interface
Table 10. Enhanced Serial Audio Interface Signals
State during
Signal Name
Signal Type
Signal Description
Reset
HCKR
Input or output
GPIO
High Frequency Clock for Receiver—When programmed
disconnected as an input, this signal provides a high frequency clock
source for the ESAI receiver as an alternate to the DSP
core clock. When programmed as an output, this signal can
serve as a high-frequency sample clock (e.g., for external
digital to analog converters [DACs]) or as an additional
system clock.
PC2
Input, output, or
disconnected
Port C2—When the ESAI is configured as GPIO, this signal
is individually programmable as input, output, or internally
disconnected.
The default state after reset is GPIO disconnected.
This pin has an internal pull up resistor.
This input is 5 V tolerant.
HCKT
PC5
Input or output
GPIO
High Frequency Clock for Transmitter—When programmed
disconnected as an input, this signal provides a high frequency clock
source for the ESAI transmitter as an alternate to the DSP
core clock. When programmed as an output, this signal can
serve as a high frequency sample clock (e.g., for external
DACs) or as an additional system clock.
Input, output, or
disconnected
Port C5—When the ESAI is configured as GPIO, this signal
is individually programmable as input, output, or internally
disconnected.
The default state after reset is GPIO disconnected.
This pin has an internal pull up resistor.
This input is 5 V tolerant.
DSP56374 Data Sheet, Rev. 4.2
12
Freescale Semiconductor
Signal Groupings
Table 10. Enhanced Serial Audio Interface Signals (continued)
State during
Signal Name
Signal Type
Signal Description
Reset
FSR
Input or output
GPIO
Frame Sync for Receiver—This is the receiver frame sync
disconnected input/output signal. In the asynchronous mode (SYN=0),
the FSR pin operates as the frame sync input or output
used by all the enabled receivers. In the synchronous mode
(SYN=1), it operates as either the serial flag 1 pin
(TEBE=0), or as the transmitter external buffer enable
control (TEBE=1, RFSD=1).
When this pin is configured as serial flag pin, its direction is
determined by the RFSD bit in the RCCR register. When
configured as the output flag OF1, this pin will reflect the
value of the OF1 bit in the SAICR register, and the data in
the OF1 bit will show up at the pin synchronized to the
frame sync in normal mode or the slot in network mode.
When configured as the input flag IF1, the data value at the
pin will be stored in the IF1 bit in the SAISR register,
synchronized by the frame sync in normal mode or the slot
in network mode.
PC1
FST
Input, output, or
disconnected
Port C1—When the ESAI is configured as GPIO, this signal
is individually programmable as input, output, or internally
disconnected.
The default state after reset is GPIO disconnected.
Internal Pull down resistor.
This input is 5 V tolerant.
Input or output
GPIO
Frame Sync for Transmitter—This is the transmitter frame
disconnected sync input/output signal. For synchronous mode, this signal
is the frame sync for both transmitters and receivers. For
asynchronous mode, FST is the frame sync for the
transmitters only. The direction is determined by the
transmitter frame sync direction (TFSD) bit in the ESAI
transmit clock control register (TCCR).
PC4
Input, output, or
disconnected
Port C4—When the ESAI is configured as GPIO, this signal
is individually programmable as input, output, or internally
disconnected.
The default state after reset is GPIO disconnected.
Internal Pull down resistor.
This input is 5 V tolerant.
DSP56374 Data Sheet, Rev. 4.2
Freescale Semiconductor
13
Signal Groupings
Table 10. Enhanced Serial Audio Interface Signals (continued)
State during
Signal Name
Signal Type
Signal Description
Reset
SCKR
Input or output
GPIO
Receiver Serial Clock—SCKR provides the receiver serial
disconnected bit clock for the ESAI. The SCKR operates as a clock input
or output used by all the enabled receivers in the
asynchronous mode (SYN=0), or as serial flag 0 pin in the
synchronous mode (SYN=1).
When this pin is configured as serial flag pin, its direction is
determined by the RCKD bit in the RCCR register. When
configured as the output flag OF0, this pin will reflect the
value of the OF0 bit in the SAICR register, and the data in
the OF0 bit will show up at the pin synchronized to the
frame sync in normal mode or the slot in network mode.
When configured as the input flag IF0, the data value at the
pin will be stored in the IF0 bit in the SAISR register,
synchronized by the frame sync in normal mode or the slot
in network mode.
PC0
Input, output, or
disconnected
Port C0—When the ESAI is configured as GPIO, this signal
is individually programmable as input, output, or internally
disconnected.
The default state after reset is GPIO disconnected.
Internal Pull down resistor.
This input is 5 V tolerant.
SCKT
PC3
Input or output
GPIO
Transmitter Serial Clock—This signal provides the serial bit
disconnected rate clock for the ESAI. SCKT is a clock input or output used
by all enabled transmitters and receivers in synchronous
mode, or by all enabled transmitters in asynchronous
mode.
Input, output, or
disconnected
Port C3—When the ESAI is configured as GPIO, this signal
is individually programmable as input, output, or internally
disconnected.
The default state after reset is GPIO disconnected.
Internal Pull down resistor.
This input is 5 V tolerant.
DSP56374 Data Sheet, Rev. 4.2
14
Freescale Semiconductor
Signal Groupings
Table 10. Enhanced Serial Audio Interface Signals (continued)
State during
Signal Name
Signal Type
Signal Description
Reset
SDO5
Output
GPIO
Serial Data Output 5—When programmed as a transmitter,
disconnected SDO5 is used to transmit data from the TX5 serial transmit
shift register.
SDI0
PC6
Input
Serial Data Input 0—When programmed as a receiver,
SDI0 is used to receive serial data into the RX0 serial
receive shift register.
Input, output, or
disconnected
Port C6—When the ESAI is configured as GPIO, this signal
is individually programmable as input, output, or internally
disconnected.
The default state after reset is GPIO disconnected.
Internal Pull down resistor.
This input is 5 V tolerant.
SDO4
SDI1
PC7
Output
Input
GPIO
Serial Data Output 4—When programmed as a transmitter,
disconnected SDO4 is used to transmit data from the TX4 serial transmit
shift register.
Serial Data Input 1—When programmed as a receiver,
SDI1 is used to receive serial data into the RX1 serial
receive shift register.
Input, output, or
disconnected
Port C7—When the ESAI is configured as GPIO, this signal
is individually programmable as input, output, or internally
disconnected.
The default state after reset is GPIO disconnected.
Internal Pull down resistor.
This input is 5 V tolerant.
SDO3
SDI2
PC8
Output
Input
GPIO
Serial Data Output 3—When programmed as a
disconnected transmitter, SDO3 is used to transmit data from the TX3
serial transmit shift register.
Serial Data Input 2—When programmed as a receiver,
SDI2 is used to receive serial data into the RX2 serial
receive shift register.
Input, output, or
disconnected
Port C8—When the ESAI is configured as GPIO, this signal
is individually programmable as input, output, or internally
disconnected.
The default state after reset is GPIO disconnected.
Internal Pull down resistor.
This input is 5 V tolerant.
DSP56374 Data Sheet, Rev. 4.2
Freescale Semiconductor
15
Signal Groupings
Table 10. Enhanced Serial Audio Interface Signals (continued)
State during
Signal Name
Signal Type
Signal Description
Reset
SDO2
Output
GPIO
Serial Data Output 2—When programmed as a transmitter,
disconnected SDO2 is used to transmit data from the TX2 serial transmit
shift register
SDI3
PC9
Input
Serial Data Input 3—When programmed as a receiver,
SDI3 is used to receive serial data into the RX3 serial
receive shift register.
Input, output, or
disconnected
Port C9—When the ESAI is configured as GPIO, this signal
is individually programmable as input, output, or internally
disconnected.
The default state after reset is GPIO disconnected.
Internal Pull down resistor.
This input is 5 V tolerant.
SDO1
PC10
Output
GPIO
Serial Data Output 1—SDO1 is used to transmit data from
disconnected the TX1 serial transmit shift register.
Input, output, or
disconnected
Port C10—When the ESAI is configured as GPIO, this
signal is individually programmable as input, output, or
internally disconnected.
The default state after reset is GPIO disconnected.
Internal Pull down resistor.
This input is 5 V tolerant.
SDO0
Output
GPIO
Serial Data Output 0—SDO0 is used to transmit data from
disconnected the TX0 serial transmit shift register.
PC11
Input, output, or
disconnected
Port C11—When the ESAI is configured as GPIO, this
signal is individually programmable as input, output, or
internally disconnected.
The default state after reset is GPIO disconnected.
Internal Pull down resistor.
This input is 5 V tolerant.
DSP56374 Data Sheet, Rev. 4.2
16
Freescale Semiconductor
Signal Groupings
4.8 Enhanced Serial Audio Interface_1
Table 11. Enhanced Serial Audio Interface_1 Signals
State during
Signal Name
Signal Type
Signal Description
High Frequency Clock for Receiver—When programmed as
Reset
HCKR_1
Input or output
GPIO
disconnected an input, this signal provides a high frequency clock source
for the ESAI_1 receiver as an alternate to the DSP core
clock. When programmed as an output, this signal can
serve as a high-frequency sample clock (e.g., for external
digital to analog converters [DACs]) or as an additional
system clock.
PE2
Input, output, or
disconnected
Port E2—When the ESAI_1 is configured as GPIO, this
signal is individually programmable as input, output, or
internally disconnected.
The default state after reset is GPIO disconnected.
Internal Pull down resistor.
This input is 5 V tolerant.
HCKT_1
Input or output
GPIO
High Frequency Clock for Transmitter—When programmed
disconnected as an input, this signal provides a high frequency clock
source for the ESAI_1 transmitter as an alternate to the
DSP core clock. When programmed as an output, this
signal can serve as a high frequency sample clock (e.g., for
external DACs) or as an additional system clock.
PE5
Input, output, or
disconnected
Port E5—When the ESAI_1 is configured as GPIO, this
signal is individually programmable as input, output, or
internally disconnected.
The default state after reset is GPIO disconnected.
Internal Pull down resistor.
This input is 5 V tolerant.
DSP56374 Data Sheet, Rev. 4.2
Freescale Semiconductor
17
Signal Groupings
Table 11. Enhanced Serial Audio Interface_1 Signals (continued)
State during
Signal Name
Signal Type
Signal Description
Reset
FSR_1
Input or output
GPIO
Frame Sync for Receiver_1—This is the receiver frame
disconnected sync input/output signal. In the asynchronous mode
(SYN=0), the FSR_1 pin operates as the frame sync input
or output used by all the enabled receivers. In the
synchronous mode (SYN=1), it operates as either the serial
flag 1 pin (TEBE=0), or as the transmitter external buffer
enable control (TEBE=1, RFSD=1).
When this pin is configured as serial flag pin, its direction is
determined by the RFSD bit in the RCCR_1 register. When
configured as the output flag OF1, this pin will reflect the
value of the OF1 bit in the SAICR_1 register, and the data
in the OF1 bit will show up at the pin synchronized to the
frame sync in normal mode or the slot in network mode.
When configured as the input flag IF1, the data value at the
pin will be stored in the IF1 bit in the SAISR_1 register,
synchronized by the frame sync in normal mode or the slot
in network mode.
PE1
Input, output, or
disconnected
Port E1—When the ESAI_1 is configured as GPIO, this
signal is individually programmable as input, output, or
internally disconnected.
The default state after reset is GPIO disconnected.
Internal Pull down resistor.
This input is 5 V tolerant
FST_1
Input or output
GPIO
Frame Sync for Transmitter_1—This is the transmitter frame
disconnected sync input/output signal. For synchronous mode, this signal
is the frame sync for both transmitters and receivers. For
asynchronous mode, FST_1 is the frame sync for the
transmitters only. The direction is determined by the
transmitter frame sync direction (TFSD) bit in the ESAI_1
transmit clock control register (TCCR_1).
PE4
Input, output, or
disconnected
Port E4—When the ESAI_1 is configured as GPIO, this
signal is individually programmable as input, output, or
internally disconnected.
The default state after reset is GPIO disconnected.
Internal Pull down resistor.
This input is 5 V tolerant.
DSP56374 Data Sheet, Rev. 4.2
18
Freescale Semiconductor
Signal Groupings
Table 11. Enhanced Serial Audio Interface_1 Signals (continued)
State during
Signal Name
Signal Type
Signal Description
Reset
SCKR_1
Input or output
GPIO
Receiver Serial Clock_1—SCKR_1 provides the receiver
disconnected serial bit clock for the ESAI_1. The SCKR_1 operates as a
clock input or output used by all the enabled receivers in the
asynchronous mode (SYN=0), or as serial flag 0 pin in the
synchronous mode (SYN=1).
When this pin is configured as serial flag pin, its direction is
determined by the RCKD bit in the RCCR_1 register. When
configured as the output flag OF0, this pin will reflect the
value of the OF0 bit in the SAICR_1 register, and the data
in the OF0 bit will show up at the pin synchronized to the
frame sync in normal mode or the slot in network mode.
When configured as the input flag IF0, the data value at the
pin will be stored in the IF0 bit in the SAISR_1 register,
synchronized by the frame sync in normal mode or the slot
in network mode.
PE0
Input, output, or
disconnected
Port E0—When the ESAI_1 is configured as GPIO, this
signal is individually programmable as input, output, or
internally disconnected.
The default state after reset is GPIO disconnected.
Internal Pull down resistor.
This input is 5 V tolerant
SCKT_1
PE3
Input or output
GPIO
Transmitter Serial Clock_1—This signal provides the serial
disconnected bit rate clock for the ESAI_1. SCKT_1 is a clock input or
output used by all enabled transmitters and receivers in
synchronous mode, or by all enabled transmitters in
asynchronous mode.
Input, output, or
disconnected
Port E3—When the ESAI_1 is configured as GPIO, this
signal is individually programmable as input, output, or
internally disconnected.
The default state after reset is GPIO disconnected.
Internal Pull down resistor.
This input is 5 V tolerant
DSP56374 Data Sheet, Rev. 4.2
Freescale Semiconductor
19
Signal Groupings
Table 11. Enhanced Serial Audio Interface_1 Signals (continued)
State during
Signal Name
Signal Type
Signal Description
Reset
SDO5_1
Output
GPIO
Serial Data Output 5_1—When programmed as a
disconnected transmitter, SDO5_1 is used to transmit data from the TX5
serial transmit shift register.
SDI0_1
PE6
Input
Serial Data Input 0_1—When programmed as a receiver,
SDI0_1 is used to receive serial data into the RX0 serial
receive shift register.
Input, output, or
disconnected
Port E6—When the ESAI_1 is configured as GPIO, this
signal is individually programmable as input, output, or
internally disconnected.
The default state after reset is GPIO disconnected.
Internal Pull down resistor.
This input is 5 V tolerant
SDO4_1
SDI1_1
PE7
Output
Input
GPIO
Serial Data Output 4_1—When programmed as a
disconnected transmitter, SDO4_1 is used to transmit data from the TX4
serial transmit shift register.
Serial Data Input 1_1—When programmed as a receiver,
SDI1_1 is used to receive serial data into the RX1 serial
receive shift register.
Input, output, or
disconnected
Port E7—When the ESAI_1 is configured as GPIO, this
signal is individually programmable as input, output, or
internally disconnected.
The default state after reset is GPIO disconnected.
Internal Pull down resistor.
This input is 5 V tolerant.
SDO3_1
SDI2_1
PE8
Output
Input
GPIO
Serial Data Output 3—When programmed as a transmitter,
disconnected SDO3_1 is used to transmit data from the TX3 serial
transmit shift register.
Serial Data Input 2—When programmed as a receiver,
SDI2_1 is used to receive serial data into the RX2 serial
receive shift register.
Input, output, or
disconnected
Port E8—When the ESAI is configured as GPIO, this signal
is individually programmable as input, output, or internally
disconnected.
The default state after reset is GPIO disconnected.
Internal Pull down resistor.
This input is 5 V tolerant.
DSP56374 Data Sheet, Rev. 4.2
20
Freescale Semiconductor
Signal Groupings
Table 11. Enhanced Serial Audio Interface_1 Signals (continued)
State during
Signal Name
Signal Type
Signal Description
Reset
SDO2_1
Output
GPIO
Serial Data Output 2—When programmed as a transmitter,
disconnected SDO2_1 is used to transmit data from the TX2 serial
transmit shift register.
SDI3_1
PE9
Input
Serial Data Input 3—When programmed as a receiver,
SDI3_1 is used to receive serial data into the RX3 serial
receive shift register.
Input, output, or
disconnected
Port E9—When the ESAI_1 is configured as GPIO, this
signal is individually programmable as input, output, or
internally disconnected.
The default state after reset is GPIO disconnected.
Internal Pull down resistor.
This input is 5 V tolerant.
SDO1_1
PE10
Output
GPIO
Serial Data Output 1—SDO1_1 is used to transmit data
disconnected from the TX1 serial transmit shift register.
Input, output, or
disconnected
Port E10—When the ESAI is configured as GPIO, this
signal is individually programmable as input, output, or
internally disconnected.
The default state after reset is GPIO disconnected.
Internal Pull down resistor.
This input is 5 V tolerant.
SDO0_1
PE11
Output
GPIO
Serial Data Output 0—SDO0_1 is used to transmit data
disconnected from the TX0 serial transmit shift register.
Input, output, or
disconnected
Port E11—When the ESAI_1 is configured as GPIO, this
signal is individually programmable as input, output, or
internally disconnected.
The default state after reset is GPIO disconnected.
Internal Pull down resistor.
This input is 5 V tolerant.
DSP56374 Data Sheet, Rev. 4.2
Freescale Semiconductor
21
Signal Groupings
4.9 Dedicated GPIO-Port G
Table 12. Dedicated GPIO-Port G Signals
Signal
Name
State During
Type
Signal Description
Port G0—This signal is individually programmable as input,
Reset
PG0
PG1
PG2
PG3
PG4
PG5
PG6
PG7
PG8
Input,
GPIO
output, or
disconnected
disconnected output, or internally disconnected.
Internal Pull down resistor.
This input is 5 V tolerant
Input,
output, or
disconnected
GPIO
Port G1—This signal is individually programmable as input,
disconnected output, or internally disconnected.
Internal Pull down resistor.
This input is 5 V tolerant
Input,
output, or
disconnected
GPIO
Port G2—This signal is individually programmable as input,
disconnected output, or internally disconnected.
Internal Pull down resistor.
This input is 5 V tolerant
Input,
output, or
disconnected
GPIO
Port G3—This signal is individually programmable as input,
disconnected output, or internally disconnected.
Internal Pull down resistor.
This input is 5 V tolerant
Input,
output, or
disconnected
GPIO
Port G4—This signal is individually programmable as input,
disconnected output, or internally disconnected.
Internal Pull down resistor.
This input is 5 V tolerant
Input,
output, or
disconnected
GPIO
Port G5—This signal is individually programmable as input,
disconnected output, or internally disconnected.
Internal Pull down resistor.
This input is 5 V tolerant
Input,
output, or
disconnected
GPIO
Port G6—This signal is individually programmable as input,
disconnected output, or internally disconnected.
Internal Pull down resistor.
This input is 5 V tolerant
Input,
output, or
disconnected
GPIO
Port G7—This signal is individually programmable as input,
disconnected output, or internally disconnected.
Internal Pull down resistor.
This input is 5 V tolerant
Input,
GPIO
Port G8—This signal is individually programmable as input,
output, or
disconnected output, or internally disconnected.
disconnected
Internal Pull down resistor.
This input is 5 V tolerant
DSP56374 Data Sheet, Rev. 4.2
22
Freescale Semiconductor
Signal Groupings
Table 12. Dedicated GPIO-Port G Signals (continued)
Signal
Name
State During
Signal Description
Reset
Type
PG9
PG10
PG11
PG12
PG13
PG14
Input,
output, or
disconnected
GPIO
Port G9—This signal is individually programmable as input,
disconnected output, or internally disconnected.
Internal Pull down resistor.
This input is 5 V tolerant
Input,
output, or
disconnected
GPIO
Port G10—This signal is individually programmable as input,
disconnected output, or internally disconnected.
Internal Pull down resistor.
This input is 5 V tolerant
Input,
output, or
disconnected
GPIO
Port G11—This signal is individually programmable as input,
disconnected output, or internally disconnected.
Internal Pull down resistor.
This input is 5 V tolerant
Input,
output, or
disconnected
GPIO
Port G12—This signal is individually programmable as input,
disconnected output, or internally disconnected.
Internal Pull down resistor.
This input is 5 V tolerant
Input,
output, or
disconnected
GPIO
Port G13—This signal is individually programmable as input,
disconnected output, or internally disconnected.
Internal Pull down resistor.
This input is 5 V tolerant
Input,
GPIO
Port G14—This signal is individually programmable as input,
output, or
disconnected output, or internally disconnected.
disconnected
Internal Pull down resistor.
This input is 5 V tolerant
DSP56374 Data Sheet, Rev. 4.2
Freescale Semiconductor
23
Signal Groupings
4.10 Timer
Table 13. Timer Signal
State
during
Reset
Signal
Name
Type
Signal Description
TIO0
Input or
Output
GPIO Input Timer 0 Schmitt-Trigger Input/Output—When timer 0 functions as an
external event counter or in measurement mode, TIO0 is used as input.
When timer 0 functions in watchdog, timer, or pulse modulation mode,
TIO0 is used as output.
The default mode after reset is GPIO input. This can be changed to
output or configured as a timer input/output through the timer 0
control/status register (TCSR0). If TIO0 is not being used, it is
recommended to either define it as GPIO output immediately at the
beginning of operation or leave it defined as GPIO input.
Internal Pull down resistor.
This input is 5 V tolerant
TIO1
Input or
Output
Watchdog Timer 1 Schmitt-Trigger Input/Output—When timer 1 functions as an
Timer
external event counter or in measurement mode, TIO1 is used as input.
When timer 1 functions in watchdog, timer, or pulse modulation mode,
TIO1 is used as output.
Output
The default mode after reset is GPIO input. This can be changed to
output or configured as a timer input/output through the timer
1control/status register (TCSR1). If TIO1 is not being used, it is
recommended to either define it as GPIO output immediately at the
beginning of operation or leave it defined as GPIO input.
WDT
TIO2
Output
WDT—When this pin is configured as a hardware watchdog timer pin,
this signal is asserted low when the hardware watchdog timer counts
down to zero.
Internal Pull down resistor.
This input is 5 V tolerant
Input or
Output
PLOCK
Output
Timer 2 Schmitt-Trigger Input/Output—When timer 2 functions as an
external event counter or in measurement mode, TIO2 is used as input.
When timer 2 functions in watchdog, timer, or pulse modulation mode,
TIO2 is used as output.
The default mode after reset is GPIO input. This can be changed to
output or configured as a timer input/output through the timer
control/status register (TCSR2). If TIO2 is not being used, it is
recommended to either define it as GPIO output immediately at the
beginning of operation or leave it defined as GPIO input .
DSP56374 Data Sheet, Rev. 4.2
24
Freescale Semiconductor
Maximum Ratings
Table 13. Timer Signal (continued)
State
Signal
Name
Type
during
Reset
Signal Description
PLOCK
Output
PLOCK—When this pin is configured as a PLL lock pin, this signal is
asserted high when the on-chip PLL enabled and locked and
de-asserted when the PLL enabled and unlocked. This pin is also
asserted high when the PLL is disabled.
Internal Pull down resistor.
This input is 5 V tolerant
4.11 JTAG/OnCE Interface
Table 14. JTAG/OnCE Interface
State
during
Reset
Signal
Name
Signal
Type
Signal Description
TCK
Input
Input
Test Clock—TCK is a test clock input signal used to synchronize the JTAG test
logic.
Internal Pull up resistor.
This input is 5 V tolerant.
TDI
Input
Input
Test Data Input—TDI is a test data serial input signal used for test instructions
and data. TDI is sampled on the rising edge of TCK.
Internal Pull up resistor.
This input is 5 V tolerant.
TDO
TMS
Output
Input
Tri-stated Test Data Output—TDO is a test data serial output signal used for test
instructions and data. TDO is tri-statable and is actively driven in the shift-IR
and shift-DR controller states. TDO changes on the falling edge of TCK.
Input
Test Mode Select—TMS is an input signal used to sequence the test
controller’s state machine. TMS is sampled on the rising edge of TCK.
Internal Pull up resistor.
This input is 5 V tolerant.
5 Maximum Ratings
CAUTION
This device contains circuitry protecting against damage due to high static voltage
or electrical fields. However, normal precautions should be taken to avoid
exceeding maximum voltage ratings. Reliability of operation is enhanced if unused
inputs are pulled to an appropriate logic voltage level (e.g., either GND or V ).
DD
The suggested value for a pullup or pulldown resistor is 4.7 kΩ.
DSP56374 Data Sheet, Rev. 4.2
Freescale Semiconductor
25
Power Requirements
NOTE
In the calculation of timing requirements, adding a maximum value of one
specification to a minimum value of another specification does not yield a
reasonable sum. A maximum specification is calculated using a worst case variation
of process parameter values in one direction. The minimum specification is
calculated using the worst case for the same parameters in the opposite direction.
Therefore, a “maximum” value for a specification will never occur in the same
device that has a “minimum” value for another specification; adding a maximum to
a minimum represents a condition that can never exist.
Table 15. Maximum Ratings
Rating1
Symbol
Value1, 2
Unit
Supply Voltage
VCORE_VDD,
VPLLD_VDD
−0.3 to + 1.6
V
VPLLP_VDD,
VIO_VDD,
VPLLA_VDD
−0.3 to + 4.0
V
,
Maximum CORE_VDD power supply ramp time4
All “5.0V tolerant” input voltages
Tr
VIN
I
10
GND − 0.3 to 6V
12
ms
V
Current drain per pin excluding VDD and GND(Except
for pads listed below)
mA
SCK_SCL
ISCK
IJTAG
TJ
16
24
mA
ma
°C
TDO
Operating temperature range3
80 LQFP = 105
52 LQFP = 110
Storage temperature
TSTG
−55 to +125
2000
°C
V
ESD protected voltage (Human Body Model)
ESD protected voltage (Machine Model)
200
V
Note:
1
GND = 0 V, TJ = -40°C to 110°C (52 LQFP) / -40°C to 105°C (80 LQFP), CL = 50pF
2
3
4
Absolute maximum ratings are stress ratings only, and functional operation at the maximum is not guaranteed.
Stress beyond the maximum rating may affect device reliability or cause permanent damage to the device.
Operating temperature qualified for automotive applications. TJ = TA + θJA x Power. Variables used were
Core Current = 100 mA, I/O Current = 60 mA, Core Voltage = 1.3 V, I/O Voltage = 3.46 V, TA = 85°C
If the power supply ramp to full supply time is longer than 10 ms, the POR circuitry will not operate correctly,
causing erroneous operation.
6 Power Requirements
To prevent high current conditions due to possible improper sequencing of the power supplies, the
connection shown below is recommended to be made between the DSP56374 IO_VDD and Core_VDD
power pins.
DSP56374 Data Sheet, Rev. 4.2
26
Freescale Semiconductor
Thermal Characteristics
IO_VDD
External
Schottky
Diode
Core_VDD
To prevent a high current condition upon power up, the IO_VDD must be applied ahead of the Core_VDD
as shown below if the external Schottky is not used.
Core_VDD
IO_VDD
For correct operation of the internal power on reset logic, the Core_VDD ramp rate (Tr) to full supply must
be less than 10 ms. This is shown below.
Tr
1.25 V
0 V
Core_VDD
7 Thermal Characteristics
Table 16. Thermal Characteristics
Characteristic
Symbol
LQFP Values
Unit
Natural Convection, Junction-to-ambient thermal
resistance1,2
RθJA or θJA
68 (52 LQFP)
50 (80 LQFP)
°C/W
Junction-to-case thermal resistance3
RθJC or θJC
17 (52 LQFP)
11 (80 LQFP)
°C/W
Note:
1
Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance,
mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components
on the board, and board thermal resistance.
Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal.
Thermal resistance between the die and the case top surface as measured by the cold plate method
(MIL SPEC-883 Method 1012.1).
2
3
DSP56374 Data Sheet, Rev. 4.2
Freescale Semiconductor
27
DC Electrical Characteristics
8 DC Electrical Characteristics
Table 17. DC Electrical Characteristics
Characteristics
Symbol
Min
Typ
Max
Unit
Supply voltages
• Core (Core_VDD)
• PLL (PLLD_VDD)
VDD
1.2
1.25
1.3
V
Supply voltages
VDDIO
3.14
2.0
3.3
—
3.46
V
• I/O (IO_VDD)
• PLL (PLLP_VDD)
• PLL (PLLA_VDD)
Input high voltage
• All pins
V
VIH
VIO_VDD+2V
Note: All 3.3-V supplies must rise prior to the rise of the 1.25-V supplies to avoid a high current condition and possible
system damage.
Input low voltage
• All pins
VIL
IIN
–0.3
—
—
—
0.8
84
V
Input leakage current
µA
pF
µA
V
Clock pin Input Capacitance (EXTAL)
High impedance (off-state) input current (@ 3.46V)
Output high voltage
CIN
ITSI
VOH
4.7
—
–10
2.4
84
—
—
•
•
I
OH = -5 mA
XTAL Pin IOH = -10mA
Output low voltage
VOL
—
—
0.4
V
•
•
IOL = 5 mA
XTAL Pin IOL = 10 mA
Internal supply current1 (core only) at internal clock of
150 MHz
• In Normal mode
ICCI
ICCW
ICCS
CIN
—
—
—
—
65
16
1.2
—
100
—
mA
mA
mA
pF
• In Wait mode
• In Stop mode2
—
Input capacitance
10
Note:
1
The Current Consumption section provides a formula to compute the estimated current requirements in Normal
mode. In order to obtain these results, all inputs must be terminated (i.e., not allowed to float). Measurements are
based on synthetic intensive DSP benchmarks. The power consumption numbers in this specification are 90% of
the measured results of this benchmark. This reflects typical DSP applications. Typical internal supply current is
measured with VCORE_VDD = 1.25V, VDD_IO = 3.3V at TJ = 25°C. Maximum internal supply current is measured
with VCORE_VDD = 1.30V, VIO_VDD) = 3.46V at TJ = 115°C.
2
In order to obtain these results, all inputs, which are not disconnected at Stop mode, must be terminated (i.e., not
allowed to float).
DSP56374 Data Sheet, Rev. 4.2
28
Freescale Semiconductor
AC Electrical Characteristics
9 AC Electrical Characteristics
The timing waveforms shown in the AC electrical characteristics section are tested with a V maximum
IL
of 0.8 V and a V minimum of 2.0 V for all pins. AC timing specifications, which are referenced to a
IH
device input signal, are measured in production with respect to the 50% point of the respective input
signal’s transition. DSP56374 output levels are measured with the production test machine V and V
OL
OH
reference levels set at 1.0 V and 1.8 V, respectively.
10 Internal Clocks
Table 18. INTERNAL CLOCKS1
No.
Characteristics
Symbol
Min
Typ
Max
Unit
Condition
1
2
3
Comparison Frequency
Input Clock Frequency
Fref
FIN
5
—
20
MHz Fref = FIN/NR
NR is input divider value
Fref*NR
Output clock Frequency (with
PLL enabled)2,3
FOUT
75
(Ef × MF x FM)/
(PDF × DF x OD)
150
MHz FOUT=FVCO/NO where
NO is output divider value
Tc
13.3
—
ns
4
5
Output clock Frequency (with
PLL disabled)2,3
FOUT
Ef
150
60
MHz
—
Duty Cycle
—
40
50
%
FVCO=300MHz~600MHz
Note:
1
See users manual for definition.
DF = Division Factor
2
Ef = External Frequency
Mf = Multiplication Factor
PDF = Predivision Factor
FM= Frequency Multiplier
OD = Output Divider
Tc = Internal Clock Period
Maximum frequency will vary depending on the ordered part number.
3
11 External Clock Operation
The DSP56374 system clock is derived from the on-chip oscillator or is externally supplied. To use the
on-chip oscillator, connect a crystal and associated resistor/capacitor components to EXTAL and XTAL;
an example is shown below.
DSP56374 Data Sheet, Rev. 4.2
Freescale Semiconductor
29
External Clock Operation
Suggested component values:
fosc = 24.576 MHz
R = 1 M 10%
C (EXTAL)= 18 pF
C (XTAL) = 47 pF
Calculations are for a 12 - 49 MHz crystal with the following parameters:
• shunt capacitance (C0) of 10 pF - 12 pF
• series resistance 40 Ohm
• drive level of 10 µW
If the DSP56374 system clock is an externally supplied square wave voltage source, it is connected to
EXTAL (Figure 2.). When the external square wave source connects to EXTAL, the XTAL pin is not used.
VIH
Midpoint
EXTAL
ETH
ETL
VIL
6
7
8
ETC
Note:
The midpoint is 0.5 (VIH + VIL).
Figure 2. External Clock Timing
Table 19. Clock Operation
No.
Characteristics
EXTAL input high 1
Symbol
Min
Max
Units
6
Eth
3.33
50
ns
(40% to 60% duty cycle)
7
8
EXTAL input low2
Etl
Etc
Icyc
3.33
50
ns
ns
ns
(40% to 60% duty cycle)
EXTAL cycle time
• With PLL disabled
• With PLL enabled
6.67
50
inf
200
3
9
Instruction cycle time= ICYC = TC
• With PLL disabled
• With PLL enabled
6.67
6.67
inf
13.33
DSP56374 Data Sheet, Rev. 4.2
30
Freescale Semiconductor
External Clock Operation
Max Units
Table 19. Clock Operation (continued)
Characteristics Symbol Min
No.
Note:
1
Measured at 50% of the input transition.
2
The indicated duty cycle is for the specified maximum frequency for which a part is rated. The
minimum clock high or low time required for correct operation, however, remains the same at lower
operating frequencies; therefore, when a lower clock frequency is used, the signal symmetry may
vary from the specified duty cycle as long as the minimum high time and low time requirements
are met.
3
A valid clock signal must be applied to the EXTAL pin within 3 ms of the DSP56374 being
powered up.
DSP56374 Data Sheet, Rev. 4.2
Freescale Semiconductor
31
Reset, Stop, Mode Select, and Interrupt Timing
12 Reset, Stop, Mode Select, and Interrupt Timing
Table 20. Reset, Stop, Mode Select, and Interrupt Timing
No.
Characteristics
Expression
Min
Max
Unit
10
Delay from RESET assertion to all pins at reset
value3
—
—
11
ns
11
13
Required RESET duration4
• Power on, external clock generator, PLL disabled
2 xTC
13.4
13.4
—
—
ns
ns
2 x TC
• Power on, external clock generator, PLL enabled
Syn reset deassert delay time
• Minimum
2× TC
13.4
5.0
—
—
—
—
—
ns
ms
ns
ns
ns
• Maximum (PLL enabled)
Mode select setup time
Mode select hold time
(2xTC)+TLOCK
14
15
16
10.0
10.0
13.4
Minimum edge-triggered interrupt request assertion
width
2 xTC
2 xTC
17
18
19
Minimum edge-triggered interrupt request
deassertion width
13.4
72
—
—
ns
ns
Delay from interrupt trigger to interrupt code
execution
10 × TC + 5
Duration of level sensitive IRQA assertion to ensure
interrupt service (when exiting Stop)1, 2, 3
• PLL is active during Stop and Stop delay is
enabled
(OMR Bit 6 = 0)
9+(128× TC)
25× TC
854
165
—
—
µs
• PLL is active during Stop and Stop delay is not
enabled
ns
(OMR Bit 6 = 1)
• PLL is not active during Stop and Stop delay is
enabled (OMR Bit 6 = 0)
9+(128xTC) + TLOCK
(25 x TC) + TLOCK
10 x TC + 3.0
5.7
5
ms
ms
ns
• PLL is not active during Stop and Stop delay is
not enabled (OMR Bit 6 = 1)
20
• Delay from IRQA, IRQB, IRQC, IRQD, NMI
assertion to general-purpose transfer output
valid caused by first interrupt instruction
execution1
69.0
DSP56374 Data Sheet, Rev. 4.2
32
Freescale Semiconductor
Reset, Stop, Mode Select, and Interrupt Timing
Table 20. Reset, Stop, Mode Select, and Interrupt Timing (continued)
No.
Characteristics
Interrupt Requests Rate1
Expression
Min
Max
Unit
21
12 x TC
• ESAI, ESAI_1, SHI, Timer
—
—
—
—
80.0
53.0
53.0
80.0
ns
ns
ns
ns
• DMA
8 x TC
8 x TC
• IRQ, NMI (edge trigger)
• IRQ (level trigger)
12 x TC
22
DMA Requests Rate
6 x TC
—
40.0
ns
• Data read from ESAI, ESAI_1, SHI
• Data write to ESAI, ESAI_1, SHI
• Timer
7 x TC
2 x TC
3 x TC
—
—
—
46.7
13.4
20.0
ns
ns
ns
• IRQ, NMI (edge trigger)
Note:
1
When using fast interrupts and IRQA, IRQB, IRQC, and IRQD are defined as level-sensitive, timings 19 through
21 apply to prevent multiple interrupt service. To avoid these timing restrictions, the Edge-triggered mode is
recommended when using fast interrupts. Long interrupts are recommended when using Level-sensitive mode.
2
For PLL disable, using external clock (PCTL Bit 16 = 1), no stabilization delay is required and recovery time will
be defined by the OMR Bit 6 settings.
For PLL enable, (if bet 12 of the PCTL register is 0), the PLL is shutdown during Stop. Recovering from Stop
requires the PLL to get locked. The PLL lock procedure duration, PLL Lock Cycles (PLC), may be in the range
of 0.5 ms.
3
4
Periodically sampled and not 100% tested.
RESET duration is measured during the time in which RESET is asserted, VDD is valid, and the EXTAL input is
active and valid. When the VDD is valid, but the other “required RESET duration” conditions (as specified
above) have not been yet met, the device circuitry will be in an uninitialized state that can result in significant
power consumption and heat-up. Designs should minimize this state to the shortest possible duration.
VIH
RESET
11
13
10
All Pins
Reset Value
Figure 3. Reset Timing
DSP56374 Data Sheet, Rev. 4.2
Freescale Semiconductor
33
Reset, Stop, Mode Select, and Interrupt Timing
19
18
IRQA, IRQB,
IRQC, IRQD,
NMI
a) First Interrupt Instruction Execution
General
Purpose
I/O
20
IRQA, IRQB,
IRQC, IRQD,
NMI
b) General Purpose I/O
Figure 4. External Fast Interrupt Timing
IRQA, IRQB,
IRQC, IRQD,
NMI
16
17
IRQA, IRQB,
IRQC, IRQD,
NMI
Figure 5. External Interrupt Timing (Negative Edge-Triggered)
VIH
RESET
14
15
VIH
VIL
VIH
VIL
IRQA, IRQB,
IRQC,IRQD, NMI
MODA, MODB,
MODC, MODD,
PINIT
Figure 6. Recovery from Stop State Using IRQA Interrupt Service
DSP56374 Data Sheet, Rev. 4.2
34
Freescale Semiconductor
Serial Host Interface SPI Protocol Timing
13 Serial Host Interface SPI Protocol Timing
Table 21. Serial Host Interface SPI Protocol Timing
No.
Characteristics1,3,4
Mode
Filter Mode
Bypassed
Very Narrow
Narrow
Expression
10.0 x TC + 9
10.0 x TC + 9
Min
76.0
76.0
Max
—
—
—
—
0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
23 Minimum serial clock cycle = tSPICC(min) Master/Slave
10.0 x TC + 133 200.0
10.0 x TC + 333 400.0
Wide
XX Tolerable Spike width on data or clock in.
—
Bypassed
Very Narrow
Narrow
—
—
—
—
10
50
100
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Wide
—
—
24 Serial clock high period
Master
Slave
Master
Slave
Bypassed
Very Narrow
Narrow
—
38.0
38.0
100.0
200.0
33.0
33.0
—
—
—
Wide
Bypassed
2.0 x TC + 19.6
Very Narrow 2.0 x TC + 19.6
Narrow
Wide
2.0 x TC + 86.6 100.0
2.0 x TC + 186.6 200.0
25 Serial clock low period
Bypassed
Very Narrow
Narrow
—
38.0
38.0
—
—
—
100.0
200.0
33.0
Wide
Bypassed
2.0 x TC + 19.6
Very Narrow 2.0 x TC + 19.6
33.0
Narrow
Wide
2.0 x TC + 86.6 100.0
2.0 x TC + 186.6 200.0
26 Serial clock rise/fall time
Master
Slave
—
—
—
—
—
—
—
—
5
ns
ns
DSP56374 Data Sheet, Rev. 4.2
Freescale Semiconductor
35
Serial Host Interface SPI Protocol Timing
Table 21. Serial Host Interface SPI Protocol Timing (continued)
No.
Characteristics1,3,4
Mode
Filter Mode
Bypassed
Very Narrow
Narrow
Expression
Min
26
16
0
Max
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
27 SS assertion to first SCK edge
Slave
2.0 x TC + 12.6
2.0 x TC + 2.6
—
CPHA = 0
2.0 x TC − 37.45
—
Wide
2.0 x TC − 87.45
0
—
CPHA = 1
Slave
Slave
Bypassed
Very Narrow
Narrow
—
—
10
0
—
—
—
0
—
Wide
—
0
—
28 Last SCK edge to SS not asserted
Bypassed
Very Narrow
Narrow
—
12
22
100
200
0
—
—
—
—
—
Wide
—
—
29 Data input valid to SCK edge (data input
set-up time)
Master
/Slave
Bypassed
Very Narrow
Narrow
—
—
—
0
—
—
0
—
Wide
—
0
—
30 SCK last sampling edge to data input not
valid
Master
/Slave
Bypassed
3.0 x TC
20
43.2
73.2
100.0
5
—
Very Narrow 3.0 x TC + 23.2
—
Narrow
Wide
—
3.0 x TC + 53.2
3.0 x TC + 80
—
—
—
31 SS assertion to data out active
Slave
Slave
—
32 SS deassertion to data high impedance2
—
—
—
9
33 SCK edge to data out valid
(data out delay time)
Master
/Slave
Bypassed
3.0 x TC + 26.1
—
46.2
110.4
136.4
223.4
—
Very Narrow 3.0 x TC + 90.4
—
Narrow
Wide
3.0 x TC + 116.4
3.0 x TC + 203.4
2.0 x TC
—
—
34 SCK edge to data out not valid
(data out hold time)
Master
/Slave
Bypassed
Very Narrow
Narrow
Wide
13.4
15
55
105
—
2.0 x TC + 1.6
2.0 x TC + 41.6
2.0 x TC + 91.6
—
—
—
—
35 SS assertion to data out valid
(CPHA = 0)
Slave
—
12.0
DSP56374 Data Sheet, Rev. 4.2
36
Freescale Semiconductor
Serial Host Interface SPI Protocol Timing
Table 21. Serial Host Interface SPI Protocol Timing (continued)
No.
Characteristics1,3,4
Mode
Filter Mode
Bypassed
Very Narrow
Narrow
Expression
3.0 x TC + 30
3.0 x TC + 40
3.0 x TC + 80
3.0 x TC + 120
4.0 x TC
Min
50
Max
—
—
—
—
—
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
36 SCK edge following the first SCK
sampling edge to HREQ output
deassertion
Slave
60
100
Wide
150
37 Last SCK sampling edge to HREQ output
not deasserted (CPHA = 1)
Slave
Slave
Bypassed
Very Narrow
Narrow
57.0
67.0
107.0
157.0
50.0
4.0 x TC
4.0 x TC
Wide
4.0 x TC
38 SS deassertion to HREQ output not
deasserted (CPHA = 0)
—
3.0 x TC + 30
39 SS deassertion pulse width (CPHA = 0)
40 HREQ in assertion to first SCK edge
Slave
—
2.0 x TC
13.4
63
—
—
ns
ns
Master
Bypassed
0.5 x TSPICC
+
3.0 x TC + 5
Very Narrow
Narrow
Wide
0.5 x TSPICC
3.0 x TC + 5
+
63
125
225
0
—
—
—
—
ns
ns
ns
ns
0.5 x TSPICC
3.0 x TC + 5
+
0.5 x TSPICC
3.0 x TC + 5
+
41 HREQ in deassertion to last SCK
sampling edge (HREQ in set-up time)
(CPHA = 1)
Master
—
—
42 First SCK edge to HREQ in not asserted
(HREQ in hold time)
Master
Master
—
—
—
0
—
—
ns
ns
43 HREQ assertion width
3.0 x TC
20
Note:
1
VCORE_VDD = 1.2 5 0.05 V; TJ = -40°C to 110°C (52 LQFP) / -40°C to 105°C (80 LQFP), CL = 50 pF
Periodically sampled, not 100% tested
All times assume noise free inputs.
All times assume internal clock frequency of 150 MHz.
Equation applies when the result is positive TC.
2
3
4
5
DSP56374 Data Sheet, Rev. 4.2
Freescale Semiconductor
37
Serial Host Interface SPI Protocol Timing
SS
(Input)
25
23
23
24
26
26
26
26
SCK (CPOL = 0)
(Output)
24
25
SCK (CPOL = 1)
(Output)
29
30
29
30
MISO
(Input)
MSB
Valid
LSB
Valid
34
33
MSB
MOSI
(Output)
LSB
40
42
HREQ
(Input)
43
Figure 7. SPI Master Timing (CPHA = 0)
DSP56374 Data Sheet, Rev. 4.2
38
Freescale Semiconductor
Serial Host Interface SPI Protocol Timing
SS
(Input)
25
24
23
26
24
25
26
SCK (CPOL = 0)
(Output)
23
26
26
SCK (CPOL = 1)
(Output)
29
29
30
30
MISO
(Input)
MSB
Valid
LSB
Valid
33
34
MOSI
(Output)
MSB
LSB
40
41
42
HREQ
(Input)
43
Figure 8. SPI Master Timing (CPHA = 1)
DSP56374 Data Sheet, Rev. 4.2
Freescale Semiconductor
39
Serial Host Interface SPI Protocol Timing
SS
(Input)
25
23
23
28
24
26
26
26
39
SCK (CPOL = 0)
(Input)
27
24
26
25
SCK (CPOL = 1)
(Input)
35
33
34
34
32
31
MISO
(Output)
MSB
LSB
29
29
30
30
MSB
Valid
MOSI
(Input)
LSB
Valid
36
38
HREQ
(Output)
Figure 9. SPI Slave Timing (CPHA = 0)
DSP56374 Data Sheet, Rev. 4.2
40
Freescale Semiconductor
Serial Host Interface (SHI) I2C Protocol Timing
SS
(Input)
25
23
28
24
26
26
26
SCK (CPOL = 0)
(Input)
27
24
26
25
SCK (CPOL = 1)
(Input)
33
33
34
32
31
MISO
(Output)
MSB
LSB
29
29
30
30
MSB
Valid
LSB
Valid
MOSI
(Input)
37
36
HREQ
(Output)
Figure 10. SPI Slave Timing (CPHA = 1)
2
14 Serial Host Interface (SHI) I C Protocol Timing
Table 22. SHI I2C Protocol Timing
Standard I2C
Standard
Min Max
Fast-Mode
Min
Unit
Symbol/
Expression
No.
Characteristics1,2,3,4,5
Max
XX Tolerable Spike Width on SCL or SDA
Filters Bypassed
—
—
—
—
—
0
—
—
—
—
0
ns
ns
ns
ns
Very Narrow Filters enabled
Narrow Filters enabled
10
10
50
50
Wide Fileters enabled.
100
100
44 SCL clock frequency
44 SCL clock cycle
FSCL
TSCL
—
10
100
—
—
400
—
kHz
µs
2.5
1.3
0.6
45 Bus free time
TBUF
4.7
4.7
—
—
µs
46 Start condition set-up time
TSUSTA
—
—
µs
DSP56374 Data Sheet, Rev. 4.2
Freescale Semiconductor
41
Serial Host Interface (SHI) I2C Protocol Timing
Table 22. SHI I2C Protocol Timing (continued)
Standard I2C
Standard
Fast-Mode
Unit
Symbol/
No.
Characteristics1,2,3,4,5
Expression
Min
Max
—
Min
0.6
1.3
1.3
—
Max
—
47 Start condition hold time
48 SCL low period
THD;STA
TLOW
4.0
4.7
4.0
—
µs
µs
µs
ns
ns
ns
µs
—
—
49 SCL high period
THIGH
—
—
50 SCL and SDA rise time
51 SCL and SDA fall time
52 Data set-up time
T
5.0
5.0
—
5.0
5.0
—
R
T
F
—
—
TSU;DAT
THD;DAT
FOSC
250
0.0
100
0.0
53 Data hold time
—
0.9
54 DSP clock frequency
• Filters bypassed
10.6
10.6
11.8
13.1
—
—
—
—
28.5
28.5
39.7
61.0
—
—
—
—
MHz
MHz
MHz
MHz
• Very Narrrow filters enabled
• Narrow filters enabled
• Wide filters enabled
55 SCL low to data out valid
56 Stop condition setup time
TVD;DAT
TSU;STO
tSU;RQI
—
3.4
—
—
0.9
—
µs
µs
ns
4.0
0.0
0.6
0.0
57 HREQ in deassertion to last SCL edge
(HREQ in set-up time)
—
—
58 First SCL sampling edge to HREQ output
deassertion2
TNG;RQO
4 × TC + 30
4 × TC + 50
4 × TC + 130
4 × TC + 230
• Filters bypassed
—
—
—
—
57.0
77.0
—
—
57.0
67.0
ns
ns
ns
ns
• Very Narrow filters enabled
• Narrow filters enabled
• Wide filters enabled
157.0
257.0
—
—
157.0
257.0
59 Last SCL edge to HREQ output not
deasserted2
TAS;RQO
2 × TC + 30
2 × TC + 40
2 × TC + 80
2 × TC + 130
44
54
—
—
—
—
44
54
—
—
—
—
ns
ns
ns
ns
• Filters bypassed
• Very Narrow filters enabled
• Narrow filters enabled
• Wide filters enabled
94
94
144
144
60 HREQ in assertion to first SCL edge
• Filters bypassed
TAS;RQI
4327
4317
4282
4227
—
—
—
—
927
917
877
827
—
—
—
—
ns
ns
ns
ns
• Very Narrow filters enabled
• Narrow filters enabled
• Wide filters enabled
61 First SCL edge to HREQ is not asserted
(HREQ in hold time.)
tHO;RQI
0.0
—
0.0
—
ns
DSP56374 Data Sheet, Rev. 4.2
42
Freescale Semiconductor
Programming the Serial Clock
Table 22. SHI I2C Protocol Timing (continued)
Standard I2C
Standard
Symbol/
Fast-Mode
Min Max
Unit
No.
Characteristics1,2,3,4,5
Expression
Min
Max
Note:
1
VCORE_VDD = 1.2 5 0.05 V; TJ = -40°C to 110°C (52 LQFP) / -40°C to 105°C (80 LQFP), CL = 50 pF
Pull-up resistor: R P (min) = 1.5 kOhm
Capacitive load: C b (max) = 50 pF
All times assume noise free inputs
All times assume internal clock frequency of 150MHz
2
3
4
5
15 Programming the Serial Clock
2
The programmed serial clock cycle, T
HCKR (SHI clock control register).
, is specified by the value of the HDM[7:0] and HRS bits of the
I CCP
2
The expression for T
is
I CCP
TI2CCP = [TC × 2 × (HDM[7:0] + 1) × (7 × (1 – HRS) + 1)]
Eqn. 1
where
— HRS is the prescaler rate select bit. When HRS is cleared, the fixed
divide-by-eight prescaler is operational. When HRS is set, the prescaler is bypassed.
— HDM[7:0] are the divider modulus select bits. A divide ratio from 1 to 256 (HDM[7:0] = $00
to $FF) may be selected.
2
In I C mode, the user may select a value for the programmed serial clock cycle from
6 × TC (if HDM[7:0] = $02 and HRS = 1)
Eqn. 2
to
4096 × TC (if HDM[7:0] = $FF and HRS = 0)
Eqn. 3
2
The programmed serial clock cycle (T
) should be chosen in order to achieve the desired SCL serial
I CCP
clock cycle (T ), as shown in Table 23.
SCL
Table 23. SCL Serial Clock Cycle (TSCL) Generated as Master
2
Nominal
TI CCP + 3 × TC + 45ns + TR
DSP56374 Data Sheet, Rev. 4.2
Freescale Semiconductor
43
Enhanced Serial Audio Interface Timing
44
46
49
48
SCL
SDA
50
53
51
45
52
MSB
LSB
ACK
Stop
Stop
Start
47
60
58
55
56
59
61
57
HREQ
Figure 11. I2C Timing
16 Enhanced Serial Audio Interface Timing
Table 24. Enhanced Serial Audio Interface Timing
No.
Characteristics1, 2, 3
Symbol
Expression3
Min
Max
Condition4
Unit
62 Clock cycle5
tSSICC
4 × T
4 × T
26.4
26.4
—
—
x ck
i ck
ns
c
c
63 Clock high period
tSSICCH
ns
ns
• For internal clock
• For external clock
64 Clock low period
2 × T − 0.5
12.8
13.4
—
—
c
2 × T
c
tSSICCL
• For internal clock
2 × T
2 × T
—
13.4
13.4
—
—
c
c
• For external clock
65 SCKR edge to FSR out (bl) high
—
—
—
—
—
—
—
17.0
7.0
x ck
ns
ns
ns
ns
ns
i ck a
66 SCKR edge to FSR out (bl) low
67 SCKR edge to FSR out (wr) high6
68 SCKR edge to FSR out (wr) low6
69 SCKR edge to FSR out (wl) high
—
—
—
—
—
—
17.0
7.0
x ck
i ck a
—
—
19.0
9.0
x ck
i ck a
—
—
19.0
9.0
x ck
i ck a
—
—
16.0
6.0
x ck
i ck a
DSP56374 Data Sheet, Rev. 4.2
44
Freescale Semiconductor
Enhanced Serial Audio Interface Timing
Table 24. Enhanced Serial Audio Interface Timing (continued)
No.
Characteristics1, 2, 3
Symbol
Expression3
Min
Max
Condition4
Unit
70 SCKR edge to FSR out (wl) low
—
—
—
—
17.0
7.0
x ck
ns
i ck a
71 Data in setup time before SCKR (SCK in
synchronous mode) edge
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
12.0
19.0
—
—
x ck
i ck
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
72 Data in hold time after SCKR edge
73 FSR input (bl, wr) high before SCKR edge 6
74 FSR input (wl) high before SCKR edge
75 FSR input hold time after SCKR edge
76 Flags input setup before SCKR edge
77 Flags input hold time after SCKR edge
78 SCKT edge to FST out (bl) high
79 SCKT edge to FST out (bl) low
3.5
9.0
—
—
x ck
i ck
2.0
—
—
x ck
12.0
i ck a
2.0
—
—
x ck
12.0
i ck a
2.5
8.5
—
—
x ck
i ck a
0.0
—
—
x ck
19.0
i ck s
6.0
0.0
—
—
x ck
i ck s
—
—
18.0
8.0
x ck
i ck
—
—
20.0
10.0
x ck
i ck
80 SCKT edge to FST out (wr) high6
81 SCKT edge to FST out (wr) low6
82 SCKT edge to FST out (wl) high
83 SCKT edge to FST out (wl) low
—
—
20.0
10.0
x ck
i ck
—
—
22.0
12.0
x ck
i ck
—
—
19.0
9.0
x ck
i ck
—
—
20.0
10.0
x ck
i ck
84 SCKT edge to data out enable from high
impedance
—
—
22.0
17.0
x ck
i ck
85 SCKT edge to transmitter #0 drive enable
assertion
—
—
17.0
11.0
x ck
i ck
86 SCKT edge to data out valid
—
—
18.0
13.0
x ck
i ck
87 SCKT edge to data out high impedance7
—
—
21.0
16.0
x ck
i ck
DSP56374 Data Sheet, Rev. 4.2
Freescale Semiconductor
45
Enhanced Serial Audio Interface Timing
Table 24. Enhanced Serial Audio Interface Timing (continued)
No.
Characteristics1, 2, 3
Symbol
Expression3
Min
Max
Condition4
Unit
88 SCKT edge to transmitter #0 drive enable
deassertion7
—
—
—
—
14.0
9.0
x ck
i ck
ns
89 FST input (bl, wr) setup time before SCKT
edge6
—
—
—
—
—
—
2.0
—
—
x ck
i ck
ns
ns
ns
18.0
90 FST input (wl) setup time before SCKT
edge
2.0
—
—
x ck
i ck
18.0
91 FST input hold time after SCKT edge
4.0
5.0
—
—
x ck
i ck
92 FST input (wl) to data out enable from high
impedance
—
—
—
—
—
—
—
21.0
—
ns
ns
ns
93 FST input (wl) to transmitter #0 drive enable
assertion
—
14.0
—
94 Flag output valid after SCKT rising edge
—
—
14.0
9.0
x ck
i ck
95 HCKR/HCKT clock cycle
—
—
—
2 x TC
—
13.4
—
—
ns
ns
ns
96 HCKT input edge to SCKT output
97 HCKR input edge to SCKR output
18.0
18.0
—
—
Note:
1
VCORE_VDD = 1.25 0.05 V; TJ = -40°C to 110°C (52 LQFP) / -40°C to 105°C (80 LQFP), CL = 50 pF
i ck = internal clock
2
x ck = external clock
i ck a = internal clock, asynchronous mode
(asynchronous implies that SCKT and SCKR are two different clocks)
i ck s = internal clock, synchronous mode
(synchronous implies that SCKT and SCKR are the same clock)
bl = bit length
wl = word length
wr = word length relative
SCKT(SCKT pin) = transmit clock
3
4
SCKR(SCKR pin) = receive clock
FST(FST pin) = transmit frame sync
FSR(FSR pin) = receive frame sync
HCKT(HCKT pin) = transmit high frequency clock
HCKR(HCKR pin) = receive high frequency clock
For the internal clock, the external clock cycle is defined by Icyc and the ESAI control register.
The word-relative frame sync signal waveform relative to the clock operates in the same manner as the bit-length frame
sync signal waveform, but spreads from one serial clock before first bit clock (same as bit length frame sync signal), until
the one before last bit clock of the first word in frame.
5
6
7
8
Periodically sampled and not 100% tested.
ESAI_1 specs match those of ESAI.
DSP56374 Data Sheet, Rev. 4.2
46
Freescale Semiconductor
Enhanced Serial Audio Interface Timing
62
63
64
SCKT
(Input/Output)
78
79
FST (Bit) Out
83
84
FST (Word) Out
87
85
87
88
Data Out
First Bit
Last Bit
92
Transmitter #0
Drive Enable
90
86
89
94
FST (Bit) In
91
94
93
FST (Word) In
Flags Out
95
See Note
Note:
In network mode, output flag transitions can occur at the start of each time slot within the
frame. In normal mode, the output flag state is asserted for the entire frame period.
Figure 12 is drawn assuming positive polarity bit clock (TCKP=0) and positive frame sync
polarity (TFSP=0).
Figure 12. ESAI Transmitter Timing
DSP56374 Data Sheet, Rev. 4.2
Freescale Semiconductor
47
Enhanced Serial Audio Interface Timing
62
63
64
SCKR
(Input/Output)
65
66
FSR (Bit)
Out
69
70
FSR (Word)
Out
72
71
Data In
Last Bit
First Bit
75
73
FSR (Bit)
In
74
75
77
FSR (Word)
In
76
Flags In
Note:
Figure 13 is drawn assuming positive polarity bit clock (RCKP=0) and positive frame sync polarity
(RFSP=0).
Figure 13. ESAI Receiver Timing
DSP56374 Data Sheet, Rev. 4.2
48
Freescale Semiconductor
Timer Timing
HCKT
95
SCKT (output)
96
Note: Figure 14 is drawn assuming positive polarity high frequency clock (THCKP=0) and positive bit clock polarity (TCKP=0).
Figure 14. ESAI HCKT Timing
HCKR
95
SCKR (output)
97
Note: Figure 15 is drawn assuming positive polarity high frequency clock (RHCKP=0) and positive bit clock polarity (RCKP=0).
Figure 15. ESAI HCKR Timing
17 Timer Timing
Table 25. Timer Timing
150 MHz
No.
Characteristics
Expression
Unit
Min
15.4
15.4
Max
—
98
99
TIO Low
TIO High
2 × TC + 2.0
2 × TC + 2.0
ns
ns
—
Note:
V
= 1.25 V 0.05 V; T = -40°C to 110°C (52 LQFP) / -40°C to 105°C (80 LQFP), C = 50 pF
CORE_VDD J L
TIO
98
99
Figure 16. TIO Timer Event Input Restrictions
DSP56374 Data Sheet, Rev. 4.2
Freescale Semiconductor
49
GPIO Timing
18 GPIO Timing
Table 26. GPIO Timing
No.
Characteristics1
Expression
Min
—
Max
7
Unit
ns
ns
ns
ns
ns
ns
ns
ns
100 EXTAL edge to GPIO out valid (GPIO out delay time)2
101 EXTAL edge to GPIO out not valid (GPIO out hold time)2
102 GPIO In valid to EXTAL edge (GPIO in set-up time)2
103 EXTAL edge to GPIO in not valid (GPIO in hold time)2
104 Minimum GPIO pulse high width
—
7
2
—
0
—
TC + 13
TC + 13
—
19.7
19.7
—
—
105 Minimum GPIO pulse low width
—
106 GPIO out rise time
13.0
13.0
107 GPIO out fall time
—
—
Note:
1
VCORE_VDD = 1.25 V 0.05 V; TJ = -40°C to 110°C (52 LQFP) / -40°C to 105°C (80 LQFP), CL = 50 pF
PLL Disabled, EXTAL driven by a square wave.
2
EXTAL
100
101
GPIO
(Output)
102
103
GPIO
(Input)
Valid
GPIO
(Output)
104
105
106
107
Figure 17. GPIO Timing
Table 27. JTAG Timing
19 JTAG Timing
All frequencies
No.
Characteristics
Unit
Min
Max
108 TCK frequency of operation (1/(TC × 3); maximum 10 MHz)
—
10.0
MHz
DSP56374 Data Sheet, Rev. 4.2
50
Freescale Semiconductor
JTAG Timing
Table 27. JTAG Timing (continued)
Characteristics
All frequencies
No.
Unit
Min
100.0
50.0
—
Max
—
109 TCK cycle time in Crystal mode
110 TCK clock pulse width measured at 1.65 V
111 TCK rise and fall times
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
—
3.0
—
112 Boundary scan input data setup time
113 Boundary scan input data hold time
114 TCK low to output data valid
115 TCK low to output high impedance
116 TMS, TDI data setup time
117 TMS, TDI data hold time
15.0
24.0
—
—
40.0
40.0
—
—
5.0
25.0
—
—
118 TCK low to TDO data valid
119 TCK low to TDO high impedance
Note:
44.0
44.0
—
1. V
= 1.25 V 0.05 V; T = -40°C to 110°C (52 LQFP) / -40°C to 105°C (80 LQFP), C = 50 pF
J L
CORE_VDD
2. All timings apply to OnCE module data transfers because it uses the JTAG port as an interface.
109
110
VM
110
VM
VIH
111
Figure 18. Test Clock Input Timing Diagram
TCK
(Input)
VIL
111
DSP56374 Data Sheet, Rev. 4.2
Freescale Semiconductor
51
JTAG Timing
VIH
TCK
(Input)
VIL
112
113
Data
Inputs
Input Data Valid
114
115
114
Data
Output Data Valid
Outputs
Data
Outputs
Data
Outputs
Output Data Valid
Figure 19. Debugger Port Timing Diagram
VIH
117
TCK
(Input)
VIL
116
TDI
TMS
Input Data Valid
(Input)
118
TDO
(Output)
Output Data Valid
119
TDO
(Output)
118
TDO
(Output)
Output Data Valid
Figure 20. Test Access Port Timing Diagram
DSP56374 Data Sheet, Rev. 4.2
52
Freescale Semiconductor
Watchdog Timer Timing
20 Watchdog Timer Timing
Table 28. Watchdog Timer Timing
Characteristics Expression
2 × T
No.
Min
13.4
13.4
Max
—
Unit
ns
120 Delay from time-out to fall of TIO1
121 Delay from timer clear to rise of TIO1
c
2 x Tc
—
ns
DSP56374 Data Sheet, Rev. 4.2
Freescale Semiconductor
53
Watchdog Timer Timing
Appendix A
Package Information
A.1 DSP56374 Pinout
IO_Vdd
1
2
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
SDO5_1_PE6
SDO4_1_PE7
SDO3_PC8
SDO2_PC9
SDO1_PC10
SDO0_PC11
SDO3_1_PE8
SDO2_1_PE9
Core_Vdd
MODA_IRQA_PH0
MODB_IRQB_PH1
GPIO_PG13
GPIO_PG12
MODC_IRQC_PH2
MODD_IRQD_PH3
GPIO_PG11
Core_Vdd
3
4
5
6
7
8
9
Core_Gnd
10
11
12
13
14
15
16
17
18
19
20
Core_Gnd
GPIO_PG10
GPIO_PG9
SDO1_1_PE10
SDO0_1_PE11
PINIT_NMI
IO_Vdd
HREQ_PH4
SS_HA2
SCK_SCL
XTAL
MISO_SDA
MOSI_HA0
EXTAL
PLLD_Vdd
PLLD_Gnd
PLLP_Gnd
PLLP_Vdd
GPIO_PG8
GPIO_PG7
IO_Gnd
1.25 V
Filter
3.3 V
Figure A-1. 80-Pin Vdd Connections
DSP56374 Data Sheet, Rev. 4.2
54
Freescale Semiconductor
Watchdog Timer Timing
IO_Vdd
1
2
39
38
37
36
35
34
33
32
31
30
29
28
27
SDO3_PC8
SDO2_PC9
SDO1_PC10
SDO0_PC11
Core_Vdd
Core_Gnd
PINIT_NMI
XTAL
MODA_IRQA_PH0
MODB_IRQB_PH1
MODC_IRQC_PH2
MODD_IRQD_PH3
Core_Vdd
3
4
5
6
Core_Gnd
7
HREQ_PH4
SS_HA2
8
9
EXTAL
SCK_SCL
10
11
12
13
PLLD_Vdd
PLLD_Gnd
PLLP_Gnd
PLLP_Vdd
MISO_SDA
MOSI_HA0
IO_Gnd
1.25 V
Filter
3.3 V
Figure A-2. 52-pin Vdd Connections
DSP56374 Data Sheet, Rev. 4.2
Freescale Semiconductor
55
Watchdog Timer Timing
A.2 Package Information
A.2.1 80-Pin Package
.
DSP56374 Data Sheet, Rev. 4.2
56
Freescale Semiconductor
Watchdog Timer Timing
DSP56374 Data Sheet, Rev. 4.2
Freescale Semiconductor
57
Watchdog Timer Timing
DSP56374 Data Sheet, Rev. 4.2
58
Freescale Semiconductor
Watchdog Timer Timing
.
DSP56374 Data Sheet, Rev. 4.2
Freescale Semiconductor
59
Watchdog Timer Timing
A.2.2 52-Pin Package
DSP56374 Data Sheet, Rev. 4.2
60
Freescale Semiconductor
Watchdog Timer Timing
DSP56374 Data Sheet, Rev. 4.2
Freescale Semiconductor
61
Watchdog Timer Timing
DSP56374 Data Sheet, Rev. 4.2
62
Freescale Semiconductor
Watchdog Timer Timing
DSP56374 Data Sheet, Rev. 4.2
Freescale Semiconductor
63
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DSP56374
Rev. 4.2, 1/2007
相关型号:
DSP56309VF100
Digital Signal Processor, 24-Bit Size, 24-Ext Bit, 100MHz, CMOS, PBGA196, MOLD ARRAY PROCESS, BGA-196
MOTOROLA
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