DSPB56364AF100 [FREESCALE]
DSPB56364AF100;
| 型号： | DSPB56364AF100 |
| 厂家： | 
Freescale |
| 描述： | DSPB56364AF100 |
| 文件： | 总55页 (文件大小：1214K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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Freescale Semiconductor
Data Sheet: Technical Data
Document Number: DSP56720
Rev.1, 12/2007
DSP56720 / DSP56721
DSP56720
144-Pin LQFP
20 mm x 20 mm
0.5 mm pitch
80-Pin LQFP
SymphonyTM DSP56720 /
DSP56721 Multi-Core Audio
Processors
DSP56721
14 mm x 14 mm
0.65 mm pitch
144-Pin LQFP
20 mm x 20 mm
0.5 mm pitch
The Symphony DSP56720/DSP56721 Multi-Core Audio
Processors are part of the DSP5672x family of programmable
CMOS DSPs, designed using multiple DSP56300 24-bit
cores.
Ordering Information
Device Marking or
The DSP56720/DSP56721 devices are intended for
Device
Operating Temperature LQFP Package
Range
automotive, consumer, and professional audio applications
that require high performance for audio processing. In
addition, the DSP56720 is ideally suited for applications that
need the capability to expand memory off-chip or to interface
to external parallel peripherals. Potential applications include
A/V receivers, HD-DVD and Blu-Ray players, car
DSP56720
DSPA56720AG
DSPB56720AG
DSPA56721AG
DSPB56721AG
DSPA56721AF
DSPB56721AF
20 mm x 20 mm
20 mm x 20 mm
20 mm x 20 mm
20 mm x 20 mm
14 mm x 14 mm
14 mm x 14 mm
DSP56720
audio/amplifiers, and professional recording equipment.
The DSP56720/DSP56721 devices excel at audio processing
for automotive and consumer audio applications requiring
high MIPs. Higher MIPs and memory requirements are driven
by the new high-definition audio standards (Dolby Digital+,
Dolby TrueHD, DTS-HD, for example) and the desire to
process multiple audio streams.
Communication (ICC), an External Memory Controller
(EMC) to support SDRAM, and a Sony/Philips Digital
Interface (S/PDIF).
The DSP56720/DSP56721 offer 200 million instructions per
second (MIPs) per core using an internal 200 MHz clock.
In addition, DSP56720/DSP56721 devices are optimal for the
professional audio market requiring audio recording, signal
processing, and digital audio synthesis.
The DSP56720/DSP56721 are high density CMOS devices
with 3.3 V inputs and outputs.
The DSP56720/DSP56721 processors provide a wealth of
on-chip audio processing functions, via a plug and play
software architecture system that supports audio decoding
algorithms, various equalization algorithms, compression,
signal generator, tone control, fade/balance, level
meter/spectrum analyzer, among others. The
The DSP56720 device is slightly different than the DSP56721
device—the DSP56720 includes an external memory
interface while the DSP56721 device does not. The
DSP56720 block diagram is shown in Figure 1; the
DSP56721 block diagram is shown in Figure 2.
DSP56720/DSP56721 devices also support various matrix
decoders and sound field processing algorithms.
With two DSP56300 cores, a single DSP56720 or DSP56721
device can replace dual-DSP designs, saving costs while
meeting high MIPs requirements. Legacy peripherals from
the previous DSP5636x/7x families are included, as well as a
variety of new modules. Included among the new modules are
an Asynchronous Sample Rate Converter (ASRC), Inter-Core
Freescale reserves the right to change the detail specifications as may be required to permit
improvements in the design of its products.
© Freescale Semiconductor, Inc., 2006, 2007. All rights reserved.
Table of Contents
1
2
Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2.2.3 Programming the SHI I2C Serial Clock . . . . . . 26
2.2.4 Enhanced Serial Audio Interface (ESAI) Timing27
2.2.5 Timer Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.2.6 GPIO Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.2.7 JTAG Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.2.8 Watchdog Timer Timing . . . . . . . . . . . . . . . . . . 35
2.2.9 Host Data Interface (HDI24) Timing. . . . . . . . . 35
2.2.10 S/PDIF Timing . . . . . . . . . . . . . . . . . . . . . . . . . 42
2.2.11 EMC Timing (DSP56720 only). . . . . . . . . . . . . 43
Functional Description and Application Information . . . . . . . 48
Hardware Design Considerations . . . . . . . . . . . . . . . . . . . . . 48
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
6.1 80-Pin Package Outline Drawing. . . . . . . . . . . . . . . . . 48
6.2 144-Pin Package Outline Drawing. . . . . . . . . . . . . . . . 51
Product Documentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
1.1 Pinout for DSP56720 144-Pin Plastic LQFP Package . .4
1.2 Pinout for DSP56721 80-Pin Plastic LQFP Package . . .6
1.3 Pinout for DSP56721 144-Pin Plastic LQFP Package . .7
1.4 Pin Multiplexing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
2.1 Chip-Level Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . .8
2.1.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . .8
2.1.2 Thermal Characteristics. . . . . . . . . . . . . . . . . . .10
2.1.3 Power Requirements . . . . . . . . . . . . . . . . . . . . .10
2.1.4 DC Electrical Characteristics. . . . . . . . . . . . . . .11
2.1.5 AC Electrical Characteristics . . . . . . . . . . . . . . .12
2.1.6 Internal Clocks . . . . . . . . . . . . . . . . . . . . . . . . .12
2.1.7 External Clock Operation. . . . . . . . . . . . . . . . . .13
2.1.8 Reset, Stop, Mode Select, and Interrupt Timing14
2.2 Module-Level Specifications . . . . . . . . . . . . . . . . . . . . .17
2.2.1 Serial Host Interface (SHI) SPI Protocol Timing 18
2.2.2 Serial Host Interface (SHI) I2C Protocol Timing.24
3
4
5
6
7
8
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1
Freescale Semiconductor
2
EXTAL/XTAL
DSP
Core-0
DSP
Core-1
CGM
ASRC
On-Chip
Memory
On-Chip
Memory
Arbiter 9
Arbiter 8
Shared Bus 0
P
X
Y
P
X
Y
Shared Bus 1
Arbiters 0–7
PCU
PCU
DMA
OnCE
OnCE
DMA
/ AGU
/ ALU
/ AGU
/ ALU
Shared Memory 8K
Blocks 0–7 (64K total)
MODA0, MODB0,
MODC0, MODD0
2 JTAGs
JTAG
MODA1, MODB1,
MODC1, MODD1
Figure 1. DSP56720 Block Diagram
HDI24
EXTAL/XTAL
DSP
Core-0
DSP
Core-1
CGM
ASRC
On-Chip
Memory
On-Chip
Memory
Arbiter 8
Shared Bus 0
Shared Bus 1
P
X
Y
P
X
Y
Arbiters 0–7
PCU
PCU
DMA
OnCE
OnCE
DMA
/ AGU
/ ALU
/ AGU
/ ALU
Shared Memory 8K
Blocks 0–7 (64K total)
MODA0, MODB0,
MODC0, MODD0
2 JTAGs
JTAG
MODA1, MODB1,
MODC1, MODD1
Figure 2. DSP56721 Block Diagram
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1
Freescale Semiconductor
3
1
Pin Assignments
DSP56720 devices are available in one package type; DSP56721 devices are available in two package types. For the pin
assignments of a specific device in a specific package, please see sections 1.2–1.1.
Table 1. Pin Assignments by Package
Device
Package
See
DSP56720
DSP56721
144-pin plastic LQFP
80-pin plastic LQFP
144-pin plastic LQFP
Figure 3 on page 5
Figure 4 on page 6
Figure 5 on page 7
For more detailed information about signals, refer to the DSP56720/DSP56721 Reference Manual (DSP56720RM).
1.1
Pinout for DSP56720 144-Pin Plastic LQFP Package
For the pinout of the DSP56720 144-pin plastic LQFP package, see Figure 3.
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1
Freescale Semiconductor
4
CORE_VDD
CORE_GND
LALE
1
2
108
107
106
105
104
103
102
101
100
99
IO_GND
IO_VDD
3
WDT
LCS0
4
PINIT/NMI
TDO
LCS1
5
LCS2
6
TDI
LCS3
7
TCK
LCS4
8
TMS
LCS5
9
SDO2_1/SDI3_1
SDO3_1/SDI2_1
SDO4_1/SDI1_1
SDO5_1/SDI0_1
CORE_GND
CORE_VDD
FSR
LCS6
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
LCS7
98
IO_VDD
IO_GND
CORE_VDD
CORE_GND
LWE
97
96
95
DSP56720
144-Pin
94
93
SCKR
LOE
LGPL5
LSDA10
LCKE
LCLK
LBCTL
92
HCKR
91
SCKT
90
FST
89
HCKT
88
SDO2/SDI3
SDO3/SDI2
SDO4/SDI1
SDO5/SDI0
SPDIFOUT1
SPDIFIN1
IO_GND
87
LSDWE
LSDCAS
LGTA
86
85
84
LA0
83
LA1
82
LA2
81
IO_VDD
IO_VDD
IO_GND
PLLP1_GND
PLLP1_VDD
PLLD1_GND
PLLD1_VDD
PLLA1_GND
PLLA1_VDD
80
EXTAL
79
XTAL
78
PLLP_GND
PLLD_GND
PLLD_VDD
PLLA_GND
PLLA_VDD
PLLP_VDD
77
76
75
74
73
Figure 3. DSP56720 144-Pin Package Pinout
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1
Freescale Semiconductor
5
1.2
Pinout for DSP56721 80-Pin Plastic LQFP Package
For the pinout of the DSP56721 80-pin plastic LQFP package, see Figure 4.
SDO2_3/SDI3_3
SDO3_3/SDI2_3
SDO4_3/SDI1_3
SDO5_3/SDI0_3
IO_VDD
1
2
3
4
5
6
7
8
9
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
WDT
PINIT/NMI
TDO
TDI
TCK
IO_GND
TMS
CORE_VDD
CORE_GND
CORE_VDD
SDO4/SDI1
SDO5/SDI0
IO_GND
IO_VDD
EXTAL
CORE_GND
DSP56721
80-Pin
SPDIFIN1/SDO2_2/SDI3_2
SPDIFOUT1/SDO3_2/SDI2_2 10
SDO4_2/SDI1_2
SDO5_2/SDI0_2
FSR_3
11
12
13
14
15
16
17
18
19
20
SCKR_3
SCKT_3
GND
XTAL
PLLP_GND
PLLD_GND
PLLD_VDD
PLLA_GND
PLLA_VDD
PLLP_VDD
GND
GND
GND
GND
Figure 4. DSP56721 80-Pin Package
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1
6
Freescale Semiconductor
1.3
Pinout for DSP56721 144-Pin Plastic LQFP Package
For the pinout of the DSP56721 144-pin plastic LQFP package, see Figure 5.
TIO0/H15/HAD15
PG18/HDI_SEL
IO_GND
1
2
108
107
106
105
104
103
102
101
100
99
IO_GND
IO_VDD
3
WDT
TIO0_1/H18/HAD18
CORE_VDD
CORE_GND
SDO2_3/SDI3_3
SDO3_3/SDI2_3
SDO4_3/SDI1_3
SDO5_3/SDI0_3
IO_VDD
4
PIINT/NMI
TDO
5
6
TDI
7
TCK
8
TMS
9
SCKR_1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
FSR_1
98
SCKT_1
IO_GND
97
FST_1
CORE_VDD
CORE_GND
SDO2_2/SDI3_2
SDO3_2/SDI2_2
SDO4_2/SDI1_2
SDO5_2/SDI0_2
HCKR_3
96
SDO0_1
95
SDO1_1
DSP56721
144-Pin
94
IO_GND
93
IO_VDD
92
CORE_GND
CORE_VDD
SDO0
91
90
FSR_3
89
SDO1
SCKR_3
88
SDO4/SDI1
SDO5/SDI0
SPDIFOUT1/H12/HAD12
SPDIFIN1/H8/HAD8
HACK/HRRQ
HOREQ/HTRQ
IO_GND
SCKT_3
87
IO_VDD
86
IO_GND
85
H6/HAD6
84
H7/HAD7
83
SPDIFIN2/H9/HAD9
SPDIFIN3/H10/HAD10
SPDIFIN4/H11/HAD11
SPDIFOUT2/H13/HAD13
SPLOCK/H14/HAD14
GND
82
81
IO_VDD
80
EXTAL
79
XTAL
78
PLLP_GND
PLLD_GND
PLLD_VDD
PLLA_GND
PLLA_VDD
PLLP_VDD
77
GND
76
GND
75
GND
74
GND
73
Figure 5. DSP56721 144-Pin Package Pinout
1.4
Pin Multiplexing
Many pins are multiplexed. For more about pin multiplexing, refer to the DSP56720/DSP56721 Reference Manual
(DSP56720RM).
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1
Freescale Semiconductor
7
2
Electrical Characteristics
For electrical characteristics, see Table 2.
Table 2. Electrical Characteristics
For
See
Section 2.1, “Chip-Level Conditions”
Section 2.2, “Module-Level Specifications”
on page 8
on page 17
2.1
Chip-Level Conditions
For a summary of chip-level conditions in this section, see Table 3.
Table 3. Chip-Level Conditions
For
See
Section 2.1.1, “Maximum Ratings”
on page 8
on page 10
on page 10
on page 11
on page 12
on page 12
on page 13
on page 14
Section 2.1.2, “Thermal Characteristics”
Section 2.1.3, “Power Requirements”
Section 2.1.4, “DC Electrical Characteristics”
Section 2.1.5, “AC Electrical Characteristics”
Section 2.1.6, “Internal Clocks”
Section 2.1.7, “External Clock Operation”
Section 2.1.8, “Reset, Stop, Mode Select, and Interrupt Timing”
2.1.1
Maximum Ratings
For maximum ratings, see Table 4.
CAUTION
This device contains circuitry protecting against damage due to high static voltage or
electrical fields. However, normal precautions should be taken to avoid exceeding
maximum voltage ratings. Reliability of operation is enhanced if unused inputs are pulled
to an appropriate logic voltage level (for example, either GND or V ). The suggested
DD
value for a pull-up or pull-down resistor is 4.7 kΩ.
NOTE
In the calculation of timing requirements, adding a maximum value of one specification to
a minimum value of another specification does not yield a reasonable sum. A maximum
specification is calculated using a worst case variation of process parameter values in one
direction. The minimum specification is calculated using the worst case for the same
parameters in the opposite direction. Therefore, a “maximum” value for a specification will
never occur in the same device that has a “minimum” value for another specification;
adding a maximum to a minimum represents a condition that can never exist.
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1
8
Freescale Semiconductor
Table 4. Maximum Ratings
Symbol
Rating1
Value1, 2
Unit
Supply Voltage
VCORE_VDD,
VPLLD_VDD
-0.3 to + 1.26
V
VPLLP_VDD,
VIO_VDD,
VPLLA_VDD
-0.3 to + 4.0
V
,
Maximum CORE_VDD power supply ramp time4
Input Voltage per pin excluding VDD and GND
Tr
VIN
I
10
GND -0.3 to 5.5V
12
ms
V
Current drain per pin excluding VDD and GND
(Except for pads listed below)
mA
LSYNC_OUT
Ilsync_out
Ilclk
16
16
mA
mA
mA
mA
°C
°C
V
LCLK
LALE
Iale
16
TDO
IJTAG
TJ
TSTG
–
24
Operating temperature range3
-40 to +125
-65 to +150
2000
Storage temperature
ESD protected voltage (Human Body Model)
ESD protected voltage (Charged Device)
–
V
• All pins
• Corner pins
500
750
Notes:
1. GND = 0 V, TJ = -40°C to 125°C, CL = 50pF
2. Absolute maximum ratings are stress ratings only, and functional operation at the maximum is not guaranteed. Stress beyond the
maximum rating may affect device reliability or cause permanent damage to the device.
3. Operating temperature qualified for consumer applications. TJ = TA + qJA x Power. Variables used were
Core Current = 900mA, I/O Current = 200mA, Core Voltage = 1.1 V, I/O Voltage = 3.6 V, TA = 105°C.
4. If the power supply ramp to full supply time is longer than 10 ms, the POR circuitry will not operate correctly, causing erroneous
operation.
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1
Freescale Semiconductor
9
2.1.2
Thermal Characteristics
For thermal characteristics, see Table 5.
Table 5. Thermal Characteristics
Board Type
Characteristic
Symbol
LQFP Values
Unit
Natural Convection, Junction-to-ambient thermal resistance1,2
Single layer board
(1s)
57 for 80 QFP
49 for 144 QFP
°C/W
RθJA or θJA
Four layer board
(2s2p)
44 for 80 QFP
40 for 144 QFP
°C/W
°C/W
Junction-to-case thermal resistance3
–
RθJC or θJC 10 for 80 QFP
9 for 144 QFP
Notes:
1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)
temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance.
2. Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal.
3. Thermal resistance between the die and the case top surface as measured by the cold plate method
(MIL SPEC-883 Method 1012.1).
2.1.3
Power Requirements
To prevent high current conditions due to possible improper sequencing of the power supplies, use an external Schottky diode
as shown in Figure 6, connected between the DSP56720/DSP56721 IO_VDD and Core_VDD power pins.
IO_VDD
External
Schottky
Diode
Core_VDD
Figure 6. Prevent High Current Conditions by Using External Schottky Diode
If an external Schottky diode is not used (to prevent a high current condition at power-up), then IO_VDD must be applied ahead
of Core_VDD, as shown in Figure 7.
Core_VDD
IO_VDD
Figure 7. Prevent High Current Conditions by Applying IO_VDD Before Core_VDD
For correct operation of the internal power-on reset logic, the Core_VDD ramp rate (Tr) to full supply must be less than 10 ms,
as shown in Figure 8.
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1
10
Freescale Semiconductor
Tr
1.0V
0 V
Core_VDD
Tr must be < 10 ms
Figure 8. Ensure Correct Operation of Power-On Reset with Fast Ramp of Core_VDD
2.1.4
DC Electrical Characteristics
For DC electrical characteristics, see Table 6.
Table 6. DC Electrical Characteristics
Characteristics
Symbol
Min
Typ
Max
Unit
Supply voltages
VDD
0.9
1.0
1.1
V
• Core (Core_VDD)
• PLL (PLLD_VDD, PLLD1_VDD)
Supply voltages
• I/O (IO_VDD)
• PLL (PLLP_VDD, PLLP1_VDD)
• PLL (PLLA_VDD, PLLA1_VDD)
VDDIO
3.14
2.0
3.3
–
3.46
V
V
Input high voltage
VIH
VIO_VDD+2V
Note: To avoid a high current condition and possible system damage, all 3.3 volt supplies must rise before the 1.0 volt
supplies rise.
Input low voltage
VIL
IIN
-0.3
–
–
–
0.8
84
V
Input leakage current
μA
pF
μA
Clock pin Input Capacitance (EXTAL)
CIN
ITSI
18
–
High impedance (off-state) input current (@ 3.3 V or
0 V)
-10
2.4
10
–
Output high voltage
VOH
–
V
IOH = -12 mA
LSYNC_OUT, LALE, LCLK Pins IOH = -16 mA, TDO
Pin IOH = -24 mA
Output low voltage
VOL
–
–
0.4
V
IOL = 12 mA
LSYNC_OUT, LALE, LCLK Pins IOL = 16 mA, TDO
Pins IOL = 24 mA
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1
Freescale Semiconductor
11
Table 6. DC Electrical Characteristics (Continued)
Characteristics
Symbol
Min
Typ
Max
Unit
Internal supply current1 (core only) at internal clock of
200 MHz
• In Normal mode
ICCI
ICCW
ICCS
CIN
–
–
–
–
190
90
50
–
780
680
640
10
mA
mA
mA
pF
• In Wait mode
• In Stop mode2
Input capacitance
Notes:
1. The Current Consumption section provides a formula to compute the estimated current requirements in Normal mode. In order
to obtain these results, all inputs must be terminated (i.e., not allowed to float). Measurements are based on synthetic intensive
DSP benchmarks. The power consumption numbers in this specification are 90% of the measured results of this benchmark. This
reflects typical DSP applications. Typical internal supply current is measured with VCORE_VDD = 1.0V, VDD_IO = 3.3V at TJ = 25°C.
Maximum internal supply current is measured with VCORE_VDD = 1.10V, VIO_VDD) = 3.6V at TJ = 125°C.
2. In order to obtain these results, all inputs, which are not disconnected at Stop mode, must be terminated (i.e., not allowed to float).
2.1.5
AC Electrical Characteristics
The timing waveforms shown in the AC electrical characteristics section are tested with a V maximum of 0.8 V and a V
IL
IH
minimum of 2.0 V for all pins. AC timing specifications, which are referenced to a device input signal, are measured in
production with respect to the 50% point of the respective input signal’s transition. DSP56720/DSP56721 output levels are
measured with the production test machine V and V reference levels set at 0.4 V and 2.4 V, respectively.
OL
OH
2.1.6
Internal Clocks
Internal clock characteristics are listed in Table 7.
Table 7. Internal Clocks
No.
Characteristics
Symbol
Min
Typ
Max
Unit
Condition
1
2
3
4
Comparison Frequency
Input Clock Frequency
PLL VCO Frequency
Fref
Fin
2
–
8
MHz Fref = Fin/NR
Max = 200 MHz
–
Fvco
Fout
200
400
MHz Fvco = (Fin * NF)/NR
Output Clock Frequency[1]
• with PLL enabled
• with PLL disabled
MHz
–
25
–
200
200
Fout= Fvco/NO
Fout = Fin
5
Duty Cycle
–
40
50
60
%
Fvco=
200 MHz – 400 MHz
Notes:
Fin = External frequency, NF = Multiplication Factor, NR = Predivision Factor, NO = Output Divider
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1
Freescale Semiconductor
12
2.1.7
External Clock Operation
The DSP56720/DSP56721 system clock is derived from the on-chip oscillator or is externally supplied. To use the on-chip
oscillator, connect a crystal and associated resistor/capacitor components to EXTAL and XTAL; see the example in Figure 9.
Suggested component values:
Fosc = 24.576 MHz
EXTAL
XTAL
R = 1 M 10%
C (EXTAL)= 18 pF
C (XTAL) = 18 pF
R
XTAL1
Calculations are for a 5 – 30 MHz crystal with the following parameters:
• Shunt capacitance (C0) of 10 pF – 12 pF
• Series resistance 40 Ohm
C
C
• Drive level of 10 μW
Figure 9. Using the On-Chip Oscillator
If the DSP56720/DSP56721 system clock is an externally supplied square wave voltage source, it is connected to EXTAL
(Figure 10). When the external square wave source is connected to EXTAL, the XTAL pin is not used.
VIH
Midpoint
EXTAL
ETH
ETL
VIL
1
2
3
ETC
Note:
The midpoint is 0.5 (VIH + VIL).
Figure 10. External Clock Timing
Table 8. Clock Operation
No.
Characteristics
EXTAL input high 1
Symbol
Min
Max
Units
1
(40% to 60% duty cycle)
• Crystal oscillator
• Square wave input
Eth
16.67
2.5
100
inf
ns
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1
Freescale Semiconductor
13
Table 8. Clock Operation (Continued)
No.
Characteristics
EXTAL input low1
Symbol
Min
Max
Units
2
(40% to 60% duty cycle)
• Crystal oscillator
• Square wave input
Etl
Etc
Tc
16.67
2.5
100
inf
ns
ns
ns
3
4
EXTAL cycle time
• With PLL disabled
• With PLL enabled
5
33.3
inf
500
Instruction cycle time
• With PLL disabled
• With PLL enabled
5.00
5.00
inf
5120
Notes:
1. Measured at 50% of the input transition.
2. The indicated duty cycle is for the specified maximum frequency for which a part is rated. The minimum clock
high or low time required for correct operation, however, remains the same at lower operating frequencies;
therefore, when a lower clock frequency is used, the signal symmetry may vary from the specified duty cycle
as long as the minimum high time and low time requirements are met.
3. A valid clock signal must be applied to the EXTAL pin within 3 ms of the DSP56720/DSP56721 being
powered up.
2.1.8
Reset, Stop, Mode Select, and Interrupt Timing
For reset, stop, mode select, and interrupt timing, see Table 9.
Table 9. Reset, Stop, Mode Select, and Interrupt Timing Parameters
No.
Characteristics
Expression
Min
Max
Unit
10
11
Delay from RESET assertion to all pins at reset value3
–
–
11
ns
Required RESET duration4
• Power on, external clock generator, PLL disabled
• Power on, external clock generator, PLL enabled
2 x TC
2 x TC
10
10
–
–
ns
ns
13
Syn reset deassert delay time
• Minimum
2 × TC
10
200
10.0
10.0
4
–
–
–
–
–
–
–
ns
us
ns
ns
ns
ns
ns
• Maximum (PLL enabled)
(2 x TC) + TLOCK
14
15
16
17
18
Mode select setup time
–
Mode select hold time
–
Minimum edge-triggered interrupt request assertion width
Minimum edge-triggered interrupt request deassertion width
Delay from interrupt trigger to interrupt code execution
–
–
4
10 × TC + 4
54
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1
Freescale Semiconductor
14
Table 9. Reset, Stop, Mode Select, and Interrupt Timing Parameters
No.
Characteristics
Expression
Min
Max
Unit
19
Duration of level sensitive IRQA assertion to ensure interrupt service
(when exiting Stop)1, 2, 3
• PLL is active during Stop and Stop delay is enabled (OMR Bit 6 = 0)
(128K × TC)
25 × TC
655
125
–
–
μs
• PLL is active during Stop and Stop delay is not enabled (OMR Bit 6 =
1)
ns
• PLL is not active during Stop and Stop delay is enabled (OMR Bit 6 =
0)
(128K x TC) +
TLOCK
855
200
–
–
–
μs
μs
ns
• PLL is not active during Stop and Stop delay is not enabled (OMR Bit (25 x TC) + TLOCK
6 = 1)
20
21
• Delay from IRQA, IRQB, IRQC, IRQD, NMI assertion to
general-purpose transfer output valid caused by first interrupt
instruction execution1
10 x TC + 3.8
53.8
Interrupt Requests Rate1
• ESAI, ESAI_1, ESAI_2, ESAI_3, SHI, SHI_1, Timer, Timer_1
12 x TC
8 x TC
8 x TC
12 x TC
–
–
–
–
60.0
40.0
40.0
60.0
ns
ns
ns
ns
• DMA
• IRQ, NMI (edge trigger)
• IRQ (level trigger)
22
DMA Requests Rate
• Data read from ESAI, ESAI_1, ESAI_2, ESAI_3, SHI, SHI_1
6 x TC
7 x TC
2 x TC
3 x TC
–
–
–
–
30.0
35.0
10.0
15.0
ns
ns
ns
ns
• Data write to ESAI, ESAI_1, ESAI_2, ESAI_3, SHI, SHI_1
• Timer, Timer_1
• IRQ, NMI (edge trigger)
Notes:
1. When using fast interrupts and when IRQA, IRQB, IRQC, and IRQD are defined as level-sensitive, timings 19 through 21 apply to
prevent multiple interrupt service. To avoid these timing restrictions, the Edge-triggered mode is recommended when using fast
interrupts. Long interrupts are recommended when using Level-sensitive mode.
2. For PLL disable, if using an external clock (PCTL Bit 13 = 1), no stabilization delay is required and recovery time will be defined by
the OMR Bit 6 settings.
For PLL enable, (if bit 12 of the PCTL register is 0), the PLL is shut down during Stop. Recovering from Stop requires the PLL to get
locked. The PLL lock procedure duration, PLL Lock Cycles (PLC), may be in the range of 200 μs.
3. Periodically sampled and not 100% tested.
4. RESET duration is measured during the time in which RESET is asserted, VDD is valid, and the EXTAL input is active and valid. When
V
DD is valid, but the other “required RESET duration” conditions (as specified above) have not been yet met, the device circuitry will
be in an uninitialized state that can result in significant power consumption and heat-up. Designs should minimize this state to the
shortest possible duration.
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1
Freescale Semiconductor
15
VIH
RESET
All Pins
11
13
10
Reset Value
Figure 11. Reset Timing Diagram
a) First Interrupt Instruction Execution
19
18
IRQA, IRQB,
IRQC, IRQD,
NMI,
NMI_1
b) General Purpose I/O
General
Purpose
I/O
20
IRQA, IRQB,
IRQC, IRQD,
NMI,
NMI_1
Figure 12. External Fast Interrupt Timing Diagram
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1
16
Freescale Semiconductor
IRQA, IRQB,
IRQC, IRQD,
NMI,
NMI_1
16
17
IRQA, IRQB,
IRQC, IRQD,
NMI,
NMI_1
Figure 13. External Interrupt Timing Diagram (Negative Edge-Triggered)
VIH
RESET
14
15
VIH
VIL
VIH
VIL
MODA, MODB,
MODC, MODD,
PINIT
IRQA, IRQB,
IRQC,IRQD, NMI
Figure 14. MODE Select Set-Up and Hold Timing Diagram
2.2
Module-Level Specifications
For a summary of the module-level specifications in this section, see Table 10.
Table 10. Module-Level Specifications
For
See
Section 2.2.1, “Serial Host Interface (SHI) SPI Protocol Timing”
Section 2.2.2, “Serial Host Interface (SHI) I2C Protocol Timing”
Section 2.2.3, “Programming the SHI I2C Serial Clock”
Section 2.2.4, “Enhanced Serial Audio Interface (ESAI) Timing”
Section 2.2.5, “Timer Timing”
on page 18
on page 24
on page 26
on page 27
on page 32
on page 32
on page 33
on page 35
on page 35
on page 42
on page 43
Section 2.2.6, “GPIO Timing”
Section 2.2.7, “JTAG Timing”
Section 2.2.8, “Watchdog Timer Timing”
Section 2.2.9, “Host Data Interface (HDI24) Timing”
Section 2.2.10, “S/PDIF Timing”
Section 2.2.11, “EMC Timing (DSP56720 only)”
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1
Freescale Semiconductor
17
2.2.1
Serial Host Interface (SHI) SPI Protocol Timing
See Table 11 for SHI SPI protocol timing parameters and Figure 15, Figure 16, Figure 17, and Figure 18 for timing diagrams.
Table 11. Serial Host Interface SPI Protocol Timing Parameters
No.
Characteristics1,3,4
Mode
Filter Mode
Expression
Min
Max
Unit
23 Minimum serial clock cycle = tSPICC(min)
XX Tolerable Spike width on data or clock in
24 Serial clock high period
Master/Slave
Bypassed
Very Narrow
Narrow
10 x TC + 9
59.0
59.0
183.0
373.0
–
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
10 x TC + 9
10 x TC + 133
–
Wide
10 x TC + 333
–
–
Bypassed
Very Narrow
Narrow
–
–
–
–
0
–
10
50
100
–
–
Wide
–
Master
Bypassed
33.0
0.5 x (tSPICC -10)
Very Narrow 0.5 x (tSPICC -10)
33.0
86.0
–
–
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
ns
ns
Narrow
Wide
0.5 x (tSPICC -10)
0.5 x (tSPICC -10) 121.5
Slave
Bypassed
Very Narrow
Narrow
2.5 x TC + 12
2.5 x TC + 12
2.5 x TC + 102
2.5 x TC + 189
22.5
22.5
114.5
201.5
33.0
Wide
25 Serial clock low period
Master
Bypassed
0.5 x (tSPICC -10)
Very Narrow 0.5 x (tSPICC -10)
33.0
86.0
–
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
ns
Narrow
Wide
0.5 x (tSPICC -10)
0.5 x (tSPICC -10) 121.5
Slave
Bypassed
Very Narrow
Narrow
2.5 x TC + 12
2.5 x TC + 12
2.5 x TC + 102
2.5 x TC + 189
22.5
22.5
114.5
201.5
Wide
26 Serial clock rise/fall time
Master
Slave
–
–
–
–
–
–
–
5
ns
ns
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1
Freescale Semiconductor
18
Table 11. Serial Host Interface SPI Protocol Timing Parameters (Continued)
No.
Characteristics1,3,4
Mode
Filter Mode
Expression
Min
Max
Unit
27 SS assertion to first SCK edge
CPHA = 0
Slave
Bypassed
32.5
–
ns
3.5 x TC+15
Very Narrow
Narrow
Wide
3.5 x TC+5
22.5
0
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
–
–
0
–
CPHA = 1
Slave
Slave
Bypassed
Very Narrow
Narrow
Wide
–
10
0
–
–
–
–
0
–
–
0
–
28 Last SCK edge to SS not asserted
Bypassed
Very Narrow
Narrow
Wide
–
12
22
100
200
0
–
–
–
–
–
–
–
29 Data input valid to SCK edge (data input
set-up time)
Master
/Slave
Bypassed
Very Narrow
Narrow
Wide
–
–
–
0
–
–
0
–
–
0
–
30 SCK last sampling edge to data input not
valid
Master
/Slave
Bypassed
Very Narrow
Narrow
Wide
2 x TC + 10
10
40
70
100.0
5
–
2 x TC + 30
–
2 x TC + 60
–
–
–
–
–
–
–
–
–
–
–
–
–
–
31 SS assertion to data out active
Slave
Slave
–
–
32 SS deassertion to data high impedance2
–
–
9
33 SCK edge to data out valid
(data out delay time)
Master
/Slave
Bypassed
Very Narrow
Narrow
Wide
–
46.2
270
376
521
–
–
–
–
34 SCK edge to data out not valid
(data out hold time)
Master
/Slave
Bypassed
Very Narrow
Narrow
Wide
11.67
15
55
105
–
–
–
–
35 SS assertion to data out valid
(CPHA = 0)
Slave
–
14.0
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1
Freescale Semiconductor
19
Table 11. Serial Host Interface SPI Protocol Timing Parameters (Continued)
No.
Characteristics1,3,4
Mode
Filter Mode
Expression
Min
Max
Unit
36 First SCK sampling edge to HREQ output
deassertion
Slave
Bypassed
Very Narrow
Narrow
–
–
–
–
–
–
–
–
–
45
55
–
–
–
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
95
Wide
145
50.0
60.0
100.0
150.0
45.0
37 Last SCK sampling edge to HREQ output
not deasserted (CPHA = 1)
Slave
Slave
Bypassed
Very Narrow
Narrow
Wide
38 SS deassertion to HREQ output not
deasserted (CPHA = 0)
–
39 SS deassertion pulse width (CPHA = 0)
40 HREQ in assertion to first SCK edge
Slave
–
–
TC + 6
11.0
–
–
ns
ns
Master
0.5 x TSPICC + 3.0 x 96.0
TC + 43
41 HREQ in deassertion to last SCK sampling
edge (HREQ in set-up time) (CPHA = 1)
Master
Master
Master
–
–
–
–
0
–
–
–
ns
ns
ns
42 First SCK edge to HREQ in not asserted
(HREQ in hold time)
–
0
43 HREQ assertion width
3.0 x TC
15
Notes:
1. VCORE_VDD = 1.0 0.10 V; TJ = -40°C to 125°C; CL = 50 pF.
2. Periodically sampled, not 100% tested.
3. All times assume noise free inputs.
4. All times assume internal clock frequency of 200 MHz.
5. SHI_1 specs match those of SHI.
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1
Freescale Semiconductor
20
SS
(Input)
25
23
23
24
25
26
26
26
26
SCK (CPOL = 0)
(Output)
24
SCK (CPOL = 1)
(Output)
29
30
29
30
MISO
(Input)
LSB
Valid
MSB
Valid
34
33
MSB
MOSI
(Output)
LSB
40
42
HREQ
(Input)
43
Figure 15. SPI Master Timing Diagram (CPHA = 0)
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1
Freescale Semiconductor
21
SS
(Input)
25
24
23
23
24
25
26
26
SCK (CPOL = 0)
(Output)
26
26
SCK (CPOL = 1)
(Output)
29
29
30
30
MISO
(Input)
MSB
Valid
LSB
Valid
33
34
MOSI
(Output)
MSB
LSB
40
41
42
HREQ
(Input)
43
Figure 16. SPI Master Timing Diagram (CPHA = 1)
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1
Freescale Semiconductor
22
SS
(Input)
25
23
23
28
24
26
26
26
39
SCK (CPOL = 0)
(Input)
27
24
26
25
SCK (CPOL = 1)
(Input)
35
33
34
34
32
LSB
31
MISO
(Output)
MSB
29
29
30
30
MSB
Valid
LSB
Valid
MOSI
(Input)
36
38
HREQ
(Output)
Figure 17. SPI Slave Timing Diagram (CPHA = 0)
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1
Freescale Semiconductor
23
SS
(Input)
25
23
28
24
26
26
26
SCK (CPOL = 0)
(Input)
27
24
26
25
SCK (CPOL = 1)
(Input)
33
33
34
32
31
MISO
(Output)
MSB
LSB
29
29
30
30
MSB
Valid
LSB
Valid
MOSI
(Input)
37
36
HREQ
(Output)
Figure 18. SPI Slave Timing Diagram (CPHA = 1)
2.2.2
Serial Host Interface (SHI) I2C Protocol Timing
2
See Table 12 for SHI I C protocol timing parameters and Figure 19 for the timing diagram.
2
Table 12. SHI I C Protocol Timing Parameters
Standard I2C
Standard
Symbol/
Fast-Mode
No.
Characteristics1,2,3,4,5
Unit
Expression
Min
Max
Min
Max
Tolerable Spike Width on SCL or SDA
Filters Bypassed
Very Narrow Filters enabled
Narrow Filters enabled
–
–
–
–
–
0
10
50
100
–
–
–
–
0
10
50
100
ns
ns
ns
ns
Wide Filters enabled.
44 SCL clock frequency
44 SCL clock cycle
FSCL
TSCL
–
100
–
–
400
–
kHz
μs
10
4.7
4.7
2.5
1.3
0.6
45 Bus free time
TBUF
–
–
μs
46 Start condition set-up time
TSUSTA
–
–
μs
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1
Freescale Semiconductor
24
2
Table 12. SHI I C Protocol Timing Parameters (Continued)
Standard I2C
Standard
Min Max
Fast-Mode
Symbol/
Expression
No.
Characteristics1,2,3,4,5
Unit
Min
Max
47 Start condition hold time
48 SCL low period
THD;STA
TLOW
4.0
4.7
4.0
–
–
–
0.6
1.3
1.3
–
–
–
μs
μs
μs
ns
ns
ns
μs
49 SCL high period
THIGH
–
–
50 SCL and SDA rise time
51 SCL and SDA fall time
52 Data set-up time
T
5.0
5.0
–
5.0
5.0
–
R
T
F
–
–
TSU;DAT
THD;DAT
FOSC
250
0.0
100
0.0
53 Data hold time
–
0.9
54 DSP clock frequency
• Filters bypassed
10.6
10.6
11.8
13.1
–
–
–
–
28.5
28.5
39.7
61.0
–
–
–
–
MHz
MHz
MHz
MHz
• Very Narrow filters enabled
• Narrow filters enabled
• Wide filters enabled
55 SCL low to data out valid
56 Stop condition setup time
TVD;DAT
TSU;STO
tSU;RQI
–
3.4
–
–
0.9
–
μs
μs
ns
4.0
0.0
0.6
0.0
57 HREQ in deassertion to last SCL edge
(HREQ in set-up time)
–
–
58 First SCL sampling edge to HREQ output
deassertion2
TNG;RQO
• Filters bypassed
4 × TC + 30
4 × TC + 50
4 × TC + 130
4 × TC + 230
–
–
–
–
50.0
70.0
250.0
150.0
–
–
–
–
50.0
70.0
150.0
250.0
ns
ns
ns
ns
• Very Narrow filters enabled
• Narrow filters enabled
• Wide filters enabled
59 Last SCL edge to HREQ output not
deasserted2
TAS;RQO
• Filters bypassed
2 × TC + 30
2 × TC + 40
2 × TC + 80
2 × TC + 130
40
50
90
–
–
–
–
40
50
90
–
–
–
–
ns
ns
ns
ns
• Very Narrow filters enabled
• Narrow filters enabled
• Wide filters enabled
140
140
60 HREQ in assertion to first SCL edge
• Filters bypassed
TAS;RQI
4327
4317
4282
4227
–
–
–
–
927
917
877
827
–
–
–
–
ns
ns
ns
ns
• Very Narrow filters enabled
• Narrow filters enabled
• Wide filters enabled
61 First SCL edge to HREQ is not asserted
(HREQ in hold time.)
tHO;RQI
0.0
–
0.0
–
ns
Notes:
1. VCORE_VDD = 1.00 0.10 V; TJ = -40°C to 125°C; CL = 50 pF.
2. Pull-up resistor: R
3. Capacitive load: C
P
(min) = 1.5K Ohms.
(max) = 50 pF.
b
4. All times assume noise free inputs.
5. All times assume internal clock frequency of 200 MHz.
6. SHI_1 specs match those of SHI.
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1
Freescale Semiconductor
25
2.2.3
Programming the SHI I2C Serial Clock
2
The programmed serial clock cycle, T
control register).
, is specified by the value of the HDM[7:0] and HRS bits of the HCKR (SHI clock
I CCP
2
The expression for T
is
I CCP
T 2
= [T × 2 × (HDM[7:0] + 1) × (7 × (1 – HRS) + 1)]
Eqn. 1
I CCP
C
where
— HRS is the pre scaler rate select bit. When HRS is cleared, the fixed
divide-by-eight pre scaler is operational. When HRS is set, the pre scaler is bypassed.
— HDM[7:0] are the divider modulus select bits. A divide ratio from 1 to 256 (HDM[7:0] = $00 to $FF) may be
selected.
2
In I C mode, the user may select a value for the programmed serial clock cycle from
6 × T (if HDM[7:0] = $02 and HRS = 1)
Eqn. 2
C
to
4096 × T (if HDM[7:0] = $FF and HRS = 0)
Eqn. 3
C
2
The programmed serial clock cycle (T
shown in Equation 4.
) should be chosen in order to achieve the desired SCL serial clock cycle (T ), as
SCL
I CCP
T 2
+ 3 × T + 45ns + T
R
(Nominal, SCL Serial Clock Cycle (TSCL) generated as master)
Eqn. 4
I CCP
C
44
46
49
48
SCL
SDA
50
53
51
45
52
MSB
LSB
ACK
Stop
Stop
Start
47
60
58
55
56
59
61
57
HREQ
2
Figure 19. I C Timing Diagram
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1
Freescale Semiconductor
26
2.2.4
Enhanced Serial Audio Interface (ESAI) Timing
See Table 13 For ESAI timing parameters and Figure 20, Figure 21, Figure 22, and Figure 23 for timing diagrams.
Table 13. Enhanced Serial Audio Interface Timing Parameters
No.
Characteristics1, 3, 4
Symbol Expression5
Min
Max Condition2 Unit
62 Clock cycle5
tSSICC
4 × T
4 × T
20.0
20.0
–
–
i ck
i ck
ns
c
c
63 Clock high period
ns
• For internal clock
–
2 × T
2 × T
10
10
–
–
–
–
c
c
• For external clock
64 Clock low period
• For internal clock
ns
–
2 × T
2 × T
–
10
10
–
–
–
–
c
c
• For external clock
65 SCKR rising edge to FSR out (bl) high
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
17.0
7.0
x ck
i ck a
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
66 SCKR rising edge to FSR out (bl) low
67 SCKR rising edge to FSR out (wr) high6
68 SCKR rising edge to FSR out (wr) low6
69 SCKR rising edge to FSR out (wl) high
70 SCKR rising edge to FSR out (wl) low
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
17.0
7.0
x ck
i ck a
–
–
19.0
9.0
x ck
i ck a
–
–
19.0
9.0
x ck
i ck a
–
–
16.0
6.0
x ck
i ck a
–
–
17.0
7.0
x ck
i ck a
71 Data in setup time before SCKR (SCK in synchronous
mode) falling edge
12.0
19.0
–
–
x ck
i ck
72 Data in hold time after SCKR falling edge
73 FSR input (bl, wr) high before SCKR falling edge 6
74 FSR input (wl) high before SCKR falling edge
75 FSR input hold time after SCKR falling edge
76 Flags input setup before SCKR falling edge
77 Flags input hold time after SCKR falling edge
78 SCKT rising edge to FST out (bl) high
3.5
9.0
–
–
x ck
i ck
2.0
12.0
–
–
x ck
i ck a
2.0
12.0
–
–
x ck
i ck a
2.5
8.5
–
–
x ck
i ck a
0.0
19.0
–
–
x ck
i ck s
6.0
0.0
–
–
x ck
i ck s
–
–
18.0
8.0
x ck
i ck
79 SCKT rising edge to FST out (bl) low
–
–
20.0
10.0
x ck
i ck
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1
Freescale Semiconductor
27
Table 13. Enhanced Serial Audio Interface Timing Parameters (Continued)
No.
Characteristics1, 3, 4
Symbol Expression5
Min
Max Condition2 Unit
80 SCKT rising edge to FST out (wr) high6
81 SCKT rising edge to FST out (wr) low6
82 SCKT rising edge to FST out (wl) high
83 SCKT rising edge to FST out (wl) low
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
20.0
10.0
x ck
i ck
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
–
–
22.0
12.0
x ck
i ck
–
–
19.0
9.0
x ck
i ck
–
–
20.0
10.0
x ck
i ck
84 SCKT rising edge to data out enable from high
impedance
–
–
22.0
17.0
x ck
i ck
85 SCKT rising edge to transmitter #0 drive enable
assertion
–
–
17.0
11.0
x ck
i ck
86 SCKT rising edge to data out valid
–
–
18.0
13.0
x ck
i ck
87 SCKT rising edge to data out high impedance7
–
–
21.0
16.0
x ck
i ck
88 SCKT rising edge to transmitter #0 drive enable
deassertion7
–
–
14.0
9.0
x ck
i ck
89 FST input (bl, wr) setup time before SCKT falling edge6
90 FST input (wl) setup time before SCKT falling edge
91 FST input hold time after SCKT falling edge
2.0
18.0
–
–
x ck
i ck
2.0
18.0
–
–
x ck
i ck
4.0
5.0
–
–
x ck
i ck
92 FST input (wl) to data out enable from high impedance
93 FST input (wl) to transmitter #0 drive enable assertion
94 Flag output valid after SCKT rising edge
–
–
–
–
–
–
–
–
21.0
14.0
–
–
ns
ns
ns
–
–
14.0
9.0
x ck
i ck
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1
Freescale Semiconductor
28
Table 13. Enhanced Serial Audio Interface Timing Parameters (Continued)
No.
Characteristics1, 3, 4
Symbol Expression5
Min
Max Condition2 Unit
95 HCKR/HCKT clock cycle
–
–
–
2 x TC
10
–
–
–
–
–
ns
ns
ns
96 HCKT input rising edge to SCKT output
97 HCKR input rising edge to SCKR output
–
–
18.0
18.0
–
Notes:
1. VCORE_VDD = 1.00 0.10 V; TJ = -40°C to 125°C; CL = 50 pF.
2. i ck = internal clock
x ck = external clock
i ck a = internal clock, asynchronous mode
(Asynchronous implies that SCKT and SCKR are two different clocks.)
i ck s = internal clock, synchronous mode
(Synchronous implies that SCKT and SCKR are the same clock.)
3. bl = bit length
wl = word length
wr = word length relative
4. SCKT(SCKT pin) = transmit clock
SCKR(SCKR pin) = receive clock
FST(FST pin) = transmit frame sync
FSR(FSR pin) = receive frame sync
HCKT(HCKT pin) = transmit high frequency clock
HCKR(HCKR pin) = receive high frequency clock
5. For the internal clock, the external clock cycle is defined by Tc and the ESAI control register.
6. The word-relative frame sync signal waveform relative to the clock operates in the same manner as the bit-length frame sync signal
waveform, but spreads from one serial clock before first bit clock (same as bit length frame sync signal), until the one before last bit
clock of the first word in frame.
7. Periodically sampled and not 100% tested.
8. ESAI_1, ESAI_2, ESAI_3 specs match those of ESAI.
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1
Freescale Semiconductor
29
62
63
64
SCKT
(Input/Output)
78
79
FST (Bit)
Out
82
83
FST (Word)
Out
86
84
86
87
First Bit
Last Bit
Data Out
93
Transmitter #0
Drive Enable
(Internal Signal)
89
85
88
91
FST (Bit) In
92
91
90
FST (Word) In
Flags Out
94
See Note
Note: In network mode, output flag transitions can occur at the start of each time slot within the
frame. In normal mode, the output flag state is asserted for the entire frame period.
Figure 20. ESAI Transmitter Timing Diagram
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1
30
Freescale Semiconductor
62
63
64
SCKR
(Input/Output)
65
66
FSR (Bit)
Out
69
70
FSR (Word)
Out
72
71
Data In
Last Bit
First Bit
75
73
FSR (Bit)
In
74
75
77
FSR (Word)
In
76
Flags In
Figure 21. ESAI Receiver Timing Diagram
HCKT
95
SCKT
(Output)
96
Figure 22. ESAI HCKT Timing Diagram
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1
Freescale Semiconductor
31
HCKR
95
SCKR
(Output)
97
Figure 23. ESAI HCKR Timing
2.2.5
Timer Timing
See Table 14 for timer timing parameters and Figure 24 for the timing diagram.
Table 14. Timer Timing Parameters
No.
Characteristics
Expression
Unit
Min
Max
98
99
TIO Low
TIO High
2 × TC + 2.0
2 × TC + 2.0
12.0
12.0
–
–
ns
ns
Notes:
1. VCORE_VDD = 1.00 V 0.10 V; TJ = -40°C to 125°C, CL = 50 pF
2. TIMER_1 specs match those of TIMER
TIO
98
99
Figure 24. TIO Timer Event Input Restrictions Diagram
2.2.6
GPIO Timing
See Table 15 for general purpose input and output (GPIO) timing and Figure 25 for the timing diagram.
Table 15. GPIO Timing Parameters
No.
Characteristics1
Expression
Min
Max
Unit
100 Fsys edge to GPIO out valid (GPIO out delay time)2
101 Fsys edge to GPIO out not valid (GPIO out hold time)2
102 Fsys In valid to EXTAL edge (GPIO in set-up time)2
103 Fsys edge to GPIO in not valid (GPIO in hold time)2
104 Minimum GPIO pulse high width
–
–
–
7
7
–
–
–
ns
ns
ns
ns
ns
–
–
–
2
0
2 x TC
10
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1
Freescale Semiconductor
32
Table 15. GPIO Timing (Continued)Parameters
No.
Characteristics1
Expression
Min
Max
Unit
105 Minimum GPIO pulse low width
106 GPIO out rise time
2 x TC
10
–
–
ns
ns
ns
–
–
13.0
13.0
107 GPIO out fall time
–
Notes:
1. VCORE_VDD = 1.0 V 0.10 V; TJ = -40°C to 125°C; CL = 50 pF
Fsys
100
101
GPIO
(Output)
102
103
GPIO
Input)
Valid
GPIO
(Output)
105
107
104
106
Figure 25. GPIO Timing Diagram
2.2.7
JTAG Timing
See Table 16 for joint test action group (JTAG) timing parameters, and Figure 26, Figure 27, and Figure 28 for timing diagrams.
Table 16. JTAG Timing Parameters
All Frequencies
No.
Characteristics
Unit
Min
Max
108 TCK frequency of operation (1/(TC × 3); maximum 10 MHz)
109 TCK cycle time in Crystal mode
–
100.0
50.0
–
10.0
–
MHz
ns
110 TCK clock pulse width measured at 1.65 V
111 TCK rise and fall times
–
ns
3.0
–
ns
112 Boundary scan input data setup time
113 Boundary scan input data hold time
114 TCK low to output data valid
15.0
24.0
–
ns
–
ns
40.0
40.0
ns
115 TCK low to output high impedance
–
ns
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1
Freescale Semiconductor
33
Table 16. JTAG Timing Parameters (Continued)
All Frequencies
No.
Characteristics
Unit
Min
Max
116 TMS, TDI data setup time
117 TMS, TDI data hold time
118 TCK low to TDO data valid
119 TCK low to TDO high impedance
5.0
25.0
–
–
ns
ns
ns
ns
–
44.0
44.0
–
Notes:
1. VCORE_VDD = 1.0 V 0.10 V; TJ = -40°C to 125°C , CL = 50 pF
2. All timings apply to OnCE module data transfers because it uses the JTAG port as an interface.
109
110
110
TCK
(Input)
VM
VM
VIH
VIL
111
111
Figure 26. Test Clock Input Timing Diagram
VIH
113
TCK
(Input)
VIL
112
Data
Inputs
Input Data Valid
114
115
114
Data
Outputs
Output Data Valid
Data
Outputs
Data
Outputs
Output Data Valid
Figure 27. Debugger Port Timing Diagram
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1
34
Freescale Semiconductor
VIH
117
TCK
(Input)
VIL
116
Input Data Valid
TDI
TMS
(Input)
118
TDO
(Output)
Output Data Valid
119
TDO
(Output)
118
TDO
(Output)
Output Data Valid
Figure 28. Test Access Port Timing Diagram
2.2.8
Watchdog Timer Timing
For watchdog timer timing, see Table 17.
Table 17. Watchdog Timer Timing Parameters
No.
Characteristics
Expression
Min
Max
Unit
120 Delay from time-out to fall of WDT, WDT_1
121 Delay from timer clear to rise of WDT, WDT_1
2 × T
10.0
10.0
–
–
ns
ns
c
2 × Tc
2.2.9
Host Data Interface (HDI24) Timing
The HDI24 module is only on the DSP56721 device; the DSP56720 device does not have a HDI24 module. Also, only 16 bits
of the HDI24 interface are pinned out on the DSP56721 device. See Table 18 for HDI24 timing and Figure 29, Figure 30,
Figure 30, Figure 31, Figure 32, Figure 33, Figure 34, and Figure 35 for timing diagrams.
Table 18. HDI24 Timing Parameters
200 MHz
2
No.
Characteristics
Expression
Unit
Min
Max
3
317 Read data strobe assertion width
HACK read assertion width
TC + 9.9
–
14.9
–
ns
ns
ns
3
318 Read data strobe deassertion width
HACK read deassertion width
9.9
–
–
3
4,5
319 Read data strobe deassertion width after “Last Data Register” reads
,
2 × TC + 6.6
16.6
6
or between two consecutive CVR, ICR, or ISR reads
HACK deassertion width after “Last Data Register” reads
4,5
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1
Freescale Semiconductor
35
Table 18. HDI24 Timing Parameters (Continued)
200 MHz
Min Max
2
No.
Characteristics
Expression
Unit
7
320 Write data strobe assertion width
HACK write assertion width
–
13.2
16.6
–
–
ns
ns
7
321 Write data strobe deassertion width
HACK write deassertion width
2 × TC + 6.6
4
• after ICR, CVR and “Last Data Register” writes
• after IVR writes, or
–
16.5
–
• after TXH:TXM writes (with HBE=0), or
• after TXL:TXM writes (with HBE=1)
322 HAS assertion width
323 HAS deassertion to data strobe assertion
–
–
–
9.9
0.0
9.9
–
–
–
ns
ns
ns
8
7
324 Host data input setup time before write data strobe deassertion
Host data input setup time before HACK write deassertion
7
325 Host data input hold time after write data strobe deassertion
–
–
–
–
–
3.3
3.3
–
–
–
ns
ns
ns
ns
ns
Host data input hold time after HACK write deassertion
3
326 Read data strobe assertion to output data active from high impedance
HACK read assertion to output data active from high impedance
3
327 Read data strobe assertion to output data valid
24.2
9.9
–
HACK read assertion to output data valid
3
328 Read data strobe deassertion to output data high impedance
–
HACK read deassertion to output data high impedance
3
329 Output data hold time after read data strobe deassertion
3.3
Output data hold time after HACK read deassertion
3
330 HCS assertion to read data strobe deassertion
TC + 9.9
14.9
9.9
–
–
–
ns
ns
ns
ns
ns
ns
ns
7
331 HCS assertion to write data strobe deassertion
–
–
–
–
–
–
332 HCS assertion to output data valid
19.1
–
8
333 HCS hold time after data strobe deassertion
0.0
4.7
3.3
0
334 Address (AD7–AD0) setup time before HAS deassertion (HMUX=1)
335 Address (AD7–AD0) hold time after HAS deassertion (HMUX=1)
336 A10–A8 (HMUX=1), A2–A0 (HMUX=0), HR/W setup time before data
–
–
–
8
strobe assertion
• Read
• Write
–
–
4.7
3.3
–
–
337 A10–A8 (HMUX=1), A2–A0 (HMUX=0), HR/W hold time after data strobe
ns
ns
8
deassertion
338 Delay from read data strobe deassertion to
TC
5.0
–
3, 4, 9
host request assertion for “Last Data Register” read
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1
Freescale Semiconductor
36
Table 18. HDI24 Timing Parameters (Continued)
200 MHz
Min Max
2
No.
Characteristics
Expression
Unit
339 Delay from write data strobe deassertion to
host request assertion for “Last Data Register” write
2 × TC
10.0
–
–
ns
ns
4, 7, 9
340 Delay from data strobe assertion to
–
19.1
host request deassertion for “Last Data Register” read or write (HROD =
4, 8, 9
0)
341 Delay from data strobe assertion to
–
–
300.0
ns
ns
host request deassertion for “Last Data Register” read or write (HROD =
4, 8, 9, 10
1, open drain Host Request)
342 Delay from DMA HACK deassertion to HOREQ assertion
4
• For “Last Data Register” read
2 × TC + 19.1
29.1
24.1
0.0
–
–
–
4
• For “Last Data Register” write
1 × TC + 19.1
• For other cases
–
–
–
343 Delay from DMA HACK assertion to HOREQ deassertion
20.2
ns
ns
4
• HROD = 0
344 Delay from DMA HACK assertion to HOREQ deassertion for “Last Data
Register” read or write
–
–
300.0
4, 10
• HROD = 1, open drain Host Request
Notes:
1. In the timing diagrams that follow, the controls pins are drawn as active low. The pin polarity is programmable.
2. CC = 1.0 V 10%; TJ = –40°C to +125°C; CL = 50 pF.
3. The read data strobe is HRD in the dual data strobe mode and HDS in the single data strobe mode.
4. The “last data register” is the register at address $7, which is the last location to be read or written in data transfers.
V
5. This timing is applicable only if a read from the “last data register” is followed by a read from the RXL, RXM, or RXH registers without
first polling RXDF or HREQ bits, or waiting for the assertion of the HOREQ signal.
6. This timing is applicable only if two consecutive reads from one of these registers are executed.
7. The write data strobe is HWR in the dual data strobe mode and HDS in the single data strobe mode.
8. The data strobe is host read (HRD) or host write (HWR) in the dual data strobe mode and host data strobe (HDS) in the single data
strobe mode.
9. The host request is HOREQ in the single host request mode and HRRQ and HTRQ in the double host request mode.
10. In this calculation, the host request signal is pulled up by a 4.7 kW resistor in the open-drain mode.
11. HDI24_1 specs match those of HDI24.
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1
Freescale Semiconductor
37
317
318
HACK
328
327
326
329
HD23–HD0
HOREQ
Figure 29. HDI24 Host Interrupt Vector Register (IVR) Read Timing Diagram
HA0–HA2
336
337
333
330
HCS
317
HRD, HDS
318
319
328
332
327
329
326
341
HD0–HD23
338
340
HOREQ,
HRRQ,
HTRQ
Figure 30. HDI24 Read Timing Diagram, Non-Multiplexed Bus
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1
Freescale Semiconductor
38
HA0–HA2
337
333
336
331
HCS
320
HWR, HDS
321
325
324
HD0–HD23
340
339
341
HOREQ,
HRRQ,
HTRQ
Figure 31. HDI24 Write Timing Diagram, Non-Multiplexed Bus
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1
Freescale Semiconductor
39
HA8–HA10
336
337
322
HAS
323
317
HRD, HDS
334
318
319
335
327
328
329
HAD0–HAD23
Address
Data
326
338
340
341
HOREQ,
HRRQ,
HTRQ
Figure 32. HDI24 Read Timing Diagram, Multiplexed Bus
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1
40
Freescale Semiconductor
HA8–HA10
336
322
HAS
323
320
HWR, HDS
334
324
321
325
335
HAD0–HAD23
Address
Data
340
339
341
HOREQ,
HRRQ,
HTRQ
Figure 33. HDI24 Write Timing Diagram, Multiplexed Bus
HOREQ
(Output)
342
343
344
320
321
TXH/M/L
Write
HACK
(Input)
324
325
Data
Valid
H0–H23
(Input)
Figure 34. HDI24 Host DMA Write Timing Diagram
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1
Freescale Semiconductor
41
HOREQ
(Output)
343
342
342
318
317
RXH
Read
HACK
(Input)
327
326
328
329
Data
Valid
H0-H23
(Output)
Figure 35. HDI24 Host DMA Read Timing Diagram
2.2.10 S/PDIF Timing
See Table 19 for Sony/Philips Digital Interconnect Format (S/PDIF) timing parameters and Figure 36 and Figure 37 for timing
diagrams.
Table 19. S/PDIF Timing Parameters
All Frequency
Characteristics
Symbol
Unit
Min
Max
–
–
0.7
ns
SPDIFIN1, SPDIFIN2, SPDIFIN3, SPDIFIN4 Skew:
asynchronous inputs, no specs apply
SPDIFOUT1,SPDIFOUT2 output (Load = 50 pf)
• Skew
• Transition Risng
–
–
–
–
–
–
1.5
24.2
31.3
ns
ns
• Transition Falling
SPDIFOUT1, SPDIFOUT2 output (Load = 30 pf)
• Skew
• Transition Risng
• Transition Falling
–
–
–
–
–
–
1.5
13.6
18.0
SRCK period
srckp
srckph
srckpl
stclkp
stclkph
stclkpl
40.0
16.0
16.0
40.0
16.0
16.0
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
SRCK high period
SRCK low period
STCLK period
STCLK high period
STCLK low period
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1
42
Freescale Semiconductor
srckp
srckpl
srckph
VM
VM
SRCK
(Output)
Figure 36. S/PDIF SRCK Timing Diagram
stclkp
stclkpl
stclkph
VM
VM
STCLK
(Input)
Figure 37. S/PIDF STCLK Timing Diagram
2.2.11 EMC Timing (DSP56720 only)
The DSP56721 device does not have an EMC module. For EMC timing parameters in DSP56720 devices, see Table 20,
Table 21, and Table 22; for timing diagrams, see Figure 38, Figure 39, and Figure 40.
Table 20. EMC Timing Parameters (EMC PLL Enabled; LCRR[CLKDIV] = 2)
Parameter
Symbol
Min
Max
Unit
LCLK cycle time
Tclk
Tclk_skew
Tin_s
10
–
–
160
–
ns
ps
ns
ns
ns
ns
ns
LCLK skew to LSYNC_OUT
Input setup to LSYNC_IN (except LGTA/LUPWAIT)
Input hold from LSYNC_IN (except LGTA/LUPWAIT)
LGTA valid time
2
Tin_h
2
–
Tgta
12
12
3
–
LUPWAIT valid time
Tupwait
Tale_h
–
LALE negedge to LAD(address phase) invaild (address latch
hold time)
–
LALE valid time
Tale
3.8
4
–
–
ns
ns
ns
ns
ns
ns
Output setup from LSYNC_IN (except LAD[23:0] and LALE)
Output hold from LSYNC_IN (except LAD[23:0] and LALE)
LAD[23:0] output setup from LSYNC_IN
LAD[23:0] output hold from LSYNC_IN
Tout_s
Tout_h
Tad_s
Tad_h
Tad_z
2
–
3.5
1.5
–
–
–
LSYNC_IN to output high impedance for LAD[23:0]
4.3
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1
Freescale Semiconductor
43
Tclk
LCLK
Tclk_skew
LSYNC_OUT
LSYNC_IN
Tsync_in_skew
Tin_s
Tin_h
LAD[23:0] (data)
LGTA
asynchronous input
Tgta
Tupwait
asynchronous input
LUPWAIT
Tout_s
Tout_h
Output Signals
LA[2:0]/LBCTL/LCS[7:0]
LOE/LWE
LCKE/LSDA10/LSDDQM
LSDWE/LSDRAS/LSDCAS
LGPL[5:0]
Tad_z
Tad_s
Tad_h
LAD[23:0]
Tale_h
Tale
LALE
Figure 38. EMC Signals (EMC PLL Enabled; LCRR[CLKDIV] = 2)
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1
Freescale Semiconductor
44
Table 21. EMC Timing Parameters (EMC PLL Bypassed; LRCC[CLKDIV] = 4)
Parameter
Symbol
Tclk
Min
20
8
Max
–
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
LCLK cycle time
Input setup to LCLK (except LGTA/LUPWAIT)
Input hold from LCLK (except LGTA/LUPWAIT)1
LGTA valid time
Tin_s
–
Tin_h
-1
22
22
4
–
Tgta
–
LUPWAIT valid time
Tupwait
Tale_h
Tale
–
LALE negedge to LAD (address phase) invalid (address latch hold time)
LALE valid time
–
14
9
–
Output setup from LCLK (except LAD[23:0] and LALE)
Output hold from LCLK (except LAD[23:0] and LALE)
LAD[23:0] output setup from LCLK
LAD[23:0] output hold from LCLK
Tout_s
Tout_h
Tad_s
Tad_h
Tad_z
–
8
–
8
–
7
–
LCLK to output high impedance for LAD[23:0]
Notes:
–
9
1. A negative hold time means that the signal could be invalid before the LCLK rising edge.
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1
Freescale Semiconductor
45
Tclk
LCLK
Tin_s
Tin_h
LAD[23:0] (data)
LGTA
asynchronous input
Tgta
Tupwait
asynchronous input
LUPWAIT
Tout_s
Tout_h
Output Signals
LA[2:0]/LBCTL/LCS[7:0]
LOE/LWE
LCKE/LSDA10/LSDDQM
LSDWE/LSDRAS/LSDCAS
LGPL[5:0]
Tad_z
Tad_s
Tad_h
LAD[23:0]
LALE
Tale_h
Tale
Figure 39. EMC Signals (EMC PLL Bypassed; LRCC[CLKDIV] = 4)
Table 22. EMC Timing Parameters (EMC PLL Bypassed; LRCC[CLKDIV] = 8)
Parameter
Symbol
Min
Max
Unit
LCLK cycle time
Tclk
Tin_s
Tin_h
Tgta
40
8
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
Input setup to LCLK (except LGTA/LUPWAIT)
Input hold from LCLK (except LGTA/LUPWAIT)1
LGTA valid time
-1
42
42
5
LUPWAIT valid time
Tupwait
Tale_h
LALE negedge to LAD (address phase) invalid (address
latch hold time)
LALE valid time
Tale
34
19
18
–
–
–
ns
ns
ns
Output setup from LCLK (except LAD[23:0] and LALE)
Output hold from LCLK (except LAD[23:0] and LALE)
Tout_s
Tout_h
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1
46
Freescale Semiconductor
Table 22. EMC Timing Parameters (EMC PLL Bypassed; LRCC[CLKDIV] = 8) (Continued)
Parameter
Symbol
Min
Max
Unit
LAD[23:0] output setup from LCLK
LAD[23:0] output hold from LCLK
LCLK to output high impedance for LAD[23:0]
Notes:
Tad_s
Tad_h
Tad_z
18
17
–
–
–
ns
ns
ns
19
1. A negative hold time means that the signal could be invalid before the LCLK rising edge.
Tclk
LCLK
Tin_s
Tin_h
LAD[23:0] (data)
asynchronous input
Tgta
LGTA
Tupwait
asynchronous input
LUPWAIT
Tout_s
Tout_h
Output Signals
LA[2:0]/LBCTL/LCS[7:0]
LOE/LWE
LCKE/LSDA10/LSDDQM
LSDWE/LSDRAS/LSDCAS
LGPL[5:0]
Tad_z
Tad_s
Tad_h
LAD[23:0]
Tale_h
Tale
LALE
Figure 40. EMC Signals (EMC PLL Bypassed; LRCC[CLKDIV] = 8)
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1
Freescale Semiconductor
47
3
Functional Description and Application Information
See the DSP56720 Reference Manual (DSP56720RM) for detailed functional and applications information.
4
Hardware Design Considerations
For design considerations, also see Section 2.1.3, “Power Requirements.”
5
Ordering Information
Table 23 provides ordering information for both the DSP56720 and DSP56721.
Table 23. Ordering Information
ROM
Version
Product
Package
Part Number
DSP56720
A
B
A
B
A
B
144-pin plastic LQFP
144-pin plastic LQFP
144-pin plastic LQFP
144-pin plastic LQFP
80-pin plastic LQFP
80-pin plastic LQFP
DSPA56720AG
DSPB56720AG
DSPA56721AG
DSPB56721AG
DSPA56721AF
DSPB56721AF
DSP56721
6
Package Information
For the outline drawings of available device packages, see Table 24 and sections 6.1–6.2.
Table 24. Package Outline Drawings
Device
Package
See
DSP56720
144-pin plastic LQFP
Figure 43 on page 51 and
Figure 44 on page 52
DSP56721
80-pin plastic LQFP
144-pin plastic LQFP
Figure 41 on page 49 and
Figure 42 on page 50
Figure 43 on page 51 and
Figure 44 on page 52
6.1
80-Pin Package Outline Drawing
For the 80-pin package outline drawings, see Figure 41 and Figure 42.
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1
Freescale Semiconductor
48
Figure 41. 80-Pin Package Outline Drawing (1 of 2)
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1
Freescale Semiconductor
49
Figure 42. 80-Pin Package Outline Drawing (2 of 2)
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1
50
Freescale Semiconductor
6.2
144-Pin Package Outline Drawing
For the 144-pin package drawings, see figures Figure 43 and Figure 44.
Figure 43. 144-Pin Package Outline Drawing (1 of 2)
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1
Freescale Semiconductor
51
Figure 44. 144-Pin Package Outline Drawing (2 of 2)
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1
52
Freescale Semiconductor
7
Product Documentation
This Data Sheet is labeled as a particular type: Product Preview, Advance Information, or Technical Data. Definitions of these
types are available at: http://www.freescale.com. Documentation is available from a local Freescale Semiconductor, Inc.
distributor, semiconductor sales office, Literature Distribution Center, or through the Freescale DSP home page on the Internet
(the source for the latest information).
The following documents are required for a complete description of the device and are necessary to design properly with the
parts:
DSP56300 Family Manual (document number DSP56300FM). Detailed description of the 56300-family architecture and the
24-bit core processor and instruction set.
DSP56720/DSP56721 Reference Manual (document number DSP56720RM). Detailed description of memory, peripherals, and
interfaces.
DSP56720 Product Brief (DSP56720PB). Brief description of the DSP56720 device.
DSP56721 Product Brief (DSP56721PB). Brief description of the DSP56721 device.
8
Revision History
Table 25 summarizes revisions to this document.
Table 25. Revision History
Revision
Date
December 2007 • Initial public release.
Description
1
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1
Freescale Semiconductor
53
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Document Number: DSP56720
Rev.1
12/2007
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