DSPB56364FU100_技术文档

Order this document by:

DSP56364/D

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Rev 3.1 11/00

Advance Information

DSP56364

24-Bit Audio Digital Signal Processor

The DSP56364 supports digital audio applications requiring sound field processing, acoustic

equalization, and other digital audio algorithms. The DSP56364 uses the high performance,

single-clock-per-cycle DSP56300 core family of programmable CMOS digital signal

processors (DSPs) combined with the audio signal processing capability of the Motorola

Symphony™ DSP family, as shown in Figure 1. This design provides a two-fold performance

increase over Motorola’s popular Symphony family of DSPs while retaining code

compatibility. Significant architectural enhancements include a barrel shifter, 24-bit

addressing, instruction cache, and direct memory access (DMA). The DSP56364 offers 100

million instructions per second (MIPS) using an internal 100 MHz clock at 3.3 V.

4

12

5

PROGRAMRAM

0.5Kx24

X

Y

MEMORY

RAM

MEMORY

RAM

SHI

GPIO

ESAI

PROGRAMROM

8Kx24

1KX24

1.5KX24

PERIPHERAL

EXPANSION

AREA

BootstrapROM

192x24

MEMORY

EXPANSION

AREA

ADDRESS

CONTROL

YAB

ADDRESS

EXTERNAL

ADDRESS BUS

SWITCH

GENERATION UNIT

XAB

PAB

DAB

18

6

SIX CHANNELS

DMA UNIT

24-BIT

DSP56300

CORE

DRAM &SRAM

BUS

INTERFACE

DDB

YDB

XDB

PDB

GDB

DATA

EXTERNAL

DATABUS

SWITCH

INTERNAL

DATA BUS

SWITCH

8

POWER

MGMT

DATA ALU

PLL

+

PROGRAM

INTERRUPT

CONT

PROGRAM

DECODE

CONT

PROGRAM

ADDRESS

GEN

24X24 56_→56-BITMAC

TWO56-BIT

4

JTAG

ACCUMULATORS

BARRELSHIFTER

CLOCK

OnCE™

EXTAL

MODA/IRQA

MODB/IRQB

MODD/IRQD

24 BITS BUS

RESET

PINIT/NMI

Figure 1 DSP56364 Block Diagram

This document contains information on a new product. Specifications and information herein are subject to change without notice.

Advance Information

DSP56364

PRELIMINARY

ii

DSP56364 Advance Information

MOTOROLA

SIGNAL/CONNECTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

PACKAGING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

DESIGN CONSIDERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1

IBIS MODEL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1

INDEX. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . INDEX-I

FOR TECHNICAL ASSISTANCE:

Telephone:

1-800-521-6274

Email:

dsphelp@dsp.sps.mot.com

http://www.motorola-dsp.com

Internet:

Data Sheet Conventions

This data sheet uses the following conventions:

OVERBAR

“asserted”

“deasserted”

Examples:

Used to indicate a signal that is active when pulled low (For example, the RESET

pin is active when low.)

Means that a high true (active high) signal is high or that a low true (active low)

signal is low

Means that a high true (active high) signal is low or that a low true (active low)

signal is high

Signal/Symbol

Logic State

Signal State

Voltage*

True

False

True

Asserted

Deasserted

Asserted

V_IL/V_OL

V_IH/V_OH

V_IL/V_OL

False

Deasserted

Note:

*Values for V_IL, V_OL, V_IH, and V_OHare defined by individual product specifications.

!!

DSP56362 Advance Information

MOTOROLA

PRELIMINARY

DSP56362/D

iv

MOTOROLA

DSP56364

Features

FEATURES

Digital Signal Processing Core

•

100 Million Instructions Per Second (MIPS) with an 100 MHz clock at 3.3V.

Object Code Compatible with the 56000 core.

Data ALU with a 24 x 24 bit multiplier-accumulator and a 56-bit barrel shifter. 16-bit

arithmetic support.

•

Program Control with position independent code support and instruction cache support.

Six-channel DMA controller.

PLL based clocking with a wide range of frequency multiplications (1 to 4096), predivider

i

factors (1 to 16) and power saving clock divider (2 : i=0 to 7). Reduces clock noise.

•

Internal address tracing support and OnCE for Hardware/Software debugging.

JTAG port.

Very low-power CMOS design, fully static design with operating frequencies down to DC.

STOP and WAIT low-power standby modes.

On-chip Memory Configuration

•

1.5Kx24 Bit Y-Data RAM.

1Kx24 Bit X-Data RAM.

8Kx24 Bit Program ROM.

0.5Kx24 Bit Program RAM and 192x24 Bit Bootstrap ROM.

0.75Kx24 Bit from Y Data RAM can be switched to Program RAM resulting in up to

1.25Kx24 Bit of Program RAM.

Off-chip memory expansion

•

External Memory Expansion Port with 8-bit data bus.

Off-chip expansion up to 2 x 16M x 8-bit word of Data/Program memory when using

DRAM.

MOTOROLA

DSP56364 Advance Information

v

DSP56364

Features

•

Off-chip expansion up to 2 x 256k x 8-bit word of Data/Program memory when using

SRAM.

Simultaneous glueless interface to SRAM and DRAM.

Peripheral modules

•

Enhanced Serial Audio Interface (ESAI): 6 serial lines, 4 selectable as receive or transmitt

and 2 transmitt only, master or slave. I S, Sony, AC97, network and other programmable

2

protocols. Unused pins of ESAI may be used as GPIO lines.

2

•

Serial Host Interface (SHI): SPI and I C protocols, 10-word receive FIFO, support for 8,

16 and 24-bit words.

Four dedicated GPIO lines.

Packaging

• 100-pin plastic TQFP package.

vi

DSP56364 Advance Information

MOTOROLA

DSP56364

Documentation

DOCUMENTATION

Table 1 lists the documents that provide a complete description of the DSP56364 and are

required to design properly with the part. Documentation is available from a local Motorola

distributor, a Motorola semiconductor sales office, a Motorola Literature Distribution Center, or

through the Motorola DSP home page on the Internet (the source for the latest information).

Table 1 DSP56364 Documentation

Document Name

Description

Order Number

DSP56300 Family Manual

Detailed description of the 56000-family

architecture and the 24-bit core processor

and instruction set

DSP56300FM/AD

DSP56364 User’s Manual

Detailed description of memory,

peripherals, and interfaces

DSP56364UM/AD

DSP56364/D

DSP56364 Technical Data Sheet

Electrical and timing specifications; pin

and package descriptions

There is also a product brief for this chip.

Brief description of the chip

DSP56364 Product Brief

DSP56364P/D

MOTOROLA

DSP56364 Advance Information

vii

DSP56364

Documentation

viii

DSP56364 Advance Information

MOTOROLA

SECTION 1

SIGNAL/CONNECTION DESCRIPTIONS

SIGNAL GROUPINGS

The input and output signals of the DSP56364 are organized into functional groups, which are

listed in Table 0-1. and illustrated in Figure 0-1..

The DSP56364 is operated from a 3.3 V supply; however, some of the inputs can tolerate 5 V. A

special notice for this feature is added to the signal descriptions of those inputs.

Table 1-1. DSP56364 Functional Signal Groupings

Number of

Signals

Detailed

Description

Functional Group

Power (V_CC

)

18

14

3

Table 0-2.

Table 0-3.

Table 0-4.

Table 0-5.

Table 0-6.

Table 0-7.

Table 0-8.

Table 0-12

Table 0-9.

Table 0-10.

Table 0-11.

Ground (GND)

Clock and PLL

Address bus

Data bus

18

8

Port A¹

Bus control

6

Interrupt and mode control

General Purpose I/O

SHI

4

Port B2

Port C3

4

5

ESAI

12

4

JTAG/OnCE Port

Notes: 1. Port A is the external memory interface port, including the external address bus, data bus, and control

signals.

2. Port B signals are the GPIO signals.

3. Port C signals are the ESAI port signals multiplexed with the GPIO signals.

MOTOROLA

DSP56364 Advance Information

1-1

Signal/Connection Descriptions

Signal Groupings

OnCE ON-CHIP EMULATION/

PORT A ADDRESS BUS

JTAG PORT

TDI

A0-A17

TCK

TDO

TMS

VCCA (4)

GNDA (4)

DSP56364

PORT A DATA BUS

D0-D7

VCCD (1)

Port B

GPIO

PB0-PB3

GNDD (1)

PORT A BUS CONTROL

AA0-AA1/RAS0-RAS1

CAS

RD

WR

TA

VCCC (1)

GNDC (1)

RESERVED (4)

SERIAL AUDIO INTERFACE (ESAI)

Port C

SCKT [PC3]

FST [PC4]

HCKT [PC5]

SCKR [PC0]

FSR [PC1]

INTERRUPT AND

MODE CONTROL

MODA/IRQA

HCKR [PC2]

SDO0 [PC11]

SDO1 [PC10]

MODB/IRQB

SDO2/SDI3 [PC9]

MODD/IRQD

SDO3/SDI2 [PC8]

SDO4/SDI1 [PC7]

SDO5/SDI0 [PC6]

VCCSS (3)

RESET

PLL AND CLOCK

GNDS (3)

PINIT/NMI

SERIAL HOST INTERFACE (SHI)

PCAP

VCCP

GNDP

MOSI/HA0

SS/HA2

MISO/SDA

SCK/SCL

HREQ

EXTAL

QUIET POWER

VCCHQ (4)

VCCLQ (4)

GNDQ (4)

Figure 1-1. Signals Identified by Functional Group

DSP56364 Advance Information

1-2

MOTOROLA

Signal/Connection Descriptions

Power

POWER

Table 1-2. Power Inputs

Description

Power Name

PLL Power—V_CCPis V_CCdedicated for PLL use. The voltage should be well-regulated

and the input should be provided with an extremely low impedance path to the V_CC

power rail. There is one V_CCPinput.

V_CCP

Quiet Core (Low) Power—V_CCQLis an isolated power for the internal processing logic.

This input must be tied externally to all other chip power inputs. The user must provide

adequate external decoupling capacitors. There are four V_CCQLinputs.

V_CCQL(4)

V_CCQH(4)

V_CCA(4)

V_CCD(1)

V_CCC(1)

V_CCS(3)

Quiet External (High) Power—V_CCQHis a quiet power source for I/O lines. This input

must be tied externally to all other chip power inputs. The user must provide adequate

decoupling capacitors. There are four V_CCQHinputs.

Address Bus Power—V_CCAis an isolated power for sections of the address bus

I/O drivers. This input must be tied externally to all other chip power inputs. The user

must provide adequate external decoupling capacitors. There are four V_CCAinputs.

Data Bus Power—V_CCDis an isolated power for sections of the data bus I/O drivers.

This input must be tied externally to all other chip power inputs. The user must provide

adequate external decoupling capacitors. There is one V_CCDinputs.

Bus Control Power—V_CCCis an isolated power for the bus control I/O drivers. This

input must be tied externally to all other chip power inputs. The user must provide

adequate external decoupling capacitors. There is one V_CCCinputs.

SHI and ESAI —V_CCSis an isolated power for the SHI and ESAI. This input must be

tied externally to all other chip power inputs_L. The user must provide adequate external

decoupling capacitors. There are three V_CCSinputs.

MOTOROLA

DSP56364 Advance Information

1-3

Signal/Connection Descriptions

Ground

GROUND

Table 1-3. Grounds

Description

Ground

Name

PLL Ground—GND_Pis ground-dedicated for PLL use. The connection should be

provided with an extremely low-impedance path to ground. V_CCPshould be bypassed

to GND_Pby a 0.47 µF capacitor located as close as possible to the chip package.

There is one GND_Pconnection.

GND_P

Quiet Ground—GND_Qis an isolated ground for the internal processing logic. This

connection must be tied externally to all other chip ground connections. The user must

provide adequate external decoupling capacitors. There are four GND_Qconnections.

GND_Q(4)

GND_{A (4)}

Address Bus Ground—GND_Ais an isolated ground for sections of the address bus I/

O drivers. This connection must be tied externally to all other chip ground connections.

The user must provide adequate external decoupling capacitors. There are four GND_A

connections.

Data Bus Ground—GND_Dis an isolated ground for sections of the data bus

I/O drivers. This connection must be tied externally to all other chip ground

connections. The user must provide adequate external decoupling capacitors. There is

one GND_Dconnections.

GND_D(1)

Bus Control Ground—GND_Cis an isolated ground for the bus control I/O drivers. This

connection must be tied externally to all other chip ground connections. The user must

provide adequate external decoupling capacitors. There is one GND_Cconnections.

GND_C(1)

GND_S(3)

SHI and ESAI —GND_Sis an isolated ground for the SHI and ESAI. This connection

must be tied externally to all other chip ground connections. The user must provide

adequate external decoupling capacitors. There are three GND_Sconnections.

1-4

DSP56364 Advance Information

MOTOROLA

Signal/Connection Descriptions

Clock and PLL

CLOCK AND PLL

Table 1-4. Clock and PLL Signals

State

during

Reset

Signal

Name

Type

Signal Description

External Clock Input—An external clock source must be connected to

EXTAL in order to supply the clock to the internal clock generator and

PLL.

EXTAL

Input

PLL Capacitor—PCAP is an input connecting an off-chip capacitor to

the PLL filter. Connect one capacitor terminal to PCAP and the other

PCAP

Input

terminal to V_CCP

.

If the PLL is not used, PCAP may be tied to V_CC, GND, or left floating.

PLL Initial/Nonmaskable Interrupt—During assertion of RESET, the

value of PINIT/NMI is written into the PLL Enable (PEN) bit of the PLL

control register, determining whether the PLL is enabled or disabled.

After RESET de assertion and during normal instruction processing,

the PINIT/NMI Schmitt-trigger input is a negative-edge-triggered

nonmaskable interrupt (NMI) request internally synchronized to internal

system clock.

PINIT/

NMI

Input

This input is 5 V tolerant.

MOTOROLA

DSP56364 Advance Information

1-5

Signal/Connection Descriptions

External Memory Expansion Port (Port A)

EXTERNAL MEMORY EXPANSION PORT (PORT A)

When the DSP56364 enters a low-power standby mode (stop or wait), it tri-states the relevant

port A signals: D0–D7, AA0, AA1, RD, WR, CAS.

External Address Bus

Table 1-5. External Address Bus Signals

State

during

Reset

Signal

Name

Type

Signal Description

Address Bus—A0–A17 are active-high outputs that specify the

address for external program and data memory accesses.

Otherwise, the signals are kept to their previous values by internal

weak keepers. To minimize power dissipation, A0–A17 do not

change state when external memory spaces are not being

accessed.

Outp

ut

Keeper

active

A0–A17

External Data Bus

Table 1-6. External Data Bus Signals

Signal

Type

State during

Signal Description

Reset

Name

Data Bus—D0–D7 are active-high, bidirectional input/

outputs that provide the bidirectional data bus for

Input/

D0–D7

Tri-stated

external program and data memory accesses. D0–D7

are tri-stated during hardware reset and when the DSP

is in the stop or wait low-power standby mode.

Output

1-6

DSP56364 Advance Information

MOTOROLA

Signal/Connection Descriptions

External Memory Expansion Port (Port A)

External Bus Control

Table 1-7. External Bus Control Signals

State

during

Reset

Signal

Name

Type

Signal Description

Address Attribute or Row Address Strobe—When defined as AA,

these signals can be used as chip selects or additional address lines.

When defined as RAS, these signals can be used as RAS for DRAM

interface. These signals are tri-statable outputs with programmable

polarity. These signals are tri-stated during hardware reset and when

the DSP is in the stop or wait low-power standby mode.

AA0–

AA1/

RAS0–

RAS1

Outp

ut

Tri-

stated

Column Address Strobe— CAS is an active-low output used by

DRAM to strobe the column address. This signal is tri-stated during

hardware reset and when the DSP is in the stop or wait low-power

standby mode.

Outp

ut

Tri-

stated

CAS

RD

Read Enable—RD is an active-low output that is asserted to read

external memory on the data bus. This signal is tri-stated during

hardware reset and when the DSP is in the stop or wait low-power

standby mode.

Outp

ut

Tri-

stated

Write Enable— WR is an active-low output that is asserted to write

external memory on the data bus. This signal is tri-stated during

hardware reset and when the DSP is in the stop or wait low-power

standby mode.

Outp

ut

Tri-

stated

WR

Transfer Acknowledge—If there is no external bus activity, the TA

input is ignored. The TA input is a data transfer acknowledge (DTACK)

function that can extend an external bus cycle indefinitely. Any number

of wait states (1, 2. . .infinity) may be added to the wait states inserted

by the BCR by keeping TA deasserted. In typical operation, TA is

deasserted at the start of a bus cycle, is asserted to enable completion

of the bus cycle, and is deasserted before the next bus cycle. The

current bus cycle completes one clock period after TA is asserted

synchronous to the internal system clock. The number of wait states is

determined by the TA input or by the bus control register (BCR),

whichever is longer. The BCR can be used to set the minimum number

of wait states in external bus cycles.

Ignored

Input

TA

Input

In order to use the TA functionality, the BCR must be programmed to at

least one wait state. A zero wait state access cannot be extended by

TA deassertion, otherwise improper operation may result. TA can

operate synchronously or asynchronously, depending on the setting of

the TAS bit in the operating mode register (OMR).

TA functionality may not be used while performing DRAM type

accesses, otherwise improper operation may result.

MOTOROLA

DSP56364 Advance Information

1-7

Signal/Connection Descriptions

Interrupt and Mode Control

INTERRUPT AND MODE CONTROL

The interrupt and mode control signals select the chip’s operating mode as it comes out of

hardware reset. After RESET is deasserted, these inputs are hardware interrupt request lines.

Table 1-8. Interrupt and Mode Control

Stat

e

duri

Signal Name Type

Signal Description

ng

Rese

t

Mode Select A/External Interrupt Request A—MODA/IRQA is an

active-low Schmitt-trigger input, internally synchronized to the internal

system clock. MODA/IRQA selects the initial chip operating mode

during hardware reset and becomes a level-sensitive or negative-

edge-triggered, maskable interrupt request input during normal

instruction processing. MODA, MODB, and MODD select one of 8

MODA/IRQA Input Input initial chip operating modes, latched into the OMR when the RESET

signal is deasserted. If IRQA is asserted synchronous to the internal

system clock, multiple processors can be re synchronized using the

WAIT instruction and asserting IRQA to exit the wait state. If the

processor is in the stop standby state and IRQA is asserted, the

processor will exit the stop state.

This input is 5 V tolerant.

Mode Select B/External Interrupt Request B—MODB/IRQB is an

active-low Schmitt-trigger input, internally synchronized to the internal

system clock. MODB/IRQB selects the initial chip operating mode

during hardware reset and becomes a level-sensitive or negative-

edge-triggered, maskable interrupt request input during normal

MODB/IRQB Input Input instruction processing. MODA, MODB, and MODD select one of 8

initial chip operating modes, latched into OMR when the RESET signal

is deasserted. If IRQB is asserted synchronous to the internal system

clock, multiple processors can be re-synchronized using the WAIT

instruction and asserting IRQB to exit the wait state.

This input is 5 V tolerant.

1-8

DSP56364 Advance Information

MOTOROLA

Signal/Connection Descriptions

Interrupt and Mode Control

Table 1-8. Interrupt and Mode Control (Continued)

Stat

e

duri

ng

Signal Name Type

Signal Description

Rese

t

Mode Select D/External Interrupt Request D—MODD/IRQD is an

active-low Schmitt-trigger input, internally synchronized to the internal

system clock. MODD/IRQD selects the initial chip operating mode

during hardware reset and becomes a level-sensitive or negative-

edge-triggered, maskable interrupt request input during normal

MODD/IRQD Input Input instruction processing. MODA, MODB, and MODD select one of 8

initial chip operating modes, latched into OMR when the RESET signal

is deasserted. If IRQD is asserted synchronous to the internal system

clock, multiple processors can be re synchronized using the WAIT

instruction and asserting IRQD to exit the wait state.

This input is 5 V tolerant.

Reset—RESET is an active-low, Schmitt-trigger input. When asserted,

the chip is placed in the reset state and the internal phase generator is

reset. The Schmitt-trigger input allows a slowly rising input (such as a

capacitor charging) to reset the chip reliably. When the RESET signal

RESET

Input Input is deasserted, the initial chip operating mode is latched from the

MODA, MODB, and MODD inputs. The RESET signal must be

asserted during power up. A stable EXTAL signal must be supplied

before deassertionof RESET.

This input is 5 V tolerant.

MOTOROLA

DSP56364 Advance Information

1-9

Signal/Connection Descriptions

Serial Host Interface

SERIAL HOST INTERFACE

The SHI has five I/O signals that can be configured to allow the SHI to operate in either SPI or

2

I C mode.

Table 1-9. Serial Host Interface Signals

State

Signal

Name

Signal

Type

during

Reset

Signal Description

SPI Serial Clock—The SCK signal is an output when the SPI is

configured as a master and a Schmitt-trigger input when the SPI is

configured as a slave. When the SPI is configured as a master, the

SCK signal is derived from the internal SHI clock generator. When the

SPI is configured as a slave, the SCK signal is an input, and the clock

signal from the external master synchronizes the data transfer. The

SCK signal is ignored by the SPI if it is defined as a slave and the slave

select (SS) signal is not asserted. In both the master and slave SPI

devices, data is shifted on one edge of the SCK signal and is sampled

on the opposite edge where data is stable. Edge polarity is determined

by the SPI transfer protocol.

Input or

output

SCK

Tri-

stated

I²C Serial Clock—SCL carries the clock for I²C bus transactions in the

I²C mode. SCL is a Schmitt-trigger input when configured as a slave

and an open-drain output when configured as a master. SCL should be

connected to V_CCthrough a pull-up resistor.

Input or

output

SCL

This signal is tri-stated during hardware, software, and individual reset.

Thus, there is no need for an external pull-up in this state.

This input is 5 V tolerant.

1-10

DSP56364 Advance Information

MOTOROLA

Signal/Connection Descriptions

Serial Host Interface

Table 1-9. Serial Host Interface Signals (Continued)

State

during

Reset

Signal

Name

Signal

Type

Signal Description

SPI Master-In-Slave-Out—When the SPI is configured as a master,

MISO is the master data input line. The MISO signal is used in

conjunction with the MOSI signal for transmitting and receiving serial

data. This signal is a Schmitt-trigger input when configured for the SPI

Master mode, an output when configured for the SPI Slave mode, and

tri-stated if configured for the SPI Slave mode when SS is deasserted.

An external pull-up resistor is not required for SPI operation.

Input or

output

MISO

I²C Data and Acknowledge—In I²C mode, SDA is a Schmitt-trigger

input when receiving and an open-drain output when transmitting. SDA

should be connected to V_CCthrough a pull-up resistor. SDA carries the

data for I²C transactions. The data in SDA must be stable during the

high period of SCL. The data in SDA is only allowed to change when

SCL is low. When the bus is free, SDA is high. The SDA line is only

allowed to change during the time SCL is high in the case of start and

stop events. A high-to-low transition of the SDA line while SCL is high

is a unique situation, and is defined as the start event. A low-to-high

transition of SDA while SCL is high is a unique situation defined as the

stop event.

Tri-

stated

Input or

open-

drain

SDA

output

This signal is tri-stated during hardware, software, and individual reset.

Thus, there is no need for an external pull-up in this state.

This input is 5 V tolerant.

SPI Master-Out-Slave-In—When the SPI is configured as a master,

MOSI is the master data output line. The MOSI signal is used in

conjunction with the MISO signal for transmitting and receiving serial

data. MOSI is the slave data input line when the SPI is configured as a

slave. This signal is a Schmitt-trigger input when configured for the SPI

Slave mode.

Input or

output

MOSI

HA0

Tri-

I²C Slave Address 0—This signal uses a Schmitt-trigger input when

stated configured for the I²C mode. When configured for I²C slave mode, the

HA0 signal is used to form the slave device address. HA0 is ignored

when configured for the I²C master mode.

Input

This signal is tri-stated during hardware, software, and individual reset.

Thus, there is no need for an external pull-up in this state.

This input is 5 V tolerant.

MOTOROLA

DSP56364 Advance Information

1-11

Signal/Connection Descriptions

Serial Host Interface

Table 1-9. Serial Host Interface Signals (Continued)

State

during

Reset

Signal

Name

Signal

Type

Signal Description

SPI Slave Select—This signal is an active low Schmitt-trigger input

when configured for the SPI mode. When configured for the SPI Slave

mode, this signal is used to enable the SPI slave for transfer. When

configured for the SPI master mode, this signal should be kept

deasserted (pulled high). If it is asserted while configured as SPI

master, a bus error condition is flagged. If SS is deasserted, the SHI

ignores SCK clocks and keeps the MISO output signal in the high-

impedance state.

SS

Input

I²C Slave Address 2—This signal uses a Schmitt-trigger input when

configured for the I²C mode. When configured for the I²C Slave mode,

the HA2 signal is used to form the slave device address. HA2 is

ignored in the I²C master mode.

HA2

This signal is tri-stated during hardware, software, and individual reset.

Thus, there is no need for an external pull-up in this state.

This input is 5 V tolerant.

Host Request—This signal is an active low Schmitt-trigger input when

configured for the master mode but an active low output when

configured for the slave mode.

Input or

Output

HREQ

When configured for the slave mode, HREQ is asserted to indicate that

the SHI is ready for the next data word transfer and deasserted at the

first clock pulse of the new data word transfer. When configured for the

master mode, HREQ is an input. When asserted by the external slave

device, it will trigger the start of the data word transfer by the master.

After finishing the data word transfer, the master will await the next

assertion of HREQ to proceed to the next transfer.

Tri-

stated

This signal is tri-stated during hardware, software, personal reset, or

when the HREQ1–HREQ0 bits in the HCSR are cleared. There is no

need for external pull-up in this state.

This input is 5 V tolerant.

1-12

DSP56364 Advance Information

MOTOROLA

Signal/Connection Descriptions

Enhanced Serial Audio Interface

ENHANCED SERIAL AUDIO INTERFACE

Table 1-10. Enhanced Serial Audio Interface Signals

Signal

Name

State during

Signal Type

Signal Description

Reset

High Frequency Clock for Receiver—When programmed

as an input, this signal provides a high frequency clock

source for the ESAI receiver as an alternate to the DSP core

clock. When programmed as an output, this signal can serve

as a high-frequency sample clock (e.g., for external digital to

analog converters [DACs]) or as an additional system clock.

Input or

output

HCKR

GPIO

Input, output, disconnected Port C 2—When the ESAI is configured as GPIO, this signal

PC2

or

is individually programmable as input, output, or internally

disconnected.

disconnected

The default state after reset is GPIO disconnected.

This input is 5 V tolerant.

High Frequency Clock for Transmitter—When

programmed as an input, this signal provides a high

frequency clock source for the ESAI transmitter as an

alternate to the DSP core clock. When programmed as an

output, this signal can serve as a high frequency sample

clock (e.g., for external DACs) or as an additional system

clock.

Input or

output

HCKT

GPIO

disconnected

Input, output,

or

disconnected

Port C 5—When the ESAI is configured as GPIO, this signal

is individually programmable as input, output, or internally

disconnected.

PC5

The default state after reset is GPIO disconnected.

This input is 5 V tolerant.

MOTOROLA

DSP56364 Advance Information

1-13

Signal/Connection Descriptions

Enhanced Serial Audio Interface

Table 1-10. Enhanced Serial Audio Interface Signals (Continued)

Signal

Name

State during

Reset

Signal Type

Signal Description

Frame Sync for Receiver—This is the receiver frame sync

input/output signal. In the asynchronous mode (SYN=0), the

FSR pin operates as the frame sync input or output used by

all the enabled receivers. In the synchronous mode (SYN=1),

it operates as either the serial flag 1 pin (TEBE=0), or as the

transmitter external buffer enable control (TEBE=1,

RFSD=1).

Input or

output

When this pin is configured as serial flag pin, its direction is

determined by the RFSD bit in the RCCR register. When

configured as the output flag OF1, this pin will reflect the

value of the OF1 bit in the SAICR register, and the data in the

OF1 bit will show up at the pin synchronized to the frame

sync in normal mode or the slot in network mode. When

configured as the input flag IF1, the data value at the pin will

be stored in the IF1 bit in the SAISR register, synchronized

by the frame sync in normal mode or the slot in network

mode.

FSR

GPIO

disconnected

Input, output,

or

disconnected

Port C 1—When the ESAI is configured as GPIO, this signal

is individually programmable as input, output, or internally

disconnected.

PC1

The default state after reset is GPIO disconnected.

This input is 5 V tolerant.

Frame Sync for Transmitter—This is the transmitter frame

sync input/output signal. For synchronous mode, this signal

is the frame sync for both transmitters and receivers. For

asynchronous mode, FST is the frame sync for the

transmitters only. The direction is determined by the

transmitter frame sync direction (TFSD) bit in the ESAI

transmit clock control register (TCCR).

Input or

output

FST

GPIO

disconnected

Input, output,

or

disconnected

Port C 4—When the ESAI is configured as GPIO, this signal

is individually programmable as input, output, or internally

disconnected.

PC4

The default state after reset is GPIO disconnected.

This input is 5 V tolerant.

1-14

DSP56364 Advance Information

MOTOROLA

Signal/Connection Descriptions

Enhanced Serial Audio Interface

Table 1-10. Enhanced Serial Audio Interface Signals (Continued)

Signal

Name

State during

Reset

Signal Type

Signal Description

Receiver Serial Clock—SCKR provides the receiver serial

bit clock for the ESAI. The SCKR operates as a clock input or

output used by all the enabled receivers in the asynchronous

mode (SYN=0), or as serial flag 0 pin in the synchronous

mode (SYN=1).

When this pin is configured as serial flag pin, its direction is

determined by the RCKD bit in the RCCR register. When

configured as the output flag OF0, this pin will reflect the

value of the OF0 bit in the SAICR register, and the data in the

OF0 bit will show up at the pin synchronized to the frame

sync in normal mode or the slot in network mode. When

configured as the input flag IF0, the data value at the pin will

be stored in the IF0 bit in the SAISR register, synchronized

by the frame sync in normal mode or the slot in network

mode.

Input or

output

SCKR

GPIO

disconnected

Input, output,

or

disconnected

Port C 0—When the ESAI is configured as GPIO, this signal

is individually programmable as input, output, or internally

disconnected.

PC0

The default state after reset is GPIO disconnected.

This input is 5 V tolerant.

Transmitter Serial Clock—This signal provides the serial bit

rate clock for the ESAI. SCKT is a clock input or output used

by all enabled transmitters and receivers in synchronous

mode, or by all enabled transmitters in asynchronous mode.

Input or

output

SCKT

PC3

Input, output,

or

disconnected

GPIO

Port C 3—When the ESAI is configured as GPIO, this signal

disconnected is individually programmable as input, output, or internally

disconnected.

The default state after reset is GPIO disconnected.

This input is 5 V tolerant.

MOTOROLA

DSP56364 Advance Information

1-15

Signal/Connection Descriptions

Enhanced Serial Audio Interface

Table 1-10. Enhanced Serial Audio Interface Signals (Continued)

Signal

Name

State during

Reset

Signal Type

Signal Description

Serial Data Output 5—When programmed as a transmitter,

SDO5 is used to transmit data from the TX5 serial transmit

shift register.

SDO5

SDI0

PC6

Output

Serial Data Input 0—When programmed as a receiver, SDI0

is used to receive serial data into the RX0 serial receive shift

register.

Input

GPIO

disconnected

Input, output,

or

disconnected

Port C 6—When the ESAI is configured as GPIO, this signal

is individually programmable as input, output, or internally

disconnected.

The default state after reset is GPIO disconnected.

This input is 5 V tolerant.

Serial Data Output 4—When programmed as a transmitter,

SDO4 is used to transmit data from the TX4 serial transmit

shift register.

SDO4

SDI1

PC7

Output

Input

Serial Data Input 1—When programmed as a receiver, SDI1

is used to receive serial data into the RX1 serial receive shift

register.

GPIO

disconnected

Input, output,

or

disconnected

Port C 7—When the ESAI is configured as GPIO, this signal

is individually programmable as input, output, or internally

disconnected.

The default state after reset is GPIO disconnected.

This input is 5 V tolerant.

1-16

DSP56364 Advance Information

MOTOROLA

Signal/Connection Descriptions

Enhanced Serial Audio Interface

Table 1-10. Enhanced Serial Audio Interface Signals (Continued)

Signal

Name

State during

Reset

Signal Type

Signal Description

Serial Data Output 3—When programmed as a transmitter,

SDO3 is used to transmit data from the TX3 serial transmit

shift register.

SDO3

SDI2

PC8

Output

Serial Data Input 2—When programmed as a receiver, SDI2

is used to receive serial data into the RX2 serial receive shift

register.

Input

GPIO

disconnected

Input, output,

or

disconnected

Port C 8—When the ESAI is configured as GPIO, this signal

is individually programmable as input, output, or internally

disconnected.

The default state after reset is GPIO disconnected.

This input is 5 V tolerant.

Serial Data Output 2—When programmed as a transmitter,

SDO2 is used to transmit data from the TX2 serial transmit

shift register

SDO2

SDI3

PC9

Output

Input

Serial Data Input 3—When programmed as a receiver, SDI3

is used to receive serial data into the RX3 serial receive shift

register.

GPIO

disconnected

Input, output,

or

disconnected

Port C 9—When the ESAI is configured as GPIO, this signal

is individually programmable as input, output, or internally

disconnected.

The default state after reset is GPIO disconnected.

This input is 5 V tolerant.

Serial Data Output 1—SDO1 is used to transmit data from

the TX1 serial transmit shift register.

SDO1

PC10

Output

Input, output,

or

Port C 10—When the ESAI is configured as GPIO, this

signal is individually programmable as input, output, or

GPIO

disconnected disconnected internally disconnected.

The default state after reset is GPIO disconnected.

This input is 5 V tolerant.

MOTOROLA

DSP56364 Advance Information

1-17

Signal/Connection Descriptions

JTAG/OnCE Interface

Table 1-10. Enhanced Serial Audio Interface Signals (Continued)

Signal

Name

State during

Reset

Signal Type

Signal Description

Serial Data Output 0—SDO0 is used to transmit data from

the TX0 serial transmit shift register.

SDO0

Output

Input, output,

or

Port C 11—When the ESAI is configured as GPIO, this

signal is individually programmable as input, output, or

PC11

GPIO

disconnected disconnected internally disconnected.

The default state after reset is GPIO disconnected.

This input is 5 V tolerant.

JTAG/OnCE INTERFACE

Table 1-11. JTAG/OnCE Interface

State

during

Reset

Signal

Name

Signal

Type

Signal Description

Test Clock—TCK is a test clock input signal used to synchronize the

JTAG test logic. It has an internal pull-up resistor.

TCK

TDI

Input

This input is 5 V tolerant.

Test Data Input—TDI is a test data serial input signal used for test

instructions and data. TDI is sampled on the rising edge of TCK and has

an internal pull-up resistor.

This input is 5 V tolerant.

Test Data Output—TDO is a test data serial output signal used for test

instructions and data. TDO is tri-statable and is actively driven in the

shift-IR and shift-DR controller states. TDO changes on the falling edge

of TCK.

Tri-

stated

TDO

TMS

Output

Input

Test Mode Select—TMS is an input signal used to sequence the test

controller’s state machine. TMS is sampled on the rising edge of TCK

and has an internal pull-up resistor.

Input

This input is 5 V tolerant.

1-18

DSP56364 Advance Information

MOTOROLA

Signal/Connection Descriptions

JTAG/OnCE Interface

Table 1-12. GPIO Signals

State

during

Reset

Signal

Name

Signal Type

Signal Description

Input, output

or

disconnecte ected

d

GPIO0-3- The General Purpose I/O pins are used for control

and handshake functions between the DSP and external

circuitry. Each Port B GPIO pin may be individually programmed

as an input, output or disconnected

GPIO0-

GPIO3

disconn

MOTOROLA

DSP56364 Advance Information

1-19

Signal/Connection Descriptions

JTAG/OnCE Interface

1-20

DSP56364 Advance Information

MOTOROLA

SECTION 2

SPECIFICATIONS

INTRODUCTION

The DSP56364 is a high density CMOS device with Transistor-Transistor Logic (TTL) compatible

inputs and outputs. The DSP56364 specifications are preliminary and are from design

simulations, and may not be fully tested or guaranteed. Finalized specifications will be published

after full characterization and device qualifications are complete.

MAXIMUM RATINGS

CAUTION

This device contains circuitry protecting

against damage due to high static voltage or

electrical fields. However, normal precautions

should be taken to avoid exceeding maximum

voltage ratings. Reliability of operation is

enhanced if unused inputs are pulled to an

appropriate logic voltage level (e.g., either

GND or V ). The suggested value for a

CC

pullup or pulldown resistor is 10 kΩ.

Note: In the calculation of timing requirements, adding a maximum value of one

specification to a minimum value of another specification does not yield a

reasonable sum. A maximum specification is calculated using a worst case

variation of process parameter values in one direction. The minimum

specification is calculated using the worst case for the same parameters in the

opposite direction. Therefore, a “maximum” value for a specification will never

occur in the same device that has a “minimum” value for another specification;

adding a maximum to a minimum represents a condition that can never exist.

MOTOROLA

DSP56364 Advance Information

2-1

Specifications

Thermal Characteristics

Table 2-1. Maximum Ratings

Symbol

Rating¹

Value^{1, 2}

Unit

Supply Voltage

V_CC

−0.3 to +4.0

GND -0.3 to V_CC+ 0.3

GND − 0.3 to V_CC+ 3.95

10

V

All input voltages excluding “5 V tolerant” inputs³

All “5 V tolerant” input voltages³

V_IN

V_IN5

I

V

Current drain per pin excluding V_CCand GND

Operating temperature range

mA

°C

T_J

-40 to +105

Storage temperature

T_STG

−55 to +125

Notes: 1. GND = 0 V, V_CC= 3.3 V ± 0.16 V, T_J= –0°C to +105°C, CL = 50 pF

2. Absolute maximum ratings are stress ratings only, and functional operation at the maximum is not

guaranteed. Stress beyond the maximum rating may affect device reliability or cause permanent

damage to the device.

3. CAUTION: All “5 V Tolerant” input voltages must not be more than 3.95 V greater than the supply

voltage; this restriction applies to “power on”, as well as during normal operation. In any case, the input

voltages cannot be more than 5.75 V. “5 V Tolerant” inputs are inputs that tolerate 5 V.

THERMAL CHARACTERISTICS

Table 2-2. Thermal Characteristics

Characteristic

Symbol

TQFP Value

Unit

Junction-to-ambient thermal resistance¹

Junction-to-case thermal resistance²

Thermal characterization parameter

R

_θJAor θ_JA

_θJCor θ_JC

Ψ_JT

49.87

9.26

2.0

°C/W

R

Notes: 1. Junction-to-ambient thermal resistance is based on measurements on a horizontal single-sided

printed circuit board per SEMI G38-87 in natural convection.(SEMI is Semiconductor Equipment and

Materials International, 805 East Middlefield Rd., Mountain View, CA 94043, (415) 964-5111.)

Measurements were done with parts mounted on thermal test boards conforming to specification EIA/

JESD51-3.

2. Junction-to-case thermal resistance is based on measurements using a cold plate per SEMI G30-88,

with the exception that the cold plate temperature is used for the case temperature.

2-2

DSP56364 Advance Information

MOTOROLA

Specifications

DC Electrical Characteristics

DC ELECTRICAL CHARACTERISTICS

6

Table 2-3. DC Electrical Characteristics

Characteristics

Supply voltage

Symbol

Min

Typ

Max

Unit

V_CC

3.14

3.3

3.46

V

Input high voltage

• D(0:7), TA

V_IH

2.0

—

V_CC

• MOD¹/IRQ¹, RESET, PINIT/NMI

and all JTAG/ESAI/GPIO/SHI (SPI

mode)pins

V_IHP

V_CC+ 3.95

V

• SHI (I2C mode) pins

• EXTAL⁸

V_IHP

V_IHX

1.5

—

V_CC+ 3.95

V_CC

0.8 × V_CC

Input low voltage

• D(0:7), TA, MOD¹/IRQ¹, RESET,

PINIT

V_IL

–0.3

—

0.8

• JTAG/ESAI/GPIO/SHI (SPI

mode)pins

V

V_ILP

• SHI (I2C mode) pins

• EXTAL⁸

V_ILP

V_ILX

I_IN

-0.3

–0.3

–10

—

0.3xV_CC

0.2 × V_CC

10

Input leakage current

µA

High impedance (off-state) input current

(@ 2.4 V / 0.4 V)

I_TSI

–10

—

10

Output high voltage

• TTL (I_OH= –0.4 mA)^5,7

2.4

—

V

V_OH

• CMOS (I_OH= –10 µA)⁵

V_CC– 0.01

Output low voltage

• TTL (I_OL= 3.0 mA, open-drain pins

—

0.4

I_OL= 6.7 mA)^5,7

V_OL

V

• CMOS (I_OL= 10 µA)⁵

0.01

Internal supply current²at internal clock of

100Mhz

I_CCI

—

127

181

mA

• In Normal mode

• In Wait mode³

• In Stop mode⁴

I_CCW

I_CCS

—

7. 5

100

11

mA

150

µA

MOTOROLA

DSP56364 Advance Information

2-3

Specifications

DC Electrical Characteristics

6

Table 2-3. DC Electrical Characteristics (Continued)

Characteristics

Symbol

Min

Typ

Max

Unit

PLL supply current

Input capacitance⁵

—

1

2.5

10

mA

pF

C_IN

—

Notes: 1. Refers to MODA/IRQA, MODB/IRQB, and MODD/IRQD pins

2. Power Consumption Considerations on page 4-4 provides a formula to compute the

estimated current requirements in Normal mode. In order to obtain these results, all inputs must be

terminated (i.e., not allowed to float). Measurements are based on synthetic intensive DSP benchmarks.

The power consumption numbers in this specification are 90% of the measured results of this

benchmark. This reflects typical DSP applications. Typical internal supply current is measured with V_CC

= 3.3 V at T_J= 105°C. Maximum internal supply current is measured with V_CC= 3.46 V at T_J= 105°C.

3. In order to obtain these results, all inputs must be terminated (i.e., not allowed to float). PLL signal is

disabled during Stop state.

4. In order to obtain these results, all inputs, which are not disconnected at Stop mode, must be terminated

(i.e., not allowed to float).

5. Periodically sampled and not 100% tested

6. V_CC= 3.3 V ± .16 V; T_J= 0°C to +105°C, C_L= 50 pF

7. This characteristic does not apply to PCAP.

8. Driving EXTAL to the low V_IHXor the high V_ILXvalue may cause additional power consumption (DC

current). To minimize power consumption, the minimum V_IHXshould be no lower than

0.9 × V_CCand the maximum V_ILXshould be no higher than 0.1 × V_CC

.

2-4

DSP56364 Advance Information

MOTOROLA

Specifications

AC Electrical Characteristics

AC ELECTRICAL CHARACTERISTICS

The timing waveforms shown in the AC electrical characteristics section are tested with a V

IL

maximum of 0.3 V and a V minimum of 2.4 V for all pins except EXTAL, which is tested using

IH

the input levels shown in Note 8 of the previous table. AC timing specifications, which are

referenced to a device input signal, are measured in production with respect to the 50% point of

the respective input signal’s transition. DSP56364 output levels are measured with the

production test machine V and V reference levels set at 0.4 V and 2.4 V, respectively.

OL

OH

Note: Although the minimum value for the frequency of EXTAL is 0 MHz, the device

AC test conditions are 15 MHz and rated speed.

MOTOROLA

DSP56364 Advance Information

2-5

Specifications

Internal Clocks

INTERNAL CLOCKS

Table 2-4. Internal Clocks

Expression^{1, 2}

Typ

Characteristics

Symbol

Min

Max

Internal operation frequency with

PLL enabled

(Ef × MF)/

(PDF × DF)

f

—

Internal operation frequency with

PLL disabled

f

Ef/2

—

Internal clock high period

•

With PLL disabled

—

ET_C

—

With PLL enabled and

MF ≤ 4

0.49 × ET_C

PDF × DF/MF

×

0.51 × ET_C×

PDF × DF/MF

T_H

•

With PLL enabled and

MF > 4

0.47 × ET_C

PDF × DF/MF

×

0.53 × ET_C

PDF × DF/MF

×

—

Internal clock low period

•

With PLL disabled

—

ET_C

—

With PLL enabled and

MF ≤ 4

0.49 × ET_C

PDF × DF/MF

×

0.51 × ET_C

PDF × DF/MF

×

T_L

•

With PLL enabled and

MF > 4

0.47 × ET_C

PDF × DF/MF

×

0.53 × ET_C×

PDF × DF/MF

—

Internal clock cycle time with PLL

enabled

ET_C× PDF ×

T_C

—

DF/MF

Internal clock cycle time with PLL

disabled

T_C

—

2 × ET_C

—

Instruction cycle time

I_CYC

T_C

Notes: 1. DF = Division Factor

Ef = External frequency

ET_C= External clock cycle

MF = Multiplication Factor

PDF = Predivision Factor

T_C= internal clock cycle

2. See the PLL and Clock Generation section in the DSP56300 Family Manual for a

detailed discussion of the PLL.

2-6

DSP56364 Advance Information

MOTOROLA

Specifications

EXTERNAL CLOCK OPERATION

The DSP56364 system clock is an externally supplied square wave voltage source connected to

EXTAL(Figure 2-1.).

V_IHC

Midpoint

EXTAL

ET_H

ET_L

V_ILC

2

3

4

ET_C

Note: The midpoint is 0.5 (V_IHC+ V_ILC).

Figure 2-1. External Clock Timing

Table 2-5. Clock Operation

No.

Characteristics

Symbol

Min

Max

Frequency of EXTAL (EXTAL Pin Frequency)

The rise and fall time of this external clock

should be 3 ns maximum.

1

Ef

0

100.0

EXTAL input high^{1, 2}

• With PLL disabled (46.7%–53.3% duty

ET_H

4.67 ns

4.25 ns

∞

cycle⁶)

2

• With PLL enabled (42.5%–57.5% duty

cycle⁶)

157.0 µs

EXTAL input low^{1, 2}

• With PLL disabled (46.7%–53.3% duty

ET_L

ET_C

4.67 ns

4.25 ns

∞

cycle⁶)

3

4

• With PLL enabled (42.5%–57.5% duty

cycle⁶)

EXTAL cycle time²

• With PLL disabled

157.0 µs

10.00 ns

∞

• With PLL enabled

273.1 µs

Notes: 1. Measured at 50% of the input transition

2. The maximum value for PLL enabled is given for minimum V_COand maximum MF.

MOTOROLA

DSP56364 Advance Information

2-7

Specifications

Phase Lock Loop (PLL) Characteristics

PHASE LOCK LOOP (PLL) CHARACTERISTICS

Table 2-6. PLL Characteristics

Characteristics

Min

Max

Unit

V_COfrequency when PLL enabled

(MF × E_f× 2/PDF)

30

200

MHz

PLL external capacitor (PCAP pin to V_CCP

(C_PCAP

)

1)

pF

• @ MF ≤ 4

(MF × 580) − 100 (MF × 780) − 140

MF × 830 MF × 1470

• @ MF > 4

Notes: 1. C_PCAPis the value of the PLL capacitor (connected between the PCAP pin and V_CCP). The

recommended value in pF for C_PCAPcan be computed from one of the following equations:

(MF x 680)-120, for MF ≤ 4, or

MF x 1100, for MF > 4.

2-8

DSP56364 Advance Information

MOTOROLA

Specifications

Reset, Stop, Mode Select, and Interrupt Timing

RESET, STOP, MODE SELECT, AND INTERRUPT TIMING

6

Table 2-7. Reset, Stop, Mode Select, and Interrupt Timing

No.

Characteristics

Expression

Min

Max Unit

Delay from RESET assertion to all pins at reset

value³

8

—

26.0

ns

Required RESET duration⁴

• Power on, external clock generator, PLL

disabled

50 × ET_C

500.0

—

ns

• Power on, external clock generator, PLL

enabled

1000 × ET_C

75000 × ET_C

10.0

0.75

—

ns

µs

• Power on, internal oscillator

9

• During STOP, XTAL disabled

(PCTL Bit 16 = 0)

ms

• During STOP, XTAL enabled

(PCTL Bit 16 = 1)

2.5 × T_C

25.0

—

ms

ns

• During normal operation

Delay from asynchronous RESET deassertion

to first external address output (internal reset

deassertion)⁵

10

• Minimum

3.25 × T_C+ 2.0

34.5

—

ns

• Maximum

20.25 T_C+ 7.50

211.5 ns

13 Mode select setup time

14 Mode select hold time

30.0

0.0

—

ns

Minimum edge-triggered interrupt request

assertion width

15

6.6

—

ns

Minimum edge-triggered interrupt request

deassertion width

16

Delay from IRQA, IRQB, IRQD, NMI assertion

to external memory access address out valid

• Caused by first interrupt instruction fetch

4.25 × T_C+ 2.0

7.25 × T_C+ 2.0

44.5

74.5

—

ns

17

• Caused by first interrupt instruction

execution

Delay from IRQA, IRQB, IRQD, NMI assertion

18 to general-purpose transfer output valid caused

by first interrupt instruction execution

10 × T_C+ 5.0

105.0

—

ns

MOTOROLA

DSP56364 Advance Information

2-9

Specifications

Reset, Stop, Mode Select, and Interrupt Timing

6

Table 2-7. Reset, Stop, Mode Select, and Interrupt Timing (Continued)

No.

Characteristics

Expression

Min

Max Unit

Delay from address output valid caused by first

19 interrupt instruction execute to interrupt request 3.75 × T_C+ WS × T_C– 10.94

—

ns

deassertion for level sensitive fast interrupts¹

Delay from RD assertion to interrupt request

20

21

24

3.25 × T_C+ WS × T_C– 10.94

—

deassertion for level sensitive fast interrupts¹

Delay from WR assertion to interrupt request

deassertion for level sensitive fast interrupts¹

(WS + 3.5) × T_C– 10.94

• DRAM for all WS

—

ns

• SRAM WS = 1

• SRAM WS = 2, 3

• SRAM WS ≥ 4

(WS + 3.5) × T_C– 10.94

(WS + 3) × T_C– 10.94

(WS + 2.5) × T_C– 10.94

—

Duration for IRQA assertion to recover from

Stop state

5.9

—

Delay from IRQA assertion to fetch of first

instruction (when exiting Stop)^{2, 3}

• PLL is not active during Stop (PCTL Bit

17 = 0) and Stop delay is enabled

(OMR Bit 6 = 0)

PLC × ET_C× PDF + (128 K −

PLC/2) × T_C

1.3

13.6

ms

ns

25

• PLL is not active during Stop (PCTL Bit

17 = 0) and Stop delay is not enabled

(OMR Bit 6 = 1)

PLC × ET_C× PDF + (23.75 ± 232.5 12.3

0.5) × T_C

ns

ms

• PLL is active during Stop (PCTL Bit 17 =

1) (Implies No Stop Delay)

(8.25 ± 0.5) × T_C

77.5

87.5

Duration of level sensitive IRQA assertion to

ensure interrupt service (when exiting Stop)^{2, 3}

• PLL is not active during Stop (PCTL Bit

17 = 0) and Stop delay is enabled

(OMR Bit 6 = 0)

PLC × ET_C× PDF + (128K −

PLC/2) × T_C

13.6

12.3

55.0

—

ms

ns

26

• PLL is not active during Stop (PCTL Bit

17 = 0) and Stop delay is not enabled

(OMR Bit 6 = 1)

PLC × ET_C× PDF + (20.5 ±

0.5) × T_C

• PLL is active during Stop (PCTL Bit 17 =

1) (implies no Stop delay)

5.5 × T_C

2-10

DSP56364 Advance Information

MOTOROLA

Specifications

Reset, Stop, Mode Select, and Interrupt Timing

6

Table 2-7. Reset, Stop, Mode Select, and Interrupt Timing (Continued)

No.

Characteristics

Expression

Min

Max Unit

Interrupt Requests Rate

• ESAI, SCI

12T_C

8T_C

—

120.0 ns

• DMA

80.0

ns

27

• IRQ, NMI (edge trigger)

• IRQ, NMI (level trigger)

8T_C

12T_C

120.0 ns

DMA Requests Rate

• Data read from ESAI, SCI

6T_C

7T_C

3T_C

—

60.0

70.0

30.0

ns

28

• Data write to ESAI, SCI

• IRQ, NMI (edge trigger)

MOTOROLA

DSP56364 Advance Information

2-11

Specifications

Reset, Stop, Mode Select, and Interrupt Timing

6

Table 2-7. Reset, Stop, Mode Select, and Interrupt Timing (Continued)

No.

Characteristics

Expression

Min

Max Unit

Delay from IRQA, IRQB, IRQD, NMI assertion

29 to external memory (DMA source) access

address out valid

4.25 × T_C+ 2.0

44.0

—

ns

Notes: 1. When using fast interrupts and IRQA, IRQB, and IRQD are defined as level-sensitive, timings 19

through 21 apply to prevent multiple interrupt service. To avoid these timing restrictions, the deasserted

Edge-triggered mode is recommended when using fast interrupts. Long interrupts are recommended

when using Level-sensitive mode.

2. This timing depends on several settings:

For PLL disable, using internal oscillator (PLL Control Register (PCTL) Bit 16 = 0) and oscillator

disabled during Stop (PCTL Bit 17 = 0), a stabilization delay is required to assure the oscillator is stable

before executing programs. In that case, resetting the Stop delay (OMR Bit 6 = 0) will provide the proper

delay. While it is possible to set OMR Bit 6 = 1, it is not recommended and these specifications do not

guarantee timings for that case.

For PLL disable, using internal oscillator (PCTL Bit 16 = 0) and oscillator enabled during Stop (PCTL Bit

17=1), no stabilization delay is required and recovery time will be minimal (OMR Bit 6 setting is ignored).

For PLL disable, using external clock (PCTL Bit 16 = 1), no stabilization delay is required and recovery

time will be defined by the PCTL Bit 17 and OMR Bit 6 settings.

For PLL enable, if PCTL Bit 17 is 0, the PLL is shutdown during Stop. Recovering from Stop requires the

PLL to get locked. The PLL lock procedure duration, PLL Lock Cycles (PLC), may be in the range of 0 to

1000 cycles. This procedure occurs in parallel with the stop delay counter, and stop recovery will end

when the last of these two events occurs. The stop delay counter completes count or PLL lock

procedure completion.

PLC value for PLL disable is 0.

The maximum value for ET_Cis 4096 (maximum MF) divided by the desired internal frequency (i.e., for

100 MHz it is 4096/100 MHz = 40 µs). During the stabilization period, T_C, T_H,and T_Lwill not be

constant, and their width may vary, so timing may vary as well.

3. Periodically sampled and not 100% tested

4. For an external clock generator, RESET duration is measured during the time in which RESET is

asserted, V_CCis valid, and the EXTAL input is active and valid.

For internal oscillator, RESET duration is measured during the time in which RESET is asserted and

V_CCis valid. The specified timing reflects the crystal oscillator stabilization time after power-up. This

number is affected both by the specifications of the crystal and other components connected to the

oscillator and reflects worst case conditions.

When the V_CCis valid, but the other “required RESET duration” conditions (as specified above) have not

been yet met, the device circuitry will be in an uninitialized state that can result in significant power

consumption and heat-up. Designs should minimize this state to the shortest possible duration.

2-12

DSP56364 Advance Information

MOTOROLA

Specifications

Reset, Stop, Mode Select, and Interrupt Timing

6

Table 2-7. Reset, Stop, Mode Select, and Interrupt Timing (Continued)

No.

Characteristics

Expression

Min

Max Unit

5. For an external clock generator, RESET duration is measured during the time in which RESET is

asserted, V_CCis valid, and the EXTAL input is active and valid.

For internal oscillator, RESET duration is measured during the time in which RESET is asserted and

V_CCis valid. The specified timing reflects the crystal oscillator stabilization time after power-up. This

number is affected both by the specifications of the crystal and other components connected to the

oscillator and reflects worst case conditions.

When the V_CCis valid, but the other “required RESET duration” conditions (as specified above) have not

been yet met, the device circuitry will be in an uninitialized state that can result in significant power

consumption and heat-up. Designs should minimize this state to the shortest possible duration.

6. If PLL does not lose lock

7. V_CC= 3.3 V ± 0.16 V; T_J= 0°C to + 105°C, C_L= 50 pF

8. WS = number of wait states (measured in clock cycles, number of T_C)

9. Use expression to compute maximum value.

V_IH

RESET

9

10

8

All Pins

Reset Value

A0–A17

First Fetch

AA0460

Figure 2-2. Reset Timing

MOTOROLA

DSP56364 Advance Information

2-13

Specifications

Reset, Stop, Mode Select, and Interrupt Timing

First Interrupt Instruction

Execution/Fetch

A0–A17

RD

20

WR

21

19

17

IRQA, IRQB,

IRQD,

NMI

a) First Interrupt Instruction Execution

General

Purpose

I/O

18

IRQA,

IRQB,

IRQD,

NMI

b) General Purpose I/O

AA0462

Figure 2-3. External Fast Interrupt Timing

2-14

DSP56364 Advance Information

MOTOROLA

Specifications

Reset, Stop, Mode Select, and Interrupt Timing

IRQA, IRQB,

IRQD, NMI

15

IRQA, IRQB,

IRQD, NMI

16

AA0463

Figure 2-4. External Interrupt Timing (Negative Edge-Triggered)

V_IH

RESET

13

14

V_IH

V_IL

V_IH

V_IL

IRQA, IRQB,

IRQD, NMI

MODA,

MODB,MODD,

PINIT

AA0465

Figure 2-5. Operating Mode Select Timing

24

IRQA

25

First Instruction Fetch

A0–A17

AA0466

Figure 2-6. Recovery from Stop State Using IRQA

MOTOROLA

DSP56364 Advance Information

2-15

Specifications

Reset, Stop, Mode Select, and Interrupt Timing

26

IRQA

25

First IRQA Interrupt

Instruction Fetch

A0–A17

AA0467

Figure 2-7. Recovery from Stop State Using IRQA Interrupt Service

DMA Source Address

A0–A17

RD

WR

29

IRQA, IRQB,

IRQD,

First Interrupt Instruction Execution

NMI

AA1104

Figure 2-8. External Memory Access (DMA Source) Timing

2-16

DSP56364 Advance Information

MOTOROLA

Specifications

External Memory Expansion Port (Port A)

EXTERNAL MEMORY EXPANSION PORT (PORT A)

SRAM Timing

3

Table 2-8. SRAM Read and Write Accesses

Symbol

Expression¹

No.

Characteristics

Min Max Unit

(WS + 1) × T_C− 4.0

[1 ≤ WS ≤ 3]

100 Address valid and AA assertion pulse width

16.0

56.0

106.0

0.5

—

ns

(WS + 2) × T_C− 4.0

[4 ≤ WS ≤ 7]

t_RC, t_WC

(WS + 3) × T_C− 4.0

[WS ≥ 8]

0.25 × T_C− 2.0

101 Address and AA valid to WR assertion

t_AS

[WS = 1]

0.75 × T_C− 2.0

[2 ≤ WS ≤ 3]

5.5

1.25 × T_C− 2.0

[WS ≥ 4]

10.5

—

ns

102 WR assertion pulse width

t_WP

1.5 × T_C− 4.0 [WS = 1] 11.0

All frequencies:

WS × T_C− 4.0

[2 ≤ WS ≤ 3]

16.0

31.0

—

ns

(WS − 0.5) × T_C− 4.0

[WS ≥ 4]

MOTOROLA

DSP56364 Advance Information

2-17

Specifications

External Memory Expansion Port (Port A)

3

Table 2-8. SRAM Read and Write Accesses (Continued)

Expression¹

No.

Characteristics

Symbol

Min Max Unit

0.25 × T_C− 2.0

[1 ≤ WS ≤ 3]

WR deassertion to address not valid

t_WR

0.5

—

ns

1.25 × T_C− 2.0

[4 ≤ WS ≤ 7]

10.5

20.5

2.25 × T_C− 2.0

[WS ≥ 8]

103

All frequencies:

1.25 × T_C− 4.0

[4 ≤ WS ≤ 7]

8.5

—

ns

2.25 × T_C− 4.0

[WS ≥ 8]

18.5

—

(WS + 0.75) × T_C− 7.0

[WS ≥ 1]

104 Address and AA valid to input data valid

105 RD assertion to input data valid

t

_AA, t_AC

10.5 ns

(WS + 0.25) × T_C− 7.0

[WS ≥ 1]

t_OE

—

5.5

—

ns

RD deassertion to data not valid (data hold

time)

106

t_OHZ

0.0

(WS + 0.75) × T_C− 4.0

[WS ≥ 1]

107 Address valid to WR deassertion²

t_AW

13.5

4.5

Data valid to WR deassertion (data setup

time)

(WS − 0.25) × T_C− 3.0

[WS ≥ 1]

108

t_DS(t_DW)

0.25 × T_C− 2.0

[1 ≤ WS ≤ 3]

Data hold time from WR deassertion

109

t_DH

0.5

1.25 × T_C− 2.0

[4 ≤ WS ≤ 7]

10.5

20.5

3.5

2.25 × T_C− 2.0

[WS ≥ 8]

0.75 × T_C− 4.0

[1 ≤ WS ≤ 3]

RD deassertion time

113

1.75 × T_C− 4.0

[4 ≤ WS ≤ 7]

13.5

23.5

2.75 × T_C− 4.0

[WS ≥ 8]

2-18

DSP56364 Advance Information

MOTOROLA

Specifications

External Memory Expansion Port (Port A)

3

Table 2-8. SRAM Read and Write Accesses (Continued)

Expression¹

No.

Characteristics

WR deassertion time

Symbol

Min Max Unit

0.5 × T_C− 4.0

1.0

6.0

—

ns

[WS = 1]

T_C− 2.0

[2 ≤ WS ≤ 3]

114

2.5 × T_C− 4.0

[4 ≤ WS ≤ 7]

21.0

3.5 × T_C− 4.0

[WS ≥ 8]

31.0

1.0

115 Address valid to RD assertion

116 RD assertion pulse width

0.5 × T_C− 4.0

—

ns

(WS + 0.25) × T_C−4.0 8.5

0.25 × T_C− 2.0

0.5

RD deassertion to address not valid

117

—

ns

[1 ≤ WS ≤ 3]

1.25 × T_C− 2.0

10.5

[4 ≤ WS ≤ 7]

2.25 × T_C− 2.0

20.5

[WS ≥ 8]

118 TA setup before RD or WR deassertion⁴

119 TA hold after RD or WR deassertion

0.25 × T_C+ 2.0

4.5

0

—

ns

Notes: 1. WS is the number of wait states specified in the BCR.

2. Timings 100, 107 are guaranteed by design, not tested.

3. All timings for 100 MHz are measured from 0.5 · Vcc to .05 · Vcc

4. In the case of TA negation: timing 118 is relative to the deassertion edge of RD or WR were TA to

remain active

MOTOROLA

DSP56364 Advance Information

2-19

Specifications

External Memory Expansion Port (Port A)

100

A0–A17

AA0–AA1

117

106

113

116

RD

115

105

WR

104

119

118

TA

Data

In

D0–D7

AA0468

Figure 2-9. SRAM Read Access

2-20

DSP56364 Advance Information

MOTOROLA

Specifications

External Memory Expansion Port (Port A)

100

A0–A17

AA0–AA3

107

101

102

103

WR

114

RD

TA

118

119

108

111

110

109

112

Data

Out

D0–D23

AA0469

Figure 2-10. SRAM Write Access

MOTOROLA

DSP56364 Advance Information

2-21

Specifications

External Memory Expansion Port (Port A)

DRAM Timing

The selection guides provided in Figure 2-11. and Figure 2-14. should be used for primary

selection only. Final selection should be based on the timing provided in the following tables. As

an example, the selection guide suggests that 4 wait states must be used for 100 MHz operation

when using Page Mode DRAM. However, by using the information in the appropriate table, a

designer may choose to evaluate whether fewer wait states might be used by determining which

timing prevents operation at 100 MHz, running the chip at a slightly lower frequency (e.g., 95

MHz), using faster DRAM (if it becomes available), and control factors such as capacitive and

resistive load to improve overall system performance.

DRAM Type

(t_RACns)

Note: This figure should be use for primary selection.

For exact and detailed timings see the

following tables.

100

80

70

60

Chip Frequency

(MHz)

50

120

40

66

80

100

1 Wait States

2 Wait States

3 Wait States

4 Wait States

AA047

Figure 2-11. DRAM Page Mode Wait States Selection Guide

2-22

DSP56364 Advance Information

MOTOROLA

Specifications

External Memory Expansion Port (Port A)

1, 2, 3

Table 2-9. DRAM Page Mode Timings, One Wait State (Low-Power Applications)

20 MHz⁶

30 MHz⁶

No.

Characteristics

Symbol

Expression

Unit

Min

Max

Min

Max

Page mode cycle time for

two consecutive accesses

of the same direction

2 × T_C

100.0

—

66.7

41.7

—

131

t_PC

ns

Page mode cycle time for

mixed (read and write)

accesses

1.25 × T_C

62.5

—

CAS assertion to data valid

(read)

132

133

134

135

136

t_CAC

T_C− 7.5

—

42.5

67.5

—

25.8

42.5

—

ns

Column address valid to

data valid (read)

t_AA

1.5 × T_C− 7.5

CAS deassertion to data not

valid (read hold time)

t_OFF

0.0

21.0

Last CAS assertion to RAS

deassertion

t_RSH

0.75 × T_C− 4.0 33.5

—

Previous CAS deassertion

to RAS deassertion

t_RHCP

t_CAS

2 × T_C− 4.0

96.0

—

62.7

21.0

—

ns

137 CAS assertion pulse width

0.75 × T_C− 4.0 33.5

1.75 × T_C− 6.0 81.5

Last CAS deassertion to

RAS deassertion⁴

• BRW[1:0] = 00

t_CRP

—

52.3

—

ns

138

• BRW[1:0] = 01

• BRW[1:0] = 10

• BRW[1:0] = 11

3.25 × T_C− 6.0 156.5

4.25 × T_C− 6.0 206.5

6.25 × T_C– 6.0 306.5

102.2

135.5

202.1

—

ns

—

CAS deassertion pulse

width

139

140

141

142

t_CP

0.5 × T_C− 4.0

21.0

12.7

21.0

62.7

—

ns

Column address valid to

CAS assertion

t_ASC

t_CAH

t_RAL

—

CAS assertion to column

address not valid

0.75 × T_C− 4.0 33.5

Last column address valid

to RAS deassertion

2 × T_C− 4.0

96.0

MOTOROLA

DSP56364 Advance Information

2-23

Specifications

External Memory Expansion Port (Port A)

1, 2, 3

Unit

Table 2-9. DRAM Page Mode Timings, One Wait State (Low-Power Applications)

20 MHz⁶

30 MHz⁶

No.

Characteristics

Symbol

Expression

Min

Max

Min

Max

WR deassertion to CAS

assertion

143

144

145

t_RCS

0.75 × T_C− 3.8 33.7

—

21.2

4.6

—

ns

CAS deassertion to WR

assertion

t_RCH

0.25 × T_C− 3.7

8.8

—

CAS assertion to WR

deassertion

t_WCH

t_WP

0.5 × T_C− 4.2

1.5 × T_C− 4.5

20.8

70.5

—

12.5

45.5

54.0

—

ns

146 WR assertion pulse width

Last WR assertion to RAS

deassertion

147

t_RWL

1.75 × T_C− 4.3 83.2

WR assertion to CAS

deassertion

148

t_CWL

—

54.0

4.3

—

ns

Data valid to CAS assertion

(Write)

149

t_DS

0.25 × T_C− 4.0

8.5

CAS assertion to data not

valid (write)

150

t_DH

0.75 × T_C− 4.0 33.5

21.0

29.0

WR assertion to CAS

assertion

151

t_WCS

T_C− 4.3

45.7

Last RD assertion to RAS

deassertion

152

t_ROH

t_GA

1.5 × T_C− 4.0

T_C− 7.5

71.0

—

42.5

—

46.0

—

25.8

—

ns

153 RD assertion to data valid

RD deassertion to data not

154

t_GZ

0.0

24.7

—

valid ⁵

155 WR assertion to data active

0.75 × T_C− 0.3 37.2

0.25 × T_C

—

WR deassertion to data high

impedance

156

—

12.5

8.3

Notes: 1. The number of wait states for Page mode access is specified in the DCR.

2. The refresh period is specified in the DCR.

3. All the timings are calculated for the worst case. Some of the timings are better for specific cases (e.g.,

t_PCequals 2 × T_Cfor read-after-read or write-after-write sequences).

4. BRW[1:0] (DRAM control register bits) defines the number of wait states that should be inserted in each

DRAM out-of-page access.

5. RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is t_OFFand not

t_GZ

.

6. Reduced DSP clock speed allows use of Page Mode DRAM with one Wait state (See Figure 2-14.).

2-24

DSP56364 Advance Information

MOTOROLA

Specifications

External Memory Expansion Port (Port A)

1, 2, 3, 7

Table 2-10. DRAM Page Mode Timings, Two Wait States

66 MHz

Min Max Min Max

80 MHz

No.

Characteristics

Symbol

Expression

2 × T_C

Unit

Page mode cycle time for

two consecutive accesses

of the same direction

45.4

—

37.5

34.4

—

131

t_PC

ns

Page mode cycle time for

mixed (read and write)

accesses

1.25 × T_C

41.1

1.5 × T_C− 7.5

1.5 × T_C− 6.5

2.5 × T_C− 7.5

2.5 × T_C− 6.5

—

15.2

—

12.3

—

ns

CAS assertion to data valid

(read)

132

133

t_CAC

30.4

—

Column address valid to

data valid (read)

t_AA

24.8

CAS deassertion to data

not valid (read hold time)

134

135

136

t_OFF

0.0

—

0.0

—

ns

Last CAS assertion to RAS

deassertion

t_RSH

1.75 × T_C− 4.0

22.5

17.9

Previous CAS deassertion

to RAS deassertion

t_RHCP

t_CAS

3.25 × T_C− 4.0

1.5 × T_C− 4.0

45.2

18.7

—

36.6

14.8

—

ns

137 CAS assertion pulse width

Last CAS deassertion to

RAS deassertion⁵

• BRW[1:0] = 00

t_CRP

2.0 × T_C− 6.0

24.4

—

19.0

—

ns

138

• BRW[1:0] = 01

• BRW[1:0] = 10

• BRW[1:0] = 11

3.5 × T_C− 6.0

4.5 × T_C− 6.0

6.5 × T_C− 6.0

47.2

62.4

92.8

—

37.8

50.3

75.3

—

ns

CAS deassertion pulse

width

139

140

141

t_CP

1.25 × T_C− 4.0

T_C− 4.0

14.9

11.2

22.5

—

11.6

8.5

—

ns

Column address valid to

CAS assertion

t_ASC

CAS assertion to column

address not valid

t_CAH

1.75 × T_C− 4.0

17.9

MOTOROLA

DSP56364 Advance Information

2-25

Specifications

External Memory Expansion Port (Port A)

1, 2, 3, 7

Table 2-10. DRAM Page Mode Timings, Two Wait States

(Continued)

80 MHz

66 MHz

No.

Characteristics

Symbol

Expression

Unit

Min Max Min Max

Last column address valid

to RAS deassertion

142

143

144

145

t_RAL

t_RCS

t_RCH

3 × T_C− 4.0

1.25 × T_C− 3.8

0.5 × T_C− 3.7

41.5

15.1

3.9

—

33.5

11.8

2.6

—

ns

WR deassertion to CAS

assertion

CAS deassertion to WR

assertion

CAS assertion to WR

deassertion

t_WCH

t_WP

1.5 × T_C− 4.2

2.5 × T_C− 4.5

2.75 × T_C− 4.3

18.5

33.5

33.4

—

14.6

26.8

—

ns

146 WR assertion pulse width

Last WR assertion to RAS

deassertion

147

t_RWL

WR assertion to CAS

deassertion

148

t_CWL

2.5 × T_C− 4.3

33.6

—

27.0

—

ns

0.25 × T_C− 3.7

0.25 × T_C− 3.0

0.1

—

ns

Data valid to CAS assertion

(write)

149

t_DS

0.1

CAS assertion to data not

valid (write)

150

t_DH

1.75 × T_C− 4.0

T_C− 4.3

22.5

10.9

33.9

—

17.9

8.2

—

ns

WR assertion to CAS

assertion

151

t_WCS

Last RD assertion to RAS

deassertion

152

t_ROH

2.5 × T_C− 4.0

1.75 × T_C− 7.5

27.3

—

19.0

—

15.4

—

ns

153 RD assertion to data valid

t_GA

1.75 × T_C− 6.5

RD deassertion to data not

154

t_GZ

0.0

11.1

—

0.0

9.1

—

valid⁶

155 WR assertion to data active

0.75 × T_C− 0.3

0.25 × T_C

—

WR deassertion to data

156

3.8

3.1

high impedance

2-26

DSP56364 Advance Information

MOTOROLA

Specifications

External Memory Expansion Port (Port A)

1, 2, 3, 7

Table 2-10. DRAM Page Mode Timings, Two Wait States

(Continued)

80 MHz

66 MHz

No.

Characteristics

Symbol

Expression

Unit

Min Max Min Max

Notes: 1. The number of wait states for Page mode access is specified in the DCR.

2. The refresh period is specified in the DCR.

3. The asynchronous delays specified in the expressions are valid for DSP56364.

4. All the timings are calculated for the worst case. Some of the timings are better for specific cases (e.g.,

t_PCequals 3 × T_Cfor read-after-read or write-after-write sequences).

5. BRW[1:0] (DRAM Control Register bits) defines the number of wait states that should be inserted in

each DRAM out-of-page access.

6. RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is t_OFFand not

t_GZ.

7. There are no DRAMs fast enough to fit to two wait states Page mode @ 100MHz (See Figure 2-11.)

1, 2, 3

Table 2-11. DRAM Page Mode Timings, Three Wait States

No.

Characteristics

Symbol Expression Min Max Unit

Page mode cycle time for two consecutive accesses

of the same direction

2 × T_C

40.0

—

131

t_PC

ns

Page mode cycle time for mixed (read and write)

accesses

1.25 × T_C

35.0

132 CAS assertion to data valid (read)

t_CAC

t_AA

2 × T_C− 7.0

3 × T_C− 7.0

—

13.0 ns

23.0 ns

133 Column address valid to data valid (read)

134 CAS deassertion to data not valid (read hold time)

135 Last CAS assertion to RAS deassertion

136 Previous CAS deassertion to RAS deassertion

137 CAS assertion pulse width

t_OFF

t_RSH

t_RHCP

t_CAS

0.0

—

ns

2.5 × T_C− 4.0 21.0

4.5 × T_C− 4.0 41.0

2 × T_C− 4.0 16.0

Last CAS deassertion to RAS assertion⁵

• BRW[1:0] = 00

t_CRP

2.25 × T_C− 6.0

3.75 × T_C− 6.0

—

ns

• BRW[1:0] = 01

138

—

ns

• BRW[1:0] = 10

4.75 × T_C− 6.0 41.5

6.75 × T_C− 6.0 61.5

1.5 × T_C− 4.0 11.0

• BRW[1:0] = 11

139 CAS deassertion pulse width

140 Column address valid to CAS assertion

141 CAS assertion to column address not valid

t_CP

t_ASC

t_CAH

T_C− 4.0

6.0

2.5 × T_C− 4.0 21.0

MOTOROLA

DSP56364 Advance Information

2-27

Specifications

External Memory Expansion Port (Port A)

1, 2, 3

Table 2-11. DRAM Page Mode Timings, Three Wait States

(Continued)

No.

Characteristics

Symbol Expression Min Max Unit

142 Last column address valid to RAS deassertion

143 WR deassertion to CAS assertion

144 CAS deassertion to WR assertion

145 CAS assertion to WR deassertion

146 WR assertion pulse width

t_RAL

t_RCS

t_RCH

t_WCH

t_WP

4 × T_C− 4.0 36.0

1.25 × T_C− 4.0 8.5

0.75 × T_C− 4.0 3.5

2.25 × T_C− 4.2 18.3

3.5 × T_C− 4.5 30.5

3.75 × T_C− 4.3 33.2

3.25 × T_C− 4.3 28.2

0.5 × T_C− 4.0 1.0

2.5 × T_C− 4.0 21.0

1.25 × T_C− 4.3 8.2

3.5 × T_C− 4.0 31.0

—

ns

147 Last WR assertion to RAS deassertion

148 WR assertion to CAS deassertion

149 Data valid to CAS assertion (write)

150 CAS assertion to data not valid (write)

151 WR assertion to CAS assertion

152 Last RD assertion to RAS deassertion

153 RD assertion to data valid

t_RWL

t_CWL

t_DS

t_DH

t_WCS

t_ROH

t_GA

2.5 × T_C− 7.0

—

18.0 ns

154 RD deassertion to data not valid⁶

155 WR assertion to data active

t_GZ

0.0

—

ns

0.75 × T_C− 0.3 7.2

0.25 × T_C

156 WR deassertion to data high impedance

—

2.5

Notes: 1. The number of wait states for Page mode access is specified in the DCR.

2. The refresh period is specified in the DCR.

3. The asynchronous delays specified in the expressions are valid for DSP56364.

4. All the timings are calculated for the worst case. Some of the timings are better for specific cases

(e.g., t_PCequals 4 × T_Cfor read-after-read or write-after-write sequences).

5. BRW[1:0] (DRAM control register bits) defines the number of wait states that should be inserted in

each DRAM out-of page-access.

6. RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is t_OFFand

not t_GZ

.

2-28

DSP56364 Advance Information

MOTOROLA

Specifications

External Memory Expansion Port (Port A)

1, 2, 3

Table 2-12. DRAM Page Mode Timings, Four Wait States

No.

Characteristics

Symbol Expression

Min Max

Page mode cycle time for two consecutive accesses

of the same direction.

2 × T_C

50.0

—

131

t_PC

ns

Page mode cycle time for mixed (read and write)

accesses

1.25 × T_C

45.0

132 CAS assertion to data valid (read)

t_CAC

t_AA

2.75 × T_C− 7.0

3.75 × T_C− 7.0

—

20.5 ns

30.5 ns

133 Column address valid to data valid (read)

134 CAS deassertion to data not valid (read hold time)

135 Last CAS assertion to RAS deassertion

136 Previous CAS deassertion to RAS deassertion

137 CAS assertion pulse width

t_OFF

t_RSH

t_RHCP

t_CAS

0.0

—

ns

3.5 × T_C− 4.0 31.0

6 × T_C− 4.0 56.0

2.5 × T_C− 4.0 21.0

Last CAS deassertion to RAS assertion⁵

• BRW[1:0] = 00

t_CRP

2.75 × T_C− 6.0

4.25 × T_C− 6.0

—

• BRW[1:0] = 01

138

—

ns

• BRW[1:0] = 10

5.25 × T_C− 6.0 46.5

7.25 × T_C− 6.0 66.5

• BRW[1:0] = 11

139 CAS deassertion pulse width

t_CP

t_ASC

t_CAH

t_RAL

t_RCS

t_RCH

t_WCH

t_WP

2 × T_C− 4.0

T_C− 4.0

16.0

6.0

ns

140 Column address valid to CAS assertion

141 CAS assertion to column address not valid

142 Last column address valid to RAS deassertion

143 WR deassertion to CAS assertion

144 CAS deassertion to WR assertion

145 CAS assertion to WR deassertion

146 WR assertion pulse width

3.5 × T_C− 4.0 31.0

5 × T_C− 4.0 46.0

1.25 × T_C− 4.0 8.5

3.25 × T_C− 4.2 28.3

4.5 × T_C− 4.5 40.5

4.75 × T_C− 4.3 43.2

3.75 × T_C− 4.3 33.2

0.5 × T_C− 4.0 1.0

3.5 × T_C− 4.0 31.0

1.25 × T_C− 4.3 8.2

147 Last WR assertion to RAS deassertion

148 WR assertion to CAS deassertion

149 Data valid to CAS assertion (write)

150 CAS assertion to data not valid (write)

151 WR assertion to CAS assertion

t_RWL

t_CWL

t_DS

t_DH

t_WCS

MOTOROLA

DSP56364 Advance Information

2-29

Specifications

External Memory Expansion Port (Port A)

1, 2, 3

Table 2-12. DRAM Page Mode Timings, Four Wait States

(Continued)

No.

Characteristics

Symbol Expression

Min Max

152 Last RD assertion to RAS deassertion

153 RD assertion to data valid

t_ROH

t_GA

4.5 × T_C− 4.0 41.0

—

ns

3.25 × T_C− 7.0

—

25.5 ns

154 RD deassertion to data not valid⁶

155 WR assertion to data active

t_GZ

0.0

—

ns

0.75 × T_C− 0.3 7.2

0.25 × T_C

156 WR deassertion to data high impedance

—

2.5

Notes: 1. The number of wait states for Page mode access is specified in the DCR.

2. The refresh period is specified in the DCR.

3. The asynchronous delays specified in the expressions are valid for DSP56364.

4. All the timings are calculated for the worst case. Some of the timings are better for specific cases (e.g.,

t_PCequals 3 × T_Cfor read-after-read or write-after-write sequences).

5. BRW[1:0] (DRAM control register bits) defines the number of wait states that should be inserted in each

DRAM out-of-page access.

6. RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is t_OFFand not

t_GZ

.

2-30

DSP56364 Advance Information

MOTOROLA

Specifications

External Memory Expansion Port (Port A)

RAS

CAS

136

131

135

137

139

141

138

140

151

142

Column

Address

Last Column

Address

Column

Address

Row

Add

A0–A17

144

143

147

145

WR

RD

146

148

155

149

156

150

D0–D7

Data Out

AA0473

Figure 2-12. DRAM Page Mode Write Accesses

MOTOROLA

DSP56364 Advance Information

2-31

Specifications

External Memory Expansion Port (Port A)

RAS

136

135

131

CAS

137

139

141

138

142

140

Row

Add

Last Column

Address

Column

Address

Column

Address

A0–A17

WR

143

132

133

153

152

RD

134

154

D0–D7

Data In

AA0474

Figure 2-13. DRAM Page Mode Read Accesses

2-32

DSP56364 Advance Information

MOTOROLA

Specifications

External Memory Expansion Port (Port A)

DRAM Type

(t_RACns)

Note: This figure should be use for primary selection. For

exact and detailed timings see the following tables.

100

80

70

60

Chip Frequency

(MHz)

50

120

40 66

80

100

4 Wait States

8 Wait States

11 Wait States

15 Wait States

AA0475

Figure 2-14. DRAM Out-of-Page Wait States Selection Guide

1, 2

Table 2-13. DRAM Out-of-Page and Refresh Timings, Four Wait States

20 MHz⁴

30 MHz⁴

Characteristics³

No.

Symbol

Expression

Unit

Min

Max

Min

Max

Random read or write cycle

time

157

158

159

160

t_RC

t_RAC

t_CAC

t_AA

5 × T_C

250.0

—

166.7

—

ns

RAS assertion to data valid

(read)

2.75 × T_C− 7.5

1.25 × T_C− 7.5

1.5 × T_C− 7.5

130.0

55.0

67.5

84.2

34.2

42.5

CAS assertion to data valid

(read)

—

Column address valid to data

valid (read)

—

MOTOROLA

DSP56364 Advance Information

2-33

Specifications

External Memory Expansion Port (Port A)

1, 2

Table 2-13. DRAM Out-of-Page and Refresh Timings, Four Wait States

(Continued)

20 MHz⁴

30 MHz⁴

Characteristics³

No.

Symbol

Expression

Unit

Min

Max

Min

Max

CAS deassertion to data not

valid (read hold time)

161

t_OFF

0.0

—

0.0

—

ns

RAS deassertion to RAS

assertion

162

t_RP

1.75 × T_C− 4.0

83.5

—

54.3

104.3

54.3

—

ns

163 RAS assertion pulse width

t_RAS

t_RSH

3.25 × T_C− 4.0 158.5

1.75 × T_C− 4.0

83.5

CAS assertion to RAS

deassertion

164

RAS assertion to CAS

deassertion

165

t_CSH

t_CAS

t_RCD

2.75 × T_C− 4.0 133.5

—

87.7

37.7

48.0

—

ns

166 CAS assertion pulse width

1.25 × T_C− 4.0

1.5 × T_C± 2

58.5

73.0

RAS assertion to CAS

assertion

167

77.0

52.0

RAS assertion to column

address valid

168

t_RAD

1.25 × T_C± 2

60.5

64.5

39.7

43.7

ns

CAS deassertion to RAS

assertion

169

t_CRP

t_CP

2.25 × T_C− 4.0 108.5

—

71.0

54.3

—

ns

170 CAS deassertion pulse width

1.75 × T_C− 4.0

83.5

Row address valid to RAS

assertion

171

t_ASR

RAS assertion to row address

not valid

172

t_RAH

t_ASC

t_CAH

t_AR

1.25 × T_C− 4.0

0.25 × T_C− 4.0

1.75 × T_C− 4.0

58.5

8.5

—

37.7

4.3

—

ns

Column address valid to CAS

assertion

173

CAS assertion to column

174

83.5

54.3

104.3

62.7

46.2

21.3

address not valid

RAS assertion to column

175

3.25 × T_C− 4.0 158.5

address not valid

Column address valid to RAS

deassertion

176

t_RAL

t_RCS

t_RCH

2 × T_C− 4.0

1.5 × T_C− 3.8

0.75 × T_C− 3.7

96.0

71.2

33.8

WR deassertion to CAS

assertion

177

CAS deassertion to WR

assertion

178

2-34

DSP56364 Advance Information

MOTOROLA

Specifications

External Memory Expansion Port (Port A)

1, 2

Table 2-13. DRAM Out-of-Page and Refresh Timings, Four Wait States

(Continued)

20 MHz⁴

30 MHz⁴

Characteristics³

No.

Symbol

Expression

Unit

Min

Max

Min

Max

RAS deassertion to WR

assertion

179

180

181

t_RRH

0.25 × T_C− 3.7

1.5 × T_C− 4.2

8.8

—

4.6

—

ns

CAS assertion to WR

deassertion

t_WCH

70.8

—

45.8

—

RAS assertion to WR

deassertion

t_WCR

t_WP

3 × T_C− 4.2

145.8

220.5

—

95.8

145.5

154.0

—

ns

182 WR assertion pulse width

4.5 × T_C− 4.5

WR assertion to RAS

deassertion

183

t_RWL

4.75 × T_C− 4.3 233.2

4.25 × T_C− 4.3 208.2

2.25 × T_C− 4.0 108.5

WR assertion to CAS

deassertion

184

t_CWL

—

137.4

71.0

54.3

—

ns

Data valid to CAS assertion

(write)

185

t_DS

CAS assertion to data not valid

(write)

186

t_DH

1.75 × T_C− 4.0

83.5

RAS assertion to data not valid

(write)

187

t_DHR

3.25 × T_C− 4.0 158.5

—

104.3

95.7

12.7

—

ns

188 WR assertion to CAS assertion t_WCS

CAS assertion to RAS

3 × T_C− 4.3

145.7

21.0

189

190

191

t_CSR

0.5 × T_C− 4.0

assertion (refresh)

RAS deassertion to CAS

assertion (refresh)

t_RPC

1.25 × T_C− 4.0

58.5

—

37.7

—

ns

RD assertion to RAS

deassertion

t_ROH

t_GA

4.5 × T_C− 4.0

4 × T_C− 7.5

221.0

—

192.5

—

146.0

—

192 RD assertion to data valid

125.8 ns

RD deassertion to data not

193

t_GZ

0.0

—

ns

valid³

194 WR assertion to data active

0.75 × T_C− 0.3

0.25 × T_C

37.2

—

24.7

—

WR deassertion to data high

impedance

195

12.5

8.3

MOTOROLA

DSP56364 Advance Information

2-35

Specifications

External Memory Expansion Port (Port A)

1, 2

Table 2-13. DRAM Out-of-Page and Refresh Timings, Four Wait States

(Continued)

20 MHz⁴

30 MHz⁴

Characteristics³

No.

Symbol

Expression

Unit

Min

Max

Min

Max

Notes: 1. The number of wait states for out of page access is specified in the DCR.

2. The refresh period is specified in the DCR.

3. RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is t_OFFand not

t_GZ

.

4. Reduced DSP clock speed allows use of DRAM out-of-page access with four Wait states (See

Figure 2-17.).

1, 2

Table 2-14. DRAM Out-of-Page and Refresh Timings, Eight Wait States

66 MHz

80 MHz

Characteristics⁴

Expression³

No.

Symbol

Unit

Min

Max

Min

Max

Random read or write cycle

time

157

t_RC

9 × T_C

136.4

—

112.5

—

ns

4.75 × T_C− 7.5

4.75 × T_C− 6.5

2.25 × T_C− 7.5

2.25 × T_C− 6.5

3 × T_C− 7.5

—

64.5

—

52.9

—

ns

RAS assertion to data valid

(read)

158

t_RAC

26.6

—

CAS assertion to data valid

(read)

159

160

t_CAC

21.6

—

40.0

—

Column address valid to data

valid (read)

t_AA

3 × T_C− 6.5

31.0

CAS deassertion to data not

valid (read hold time)

161

162

t_OFF

0.0

—

0.0

—

ns

RAS deassertion to RAS

assertion

t_RP

3.25 × T_C− 4.0 45.2

5.75 × T_C− 4.0 83.1

3.25 × T_C− 4.0 45.2

—

36.6

67.9

36.6

—

ns

163 RAS assertion pulse width

t_RAS

t_RSH

CAS assertion to RAS

deassertion

164

RAS assertion to CAS

deassertion

165

t_CSH

t_CAS

t_RCD

4.75 × T_C− 4.0 68.0

2.25 × T_C− 4.0 30.1

—

55.5

24.1

29.3

—

ns

166 CAS assertion pulse width

RAS assertion to CAS

assertion

167

2.5 × T_C± 2

35.9

39.9

33.3

2-36

DSP56364 Advance Information

MOTOROLA

Specifications

External Memory Expansion Port (Port A)

1, 2

Table 2-14. DRAM Out-of-Page and Refresh Timings, Eight Wait States

(Continued)

66 MHz

80 MHz

Characteristics⁴

Expression³

No.

Symbol

Unit

Min

24.5

Max

Min

Max

RAS assertion to column

address valid

168

169

t_RAD

1.75 × T_C± 2

28.5

19.9

23.9

ns

CAS deassertion to RAS

assertion

t_CRP

t_CP

4.25 × T_C− 4.0 59.8

2.75 × T_C− 4.0 37.7

3.25 × T_C− 4.0 45.2

—

49.1

30.4

36.6

—

ns

170 CAS deassertion pulse width

Row address valid to RAS

assertion

171

t_ASR

RAS assertion to row address

not valid

172

t_RAH

t_ASC

t_CAH

t_AR

1.75 × T_C− 4.0 22.5

—

17.9

5.4

—

ns

Column address valid to CAS

assertion

173

0.75 × T_C− 4.0

7.4

CAS assertion to column

174

3.25 × T_C− 4.0 45.2

5.75 × T_C− 4.0 83.1

36.6

67.9

46.0

21.2

11.9

address not valid

RAS assertion to column

175

address not valid

Column address valid to RAS

deassertion

176

t_RAL

t_RCS

t_RCH

4 × T_C− 4.0

2 × T_C− 3.8

56.6

26.5

WR deassertion to CAS

assertion

177

CAS deassertion to WR⁵

assertion

178

1.25 × T_C− 3.7 15.2

0.25 × T_C− 3.7

0.25 × T_C− 3.0

0.1

—

ns

RAS deassertion to WR⁵

assertion

179

t_RRH

0.1

CAS assertion to WR

deassertion

180

t_WCH

3 × T_C− 4.2

41.3

79.1

—

33.3

—

ns

RAS assertion to WR

deassertion

181

t_WCR

t_WP

5.5 × T_C− 4.2

—

64.6

101.8

105.1

—

ns

182 WR assertion pulse width

8.5 × T_C− 4.5 124.3

8.75 × T_C− 4.3 128.3

WR assertion to RAS

deassertion

183

t_RWL

WR assertion to CAS

deassertion

184

t_CWL

7.75 × T_C− 4.3 113.1

—

92.6

—

ns

MOTOROLA

DSP56364 Advance Information

2-37

Specifications

External Memory Expansion Port (Port A)

1, 2

Table 2-14. DRAM Out-of-Page and Refresh Timings, Eight Wait States

(Continued)

66 MHz

80 MHz

Characteristics⁴

Expression³

No.

Symbol

Unit

Min

Max

Min

Max

Data valid to CAS assertion

(write)

185

186

187

t_DS

4.75 × T_C− 4.0 68.0

3.25 × T_C− 4.0 45.2

5.75 × T_C− 4.0 83.1

—

55.4

36.6

—

ns

CAS assertion to data not valid

(write)

t_DH

—

RAS assertion to data not valid

(write)

t_DHR

t_WCS

t_CSR

—

67.9

64.5

14.8

—

ns

188 WR assertion to CAS assertion

5.5 × T_C− 4.3

1.5 × T_C− 4.0

79.0

18.7

CAS assertion to RAS

189

assertion (refresh)

RAS deassertion to CAS

190

t_RPC

1.75 × T_C− 4.0 22.5

8.5 × T_C− 4.0 124.8

—

17.9

—

ns

assertion (refresh)

RD assertion to RAS

191

t_ROH

102.3

deassertion

7.5 × T_C− 7.5

7.5 × T_C− 6.5

—

106.1

—

ns

192 RD assertion to data valid

t_GA

87.3

RD deassertion to data not

193

t_GZ

0.0

—

0.0

9.1

—

ns

valid⁴

194 WR assertion to data active

0.75 × T_C− 0.3 11.1

0.25 × T_C

WR deassertion to data high

impedance

195

—

3.8

3.1

Notes: 1. The number of wait states for out-of-page access is specified in the DCR.

2. The refresh period is specified in the DCR.

3. The asynchronous delays specified in the expressions are valid for DSP56364.

4. RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is t_OFFand

not t_GZ

5. Either t_RCHor t_RRHmust be satisfied for read cycles.

.

2-38

DSP56364 Advance Information

MOTOROLA

Specifications

External Memory Expansion Port (Port A)

1, 2

Table 2-15. DRAM Out-of-Page and Refresh Timings, Eleven Wait States

Characteristics⁴

Expression³

No.

Symbol

Min Max Unit

157 Random read or write cycle time

158 RAS assertion to data valid (read)

159 CAS assertion to data valid (read)

160 Column address valid to data valid (read)

t_RC

t_RAC

t_CAC

t_AA

12 × T_C

120.0

—

ns

6.25 × T_C− 7.0

3.75 × T_C− 7.0

4.5 × T_C− 7.0

55.5

30.5

38.0

—

CAS deassertion to data not valid (read hold

time)

161

t_OFF

0.0

—

ns

162 RAS deassertion to RAS assertion

163 RAS assertion pulse width

t_RP

t_RAS

t_RSH

t_CSH

t_CAS

t_RCD

t_RAD

t_CRP

t_CP

4.25 × T_C− 4.0 38.5

7.75 × T_C− 4.0 73.5

5.25 × T_C− 4.0 48.5

6.25 × T_C− 4.0 58.5

3.75 × T_C− 4.0 33.5

—

ns

164 CAS assertion to RAS deassertion

165 RAS assertion to CAS deassertion

166 CAS assertion pulse width

167 RAS assertion to CAS assertion

168 RAS assertion to column address valid

169 CAS deassertion to RAS assertion

170 CAS deassertion pulse width

2.5 × T_C± 4.0 21.0 29.0

1.75 × T_C± 4.0 13.5 21.5

5.75 × T_C− 4.0 53.5

4.25 × T_C− 4.0 38.5

1.75 × T_C− 4.0 13.5

0.75 × T_C− 4.0 3.5

5.25 × T_C− 4.0 48.5

7.75 × T_C− 4.0 73.5

—

171 Row address valid to RAS assertion

172 RAS assertion to row address not valid

173 Column address valid to CAS assertion

174 CAS assertion to column address not valid

175 RAS assertion to column address not valid

176 Column address valid to RAS deassertion

177 WR deassertion to CAS assertion

178 CAS deassertion to WR⁵assertion

179 RAS deassertion to WR⁵assertion

180 CAS assertion to WR deassertion

181 RAS assertion to WR deassertion

182 WR assertion pulse width

t_ASR

t_RAH

t_ASC

t_CAH

t_AR

t_RAL

t_RCS

t_RCH

t_RRH

t_WCH

t_WCR

t_WP

6 × T_C− 4.0

56.0

3.0 × T_C− 4.0 26.0

1.75 × T_C− 4.0 13.5

0.25 × T_C− 2.0 0.5

5 × T_C− 4.2

45.8

7.5 × T_C− 4.2 70.8

11.5 × T_C− 4.5 110.5

MOTOROLA

DSP56364 Advance Information

2-39

Specifications

External Memory Expansion Port (Port A)

1, 2

Table 2-15. DRAM Out-of-Page and Refresh Timings, Eleven Wait States

(Continued)

Characteristics⁴

Expression³

No.

Symbol

Min Max Unit

183 WR assertion to RAS deassertion

184 WR assertion to CAS deassertion

185 Data valid to CAS assertion (write)

186 CAS assertion to data not valid (write)

187 RAS assertion to data not valid (write)

188 WR assertion to CAS assertion

t_RWL11.75 × T_C− 4.3 113.2

t_CWL10.25 × T_C− 4.3 103.2

—

ns

t_DS

t_DH

5.75 × T_C− 4.0 53.5

5.25 × T_C− 4.0 48.5

7.75 × T_C− 4.0 73.5

6.5 × T_C− 4.3 60.7

1.5 × T_C− 4.0 11.0

2.75 × T_C− 4.0 23.5

11.5 × T_C− 4.0 111.0

t_DHR

t_WCS

t_CSR

t_RPC

t_ROH

189 CAS assertion to RAS assertion (refresh)

190 RAS deassertion to CAS assertion (refresh)

191 RD assertion to RAS deassertion

192 RD assertion to data valid

t_GA

t_GZ

—

93.0

ns

10 × T_C− 7.0

193 RD deassertion to data not valid⁴

194 WR assertion to data active

0.0

—

ns

0.75 × T_C− 0.3 7.2

195 WR deassertion to data high impedance

0.25 × T_C

—

2.5

Notes: 1. The number of wait states for out-of-page access is specified in the DCR.

2. The refresh period is specified in the DCR.

3. The asynchronous delays specified in the expressions are valid for DSP56364.

4. RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is t_OFFand

not t_GZ

5. Either t_RCHor t_RRHmust be satisfied for read cycles.

.

2-40

DSP56364 Advance Information

MOTOROLA

Specifications

External Memory Expansion Port (Port A)

1, 2

Table 2-16. DRAM Out-of-Page and Refresh Timings, Fifteen Wait States

Characteristics³

No.

Symbol

Expression

Min

Max Unit

157 Random read or write cycle time

158 RAS assertion to data valid (read)

159 CAS assertion to data valid (read)

160 Column address valid to data valid (read)

t_RC

t_RAC

t_CAC

t_AA

16 × T_C

160.0

—

ns

8.25 × T_C− 5.7

4.75 × T_C− 5.7

5.5 × T_C− 5.7

76.8

41.8

49.3

—

CAS deassertion to data not valid (read hold

time)

161

t_OFF

0.0

—

ns

162 RAS deassertion to RAS assertion

163 RAS assertion pulse width

t_RP

t_RAS

t_RSH

t_CSH

t_CAS

t_RCD

t_RAD

t_CRP

t_CP

6.25 × T_C− 4.0

9.75 × T_C− 4.0

6.25 × T_C− 4.0

8.25 × T_C− 4.0

4.75 × T_C− 4.0

3.5 × T_C± 2

58.5

93.5

58.5

78.5

43.5

33.0

25.5

73.5

58.5

23.5

3.5

—

ns

164 CAS assertion to RAS deassertion

165 RAS assertion to CAS deassertion

166 CAS assertion pulse width

—

167 RAS assertion to CAS assertion

168 RAS assertion to column address valid

169 CAS deassertion to RAS assertion

170 CAS deassertion pulse width

37.0

29.5

—

2.75 × T_C± 2

7.75 × T_C− 4.0

6.25 × T_C− 4.0

2.75 × T_C− 4.0

0.75 × T_C− 4.0

6.25 × T_C− 4.0

9.75 × T_C− 4.0

7 × T_C− 4.0

—

171 Row address valid to RAS assertion

172 RAS assertion to row address not valid

173 Column address valid to CAS assertion

174 CAS assertion to column address not valid

175 RAS assertion to column address not valid

176 Column address valid to RAS deassertion

177 WR deassertion to CAS assertion

178 CAS deassertion to WR⁵assertion

179 RAS deassertion to WR⁵assertion

180 CAS assertion to WR deassertion

181 RAS assertion to WR deassertion

t_ASR

t_RAH

t_ASC

t_CAH

t_AR

—

58.5

93.5

66.0

46.2

13.8

0.5

—

t_RAL

t_RCS

t_RCH

t_RRH

t_WCH

t_WCR

—

5 × T_C− 3.8

—

1.75 × T_C− 3.7

0.25 × T_C− 2.0

6 × T_C− 4.2

—

55.8

90.8

—

9.5 × T_C− 4.2

—

MOTOROLA

DSP56364 Advance Information

2-41

Specifications

External Memory Expansion Port (Port A)

1, 2

Table 2-16. DRAM Out-of-Page and Refresh Timings, Fifteen Wait States

(Continued)

Max Unit

Characteristics³

No.

Symbol

Expression

Min

150.5

182 WR assertion pulse width

t_WP

t_RWL

t_CWL

t_DS

15.5 × T_C− 4.5

—

ns

183 WR assertion to RAS deassertion

184 WR assertion to CAS deassertion

185 Data valid to CAS assertion (write)

186 CAS assertion to data not valid (write)

187 RAS assertion to data not valid (write)

188 WR assertion to CAS assertion

189 CAS assertion to RAS assertion (refresh)

190 RAS deassertion to CAS assertion (refresh)

191 RD assertion to RAS deassertion

192 RD assertion to data valid

15.75 × T_C− 4.3 153.2

14.25 × T_C− 4.3 138.2

8.75 × T_C− 4.0

6.25 × T_C− 4.0

9.75 × T_C− 4.0

9.5 × T_C− 4.3

1.5 × T_C− 4.0

4.75 × T_C− 4.0

15.5 × T_C− 4.0

14 × T_C− 5.7

83.5

58.5

93.5

90.7

11.0

43.5

151.0

—

t_DH

t_DHR

t_WCS

t_CSR

t_RPC

t_ROH

t_GA

134.3 ns

193 RD deassertion to data not valid³

194 WR assertion to data active

t_GZ

0.0

—

ns

0.75 × T_C− 0.3

0.25 × T_C

7.2

195 WR deassertion to data high impedance

—

2.5

Notes: 1. The number of wait states for out-of-page access is specified in the DCR.

2. The refresh period is specified in the DCR.

3. RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is t_OFFand not

t_GZ

4. Either t_RCHor t_RRHmust be satisfied for read cycles.

.

2-42

DSP56364 Advance Information

MOTOROLA

Specifications

External Memory Expansion Port (Port A)

157

162

169

163

165

162

RAS

167

168

164

170

166

CAS

171

173

174

175

Row Address

Column Address

A0–A17

172

176

177

179

191

WR

RD

168

160

159

193

158

192

161

Data

In

D0–D7

AA0476

Figure 2-15. DRAM Out-of-Page Read Access

MOTOROLA

DSP56364 Advance Information

2-43

Specifications

External Memory Expansion Port (Port A)

157

162

163

165

162

RAS

167

168

164

169

170

166

CAS

171

173

172

174

176

Row Address

Column Address

A0–A17

181

175

188

180

182

WR

RD

184

183

187

186

185

195

194

Data Out

D0–D7

AA0477

Figure 2-16. DRAM Out-of-Page Write Access

2-44

DSP56364 Advance Information

MOTOROLA

Specifications

External Memory Expansion Port (Port A)

157

162

163

165

162

RAS

CAS

190

170

189

177

WR

AA0478

Figure 2-17. DRAM Refresh Access

MOTOROLA

DSP56364 Advance Information

2-45

Specifications

Serial Host Interface SPI Protocol Timing

SERIAL HOST INTERFACE SPI PROTOCOL TIMING

Table 2-17. Serial Host Interface SPI Protocol Timing

Filter

No.

Characteristics

Mode

Expression

Min

Max

Unit

Mode

Bypassed

Narrow

—

0

50

100

—

ns

Tolerable spike width on clock or data

in

140

—

Wide

—

Bypassed

6×T_C+46

6×T_C+152

6×T_C+223

106

212

283

43

Minimum serial clock cycle =

t_SPICC(min)

141

Master Narrow

Wide

—

Bypassed 0.5×t_SPICC–10

—

Master Narrow

0.5×t_SPICC–10

2.5×T_C+12

96

—

Wide

Bypassed

Narrow

Wide

131

37

—

142 Serial clock high period

—

Slave

2.5×T_C+102

2.5×T_C+189

127

214

43

—

Bypassed 0.5×t_SPICC–10

—

Master Narrow

Wide

0.5×t_SPICC–10

2.5×T_C+12

2.5×T_C+102

2.5×T_C+189

—

96

—

131

37

—

143 Serial clock low period

144 Serial clock rise/fall time

Bypassed

—

Slave

Narrow

Wide

—

127

214

—

Master

Slave

10

2000

—

2-46

DSP56364 Advance Information

MOTOROLA

Specifications

Serial Host Interface SPI Protocol Timing

Table 2-17. Serial Host Interface SPI Protocol Timing (Continued)

Filter

Mode

No.

Characteristics

Mode

Expression

Min

Max

Unit

Bypassed

Narrow

Wide

3.5×T_C+15

50

0

—

ns

SS assertion to first SCK edge

CPHA = 0

0

Slave

0

146

Slave Bypassed

Narrow

10

0

10

0

—

ns

CPHA = 1

Wide

0

Bypassed

12

102

189

0

12

102

189

0

147 Last SCK edge to SS not asserted

Slave

Narrow

Wide

Bypassed

Data input valid to SCK edge (data

input set-up time)

Master

/Slave

148

Narrow MAX{(20-T_C), 0}

10

30

35

55

75

2

Wide

Bypassed

Narrow

Wide

MAX{(40-T_C), 0}

2.5×T_C+10

2.5×T_C+30

2.5×T_C+50

2

SCK last sampling edge to data input Master

149

not valid

/Slave

150 SS assertion to data out active

Slave

—

SS deassertion to data high

impedance

151

—

9

—

9

ns

Bypassed

Narrow

Wide

2×T_C+33

2×T_C+123

2×T_C+210

T_C+5

—

53

143

230

—

ns

SCK edge to data out valid

152

Master

/Slave

(data out delay time)

—

Bypassed

Narrow

Wide

15

65

116

SCK edge to data out not valid

Master

/Slave

153

T_C+55

—

(data out hold time)

T_C+106

—

SS assertion to data out valid

(CPHA = 0)

154

Slave

—

T_C+33

—

43

ns

MOTOROLA

DSP56364 Advance Information

2-47

Specifications

Serial Host Interface SPI Protocol Timing

Table 2-17. Serial Host Interface SPI Protocol Timing (Continued)

Filter

Mode

No.

Characteristics

Mode

Expression

Min

Max

Unit

Bypassed

Narrow

Wide

2.5×T_C+30

2.5×T_C+120

2.5×T_C+217

2.5×T_C+30

2.5×T_C+80

2.5×T_C+136

—

55

145

242

—

ns

First SCK sampling edge to HREQ

output deassertion

157

Slave

—

Bypassed

Narrow

Wide

55

Last SCK sampling edge to HREQ

output not deasserted (CPHA = 1)

158

Slave

105

161

—

SS deassertion to HREQ output not

deasserted (CPHA = 0)

159

160

Slave

—

2.5×T_C+30

55

16

—

ns

SS deassertion pulse width (CPHA =

0)

T_C+6

0.5 × t_SPICC

2.5×T_C+43

+

Bypassed

121

174

209

0.5 ×t_SPICC

+

161 HREQ in assertion to first SCK edge Master Narrow

2.5×T_C+43

0.5 ×t_SPICC

+

Wide

2.5×T_C+43

HREQ in deassertion to last SCK

162 sampling edge (HREQ in set-up time) Master

(CPHA = 1)

—

0

—

ns

First SCK edge to HREQ in not

163 asserted

(HREQ in hold time)

Master

Note:

Periodically sampled, not 100% tested

2-48

DSP56364 Advance Information

MOTOROLA

Specifications

Serial Host Interface SPI Protocol Timing

SS

(Input)

143

141

144

142

143

144

SCK (CPOL = 0)

(Output)

141

144

142

SCK (CPOL = 1)

(Output)

148

149

148

149

MISO

(Input)

MSB

Valid

LSB

Valid

153

152

MSB

MOSI

(Output)

LSB

161

163

HREQ

(Input)

AA0271

Figure 2-18. SPI Master Timing (CPHA = 0)

MOTOROLA

DSP56364 Advance Information

2-49

Specifications

Serial Host Interface SPI Protocol Timing

SS

(Input)

143

141

142

143

144

SCK (CPOL = 0)

(Output)

142

144

SCK (CPOL = 1)

(Output)

148

149

MISO

(Input)

MSB

Valid

LSB

Valid

152

153

MOSI

(Output)

MSB

LSB

161

162

163

HREQ

(Input)

AA0272

Figure 2-19. SPI Master Timing (CPHA = 1)

2-50

DSP56364 Advance Information

MOTOROLA

Specifications

Serial Host Interface SPI Protocol Timing

SS

(Input)

143

141

147

142

144

160

SCK (CPOL = 0)

(Input)

146

142

144

143

SCK (CPOL = 1)

(Input)

154

152

153

151

LSB

150

MISO

(Output)

MSB

148

149

MSB

Valid

MOSI

(Input)

LSB

Valid

157

159

HREQ

(Output)

AA0273

Figure 2-20. SPI Slave Timing (CPHA = 0)

MOTOROLA

DSP56364 Advance Information

2-51

Specifications

Serial Host Interface SPI Protocol Timing

SS

(Input)

143

141

147

142

144

SCK (CPOL = 0)

(Input)

146

142

144

143

SCK (CPOL = 1)

(Input)

152

153

151

150

MISO

(Output)

MSB

LSB

148

149

MSB

Valid

LSB

Valid

MOSI

(Input)

157

158

HREQ

(Output)

AA0274

Figure 2-21. SPI Slave Timing (CPHA = 1)

2-52

DSP56364 Advance Information

MOTOROLA

Specifications

Serial Host Interface (SHI) I²C Protocol Timing

2

SERIAL HOST INTERFACE (SHI) I C PROTOCOL TIMING

2

Table 2-18. SHI I C Protocol Timing

Standard I²C*

Standard-

Mode

Fast-Mode

Unit

Symbol/

Expression

No.

Characteristics

Min

Max

Min

Max

Tolerable spike width on SCL

or SDA

Filters bypassed

—

0

50

—

0

ns

kHz

µs

ns

µs

pF

—

Narrow filters enabled

Wide filters enabled

—

50

—

100

—

100

400

—

171 SCL clock frequency

172 Bus free time

F_SCL

T_BUF

—

4.7

4.0

4.7

4.0

—

1.3

173 Start condition set-up time

174 Start condition hold time

175 SCL low period

T_SU;STA

T_HD;STA

T_LOW

—

0.6

—

0.6

—

1.3

—

176 SCL high period

T_HIGH

—

1.3

—

177 SCL and SDA rise time

178 SCL and SDA fall time

179 Data set-up time

T

1000

300

—

20 + 0.1 × C_b

300

—

R

T

—

20 + 0.1 × C_b

F

T_SU;DAT

T_HD;DAT

T_SU;STO

C_b

250

0.0

4.0

—

100

0.0

0.6

—

180 Data hold time

—

0.9

—

181 Stop condition set-up time

182 Capacitive load for each line

—

400

DSP clock frequency

Filters bypassed

10.6

11.8

13.1

—

28.5

39.7

61.0

—

MHz

183

F_DSP

Narrow filters enabled

Wide filters enabled

MOTOROLA

DSP56364 Advance Information

2-53

Specifications

Serial Host Interface (SHI) I²C Protocol Timing

2

Table 2-18. SHI I C Protocol Timing (Continued)

Standard I²C*

Standard-

Mode

Fast-Mode

Min

Unit

Symbol/

Expression

No.

Characteristics

Min

Max

HREQ in deassertion to last

184 SCL edge

(HREQ in set-up time)

t_SU;RQI

0.0

—

0.0

—

ns

First SCL sampling edge to

HREQ output deassertion²

T_NG;RQO

Filters bypassed

Narrow filters enabled

Wide filters enabled

2 × T_C+ 30

2 × T_C+ 120

2 × T_C+ 208

—

50

—

50

186

ns

140

228

140

228

Last SCL edge to HREQ

output not deasserted²

T_AS;RQO

Filters bypassed

Narrow filters enabled

Wide filters enabled

2 × T_C+ 30

2 × T_C+ 80

2 × T_C+ 135

50

—

50

—

187

100

155

100

155

HREQ in assertion to first SCL

edge

T_AS;RQI

Filters bypassed

Narrow filters enabled

Wide filters enabled

R_P(min) = 1.5 k¾

4327

4282

4238

—

927

882

838

—

188

0.5 × T_I2_CCP

-

0.5 × T_C- 21

Note:

2-54

DSP56364 Advance Information

MOTOROLA

Specifications

Serial Host Interface (SHI) I²C Protocol Timing

Programming the Serial Clock

2

The programmed serial clock cycle, T

, is specified by the value of the HDM[5:0] and HRS

I CCP

bits of the HCKR (SHI clock control register).

2

The expression for T

is

I CCP

I²CCP

T

= [T × 2 × (HDM[7:0] + 1) × (7 × (1 – HRS) + 1)]

C

where

–

HRS is the prescaler rate select bit. When HRS is cleared, the fixed

divide-by-eight prescaler is operational. When HRS is set, the prescaler is bypassed.

–

HDM[7:0] are the divider modulus select bits.

A divide ratio from 1 to 64 (HDM[5:0] = 0 to $3F) may be selected.

2

In I C mode, the user may select a value for the programmed serial clock cycle from

6 × T

(if HDM[5:0] = $02 and HRS = 1)

C

to

4096 × T

(if HDM[7:0] = $FF and HRS = 0)

C

2

The programmed serial clock cycle (T

), SCL rise time (T ), and the filters selected should

R

I CCP

be chosen in order to achieve the desired SCL frequency, as shown in Table 2-23.

Table 2-19. SCL Serial Clock Cycle generated as Master

2

Filters bypassed

T

+ 2.5 × T_C+ 45ns + T

I CCP

R

2

Narrow filters enabled T

+ 2.5 × T_C+ 135ns + T

+ 2.5 × T_C+ 223ns + T

I CCP

R

2

Wide filters enabled

T

I CCP

EXAMPLE:

For DSP clock frequency of 100 MHz (i.e. T = 10ns), operating in a standard-mode I C

2

C

environment (F

= 100 KHz (i.e. T

= 10µs), T = 1000ns), with filters bypassed

SCL

SCL R

2

T

= 10µs - 2.5×10ns - 45ns - 1000ns = 8930ns

ICCP

MOTOROLA

DSP56364 Advance Information

2-55

Specifications

Serial Host Interface (SHI) I²C Protocol Timing

Choosing HRS = 0 gives

HDM[7:0] = 8930ns / (2× 10ns× 8) - 1 = 55.8

Thus the HDM[7:0] value should be programmed to $38 (=56).

171

173

176

175

SCL

SDA

177

180

178

172

179

MSB

LSB

ACK

Stop

Start

174

188

186

182

183

187

189

184

HREQ

AA0275

2

Figure 2-22. I C Timing

2-56

DSP56364 Advance Information

MOTOROLA

Specifications

Enhanced Serial Audio Interface Timing

ENHANCED SERIAL AUDIO INTERFACE TIMING

Table 2-20. Enhanced Serial Audio Interface Timing

Cond-

ition⁴

Characteristics^{1, 2, 3}

No.

Symbol

Expression

Min

Max

Unit

4 × T

3 × T

40.0

—

i ck

C

30.0

x ck

430 Clock cycle⁵

t_SSICC

ns

TXC:max[3*tc;

t454]

40.0

—

x ck

Clock high period

—

2 × T − 10.0

10.0

15.0

10.0

15.0

—

C

• For internal clock

431

432

ns

• For external clock

1.5 × T

C

Clock low period

—

2 × T − 10.0

C

• For internal clock

• For external clock

1.5 × T

—

C

—

37.0

22.0 i ck a

x ck

433 RXC rising edge to FSR out (bl) high

434 RXC rising edge to FSR out (bl) low

435 RXC rising edge to FSR out (wr) high⁶

436 RXC rising edge to FSR out (wr) low⁶

437 RXC rising edge to FSR out (wl) high

438 RXC rising edge to FSR out (wl) low

—

ns

—

37.0 x ck

—

22.0 i ck a

39.0 x ck

—

24.0 i ck a

—

39.0 x ck

24.0 i ck a

36.0 x ck

—

21.0 i ck a

—

37.0 x ck

22.0 i ck a

Data in setup time before RXC (SCK in

439

0.0

19.0

—

x ck

i ck

synchronous mode) falling edge

5.0

3.0

—

x ck

i ck

440 Data in hold time after RXC falling edge

FSR input (bl, wr) high before RXC

23.0

1.0

—

x ck

i ck a

441

falling edge ⁶

FSR input (wl) high before RXC falling

edge

1.0

23.0

—

x ck

i ck a

442

MOTOROLA

DSP56364 Advance Information

2-57

Specifications

Enhanced Serial Audio Interface Timing

Table 2-20. Enhanced Serial Audio Interface Timing (Continued)

Cond-

ition⁴

Characteristics^{1, 2, 3}

No.

Symbol

Expression

Min

Max

Unit

FSR input hold time after RXC falling

edge

3.0

0.0

—

x ck

i ck a

443

444

445

—

ns

—

Flags input setup before RXC falling

edge

0.0

19.0

—

x ck

i ck s

Flags input hold time after RXC falling

edge

6.0

0.0

—

x ck

i ck s

—

29.0

15.0

x ck

i ck

446 TXC rising edge to FST out (bl) high

447 TXC rising edge to FST out (bl) low

448 TXC rising edge to FST out (wr) high⁶

449 TXC rising edge to FST out (wr) low⁶

450 TXC rising edge to FST out (wl) high

451 TXC rising edge to FST out (wl) low

—

31.0

17.0

x ck

i ck

—

31.0

17.0

x ck

i ck

—

33.0

19.0

x ck

i ck

—

30.0

16.0

x ck

i ck

—

31.0

17.0

x ck

i ck

TXC rising edge to data out enable from

high impedance

—

31.0

17.0

x ck

i ck

452

TXC rising edge to transmitter #0 drive

enable assertion

—

34.0

20.0

x ck

i ck

453

23 + 0.5 × T

—

28.0

21.0

x ck

i ck

C

454 TXC rising edge to data out valid

21.0

TXC rising edge to data out high

—

31.0

16.0

x ck

i ck

455

—

impedance⁷

TXC rising edge to transmitter #0 drive

—

34.0

20.0

x ck

i ck

456

enable deassertion⁷

FST input (bl, wr) setup time before

2.0

21.0

—

x ck

i ck

457

—

TXC falling edge⁶

—

FST input (wl) to data out enable from

high impedance

458

—

27.0

—

2-58

DSP56364 Advance Information

MOTOROLA

Specifications

Enhanced Serial Audio Interface Timing

Table 2-20. Enhanced Serial Audio Interface Timing (Continued)

Cond-

ition⁴

Characteristics^{1, 2, 3}

No.

Symbol

Expression

Min

Max

Unit

FST input (wl) to transmitter #0 drive

enable assertion

459

460

461

—

31.0

—

ns

FST input (wl) setup time before TXC

falling edge

2.0

21.0

—

x ck

i ck

FST input hold time after TXC falling

edge

4.0

0.0

—

x ck

i ck

ns

—

32.0

18.0

x ck

i ck

462 Flag output valid after TXC rising edge

463 HCKR/HCKT clock cycle

—

40.0

—

ns

464 HCKT input rising edge to TXC output

465 HCKR input rising edge to RXC output

27.5

—

Notes: 1. V_CC= 3.16 V ± 0.16 V; T_J= 0°C to +105°C, C_L= 50 pF

2. i ck = internal clock

x ck = external clock

i ck a = internal clock, asynchronous mode

(asynchronous implies that TXC and RXC are two different clocks)

i ck s = internal clock, synchronous mode

(synchronous implies that TXC and RXC are the same clock)

3. bl = bit length

wl = word length

wr = word length relative

4. TXC(SCKT pin) = transmit clock

RXC(SCKR pin) = receive clock

FST(FST pin) = transmit frame sync

FSR(FSR pin) = receive frame sync

HCKT(HCKT pin) = transmit high speed clock

HCKR(HCKR pin) = receive high speed clock

5. For the internal clock, the external clock cycle is defined by Icyc and the ESAI control register.

6. The word-relative frame sync signal waveform relative to the clock operates in the same manner as the

bit-length frame sync signal waveform, but spreads from one serial clock before first bit clock (same as

bit length frame sync signal), until the one before last bit clock of the first word in frame.

7. Periodically sampled and not 100% tested

MOTOROLA

DSP56364 Advance Information

2-59

Specifications

Enhanced Serial Audio Interface Timing

430

431

432

TXC

(Input/

Output)

446

447

FST (Bit)

Out

450

451

FST (Word)

Out

454

452

454

455

First Bit

Last Bit

Data Out

459

Transmitter

#0 Drive

Enable

457

453

456

461

460

FST (Bit) In

458

461

FST (Word)

In

462

See Note

Flags Out

Note: In network mode, output flag transitions can occur at the start of each time slot

within the frame. In normal mode, the output flag state is asserted for the entire

frame period.

AA0490

Figure 2-23. ESAI Transmitter Timing

2-60

DSP56364 Advance Information

MOTOROLA

Specifications

Enhanced Serial Audio Interface Timing

430

431

432

RXC

(Input/Output)

433

434

FSR (Bit)

Out

437

438

FSR (Word)

Out

440

439

443

Data In

Last Bit

First Bit

441

FSR (Bit)

In

442

443

445

FSR (Word)

In

444

Flags In

AA0491

Figure 2-24. ESAI Receiver Timing

MOTOROLA

DSP56364 Advance Information

2-61

Specifications

Enhanced Serial Audio Interface Timing

HCKT

463

SCKT(output)

464

Figure 2-25. ESAI HCKT Timing

HCKR

463

SCKR (output)

465

Figure 2-26. ESAI HCKR Timing

2-62

DSP56364 Advance Information

MOTOROLA

Specifications

GPIO Timing

GPIO TIMING

Table 2-21. GPIO Timing

Characteristics¹

No.

Expression Min Max Unit

490²EXTAL edge to GPIO out valid (GPIO out delay time)

491 EXTAL edge to GPIO out not valid (GPIO out hold time)

492 GPIO In valid to EXTAL edge (GPIO in set-up time)

493 EXTAL edge to GPIO in not valid (GPIO in hold time)

494²Fetch to EXTAL edge before GPIO change

495 GPIO out rise time

—

32.8 ns

4.8

—

13

ns

10.2

1.8

6.75 × T_C-1.8 65.7

—

496 GPIO out fall time

Notes: 1. V_CC= 3.3 V ± 0.16 V; T_J= 0°C to +105°C, C_L= 50 pF

2. Valid only when PLL enabled with multiplication factor equal to one.

EXTAL

(Input)

490

491

GPIO

(Output)

492

493

GPIO

(Input)

Valid

A0–A17

494

Fetch the instruction MOVE X0,X:(R0); X0 contains the new value of GPIO

and R0 contains the address of GPIO data register.

GPIO

(Output)

495

496

Figure 2-27. GPIO Timing

MOTOROLA

DSP56364 Advance Information

2-63

Specifications

JTAG Timing

JTAG TIMING

Table 2-22. JTAG Timing

All frequencies

No.

Characteristics

Unit

Min

Max

500 TCK frequency of operation (1/(T_C× 3); maximum 22 MHz)

501 TCK cycle time in Crystal mode

502 TCK clock pulse width measured at 1.5 V

503 TCK rise and fall times

0.0

45.0

20.0

0.0

22.0

—

MHz

ns

—

3.0

—

504 Boundary scan input data setup time

505 Boundary scan input data hold time

506 TCK low to output data valid

5.0

24.0

0.0

—

40.0

—

507 TCK low to output high impedance

508 TMS, TDI data setup time

0.0

5.0

509 TMS, TDI data hold time

25.0

0.0

—

510 TCK low to TDO data valid

44.0

511 TCK low to TDO high impedance

0.0

Notes: 1. V_CC= 3.3 V ± 0.16 V; T_J= 0°C to +105°C, C_L= 50 pF

2. All timings apply to OnCE module data transfers because it uses the JTAG port as an interface.

501

502

V

M

V

M

TCK

(Input)

IH

V

IL

503

AA0496

Figure 2-28. Test Clock Input Timing Diagram

DSP56364 Advance Information

2-64

MOTOROLA

Specifications

JTAG Timing

V_IH

505

TCK

(Input)

V_IL

504

Data

Inputs

Input Data Valid

506

507

506

Data

Output Data Valid

Outputs

Data

Outputs

Data

Outputs

Output Data Valid

AA0497

Figure 2-29. Boundary Scan (JTAG) Timing Diagram

V_IH

509

Input Data Valid

TCK

V_IL

(Input)

508

TDI

TMS

(Input)

510

TDO

(Output)

Output Data Valid

511

TDO

(Output)

510

TDO

(Output)

Output Data Valid

AA0498

Figure 2-30. Test Access Port Timing Diagram

MOTOROLA

DSP56364 Advance Information

2-65

Specifications

JTAG Timing

2-66

DSP56364 Advance Information

MOTOROLA

SECTION 3

PACKAGING

PIN-OUT AND PACKAGE INFORMATION

This section provides information about the available package for this product, including

diagrams of the package pinouts and tables describing how the signals described in Section 1

are allocated for the package. The DSP56364 is available in a 100-pin TQFP package. Tables 3-

1 and 3-2 show the pin/name assignments for the packages.

TQFP Package Description

Top view of the 100-pin TQFP package is shown in Figure 3-1 with its pin-outs. The 100-pin

TQFP package mechanical drawing is shown in Figure 3-2.

MOTOROLA

DSP56364 Advance Information

3-1

Packaging

Pin-out and Package Information

MODD

MODB

MODA

FST

1

2

3

4

5

6

7

8

9

75 D0

74 A17

73 A16

72 GNDA

71 VCCA

70 A15

69 A14

68 A13

67 A12

66 VCCLQ

65 GNDQ

64 GNDA

63 VCCA

62 A11

61 VCCQH

60 A10

59 A9

FSR

SCKT

SCKR

VCCS

GNDS

HCKT 10

VCCLQ 11

GNDQ 12

DSP56364

100-Pin

TQPF

HCKR 13

SDO0 14

VCCHQ 15

SDO1 16

SDO2/SDI3 17

SDO3/SDI2 18

SDO4/SDI1 19

SDO5/SDI0 20

VCCS 21

58 A8

57 A7

56 GNDA

55 VCCA

54 A6

GNDS 22

SS/HA2 23

MOSI/HA0 24

MISO/SDA 25

53 A5

52 A4

51 A3

Figure 3-1 DSP56364 100-Pin Thin Quad Flat Pack (TQFP), Top View

3-2

DSP56364 Advance Information

MOTOROLA

Packaging

Pin-out and Package Information

Table 3-1 DSP56364 100-Pin TQFP Signal Identification by Pin Number

No.

Signal Name

1

2

3

4

5

6

7

8

9

MODD/IRQD

MODB/IRQB

MODA/IRQA

FST

26 SCK/SCL

27 HREQ

28 PINIT/NMI

29 RESET

30 No Connect

31 VCCP

32 PCAP

33 GNDP

34 EXTAL

35 VCCHQ

36 GNDQ

37 VCCLQ

38 TA

51 A3

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

D1

D2

D3

52 A4

53 A5

54 A6

VCCD

GNDD

D4

FSR

55 VCCA

56 GNDA

57 A7

SCKT

SCKR

D5

VCCS

58 A8

D6

GNDS

59 A9

D7

10 HCKT

60 A10

61 VCCHQ

62 A11

63 VCCA

64 GNDA

65 GNDQ

66 VCCLQ

67 A12

68 A13

69 A14

70 A15

71 VCCA

72 GNDA

73 A16

74 A17

75 D0

No Connect

VCCLQ

GNDQ

VCCHQ

No Connect

GPIO0

VCCS

GNDS

GPIO1

GPIO2

GPIO3

TDO

11 VCCLQ

12 GNDQ

13 HCKR

14 SDO0

39 CAS

15 VCCHQ

16 SDO1

40 WR

41 RD

17 SDO2/SDI3

18 SDO3/SDI2

19 SDO4/SDI1

20 SDO5/SDI0

21 VCCS

42 VCCC

43 GNDC

44 AA1/RAS1

45 AA0/RAS0

46 A0

22 GNDS

47 A1

23 SS/HA2

24 MOSI/HA0

25 MISO/SDA

48 VCCQ

49 GNDQ

50 A2

TDI

TCK

100 TMS

Note:

Signal names are based on configured functionality. Most pins supply a single signal. Some pins provide a

signal with dual functionality, such as the MODx/IRQx pins that select an operating mode after RESET is

deasserted, but act as interrupt lines during operation.

MOTOROLA

DSP56364 Advance Information

3-3

Packaging

Pin-out and Package Information

Table 3-2 DSP56364 100-Pin TQFP Signal Identification by Name

No.

Signal Name

A0

A1

46

47

60

62

67

68

69

70

73

74

50

51

52

53

54

57

58

59

45

44

39

75

76

77

78

D4

81

82

83

84

34

5

HCKR

HCKT

13

10

27

25

3

SDO4/SDI1

TA

19

38

99

98

97

100

48

55

63

71

42

79

15

35

61

89

11

37

66

87

31

8

D5

A10

A11

A12

A13

A14

A15

A16

A17

A2

D6

HREQ

TCK

D7

MISO/SDA

MODA/IRQA

MODB/IRQB

MODD/IRQD

MOSI/HA0

No Connect

PCAP

TDI

EXTAL

FSR

TD0

2

TMS

FST

4

1

VCCA

VCCC

VCCD

VCCHQ

VCCLQ

VCCP

VCCS

WR

GNDA

GNDC

GNDD

GNDP

GNDQ

GNDS

GPIO0

GPIO1

GPIO2

GPIO3

49

56

64

72

43

80

33

12

36

65

88

9

24

30

85

86

90

32

28

41

29

26

7

A3

A4

A5

PINIT/NMI

RD

A6

A7

RESET

A8

SCK/SCL

SCKR

A9

AA0

AA1

CAS

D0

SCKT

6

22

93

91

94

95

96

SDO0

14

16

20

23

17

18

SDO1

SDO5/SDI0

SS/HA2

D1

21

92

40

D2

SDO2/SDI3

SDO3/SDI2

D3

3-4

DSP56364 Advance Information

MOTOROLA

Packaging

Pin-out and Package Information

TQFP Package Mechanical Drawing

Figure 3-2 DSP56364 100-pin TQFP Package

MOTOROLA

DSP56364 Advance Information

3-5

Packaging

Ordering Drawings

ORDERING DRAWINGS

The detailed package drawing is available on the Motorola web page at:

http://mot.sps.com/cgi-bin/cases

Use package 983 for the search.

3-6

DSP56364 Advance Information

MOTOROLA

Packaging

Ordering Drawings

MOTOROLA

DSP56364 Advance Information

3-7

Packaging

Ordering Drawings

3-8

DSP56364 Advance Information

MOTOROLA

Packaging

Ordering Drawings

4X

0.20

T L±M N

4X 28 TIPS

85

0.20

T L±M N

4X

P

J1

PIN 1

IDENT

112

C

L

1

84

VIEW Y

X

108X

G

X=L, M OR N

VIEW Y

V

B

L

M

AA

J

B1

V1

28

57

BASE

METAL

F

D

29

56

M

0.13

T

L±M

N

SECTION J1±J1

ROTATED 90 COUNTERCLOCKWISE

A1

S1

A

S

NOTES:

1. DIMENSIONS AND TOLERANCES PER ASME

Y14.5M, 1994.

2. DIMENSIONS IN MILLIMETERS.

3. DATUMS L, M AND N TO BE DETERMINED AT

SEATING PLANE, DATUM T.

4. DIMENSIONS S AND V TO BE DETERMINED AT

SEATING PLANE, DATUM T.

5. DIMENSIONS A AND B DO NOT INCLUDE MOLD

PROTRUSION. ALLOWABLE PROTRUSION IS

0.25 PER SIDE. DIMENSIONS A AND B INCLUDE

MOLD MISMATCH.

6. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL NOT CAUSE THE D

DIMENSION TO EXCEED 0.46.

C2

VIEW AB

2

3

C

0.050

112X

0.10

T

SEATING

PLANE

T

MILLIMETERS

DIM

A

MIN

20.000 BSC

MAX

A1

B

B1

C

C1

C2

D

10.000 BSC

20.000 BSC

10.000 BSC

±±±

0.050

1.350

0.270

0.450

0.270

1.600

0.150

1.450

0.370

0.750

0.330

R

R2

R

E

F

G

0.650 BSC

J

K

P

R1

R2

S

0.090

0.500 REF

0.325 BSC

0.100

22.000 BSC

0.170

0.25

R1

GAGE PLANE

0.200

S1

V

V1

Y

Z

AA

11.000 BSC

22.000 BSC

11.000 BSC

0.250 REF

1.000 REF

(K)

E

C1

1

(Y)

(Z)

0.090

0.160

0

8

°

VIEW AB

3

7

1

2

3

°

CASE 987±01

ISSUE A

11

13

°

DATE 01/30/96

MOTOROLA

DSP56364 Advance Information

3-9

Packaging

Ordering Drawings

3-10

DSP56364 Advance Information

MOTOROLA

SECTION 4

DESIGN CONSIDERATIONS

THERMAL DESIGN CONSIDERATIONS

An estimation of the chip junction temperature, T , in °C can be obtained from the following

J

equation:

T_J= T_A+ (P_D× R_θJA

)

Where:

T = ambient temperature °C

A

R

= package junction-to-ambient thermal resistance °C/W

qJA

P = power dissipation in package W

D

Historically, thermal resistance has been expressed as the sum of a junction-to-case thermal

resistance and a case-to-ambient thermal resistance.

R_θJA= R_θJC+ R_θCA

Where:

R

= package junction-to-ambient thermal resistance °C/W

= package junction-to-case thermal resistance °C/W

= package case-to-ambient thermal resistance °C/W

θJA

θJC

θCA

R

is device-related and cannot be influenced by the user. The user controls the thermal

θJC

environment to change the case-to-ambient thermal resistance, R

. For example, the user

θCA

can change the air flow around the device, add a heat sink, change the mounting

arrangement on the printed circuit board (PCB), or otherwise change the thermal dissipation

capability of the area surrounding the device on a PCB. This model is most useful for ceramic

packages with heat sinks; some 90% of the heat flow is dissipated through the case to the

heat sink and out to the ambient environment. For ceramic packages, in situations where the

heat flow is split between a path to the case and an alternate path through the PCB, analysis

of the device thermal performance may need the additional modeling capability of a system

level thermal simulation tool.

The thermal performance of plastic packages is more dependent on the temperature of the

PCB to which the package is mounted. Again, if the estimations obtained from R

do not

θJA

satisfactorily answer whether the thermal performance is adequate, a system level model

may be appropriate.

MOTOROLA

DSP56364 Advance Information

4-1

Design Considerations

Thermal Design Considerations

A complicating factor is the existence of three common ways for determining the junction-to-

case thermal resistance in plastic packages.

•

To minimize temperature variation across the surface, the thermal resistance is

measured from the junction to the outside surface of the package (case) closest to the

chip mounting area when that surface has a proper heat sink.

To define a value approximately equal to a junction-to-board thermal resistance, the

thermal resistance is measured from the junction to where the leads are attached to

the case.

If the temperature of the package case (T ) is determined by a thermocouple, the

T

thermal resistance is computed using the value obtained by the equation

(T – T )/P .

J

T

D

As noted above, the junction-to-case thermal resistances quoted in this data sheet are

determined using the first definition. From a practical standpoint, that value is also suitable for

determining the junction temperature from a case thermocouple reading in forced convection

environments. In natural convection, using the junction-to-case thermal resistance to

estimate junction temperature from a thermocouple reading on the case of the package will

estimate a junction temperature slightly hotter than actual temperature. Hence, the new

thermal metric, thermal characterization parameter or Ψ , has been defined to be (T – T )/

JT

J

T

P . This value gives a better estimate of the junction temperature in natural convection when

D

using the surface temperature of the package. Remember that surface temperature readings

of packages are subject to significant errors caused by inadequate attachment of the sensor

to the surface and to errors caused by heat loss to the sensor. The recommended technique

is to attach a 40-gauge thermocouple wire and bead to the top center of the package with

thermally conductive epoxy.

4-2

DSP56364 Advance Information

MOTOROLA

Design Considerations

Electrical Design Considerations

ELECTRICAL DESIGN CONSIDERATIONS

CAUTION

This device contains circuitry protecting

against damage due to high static voltage or

electrical fields. However, normal precautions

should be taken to avoid exceeding maximum

voltage ratings. Reliability of operation is

enhanced if unused inputs are tied to an

appropriate logic voltage level (e.g., either

GND or V ). The suggested value for a

CC

pullup or pulldown resistor is 10 k ohm.

Use the following list of recommendations to assure correct DSP operation:

•

Provide a low-impedance path from the board power supply to each V pin on the

DSP and from the board ground to each GND pin.

CC

Use at least six 0.01–0.1 µF bypass capacitors positioned as close as possible to the

four sides of the package to connect the V power source to GND.

CC

Ensure that capacitor leads and associated printed circuit traces that connect to the

chip V and GND pins are less than 1.2 cm (0.5 inch) per capacitor lead.

CC

•

Use at least a four-layer PCB with two inner layers for V and GND.

CC

Because the DSP output signals have fast rise and fall times, PCB trace lengths

should be minimal. This recommendation particularly applies to the address and data

buses as well as the IRQA, IRQB, IRQD, and TA pins. Maximum PCB trace lengths

on the order of 15 cm (6 inches) are recommended.

•

Consider all device loads as well as parasitic capacitance due to PCB traces when

calculating capacitance. This is especially critical in systems with higher capacitive

loads that could create higher transient currents in the V and GND circuits.

CC

All inputs must be terminated (i.e., not allowed to float) using CMOS levels, except for

the three pins with internal pull-up resistors (TMS, TDI, TCK).

•

Take special care to minimize noise levels on the V

and GND pins.

CCP P

If multiple DSP56364 devices are on the same board, check for cross-talk or

excessive spikes on the supplies due to synchronous operation of the devices.

•

RESET must be asserted when the chip is powered up. A stable EXTAL signal must

be supplied before deassertion of RESET.

MOTOROLA

DSP56364 Advance Information

4-3

Design Considerations

Power Consumption Considerations

•

At power-up, ensure that the voltage difference between the 5 V tolerant pins and the

chip V never exceeds 3.95 V.

CC

POWER CONSUMPTION CONSIDERATIONS

Power dissipation is a key issue in portable DSP applications. Some of the factors which

affect current consumption are described in this section. Most of the current consumed by

CMOS devices is alternating current (ac), which is charging and discharging the

capacitances of the pins and internal nodes.

Current consumption is described by the following formula:

I = C × V × f

where

C = node/pin capacitance

V = voltage swing

f = frequency of node/pin toggle

Example 1 Current Consumption

For a Port A address pin loaded with 50 pF capacitance, operating at 3.3 V, and with a 100 MHz clock, toggling

at its maximum possible rate (50 MHz), the current consumption is

I = 50 × 10^–12× 3.3 × 50 × 10⁶= 8.25mA

The maximum internal current (I max) value reflects the typical possible switching of the

CCI

internal buses on best-case operation conditions, which is not necessarily a real application

case. The typical internal current (I

) value reflects the average switching of the internal

CCItyp

buses on typical operating conditions.

For applications that require very low current consumption, do the following:

•

Set the EBD bit when not accessing external memory.

Minimize external memory accesses and use internal memory accesses.

Minimize the number of pins that are switching.

Minimize the capacitive load on the pins.

Connect the unused inputs to pull-up or pull-down resistors.

Disable unused peripherals.

4-4

DSP56364 Advance Information

MOTOROLA

Design Considerations

PLL Performance Issues

One way to evaluate power consumption is to use a current per MIPS measurement

methodology to minimize specific board effects (i.e., to compensate for measured board

current not caused by the DSP). A benchmark power consumption test algorithm is listed in

Appendix A. Use the test algorithm, specific test current measurements, and the following

equation to derive the current per MIPS value.

I ⁄ MIPS = I ⁄ MHz = (I_typF2– I_typF1) ⁄ (F2 – F1)

where :

I

= current at F2

= current at F1

typF2

typF1

F2 = high frequency (any specified operating frequency)

F1 = low frequency (any specified operating frequency lower than

F2)

Note: F1 should be significantly less than F2. For example, F2 could be 66 MHz

and F1 could be 33 MHz. The degree of difference between F1 and F2

determines the amount of precision with which the current rating can be

determined for an application.

PLL PERFORMANCE ISSUES

The following explanations should be considered as general observations on expected PLL

behavior. There is no testing that verifies these exact numbers. These observations were

measured on a limited number of parts and were not verified over the entire temperature and

voltage ranges.

Input (EXTAL) Jitter Requirements

The allowed jitter on the frequency of EXTAL is 0.5%. If the rate of change of the frequency of

EXTAL is slow (i.e., it does not jump between the minimum and maximum values in one

cycle) or the frequency of the jitter is fast (i.e., it does not stay at an extreme value for a long

time), then the allowed jitter can be 2%. The phase and frequency jitter performance results

are only valid if the input jitter is less than the prescribed values.

MOTOROLA

DSP56364 Advance Information

4-5

Design Considerations

PLL Performance Issues

4-6

DSP56364 Advance Information

MOTOROLA

SECTION 5

ORDERING INFORMATION

Consult a Motorola Semiconductor sales office or authorized distributor to determine product

availability and to place an order.

Table 5-1 Ordering Information

Supply

Voltage

Count

Frequency

(MHz)

Part

Package Type

Order Number

Thin quad flat pack (TQFP)

Quad flat pack (QFP)

100

112

100

XCB56364FU100

XCB56364PV100

DSP56364

3.3 V

Notes: 1. The DSP56364 can include factory-programmed ROM. The listed ‘B’ ROM code is a

generic unused ROM available to any customer. Variations will be supported for Dolby

digital (AC-3), DTS, MPEG2, and other features. These products are only available to

authorized licensees of those technologies. Please consult the web site at

www.dspaudio.motorola.com for current availability.

2. Future products in the DSP56364 family may include other ROM-based options. For

additional information on future part development, or to request customer-specific ROM-

based support, call your local Motorola Semiconductor sales office or authorized

distributor.

MOTOROLA

DSP56364 Advance Information

5-1

Ordering Information

5-2

DSP56364 Advance Information

MOTOROLA

APPENDIX A

IBIS MODEL

[IBIS ver]

[File name]

[File Rev]

[Date]

2.1

56364.ibs

0.0

29/6/2000

56364

[Component]

[Manufacturer] Motorola

[Package]

|variable

R_pkg

typ

45m

min

22m

max

75m

L_pkg

C_pkg

2.5nH

1.3pF

1.1nH

1.2pF

4.3nH

1.4pF

[Pin]signal_name model_name

1 irqc_ ip5b_i

2 irqb_

ip5b_i

ip5b_io

power

3 irqa_

4 fst

5 fsr

6 sckt

7 sckr

8 svcc

9 sgnd

gnd

10 hsckt

11 qvccl

12 qgnd

13 hsckr

14 sdo0

15 qvcch

16 sdo1

17 sdo2

18 sdo3

19 sdo4

20 sdo5

21 svcc

22 sgnd

23 ss_

24 mosi

25 sda

26 sck

27 hreq_

28 nmi_

29 ires_

31 pvcc

32 pcap

ip5b_io

power

gnd

ip5b_io

power

ip5b_io

power

gnd

ip5b_io

ip5b_i

power

MOTOROLA

DSP56364 Advance Information

Appendix A-1

IBIS Model

33 pgnd

34 cxtldis_

35 qvcch

36 qgnd

37 qvccl

38 ta_

39 cas_

40 wr_

41 rd_

gnd

iexlh_i

power

gnd

power

icbc_o

power

42 cvcc

43 cgnd

44 aa1

gnd

icbc_o

icba_o

power

45 aa0

46 eab0

47 eab1

48 avcc

49 agnd

50 eab2

51 eab3

52 eab4

53 eab5

54 eab6

55 avcc

56 agnd

57 eab7

58 eab8

59 eab9

60 eab10

61 qvcch

62 eab11

63 avcc

64 agnd

65 qgnd

66 qvccl

67 eab12

68 eab13

69 eab14

70 eab15

71 avcc

72 agnd

73 eab16

74 eab17

75 edb0

76 edb1

77 edb2

78 edb3

79 dvcc

80 dgnd

81 edb4

82 edb5

83 edb6

84 edb7

87 qvccl

gnd

icba_o

power

gnd

icba_o

power

icba_o

power

gnd

power

icba_o

power

gnd

icba_o

icba_io

power

gnd

icba_io

power

Appendix A-2

DSP56364 Advance Information

MOTOROLA

IBIS Model

88 qgnd

89 qvcch

91 edb8

92 svcc

93 sgnd

94 edb9

95 edb10

96 edb11

97 tdo

98 tdi

99 tck

100 tms

|

gnd

power

ip5b_io

power

gnd

ip5b_io

ip5b_o

ip5b_i

[Model]

Model_type

Polarity

Vinl= 0.8000v

Vinh= 2.000v

C_comp

ip5b_i

Input

Non-Inverting

5.00pF

|

[Voltage Range]

[GND_clamp]

|voltage

|

3.3v

I(typ)

3v

3.6v

I(min)

I(max)

-3.30e+00 -5.21e+02 -3.65e+02 -5.18e+02

-3.10e+00 -4.69e+02 -3.30e+02 -4.67e+02

-2.90e+00 -4.18e+02 -2.94e+02 -4.16e+02

-2.70e+00 -3.67e+02 -2.59e+02 -3.65e+02

-2.50e+00 -3.16e+02 -2.23e+02 -3.14e+02

-2.30e+00 -2.65e+02 -1.88e+02 -2.63e+02

-2.10e+00 -2.14e+02 -1.52e+02 -2.12e+02

-1.90e+00 -1.63e+02 -1.17e+02 -1.61e+02

-1.70e+00 -1.13e+02 -9.25e+01 -1.10e+02

-1.50e+00 -7.83e+01 -6.88e+01 -7.58e+01

-1.30e+00 -4.43e+01 -4.52e+01 -4.17e+01

-1.10e+00 -1.02e+01 -2.15e+01 -7.67e+00

-9.00e-01 -9.69e-03 -1.18e+00 -7.81e-03

-7.00e-01 -2.83e-04 -5.70e-03 -8.42e-04

-5.00e-01 -1.35e-06 -4.53e-05 -1.00e-05

-3.00e-01 -1.31e-09 -3.74e-07 -8.58e-09

-1.00e-01 -2.92e-11 -3.00e-09 -3.64e-11

0.000e+00 -2.44e-11 -5.14e-10 -2.79e-11

|

[End]|

[Model]

Model_type

Polarity

Vinl= 0.8000v

Vinh= 2.000v

C_comp

ip5b_io

I/O

Non-Inverting

5.00pF

|

MOTOROLA

DSP56364 Advance Information

Appendix A-3

IBIS Model

[Voltage Range]

[Pulldown]

|voltage

|

3.3v

I(typ)

3v

3.6v

I(min)

I(max)

-3.30e+00 -5.21e+02 -3.65e+02 -5.18e+02

-3.10e+00 -4.69e+02 -3.30e+02 -4.67e+02

-2.90e+00 -4.18e+02 -2.94e+02 -4.16e+02

-2.70e+00 -3.67e+02 -2.59e+02 -3.65e+02

-2.50e+00 -3.16e+02 -2.23e+02 -3.14e+02

-2.30e+00 -2.65e+02 -1.88e+02 -2.63e+02

-2.10e+00 -2.14e+02 -1.52e+02 -2.12e+02

-1.90e+00 -1.63e+02 -1.17e+02 -1.61e+02

-1.70e+00 -1.13e+02 -9.25e+01 -1.10e+02

-1.50e+00 -7.83e+01 -6.88e+01 -7.58e+01

-1.30e+00 -4.43e+01 -4.52e+01 -4.17e+01

-1.10e+00 -1.02e+01 -2.15e+01 -7.69e+00

-9.00e-01 -5.10e-02 -1.18e+00 -5.63e-02

-7.00e-01 -3.65e-02 -2.25e-02 -4.28e-02

-5.00e-01 -2.65e-02 -1.38e-02 -3.12e-02

-3.00e-01 -1.62e-02 -8.35e-03 -1.91e-02

-1.00e-01 -5.49e-03 -2.80e-03 -6.52e-03

1.000e-01 5.377e-03 2.744e-03 6.427e-03

3.000e-01 1.516e-02 7.871e-03 1.823e-02

5.000e-01 2.370e-02 1.252e-02 2.869e-02

7.000e-01 3.098e-02 1.667e-02 3.776e-02

9.000e-01 3.700e-02 2.026e-02 4.544e-02

1.100e+00 4.175e-02 2.324e-02 5.171e-02

1.300e+00 4.531e-02 2.553e-02 5.660e-02

1.500e+00 4.779e-02 2.709e-02 6.023e-02

1.700e+00 4.935e-02 2.803e-02 6.271e-02

1.900e+00 5.013e-02 2.851e-02 6.419e-02

2.100e+00 5.046e-02 2.876e-02 6.494e-02

2.300e+00 5.063e-02 2.892e-02 6.525e-02

2.500e+00 5.075e-02 2.904e-02 6.540e-02

2.700e+00 5.085e-02 2.912e-02 6.549e-02

2.900e+00 5.090e-02 2.876e-02 6.555e-02

3.100e+00 4.771e-02 2.994e-02 6.561e-02

3.300e+00 4.525e-02 3.321e-02 6.182e-02

3.500e+00 4.657e-02 3.570e-02 6.049e-02

3.700e+00 4.904e-02 3.801e-02 6.178e-02

3.900e+00 5.221e-02 4.029e-02 6.450e-02

4.100e+00 5.524e-02 4.253e-02 6.659e-02

4.300e+00 5.634e-02 4.463e-02 6.867e-02

4.500e+00 5.751e-02 4.645e-02 6.970e-02

4.700e+00 5.634e-02 4.786e-02 6.938e-02

4.900e+00 5.648e-02 4.881e-02 6.960e-02

5.100e+00 5.664e-02 4.912e-02 6.983e-02

5.300e+00 5.679e-02 4.795e-02 7.005e-02

5.500e+00 5.693e-02 4.679e-02 7.026e-02

5.700e+00 5.707e-02 4.688e-02 7.049e-02

5.900e+00 5.722e-02 4.700e-02 7.074e-02

6.100e+00 5.741e-02 4.712e-02 7.105e-02

6.300e+00 5.766e-02 4.723e-02 7.147e-02

Appendix A-4

DSP56364 Advance Information

MOTOROLA

IBIS Model

6.500e+00 5.801e-02 4.733e-02 7.205e-02

6.600e+00 5.824e-02 4.737e-02 7.242e-02

|

[Pullup]

|voltage

|

I(typ)

I(min)

I(max)

-3.30e+00 2.922e-04 2.177e-04 4.123e-04

-3.10e+00 2.881e-04 2.175e-04 4.021e-04

-2.90e+00 2.853e-04 2.173e-04 3.946e-04

-2.70e+00 2.836e-04 2.172e-04 3.893e-04

-2.50e+00 2.825e-04 2.171e-04 3.857e-04

-2.30e+00 2.819e-04 2.170e-04 3.834e-04

-2.10e+00 2.815e-04 2.169e-04 3.820e-04

-1.90e+00 2.813e-04 2.167e-04 3.812e-04

-1.70e+00 2.812e-04 2.520e-04 3.808e-04

-1.50e+00 2.811e-04 3.078e-02 3.806e-04

-1.30e+00 2.810e-04 2.684e-02 3.804e-04

-1.10e+00 2.809e-04 2.277e-02 3.802e-04

-9.00e-01 2.808e-04 1.864e-02 3.801e-04

-7.00e-01 2.997e-04 1.447e-02 3.799e-04

-5.00e-01 1.750e-02 1.031e-02 3.797e-04

-3.00e-01 1.048e-02 6.181e-03 3.776e-04

-1.00e-01 3.487e-03 2.084e-03 4.568e-03

1.000e-01 -3.40e-03 -2.03e-03 -4.22e-03

3.000e-01 -9.69e-03 -5.71e-03 -1.24e-02

5.000e-01 -1.52e-02 -8.99e-03 -1.95e-02

7.000e-01 -2.02e-02 -1.19e-02 -2.61e-02

9.000e-01 -2.46e-02 -1.43e-02 -3.21e-02

1.100e+00 -2.84e-02 -1.62e-02 -3.73e-02

1.300e+00 -3.14e-02 -1.77e-02 -4.18e-02

1.500e+00 -3.37e-02 -1.88e-02 -4.55e-02

1.700e+00 -3.55e-02 -1.95e-02 -4.85e-02

1.900e+00 -3.68e-02 -2.00e-02 -5.09e-02

2.100e+00 -3.78e-02 -2.04e-02 -5.27e-02

2.300e+00 -3.85e-02 -2.07e-02 -5.41e-02

2.500e+00 -3.91e-02 -2.10e-02 -5.51e-02

2.700e+00 -3.96e-02 -2.12e-02 -5.60e-02

2.900e+00 -4.01e-02 -2.15e-02 -5.67e-02

3.100e+00 -4.04e-02 -2.17e-02 -5.74e-02

3.300e+00 -4.08e-02 -2.18e-02 -5.79e-02

3.500e+00 -4.11e-02 -2.20e-02 -5.84e-02

3.700e+00 -4.14e-02 -2.78e-02 -5.89e-02

3.900e+00 -4.17e-02 -1.20e+00 -5.94e-02

4.100e+00 -4.32e-02 -2.15e+01 -5.98e-02

4.300e+00 -4.08e-01 -4.52e+01 -6.10e-02

4.500e+00 -2.73e+01 -6.89e+01 -6.84e-02

4.700e+00 -6.13e+01 -9.25e+01 -7.73e+00

4.900e+00 -9.54e+01 -1.17e+02 -4.18e+01

5.100e+00 -1.38e+02 -1.52e+02 -7.59e+01

5.300e+00 -1.89e+02 -1.88e+02 -1.11e+02

5.500e+00 -2.40e+02 -2.23e+02 -1.61e+02

5.700e+00 -2.91e+02 -2.59e+02 -2.12e+02

5.900e+00 -3.42e+02 -2.94e+02 -2.63e+02

MOTOROLA

DSP56364 Advance Information

Appendix A-5

IBIS Model

6.100e+00 -3.93e+02 -3.30e+02 -3.14e+02

6.300e+00 -4.44e+02 -3.65e+02 -3.65e+02

6.500e+00 -4.95e+02 -4.01e+02 -4.16e+02

6.600e+00 -5.21e+02 -4.18e+02 -4.41e+02

|

[GND_clamp]

|voltage

|

I(typ)

I(min)

I(max)

-3.30e+00 -5.21e+02 -3.65e+02 -5.18e+02

-3.10e+00 -4.69e+02 -3.30e+02 -4.67e+02

-2.90e+00 -4.18e+02 -2.94e+02 -4.16e+02

-2.70e+00 -3.67e+02 -2.59e+02 -3.65e+02

-2.50e+00 -3.16e+02 -2.23e+02 -3.14e+02

-2.30e+00 -2.65e+02 -1.88e+02 -2.63e+02

-2.10e+00 -2.14e+02 -1.52e+02 -2.12e+02

-1.90e+00 -1.63e+02 -1.17e+02 -1.61e+02

-1.70e+00 -1.13e+02 -9.25e+01 -1.10e+02

-1.50e+00 -7.83e+01 -6.88e+01 -7.58e+01

-1.30e+00 -4.43e+01 -4.52e+01 -4.17e+01

-1.10e+00 -1.02e+01 -2.15e+01 -7.67e+00

-9.00e-01 -9.69e-03 -1.18e+00 -7.81e-03

-7.00e-01 -2.83e-04 -5.70e-03 -8.42e-04

-5.00e-01 -1.35e-06 -4.53e-05 -1.00e-05

-3.00e-01 -1.31e-09 -3.74e-07 -8.58e-09

-1.00e-01 -2.92e-11 -3.00e-09 -3.64e-11

0.000e+00 -2.44e-11 -5.14e-10 -2.79e-11

|

[Ramp]

R_load = 50.00

|voltage

I(typ)

I(min)

I(max)

|

dV/dt_r

|

dV/dt_f

|

1.030/0.465

1.290/0.671

0.605/0.676

0.829/0.122

1.320/0.366

1.520/0.431

[End]|

[Model]

Model_type

Polarity

C_comp

|

ip5b_o

3-state

Non-Inverting

5.00pF

|

[Voltage Range]

[Pulldown]

|voltage

|

3.3v

I(typ)

3v

3.6v

I(min)

I(max)

-3.30e+00 -5.21e+02 -3.65e+02 -5.18e+02

-3.10e+00 -4.69e+02 -3.30e+02 -4.67e+02

-2.90e+00 -4.18e+02 -2.94e+02 -4.16e+02

-2.70e+00 -3.67e+02 -2.59e+02 -3.65e+02

-2.50e+00 -3.16e+02 -2.23e+02 -3.14e+02

Appendix A-6

DSP56364 Advance Information

MOTOROLA

IBIS Model

-2.30e+00 -2.65e+02 -1.88e+02 -2.63e+02

-2.10e+00 -2.14e+02 -1.52e+02 -2.12e+02

-1.90e+00 -1.63e+02 -1.17e+02 -1.61e+02

-1.70e+00 -1.13e+02 -9.25e+01 -1.10e+02

-1.50e+00 -7.83e+01 -6.88e+01 -7.58e+01

-1.30e+00 -4.43e+01 -4.52e+01 -4.17e+01

-1.10e+00 -1.02e+01 -2.15e+01 -7.69e+00

-9.00e-01 -5.10e-02 -1.18e+00 -5.63e-02

-7.00e-01 -3.65e-02 -2.25e-02 -4.28e-02

-5.00e-01 -2.65e-02 -1.38e-02 -3.12e-02

-3.00e-01 -1.62e-02 -8.35e-03 -1.91e-02

-1.00e-01 -5.49e-03 -2.80e-03 -6.52e-03

1.000e-01 5.377e-03 2.744e-03 6.427e-03

3.000e-01 1.516e-02 7.871e-03 1.823e-02

5.000e-01 2.370e-02 1.252e-02 2.869e-02

7.000e-01 3.098e-02 1.667e-02 3.776e-02

9.000e-01 3.700e-02 2.026e-02 4.544e-02

1.100e+00 4.175e-02 2.324e-02 5.171e-02

1.300e+00 4.531e-02 2.553e-02 5.660e-02

1.500e+00 4.779e-02 2.709e-02 6.023e-02

1.700e+00 4.935e-02 2.803e-02 6.271e-02

1.900e+00 5.013e-02 2.851e-02 6.419e-02

2.100e+00 5.046e-02 2.876e-02 6.494e-02

2.300e+00 5.063e-02 2.892e-02 6.525e-02

2.500e+00 5.075e-02 2.904e-02 6.540e-02

2.700e+00 5.085e-02 2.912e-02 6.549e-02

2.900e+00 5.090e-02 2.876e-02 6.555e-02

3.100e+00 4.771e-02 2.994e-02 6.561e-02

3.300e+00 4.525e-02 3.321e-02 6.182e-02

3.500e+00 4.657e-02 3.570e-02 6.049e-02

3.700e+00 4.904e-02 3.801e-02 6.178e-02

3.900e+00 5.221e-02 4.029e-02 6.450e-02

4.100e+00 5.524e-02 4.253e-02 6.659e-02

4.300e+00 5.634e-02 4.463e-02 6.867e-02

4.500e+00 5.751e-02 4.645e-02 6.970e-02

4.700e+00 5.634e-02 4.786e-02 6.938e-02

4.900e+00 5.648e-02 4.881e-02 6.960e-02

5.100e+00 5.664e-02 4.912e-02 6.983e-02

5.300e+00 5.679e-02 4.795e-02 7.005e-02

5.500e+00 5.693e-02 4.679e-02 7.026e-02

5.700e+00 5.707e-02 4.688e-02 7.049e-02

5.900e+00 5.722e-02 4.700e-02 7.074e-02

6.100e+00 5.741e-02 4.712e-02 7.105e-02

6.300e+00 5.766e-02 4.723e-02 7.147e-02

6.500e+00 5.801e-02 4.733e-02 7.205e-02

6.600e+00 5.824e-02 4.737e-02 7.242e-02

|

[Pullup]

|voltage

|

I(typ)

I(min)

I(max)

-3.30e+00 2.922e-04 2.177e-04 4.123e-04

-3.10e+00 2.881e-04 2.175e-04 4.021e-04

-2.90e+00 2.853e-04 2.173e-04 3.946e-04

MOTOROLA

DSP56364 Advance Information

Appendix A-7

IBIS Model

-2.70e+00 2.836e-04 2.172e-04 3.893e-04

-2.50e+00 2.825e-04 2.171e-04 3.857e-04

-2.30e+00 2.819e-04 2.170e-04 3.834e-04

-2.10e+00 2.815e-04 2.169e-04 3.820e-04

-1.90e+00 2.813e-04 2.167e-04 3.812e-04

-1.70e+00 2.812e-04 2.520e-04 3.808e-04

-1.50e+00 2.811e-04 3.078e-02 3.806e-04

-1.30e+00 2.810e-04 2.684e-02 3.804e-04

-1.10e+00 2.809e-04 2.277e-02 3.802e-04

-9.00e-01 2.808e-04 1.864e-02 3.801e-04

-7.00e-01 2.997e-04 1.447e-02 3.799e-04

-5.00e-01 1.750e-02 1.031e-02 3.797e-04

-3.00e-01 1.048e-02 6.181e-03 3.776e-04

-1.00e-01 3.487e-03 2.084e-03 4.568e-03

1.000e-01 -3.40e-03 -2.03e-03 -4.22e-03

3.000e-01 -9.69e-03 -5.71e-03 -1.24e-02

5.000e-01 -1.52e-02 -8.99e-03 -1.95e-02

7.000e-01 -2.02e-02 -1.19e-02 -2.61e-02

9.000e-01 -2.46e-02 -1.43e-02 -3.21e-02

1.100e+00 -2.84e-02 -1.62e-02 -3.73e-02

1.300e+00 -3.14e-02 -1.77e-02 -4.18e-02

1.500e+00 -3.37e-02 -1.88e-02 -4.55e-02

1.700e+00 -3.55e-02 -1.95e-02 -4.85e-02

1.900e+00 -3.68e-02 -2.00e-02 -5.09e-02

2.100e+00 -3.78e-02 -2.04e-02 -5.27e-02

2.300e+00 -3.85e-02 -2.07e-02 -5.41e-02

2.500e+00 -3.91e-02 -2.10e-02 -5.51e-02

2.700e+00 -3.96e-02 -2.12e-02 -5.60e-02

2.900e+00 -4.01e-02 -2.15e-02 -5.67e-02

3.100e+00 -4.04e-02 -2.17e-02 -5.74e-02

3.300e+00 -4.08e-02 -2.18e-02 -5.79e-02

3.500e+00 -4.11e-02 -2.20e-02 -5.84e-02

3.700e+00 -4.14e-02 -2.78e-02 -5.89e-02

3.900e+00 -4.17e-02 -1.20e+00 -5.94e-02

4.100e+00 -4.32e-02 -2.15e+01 -5.98e-02

4.300e+00 -4.08e-01 -4.52e+01 -6.10e-02

4.500e+00 -2.73e+01 -6.89e+01 -6.84e-02

4.700e+00 -6.13e+01 -9.25e+01 -7.73e+00

4.900e+00 -9.54e+01 -1.17e+02 -4.18e+01

5.100e+00 -1.38e+02 -1.52e+02 -7.59e+01

5.300e+00 -1.89e+02 -1.88e+02 -1.11e+02

5.500e+00 -2.40e+02 -2.23e+02 -1.61e+02

5.700e+00 -2.91e+02 -2.59e+02 -2.12e+02

5.900e+00 -3.42e+02 -2.94e+02 -2.63e+02

6.100e+00 -3.93e+02 -3.30e+02 -3.14e+02

6.300e+00 -4.44e+02 -3.65e+02 -3.65e+02

6.500e+00 -4.95e+02 -4.01e+02 -4.16e+02

6.600e+00 -5.21e+02 -4.18e+02 -4.41e+02

|

[GND_clamp]

|voltage

|

I(typ)

I(min)

I(max)

-3.30e+00 -5.21e+02 -3.65e+02 -5.18e+02

Appendix A-8

DSP56364 Advance Information

MOTOROLA

IBIS Model

-3.10e+00 -4.69e+02 -3.30e+02 -4.67e+02

-2.90e+00 -4.18e+02 -2.94e+02 -4.16e+02

-2.70e+00 -3.67e+02 -2.59e+02 -3.65e+02

-2.50e+00 -3.16e+02 -2.23e+02 -3.14e+02

-2.30e+00 -2.65e+02 -1.88e+02 -2.63e+02

-2.10e+00 -2.14e+02 -1.52e+02 -2.12e+02

-1.90e+00 -1.63e+02 -1.17e+02 -1.61e+02

-1.70e+00 -1.13e+02 -9.25e+01 -1.10e+02

-1.50e+00 -7.83e+01 -6.88e+01 -7.58e+01

-1.30e+00 -4.43e+01 -4.52e+01 -4.17e+01

-1.10e+00 -1.02e+01 -2.15e+01 -7.67e+00

-9.00e-01 -9.69e-03 -1.18e+00 -7.81e-03

-7.00e-01 -2.83e-04 -5.70e-03 -8.42e-04

-5.00e-01 -1.35e-06 -4.53e-05 -1.00e-05

-3.00e-01 -1.31e-09 -3.74e-07 -8.58e-09

-1.00e-01 -2.92e-11 -3.00e-09 -3.64e-11

0.000e+00 -2.44e-11 -5.14e-10 -2.79e-11

|

[Ramp]

R_load = 50.00

|voltage

I(typ)

I(min)

I(max)

|

dV/dt_r

|

dV/dt_f

|

1.030/0.465

1.290/0.671

0.605/0.676

0.829/0.122

1.320/0.366

1.520/0.431

[End]|

[Model]

Model_type

Polarity

Vinl= 0.8000v

Vinh= 2.000v

C_comp

|

icba_io

I/O

Non-Inverting

5.00pF

|

[Voltage Range]

[Pulldown]

|voltage

|

3.3v

I(typ)

3v

3.6v

I(min)

I(max)

-3.30e+00 -5.20e+02 -3.65e+02 -5.18e+02

-3.10e+00 -4.69e+02 -3.30e+02 -4.67e+02

-2.90e+00 -4.18e+02 -2.94e+02 -4.16e+02

-2.70e+00 -3.67e+02 -2.59e+02 -3.65e+02

-2.50e+00 -3.16e+02 -2.23e+02 -3.14e+02

-2.30e+00 -2.65e+02 -1.88e+02 -2.63e+02

-2.10e+00 -2.14e+02 -1.52e+02 -2.12e+02

-1.90e+00 -1.63e+02 -1.17e+02 -1.60e+02

-1.70e+00 -1.13e+02 -9.25e+01 -1.10e+02

-1.50e+00 -7.83e+01 -6.88e+01 -7.58e+01

-1.30e+00 -4.43e+01 -4.52e+01 -4.17e+01

-1.10e+00 -1.02e+01 -2.15e+01 -7.68e+00

MOTOROLA

DSP56364 Advance Information

Appendix A-9

IBIS Model

-9.00e-01 -2.70e-02 -1.19e+00 -2.90e-02

-7.00e-01 -1.32e-02 -1.25e-02 -1.63e-02

-5.00e-01 -9.33e-03 -4.69e-03 -1.10e-02

-3.00e-01 -5.75e-03 -2.81e-03 -6.76e-03

-1.00e-01 -1.97e-03 -9.48e-04 -2.32e-03

1.000e-01 1.945e-03 9.285e-04 2.307e-03

3.000e-01 5.507e-03 2.640e-03 6.599e-03

5.000e-01 8.649e-03 4.168e-03 1.048e-02

7.000e-01 1.136e-02 5.504e-03 1.393e-02

9.000e-01 1.364e-02 6.636e-03 1.693e-02

1.100e+00 1.547e-02 7.551e-03 1.950e-02

1.300e+00 1.688e-02 8.240e-03 2.162e-02

1.500e+00 1.299e-01 6.458e-02 2.331e-02

1.700e+00 1.366e-01 6.746e-02 1.755e-01

1.900e+00 1.404e-01 6.916e-02 1.847e-01

2.100e+00 1.423e-01 7.006e-02 1.907e-01

2.300e+00 1.433e-01 7.059e-02 1.940e-01

2.500e+00 1.440e-01 7.098e-02 1.958e-01

2.700e+00 1.445e-01 7.128e-02 1.970e-01

2.900e+00 1.450e-01 7.154e-02 1.979e-01

3.100e+00 1.454e-01 7.176e-02 1.986e-01

3.300e+00 1.458e-01 7.196e-02 1.993e-01

3.500e+00 1.461e-01 7.223e-02 1.999e-01

3.700e+00 1.464e-01 8.810e-02 2.004e-01

3.900e+00 1.469e-01 2.589e+00 2.009e-01

4.100e+00 1.490e-01 1.451e+01 2.015e-01

4.300e+00 1.501e+00 2.658e+01 2.030e-01

4.500e+00 1.813e+01 3.866e+01 2.385e-01

4.700e+00 3.540e+01 5.076e+01 9.563e+00

4.900e+00 5.269e+01 6.461e+01 2.682e+01

5.100e+00 7.541e+01 8.261e+01 4.409e+01

5.300e+00 1.012e+02 1.006e+02 6.258e+01

5.500e+00 1.270e+02 1.186e+02 8.836e+01

5.700e+00 1.527e+02 1.366e+02 1.141e+02

5.900e+00 1.785e+02 1.546e+02 1.399e+02

6.100e+00 2.043e+02 1.726e+02 1.657e+02

6.300e+00 2.301e+02 1.906e+02 1.915e+02

6.500e+00 2.559e+02 2.086e+02 2.173e+02

6.600e+00 2.688e+02 2.176e+02 2.302e+02

|

[Pullup]

|voltage

|

I(typ)

I(min)

I(max)

-3.30e+00 2.686e+02 1.905e+02 2.686e+02

-3.10e+00 2.428e+02 1.725e+02 2.428e+02

-2.90e+00 2.170e+02 1.545e+02 2.170e+02

-2.70e+00 1.912e+02 1.365e+02 1.912e+02

-2.50e+00 1.655e+02 1.185e+02 1.655e+02

-2.30e+00 1.397e+02 1.005e+02 1.397e+02

-2.10e+00 1.139e+02 8.253e+01 1.139e+02

-1.90e+00 8.814e+01 6.454e+01 8.814e+01

-1.70e+00 6.237e+01 5.068e+01 6.237e+01

-1.50e+00 4.389e+01 3.859e+01 4.389e+01

Appendix A-10

DSP56364 Advance Information

MOTOROLA

IBIS Model

-1.30e+00 2.662e+01 2.651e+01 2.662e+01

-1.10e+00 9.360e+00 1.444e+01 9.362e+00

-9.00e-01 4.275e-02 2.518e+00 4.663e-02

-7.00e-01 8.208e-03 2.012e-02 1.070e-02

-5.00e-01 5.635e-03 3.518e-03 7.068e-03

-3.00e-01 3.370e-03 2.053e-03 4.233e-03

-1.00e-01 1.118e-03 6.789e-04 1.410e-03

1.000e-01 -1.09e-03 -6.56e-04 -1.38e-03

3.000e-01 -3.12e-03 -1.86e-03 -3.99e-03

5.000e-01 -4.96e-03 -2.93e-03 -6.39e-03

7.000e-01 -6.60e-03 -3.87e-03 -8.59e-03

9.000e-01 -8.04e-03 -4.66e-03 -1.06e-02

1.100e+00 -9.26e-03 -5.30e-03 -1.23e-02

1.300e+00 -1.03e-02 -6.55e-02 -1.38e-02

1.500e+00 -1.25e-01 -6.93e-02 -1.70e-01

1.700e+00 -1.31e-01 -7.19e-02 -1.82e-01

1.900e+00 -1.36e-01 -7.38e-02 -1.91e-01

2.100e+00 -1.40e-01 -7.53e-02 -1.97e-01

2.300e+00 -1.42e-01 -7.65e-02 -2.03e-01

2.500e+00 -1.44e-01 -7.76e-02 -2.07e-01

2.700e+00 -1.46e-01 -7.85e-02 -2.10e-01

2.900e+00 -1.48e-01 -7.93e-02 -2.13e-01

3.100e+00 -1.49e-01 -8.00e-02 -2.15e-01

3.300e+00 -1.50e-01 -8.06e-02 -2.17e-01

3.500e+00 -1.52e-01 -8.13e-02 -2.19e-01

3.700e+00 -1.53e-01 -8.84e-02 -2.21e-01

3.900e+00 -1.54e-01 -1.26e+00 -2.22e-01

4.100e+00 -1.57e-01 -2.16e+01 -2.24e-01

4.300e+00 -5.25e-01 -4.53e+01 -2.27e-01

4.500e+00 -2.74e+01 -6.89e+01 -2.38e-01

4.700e+00 -6.14e+01 -9.26e+01 -7.90e+00

4.900e+00 -9.55e+01 -1.17e+02 -4.20e+01

5.100e+00 -1.38e+02 -1.52e+02 -7.60e+01

5.300e+00 -1.89e+02 -1.88e+02 -1.11e+02

5.500e+00 -2.40e+02 -2.23e+02 -1.61e+02

5.700e+00 -2.91e+02 -2.59e+02 -2.12e+02

5.900e+00 -3.42e+02 -2.94e+02 -2.63e+02

6.100e+00 -3.93e+02 -3.30e+02 -3.14e+02

6.300e+00 -4.44e+02 -3.65e+02 -3.65e+02

6.500e+00 -4.95e+02 -4.01e+02 -4.16e+02

6.600e+00 -5.21e+02 -4.19e+02 -4.42e+02

|

[GND_clamp]

|voltage

|

I(typ)

I(min)

I(max)

-3.30e+00 -5.20e+02 -3.65e+02 -5.18e+02

-3.10e+00 -4.69e+02 -3.30e+02 -4.67e+02

-2.90e+00 -4.18e+02 -2.94e+02 -4.16e+02

-2.70e+00 -3.67e+02 -2.59e+02 -3.65e+02

-2.50e+00 -3.16e+02 -2.23e+02 -3.14e+02

-2.30e+00 -2.65e+02 -1.88e+02 -2.63e+02

-2.10e+00 -2.14e+02 -1.52e+02 -2.12e+02

-1.90e+00 -1.63e+02 -1.17e+02 -1.60e+02

MOTOROLA

DSP56364 Advance Information

Appendix A-11

IBIS Model

-1.70e+00 -1.13e+02 -9.25e+01 -1.10e+02

-1.50e+00 -7.83e+01 -6.88e+01 -7.58e+01

-1.30e+00 -4.43e+01 -4.52e+01 -4.17e+01

-1.10e+00 -1.02e+01 -2.15e+01 -7.67e+00

-9.00e-01 -1.22e-02 -1.18e+00 -1.17e-02

-7.00e-01 -5.18e-04 -6.62e-03 -1.56e-03

-5.00e-01 -2.43e-06 -6.64e-05 -1.80e-05

-3.00e-01 -2.33e-09 -6.35e-07 -1.54e-08

-1.00e-01 -2.10e-11 -6.31e-09 -2.99e-11

0.000e+00 -1.70e-11 -1.95e-09 -1.91e-11

|

[POWER_clamp]

|voltage

|

I(typ)

I(min)

I(max)

-3.30e+00 2.686e+02 1.905e+02 2.686e+02

-3.10e+00 2.428e+02 1.725e+02 2.428e+02

-2.90e+00 2.170e+02 1.545e+02 2.170e+02

-2.70e+00 1.912e+02 1.365e+02 1.912e+02

-2.50e+00 1.655e+02 1.185e+02 1.655e+02

-2.30e+00 1.397e+02 1.005e+02 1.397e+02

-2.10e+00 1.139e+02 8.253e+01 1.139e+02

-1.90e+00 8.814e+01 6.454e+01 8.814e+01

-1.70e+00 6.236e+01 5.068e+01 6.237e+01

-1.50e+00 4.389e+01 3.859e+01 4.389e+01

-1.30e+00 2.662e+01 2.651e+01 2.662e+01

-1.10e+00 9.358e+00 1.444e+01 9.359e+00

-9.00e-01 3.399e-02 2.517e+00 3.554e-02

-7.00e-01 3.426e-04 1.577e-02 9.211e-04

-5.00e-01 2.840e-06 7.857e-05 1.655e-05

-3.00e-01 3.401e-09 6.836e-07 1.946e-08

-1.00e-01 6.162e-11 7.379e-09 7.622e-11

0.000e+00 5.758e-11 2.438e-09 6.240e-11

|

[Ramp]

R_load = 50.00

|voltage

I(typ)

I(min)

I(max)

|

dV/dt_r

|

dV/dt_f

|

1.680/0.164

1.690/0.219

1.360/0.329

1.310/0.442

1.900/0.124

1.880/0.155

[End]|

[Model]

Model_type

Polarity

C_comp

|

icba_o

3-state

Non-Inverting

5.00pF

|

[Voltage Range]

[Pulldown]

|voltage

3.3v

I(typ)

3v

3.6v

I(min)

I(max)

Appendix A-12

DSP56364 Advance Information

MOTOROLA

IBIS Model

|

-3.30e+00 -5.20e+02 -3.65e+02 -5.18e+02

-3.10e+00 -4.69e+02 -3.30e+02 -4.67e+02

-2.90e+00 -4.18e+02 -2.94e+02 -4.16e+02

-2.70e+00 -3.67e+02 -2.59e+02 -3.65e+02

-2.50e+00 -3.16e+02 -2.23e+02 -3.14e+02

-2.30e+00 -2.65e+02 -1.88e+02 -2.63e+02

-2.10e+00 -2.14e+02 -1.52e+02 -2.12e+02

-1.90e+00 -1.63e+02 -1.17e+02 -1.60e+02

-1.70e+00 -1.13e+02 -9.25e+01 -1.10e+02

-1.50e+00 -7.83e+01 -6.88e+01 -7.58e+01

-1.30e+00 -4.43e+01 -4.52e+01 -4.17e+01

-1.10e+00 -1.02e+01 -2.15e+01 -7.68e+00

-9.00e-01 -2.70e-02 -1.19e+00 -2.90e-02

-7.00e-01 -1.32e-02 -1.25e-02 -1.63e-02

-5.00e-01 -9.33e-03 -4.69e-03 -1.10e-02

-3.00e-01 -5.75e-03 -2.81e-03 -6.76e-03

-1.00e-01 -1.97e-03 -9.48e-04 -2.32e-03

1.000e-01 1.945e-03 9.285e-04 2.307e-03

3.000e-01 5.507e-03 2.640e-03 6.599e-03

5.000e-01 8.649e-03 4.168e-03 1.048e-02

7.000e-01 1.136e-02 5.504e-03 1.393e-02

9.000e-01 1.364e-02 6.636e-03 1.693e-02

1.100e+00 1.547e-02 7.551e-03 1.950e-02

1.300e+00 1.688e-02 8.240e-03 2.162e-02

1.500e+00 1.299e-01 6.458e-02 2.331e-02

1.700e+00 1.366e-01 6.746e-02 1.755e-01

1.900e+00 1.404e-01 6.916e-02 1.847e-01

2.100e+00 1.423e-01 7.006e-02 1.907e-01

2.300e+00 1.433e-01 7.059e-02 1.940e-01

2.500e+00 1.440e-01 7.098e-02 1.958e-01

2.700e+00 1.445e-01 7.128e-02 1.970e-01

2.900e+00 1.450e-01 7.154e-02 1.979e-01

3.100e+00 1.454e-01 7.176e-02 1.986e-01

3.300e+00 1.458e-01 7.196e-02 1.993e-01

3.500e+00 1.461e-01 7.223e-02 1.999e-01

3.700e+00 1.464e-01 8.810e-02 2.004e-01

3.900e+00 1.469e-01 2.589e+00 2.009e-01

4.100e+00 1.490e-01 1.451e+01 2.015e-01

4.300e+00 1.501e+00 2.658e+01 2.030e-01

4.500e+00 1.813e+01 3.866e+01 2.385e-01

4.700e+00 3.540e+01 5.076e+01 9.563e+00

4.900e+00 5.269e+01 6.461e+01 2.682e+01

5.100e+00 7.541e+01 8.261e+01 4.409e+01

5.300e+00 1.012e+02 1.006e+02 6.258e+01

5.500e+00 1.270e+02 1.186e+02 8.836e+01

5.700e+00 1.527e+02 1.366e+02 1.141e+02

5.900e+00 1.785e+02 1.546e+02 1.399e+02

6.100e+00 2.043e+02 1.726e+02 1.657e+02

6.300e+00 2.301e+02 1.906e+02 1.915e+02

6.500e+00 2.559e+02 2.086e+02 2.173e+02

6.600e+00 2.688e+02 2.176e+02 2.302e+02

|

MOTOROLA

DSP56364 Advance Information

Appendix A-13

IBIS Model

[Pullup]

|voltage

|

I(typ)

I(min)

I(max)

-3.30e+00 2.686e+02 1.905e+02 2.686e+02

-3.10e+00 2.428e+02 1.725e+02 2.428e+02

-2.90e+00 2.170e+02 1.545e+02 2.170e+02

-2.70e+00 1.912e+02 1.365e+02 1.912e+02

-2.50e+00 1.655e+02 1.185e+02 1.655e+02

-2.30e+00 1.397e+02 1.005e+02 1.397e+02

-2.10e+00 1.139e+02 8.253e+01 1.139e+02

-1.90e+00 8.814e+01 6.454e+01 8.814e+01

-1.70e+00 6.237e+01 5.068e+01 6.237e+01

-1.50e+00 4.389e+01 3.859e+01 4.389e+01

-1.30e+00 2.662e+01 2.651e+01 2.662e+01

-1.10e+00 9.360e+00 1.444e+01 9.362e+00

-9.00e-01 4.275e-02 2.518e+00 4.663e-02

-7.00e-01 8.208e-03 2.012e-02 1.070e-02

-5.00e-01 5.635e-03 3.518e-03 7.068e-03

-3.00e-01 3.370e-03 2.053e-03 4.233e-03

-1.00e-01 1.118e-03 6.789e-04 1.410e-03

1.000e-01 -1.09e-03 -6.56e-04 -1.38e-03

3.000e-01 -3.12e-03 -1.86e-03 -3.99e-03

5.000e-01 -4.96e-03 -2.93e-03 -6.39e-03

7.000e-01 -6.60e-03 -3.87e-03 -8.59e-03

9.000e-01 -8.04e-03 -4.66e-03 -1.06e-02

1.100e+00 -9.26e-03 -5.30e-03 -1.23e-02

1.300e+00 -1.03e-02 -6.55e-02 -1.38e-02

1.500e+00 -1.25e-01 -6.93e-02 -1.70e-01

1.700e+00 -1.31e-01 -7.19e-02 -1.82e-01

1.900e+00 -1.36e-01 -7.38e-02 -1.91e-01

2.100e+00 -1.40e-01 -7.53e-02 -1.97e-01

2.300e+00 -1.42e-01 -7.65e-02 -2.03e-01

2.500e+00 -1.44e-01 -7.76e-02 -2.07e-01

2.700e+00 -1.46e-01 -7.85e-02 -2.10e-01

2.900e+00 -1.48e-01 -7.93e-02 -2.13e-01

3.100e+00 -1.49e-01 -8.00e-02 -2.15e-01

3.300e+00 -1.50e-01 -8.06e-02 -2.17e-01

3.500e+00 -1.52e-01 -8.13e-02 -2.19e-01

3.700e+00 -1.53e-01 -8.84e-02 -2.21e-01

3.900e+00 -1.54e-01 -1.26e+00 -2.22e-01

4.100e+00 -1.57e-01 -2.16e+01 -2.24e-01

4.300e+00 -5.25e-01 -4.53e+01 -2.27e-01

4.500e+00 -2.74e+01 -6.89e+01 -2.38e-01

4.700e+00 -6.14e+01 -9.26e+01 -7.90e+00

4.900e+00 -9.55e+01 -1.17e+02 -4.20e+01

5.100e+00 -1.38e+02 -1.52e+02 -7.60e+01

5.300e+00 -1.89e+02 -1.88e+02 -1.11e+02

5.500e+00 -2.40e+02 -2.23e+02 -1.61e+02

5.700e+00 -2.91e+02 -2.59e+02 -2.12e+02

5.900e+00 -3.42e+02 -2.94e+02 -2.63e+02

6.100e+00 -3.93e+02 -3.30e+02 -3.14e+02

6.300e+00 -4.44e+02 -3.65e+02 -3.65e+02

6.500e+00 -4.95e+02 -4.01e+02 -4.16e+02

Appendix A-14

DSP56364 Advance Information

MOTOROLA

IBIS Model

6.600e+00 -5.21e+02 -4.19e+02 -4.42e+02

|

[GND_clamp]

|voltage

|

I(typ)

I(min)

I(max)

-3.30e+00 -5.20e+02 -3.65e+02 -5.18e+02

-3.10e+00 -4.69e+02 -3.30e+02 -4.67e+02

-2.90e+00 -4.18e+02 -2.94e+02 -4.16e+02

-2.70e+00 -3.67e+02 -2.59e+02 -3.65e+02

-2.50e+00 -3.16e+02 -2.23e+02 -3.14e+02

-2.30e+00 -2.65e+02 -1.88e+02 -2.63e+02

-2.10e+00 -2.14e+02 -1.52e+02 -2.12e+02

-1.90e+00 -1.63e+02 -1.17e+02 -1.60e+02

-1.70e+00 -1.13e+02 -9.25e+01 -1.10e+02

-1.50e+00 -7.83e+01 -6.88e+01 -7.58e+01

-1.30e+00 -4.43e+01 -4.52e+01 -4.17e+01

-1.10e+00 -1.02e+01 -2.15e+01 -7.67e+00

-9.00e-01 -1.22e-02 -1.18e+00 -1.17e-02

-7.00e-01 -5.18e-04 -6.62e-03 -1.56e-03

-5.00e-01 -2.43e-06 -6.64e-05 -1.80e-05

-3.00e-01 -2.33e-09 -6.35e-07 -1.54e-08

-1.00e-01 -2.10e-11 -6.31e-09 -2.99e-11

0.000e+00 -1.70e-11 -1.95e-09 -1.91e-11

|

[POWER_clamp]

|voltage

|

I(typ)

I(min)

I(max)

-3.30e+00 2.686e+02 1.905e+02 2.686e+02

-3.10e+00 2.428e+02 1.725e+02 2.428e+02

-2.90e+00 2.170e+02 1.545e+02 2.170e+02

-2.70e+00 1.912e+02 1.365e+02 1.912e+02

-2.50e+00 1.655e+02 1.185e+02 1.655e+02

-2.30e+00 1.397e+02 1.005e+02 1.397e+02

-2.10e+00 1.139e+02 8.253e+01 1.139e+02

-1.90e+00 8.814e+01 6.454e+01 8.814e+01

-1.70e+00 6.236e+01 5.068e+01 6.237e+01

-1.50e+00 4.389e+01 3.859e+01 4.389e+01

-1.30e+00 2.662e+01 2.651e+01 2.662e+01

-1.10e+00 9.358e+00 1.444e+01 9.359e+00

-9.00e-01 3.399e-02 2.517e+00 3.554e-02

-7.00e-01 3.426e-04 1.577e-02 9.211e-04

-5.00e-01 2.840e-06 7.857e-05 1.655e-05

-3.00e-01 3.401e-09 6.836e-07 1.946e-08

-1.00e-01 6.162e-11 7.379e-09 7.622e-11

0.000e+00 5.758e-11 2.438e-09 6.240e-11

|

[Ramp]

R_load = 50.00

|voltage

I(typ)

I(min)

I(max)

|

dV/dt_r

|

1.680/0.164

1.360/0.329

1.900/0.124

MOTOROLA

DSP56364 Advance Information

Appendix A-15

IBIS Model

|

dV/dt_f

|

1.690/0.219

1.310/0.442

1.880/0.155

[End]|

[Model]

Model_type

Polarity

C_comp

|

icbc_o

3-state

Non-Inverting

5.00pF

|

[Voltage Range]

[Pulldown]

|voltage

|

3.3v

I(typ)

3v

3.6v

I(min)

I(max)

-3.30e+00 -5.20e+02 -3.65e+02 -5.18e+02

-3.10e+00 -4.69e+02 -3.30e+02 -4.67e+02

-2.90e+00 -4.18e+02 -2.94e+02 -4.16e+02

-2.70e+00 -3.67e+02 -2.59e+02 -3.65e+02

-2.50e+00 -3.16e+02 -2.23e+02 -3.14e+02

-2.30e+00 -2.65e+02 -1.88e+02 -2.63e+02

-2.10e+00 -2.14e+02 -1.52e+02 -2.11e+02

-1.90e+00 -1.63e+02 -1.17e+02 -1.60e+02

-1.70e+00 -1.13e+02 -9.25e+01 -1.10e+02

-1.50e+00 -7.83e+01 -6.88e+01 -7.58e+01

-1.30e+00 -4.42e+01 -4.51e+01 -4.17e+01

-1.10e+00 -1.02e+01 -2.15e+01 -7.67e+00

-9.00e-01 -2.51e-02 -1.18e+00 -2.65e-02

-7.00e-01 -1.30e-02 -1.16e-02 -1.58e-02

-5.00e-01 -9.33e-03 -4.67e-03 -1.10e-02

-3.00e-01 -5.75e-03 -2.81e-03 -6.76e-03

-1.00e-01 -1.97e-03 -9.48e-04 -2.32e-03

1.000e-01 1.945e-03 9.285e-04 2.307e-03

3.000e-01 5.507e-03 2.640e-03 6.599e-03

5.000e-01 8.649e-03 4.168e-03 1.048e-02

7.000e-01 1.136e-02 5.504e-03 1.393e-02

9.000e-01 1.364e-02 6.636e-03 1.693e-02

1.100e+00 1.547e-02 7.551e-03 1.950e-02

1.300e+00 1.688e-02 8.240e-03 2.162e-02

1.500e+00 9.632e-02 4.783e-02 2.331e-02

1.700e+00 1.012e-01 4.994e-02 1.302e-01

1.900e+00 1.039e-01 5.118e-02 1.369e-01

2.100e+00 1.053e-01 5.184e-02 1.412e-01

2.300e+00 1.060e-01 5.223e-02 1.436e-01

2.500e+00 1.065e-01 5.251e-02 1.449e-01

2.700e+00 1.069e-01 5.274e-02 1.458e-01

2.900e+00 1.073e-01 5.293e-02 1.464e-01

3.100e+00 1.076e-01 5.309e-02 1.470e-01

3.300e+00 1.078e-01 5.324e-02 1.475e-01

3.500e+00 1.081e-01 5.344e-02 1.479e-01

3.700e+00 1.083e-01 6.705e-02 1.483e-01

3.900e+00 1.086e-01 2.529e+00 1.487e-01

4.100e+00 1.103e-01 1.438e+01 1.491e-01

4.300e+00 1.437e+00 2.638e+01 1.503e-01

Appendix A-16

DSP56364 Advance Information

MOTOROLA

IBIS Model

4.500e+00 1.800e+01 3.839e+01 1.810e-01

4.700e+00 3.519e+01 5.041e+01 9.452e+00

4.900e+00 5.241e+01 6.419e+01 2.664e+01

5.100e+00 7.505e+01 8.210e+01 4.384e+01

5.300e+00 1.007e+02 1.000e+02 6.224e+01

5.500e+00 1.264e+02 1.179e+02 8.794e+01

5.700e+00 1.522e+02 1.359e+02 1.136e+02

5.900e+00 1.779e+02 1.538e+02 1.394e+02

6.100e+00 2.036e+02 1.717e+02 1.651e+02

6.300e+00 2.293e+02 1.896e+02 1.908e+02

6.500e+00 2.550e+02 2.075e+02 2.165e+02

6.600e+00 2.678e+02 2.165e+02 2.293e+02

|

[Pullup]

|voltage

|

I(typ)

I(min)

I(max)

-3.30e+00 2.677e+02 1.896e+02 2.677e+02

-3.10e+00 2.420e+02 1.716e+02 2.420e+02

-2.90e+00 2.163e+02 1.537e+02 2.163e+02

-2.70e+00 1.906e+02 1.358e+02 1.906e+02

-2.50e+00 1.649e+02 1.179e+02 1.649e+02

-2.30e+00 1.392e+02 9.996e+01 1.392e+02

-2.10e+00 1.135e+02 8.205e+01 1.135e+02

-1.90e+00 8.778e+01 6.413e+01 8.778e+01

-1.70e+00 6.208e+01 5.035e+01 6.208e+01

-1.50e+00 4.368e+01 3.834e+01 4.368e+01

-1.30e+00 2.649e+01 2.633e+01 2.649e+01

-1.10e+00 9.302e+00 1.433e+01 9.303e+00

-9.00e-01 3.838e-02 2.477e+00 4.183e-02

-7.00e-01 8.115e-03 1.789e-02 1.045e-02

-5.00e-01 5.634e-03 3.503e-03 7.064e-03

-3.00e-01 3.370e-03 2.053e-03 4.233e-03

-1.00e-01 1.118e-03 6.789e-04 1.410e-03

1.000e-01 -1.09e-03 -6.56e-04 -1.38e-03

3.000e-01 -3.12e-03 -1.86e-03 -3.99e-03

5.000e-01 -4.96e-03 -2.93e-03 -6.39e-03

7.000e-01 -6.60e-03 -3.87e-03 -8.59e-03

9.000e-01 -8.04e-03 -4.66e-03 -1.06e-02

1.100e+00 -9.26e-03 -5.30e-03 -1.23e-02

1.300e+00 -1.03e-02 -4.75e-02 -1.41e-02

1.500e+00 -9.03e-02 -5.02e-02 -1.23e-01

1.700e+00 -9.49e-02 -5.21e-02 -1.31e-01

1.900e+00 -9.84e-02 -5.34e-02 -1.38e-01

2.100e+00 -1.01e-01 -5.45e-02 -1.43e-01

2.300e+00 -1.03e-01 -5.54e-02 -1.47e-01

2.500e+00 -1.05e-01 -5.62e-02 -1.50e-01

2.700e+00 -1.06e-01 -5.68e-02 -1.52e-01

2.900e+00 -1.07e-01 -5.74e-02 -1.54e-01

3.100e+00 -1.08e-01 -5.79e-02 -1.56e-01

3.300e+00 -1.09e-01 -5.84e-02 -1.57e-01

3.500e+00 -1.10e-01 -5.89e-02 -1.59e-01

3.700e+00 -1.11e-01 -6.49e-02 -1.60e-01

3.900e+00 -1.11e-01 -1.23e+00 -1.61e-01

MOTOROLA

DSP56364 Advance Information

Appendix A-17

IBIS Model

4.100e+00 -1.14e-01 -2.16e+01 -1.62e-01

4.300e+00 -4.76e-01 -4.52e+01 -1.64e-01

4.500e+00 -2.73e+01 -6.89e+01 -1.73e-01

4.700e+00 -6.14e+01 -9.25e+01 -7.82e+00

4.900e+00 -9.54e+01 -1.17e+02 -4.19e+01

5.100e+00 -1.38e+02 -1.52e+02 -7.59e+01

5.300e+00 -1.89e+02 -1.88e+02 -1.11e+02

5.500e+00 -2.40e+02 -2.23e+02 -1.61e+02

5.700e+00 -2.91e+02 -2.59e+02 -2.12e+02

5.900e+00 -3.42e+02 -2.94e+02 -2.63e+02

6.100e+00 -3.93e+02 -3.30e+02 -3.14e+02

6.300e+00 -4.44e+02 -3.65e+02 -3.65e+02

6.500e+00 -4.95e+02 -4.01e+02 -4.16e+02

6.600e+00 -5.20e+02 -4.18e+02 -4.41e+02

|

[GND_clamp]

|voltage

|

I(typ)

I(min)

I(max)

-3.30e+00 -5.20e+02 -3.65e+02 -5.18e+02

-3.10e+00 -4.69e+02 -3.30e+02 -4.67e+02

-2.90e+00 -4.18e+02 -2.94e+02 -4.16e+02

-2.70e+00 -3.67e+02 -2.59e+02 -3.65e+02

-2.50e+00 -3.16e+02 -2.23e+02 -3.14e+02

-2.30e+00 -2.65e+02 -1.88e+02 -2.63e+02

-2.10e+00 -2.14e+02 -1.52e+02 -2.11e+02

-1.90e+00 -1.63e+02 -1.17e+02 -1.60e+02

-1.70e+00 -1.13e+02 -9.25e+01 -1.10e+02

-1.50e+00 -7.83e+01 -6.88e+01 -7.58e+01

-1.30e+00 -4.42e+01 -4.51e+01 -4.17e+01

-1.10e+00 -1.02e+01 -2.15e+01 -7.66e+00

-9.00e-01 -1.03e-02 -1.17e+00 -9.27e-03

-7.00e-01 -3.74e-04 -5.73e-03 -1.14e-03

-5.00e-01 -1.72e-06 -5.06e-05 -1.28e-05

-3.00e-01 -1.67e-09 -4.65e-07 -1.10e-08

-1.00e-01 -2.03e-11 -4.80e-09 -2.71e-11

0.000e+00 -1.69e-11 -1.61e-09 -1.89e-11

|

[POWER_clamp]

|voltage

|

I(typ)

I(min)

I(max)

-3.30e+00 2.677e+02 1.896e+02 2.677e+02

-3.10e+00 2.420e+02 1.716e+02 2.420e+02

-2.90e+00 2.163e+02 1.537e+02 2.163e+02

-2.70e+00 1.906e+02 1.358e+02 1.906e+02

-2.50e+00 1.649e+02 1.179e+02 1.649e+02

-2.30e+00 1.392e+02 9.996e+01 1.392e+02

-2.10e+00 1.135e+02 8.205e+01 1.135e+02

-1.90e+00 8.778e+01 6.413e+01 8.778e+01

-1.70e+00 6.208e+01 5.035e+01 6.208e+01

-1.50e+00 4.368e+01 3.834e+01 4.368e+01

-1.30e+00 2.649e+01 2.633e+01 2.649e+01

-1.10e+00 9.300e+00 1.433e+01 9.301e+00

-9.00e-01 2.962e-02 2.475e+00 3.075e-02

Appendix A-18

DSP56364 Advance Information

MOTOROLA

IBIS Model

-7.00e-01 2.501e-04 1.354e-02 6.708e-04

-5.00e-01 2.066e-06 6.280e-05 1.204e-05

-3.00e-01 2.487e-09 5.128e-07 1.417e-08

-1.00e-01 5.672e-11 5.639e-09 6.832e-11

0.000e+00 5.334e-11 1.992e-09 5.783e-11

|

[Ramp]

R_load = 50.00

|voltage

I(typ)

I(min)

I(max)

|

dV/dt_r

|

dV/dt_f

|

1.570/0.200

1.590/0.304

1.210/0.411

1.170/0.673

1.810/0.149

1.800/0.205

[End]|

[Model]

Model_type

Polarity

Vinl= 0.8000v

Vinh= 2.000v

C_comp

|

ipbw_i

Input

Non-Inverting

5.00pF

|

[Voltage Range]

[GND_clamp]

|voltage

|

3.3v

I(typ)

3v

3.6v

I(min)

I(max)

-3.30e+00 -5.20e+02 -3.65e+02 -5.17e+02

-3.10e+00 -4.69e+02 -3.29e+02 -4.66e+02

-2.90e+00 -4.18e+02 -2.94e+02 -4.15e+02

-2.70e+00 -3.67e+02 -2.58e+02 -3.64e+02

-2.50e+00 -3.16e+02 -2.23e+02 -3.13e+02

-2.30e+00 -2.65e+02 -1.88e+02 -2.62e+02

-2.10e+00 -2.14e+02 -1.52e+02 -2.11e+02

-1.90e+00 -1.63e+02 -1.17e+02 -1.60e+02

-1.70e+00 -1.13e+02 -9.24e+01 -1.10e+02

-1.50e+00 -7.82e+01 -6.87e+01 -7.57e+01

-1.30e+00 -4.42e+01 -4.51e+01 -4.16e+01

-1.10e+00 -1.02e+01 -2.15e+01 -7.64e+00

-9.00e-01 -7.17e-03 -1.16e+00 -4.87e-03

-7.00e-01 -1.14e-04 -4.39e-03 -3.03e-04

-5.00e-01 -4.86e-07 -2.55e-05 -2.73e-06

-3.00e-01 -5.19e-10 -1.91e-07 -2.57e-09

-1.00e-01 -1.91e-11 -2.47e-09 -2.19e-11

0.000e+00 -1.68e-11 -1.17e-09 -1.84e-11

|

[POWER_clamp]

|voltage

|

I(typ)

I(min)

I(max)

-3.30e+00 2.667e+02 1.885e+02 2.667e+02

-3.10e+00 2.411e+02 1.707e+02 2.411e+02

MOTOROLA

DSP56364 Advance Information

Appendix A-19

IBIS Model

-2.90e+00 2.155e+02 1.528e+02 2.155e+02

-2.70e+00 1.898e+02 1.350e+02 1.898e+02

-2.50e+00 1.642e+02 1.172e+02 1.642e+02

-2.30e+00 1.386e+02 9.935e+01 1.386e+02

-2.10e+00 1.130e+02 8.152e+01 1.130e+02

-1.90e+00 8.739e+01 6.369e+01 8.739e+01

-1.70e+00 6.178e+01 4.999e+01 6.178e+01

-1.50e+00 4.346e+01 3.806e+01 4.346e+01

-1.30e+00 2.634e+01 2.613e+01 2.634e+01

-1.10e+00 9.237e+00 1.421e+01 9.237e+00

-9.00e-01 2.454e-02 2.430e+00 2.488e-02

-7.00e-01 8.741e-05 1.104e-02 2.050e-04

-5.00e-01 6.316e-07 4.079e-05 2.961e-06

-3.00e-01 8.479e-10 2.484e-07 3.721e-09

-1.00e-01 4.420e-11 3.001e-09 4.943e-11

0.000e+00 4.215e-11 1.346e-09 4.543e-11

|

[End]|

[Model]

Model_type

Polarity

Vinl= 0.8000v

Vinh= 2.000v

C_comp

ipbw_io

I/O

Non-Inverting

5.00pF

|

[Voltage Range]

[Pulldown]

|voltage

|

3.3v

I(typ)

3v

3.6v

I(min)

I(max)

-3.30e+00 -5.20e+02 -3.65e+02 -5.17e+02

-3.10e+00 -4.69e+02 -3.29e+02 -4.66e+02

-2.90e+00 -4.18e+02 -2.94e+02 -4.15e+02

-2.70e+00 -3.67e+02 -2.58e+02 -3.64e+02

-2.50e+00 -3.16e+02 -2.23e+02 -3.13e+02

-2.30e+00 -2.65e+02 -1.88e+02 -2.62e+02

-2.10e+00 -2.14e+02 -1.52e+02 -2.11e+02

-1.90e+00 -1.63e+02 -1.17e+02 -1.60e+02

-1.70e+00 -1.13e+02 -9.24e+01 -1.10e+02

-1.50e+00 -7.82e+01 -6.87e+01 -7.57e+01

-1.30e+00 -4.42e+01 -4.51e+01 -4.17e+01

-1.10e+00 -1.02e+01 -2.15e+01 -7.66e+00

-9.00e-01 -3.69e-02 -1.17e+00 -3.79e-02

-7.00e-01 -2.52e-02 -1.67e-02 -2.81e-02

-5.00e-01 -1.83e-02 -9.77e-03 -2.04e-02

-3.00e-01 -1.11e-02 -5.89e-03 -1.24e-02

-1.00e-01 -3.77e-03 -1.98e-03 -4.20e-03

1.000e-01 3.729e-03 1.940e-03 4.177e-03

3.000e-01 1.076e-02 5.578e-03 1.216e-02

5.000e-01 1.723e-02 8.907e-03 1.965e-02

7.000e-01 2.311e-02 1.191e-02 2.663e-02

9.000e-01 2.836e-02 1.455e-02 3.305e-02

1.100e+00 3.292e-02 1.680e-02 3.887e-02

Appendix A-20

DSP56364 Advance Information

MOTOROLA

IBIS Model

1.300e+00 3.675e-02 1.862e-02 4.404e-02

1.500e+00 3.979e-02 1.997e-02 4.850e-02

1.700e+00 4.205e-02 2.085e-02 5.223e-02

1.900e+00 4.347e-02 2.136e-02 5.518e-02

2.100e+00 4.413e-02 2.162e-02 5.728e-02

2.300e+00 4.445e-02 2.176e-02 5.843e-02

2.500e+00 4.465e-02 2.186e-02 5.899e-02

2.700e+00 4.479e-02 2.194e-02 5.931e-02

2.900e+00 4.492e-02 2.200e-02 5.953e-02

3.100e+00 4.502e-02 2.206e-02 5.971e-02

3.300e+00 4.511e-02 2.211e-02 5.986e-02

3.500e+00 4.519e-02 2.219e-02 5.999e-02

3.700e+00 4.526e-02 3.324e-02 6.010e-02

3.900e+00 4.536e-02 2.452e+00 6.021e-02

4.100e+00 4.614e-02 1.423e+01 6.032e-02

4.300e+00 1.344e+00 2.615e+01 6.065e-02

4.500e+00 1.783e+01 3.808e+01 8.548e-02

4.700e+00 3.495e+01 5.001e+01 9.298e+00

4.900e+00 5.208e+01 6.371e+01 2.640e+01

5.100e+00 7.463e+01 8.154e+01 4.352e+01

5.300e+00 1.002e+02 9.937e+01 6.184e+01

5.500e+00 1.259e+02 1.172e+02 8.745e+01

5.700e+00 1.515e+02 1.350e+02 1.131e+02

5.900e+00 1.771e+02 1.529e+02 1.387e+02

6.100e+00 2.027e+02 1.707e+02 1.643e+02

6.300e+00 2.283e+02 1.885e+02 1.899e+02

6.500e+00 2.539e+02 2.064e+02 2.155e+02

6.600e+00 2.667e+02 2.153e+02 2.283e+02

|

[Pullup]

|voltage

|

I(typ)

I(min)

I(max)

-3.30e+00 2.667e+02 1.885e+02 2.667e+02

-3.10e+00 2.411e+02 1.707e+02 2.411e+02

-2.90e+00 2.155e+02 1.528e+02 2.155e+02

-2.70e+00 1.898e+02 1.350e+02 1.898e+02

-2.50e+00 1.642e+02 1.172e+02 1.642e+02

-2.30e+00 1.386e+02 9.935e+01 1.386e+02

-2.10e+00 1.130e+02 8.152e+01 1.130e+02

-1.90e+00 8.739e+01 6.369e+01 8.739e+01

-1.70e+00 6.178e+01 4.999e+01 6.178e+01

-1.50e+00 4.346e+01 3.806e+01 4.346e+01

-1.30e+00 2.635e+01 2.613e+01 2.635e+01

-1.10e+00 9.243e+00 1.421e+01 9.245e+00

-9.00e-01 5.536e-02 2.435e+00 6.260e-02

-7.00e-01 2.847e-02 2.689e-02 3.437e-02

-5.00e-01 2.025e-02 1.265e-02 2.451e-02

-3.00e-01 1.208e-02 7.503e-03 1.467e-02

-1.00e-01 3.994e-03 2.474e-03 4.868e-03

1.000e-01 -3.88e-03 -2.38e-03 -4.76e-03

3.000e-01 -1.11e-02 -6.76e-03 -1.37e-02

5.000e-01 -1.76e-02 -1.06e-02 -2.20e-02

7.000e-01 -2.35e-02 -1.40e-02 -2.95e-02

MOTOROLA

DSP56364 Advance Information

Appendix A-21

IBIS Model

9.000e-01 -2.86e-02 -1.69e-02 -3.63e-02

1.100e+00 -3.30e-02 -1.93e-02 -4.23e-02

1.300e+00 -3.65e-02 -2.10e-02 -4.75e-02

1.500e+00 -3.92e-02 -2.22e-02 -5.17e-02

1.700e+00 -4.12e-02 -2.29e-02 -5.51e-02

1.900e+00 -4.26e-02 -2.35e-02 -5.77e-02

2.100e+00 -4.36e-02 -2.38e-02 -5.97e-02

2.300e+00 -4.43e-02 -2.42e-02 -6.11e-02

2.500e+00 -4.49e-02 -2.44e-02 -6.22e-02

2.700e+00 -4.54e-02 -2.47e-02 -6.31e-02

2.900e+00 -4.58e-02 -2.49e-02 -6.38e-02

3.100e+00 -4.61e-02 -2.50e-02 -6.44e-02

3.300e+00 -4.65e-02 -2.52e-02 -6.49e-02

3.500e+00 -4.68e-02 -2.54e-02 -6.54e-02

3.700e+00 -4.70e-02 -2.99e-02 -6.58e-02

3.900e+00 -4.73e-02 -1.19e+00 -6.62e-02

4.100e+00 -4.81e-02 -2.15e+01 -6.66e-02

4.300e+00 -4.00e-01 -4.51e+01 -6.72e-02

4.500e+00 -2.72e+01 -6.87e+01 -7.21e-02

4.700e+00 -6.12e+01 -9.24e+01 -7.70e+00

4.900e+00 -9.52e+01 -1.17e+02 -4.17e+01

5.100e+00 -1.37e+02 -1.52e+02 -7.57e+01

5.300e+00 -1.88e+02 -1.88e+02 -1.10e+02

5.500e+00 -2.39e+02 -2.23e+02 -1.60e+02

5.700e+00 -2.90e+02 -2.58e+02 -2.11e+02

5.900e+00 -3.41e+02 -2.94e+02 -2.62e+02

6.100e+00 -3.92e+02 -3.29e+02 -3.13e+02

6.300e+00 -4.43e+02 -3.65e+02 -3.64e+02

6.500e+00 -4.94e+02 -4.00e+02 -4.15e+02

6.600e+00 -5.20e+02 -4.18e+02 -4.41e+02

|

[GND_clamp]

|voltage

|

I(typ)

I(min)

I(max)

-3.30e+00 -5.20e+02 -3.65e+02 -5.17e+02

-3.10e+00 -4.69e+02 -3.29e+02 -4.66e+02

-2.90e+00 -4.18e+02 -2.94e+02 -4.15e+02

-2.70e+00 -3.67e+02 -2.58e+02 -3.64e+02

-2.50e+00 -3.16e+02 -2.23e+02 -3.13e+02

-2.30e+00 -2.65e+02 -1.88e+02 -2.62e+02

-2.10e+00 -2.14e+02 -1.52e+02 -2.11e+02

-1.90e+00 -1.63e+02 -1.17e+02 -1.60e+02

-1.70e+00 -1.13e+02 -9.24e+01 -1.10e+02

-1.50e+00 -7.82e+01 -6.87e+01 -7.57e+01

-1.30e+00 -4.42e+01 -4.51e+01 -4.16e+01

-1.10e+00 -1.02e+01 -2.15e+01 -7.64e+00

-9.00e-01 -7.17e-03 -1.16e+00 -4.87e-03

-7.00e-01 -1.14e-04 -4.39e-03 -3.03e-04

-5.00e-01 -4.86e-07 -2.55e-05 -2.73e-06

-3.00e-01 -5.19e-10 -1.91e-07 -2.57e-09

-1.00e-01 -1.91e-11 -2.47e-09 -2.19e-11

0.000e+00 -1.68e-11 -1.17e-09 -1.84e-11

|

Appendix A-22

DSP56364 Advance Information

MOTOROLA

IBIS Model

[POWER_clamp]

|voltage

|

I(typ)

I(min)

I(max)

-3.30e+00 2.667e+02 1.885e+02 2.667e+02

-3.10e+00 2.411e+02 1.707e+02 2.411e+02

-2.90e+00 2.155e+02 1.528e+02 2.155e+02

-2.70e+00 1.898e+02 1.350e+02 1.898e+02

-2.50e+00 1.642e+02 1.172e+02 1.642e+02

-2.30e+00 1.386e+02 9.935e+01 1.386e+02

-2.10e+00 1.130e+02 8.152e+01 1.130e+02

-1.90e+00 8.739e+01 6.369e+01 8.739e+01

-1.70e+00 6.178e+01 4.999e+01 6.178e+01

-1.50e+00 4.346e+01 3.806e+01 4.346e+01

-1.30e+00 2.634e+01 2.613e+01 2.634e+01

-1.10e+00 9.237e+00 1.421e+01 9.237e+00

-9.00e-01 2.454e-02 2.430e+00 2.488e-02

-7.00e-01 8.741e-05 1.104e-02 2.050e-04

-5.00e-01 6.316e-07 4.079e-05 2.961e-06

-3.00e-01 8.479e-10 2.484e-07 3.721e-09

-1.00e-01 4.420e-11 3.001e-09 4.943e-11

0.000e+00 4.215e-11 1.346e-09 4.543e-11

|

[Ramp]

R_load = 50.00

|voltage

I(typ)

I(min)

I(max)

|

dV/dt_r

|

dV/dt_f

|

1.140/0.494

1.150/0.505

0.699/0.978

0.642/0.956

1.400/0.354

1.350/0.350

[End]|

[Model]

Model_type

Polarity

Vinl= 0.8000v

Vinh= 2.000v

C_comp

|

iexlh_i

Input

Non-Inverting

5.00pF

|

[Voltage Range]

[GND_clamp]

|voltage

|

3.3v

I(typ)

3v

3.6v

I(min)

I(max)

-3.30e+00 -5.21e+02 -3.66e+02 -5.18e+02

-3.10e+00 -4.70e+02 -3.30e+02 -4.67e+02

-2.90e+00 -4.19e+02 -2.95e+02 -4.16e+02

-2.70e+00 -3.68e+02 -2.59e+02 -3.65e+02

-2.50e+00 -3.17e+02 -2.24e+02 -3.14e+02

-2.30e+00 -2.66e+02 -1.89e+02 -2.63e+02

-2.10e+00 -2.15e+02 -1.53e+02 -2.12e+02

-1.90e+00 -1.64e+02 -1.18e+02 -1.61e+02

MOTOROLA

DSP56364 Advance Information

Appendix A-23

IBIS Model

-1.70e+00 -1.14e+02 -9.34e+01 -1.11e+02

-1.50e+00 -7.93e+01 -6.98e+01 -7.68e+01

-1.30e+00 -4.53e+01 -4.62e+01 -4.28e+01

-1.10e+00 -1.13e+01 -2.26e+01 -8.78e+00

-9.00e-01 -7.94e-03 -1.87e+00 -3.77e-03

-7.00e-01 -1.62e-06 -5.11e-03 -7.69e-07

-5.00e-01 -3.45e-10 -1.40e-05 -1.72e-10

-3.00e-01 -1.29e-11 -3.90e-08 -1.38e-11

-1.00e-01 -1.10e-11 -8.67e-10 -1.19e-11

0.000e+00 -1.01e-11 -7.13e-10 -1.10e-11

|

[POWER_clamp]

|voltage

|

I(typ)

I(min)

I(max)

-3.30e+00 2.653e+02 1.870e+02 2.653e+02

-3.10e+00 2.398e+02 1.693e+02 2.398e+02

-2.90e+00 2.143e+02 1.516e+02 2.143e+02

-2.70e+00 1.888e+02 1.339e+02 1.888e+02

-2.50e+00 1.633e+02 1.162e+02 1.633e+02

-2.30e+00 1.378e+02 9.847e+01 1.378e+02

-2.10e+00 1.123e+02 8.076e+01 1.123e+02

-1.90e+00 8.682e+01 6.305e+01 8.682e+01

-1.70e+00 6.133e+01 4.947e+01 6.133e+01

-1.50e+00 4.313e+01 3.766e+01 4.313e+01

-1.30e+00 2.614e+01 2.585e+01 2.614e+01

-1.10e+00 9.145e+00 1.404e+01 9.145e+00

-9.00e-01 1.797e-02 2.364e+00 1.797e-02

-7.00e-01 3.667e-06 7.589e-03 3.667e-06

-5.00e-01 7.730e-10 2.072e-05 7.748e-10

-3.00e-01 2.293e-11 5.767e-08 2.476e-11

-1.00e-01 2.096e-11 1.163e-09 2.278e-11

0.000e+00 2.004e-11 9.618e-10 2.186e-11

|

[End]

Appendix A-24

DSP56364 Advance Information

MOTOROLA

INDEX

Numerics

5 V tolerance 1-1

A

wait states selection guide 2-33

write access 2-44

out of page and refresh timings

11 wait states 2-39

15 wait states 2-41

4 wait states 2-33

8 wait states 2-36

Page mode

ac electrical characteristics 2-5

address bus 1-1

ALU v

Arithmetic Logic Unit v

read accesses 2-32

wait states selection guide 2-22

write accesses 2-31

Page mode timings

B

benchmark test algorithm A-1

Boundary Scan (JTAG Port) timing diagram 2-

65

1 wait state 2-23

bus

2 wait states 2-25

3 wait states 2-27

4 wait states 2-29

refresh access 2-45

external address 1-6

external data 1-6

bus control 1-1

C

DSP56300

core features v

DSP56362

case outline drawing 3-6

Clock 1-5

clock 1-1

external 2-6

operation 2-7

clocks

features v

specifications 2-1

E

electrical design considerations 4-3

emory v

internal 2-6

configuration v

Enhanced Serial Audio Interface 1-12

Enhanced Synchronous Audio Interface 1-1

ESAI 1-1, 1-12

D

Data Arithmetic Logic Unit v

data bus 1-1

DAX 1-1

dc electrical characteristics 2-3

design considerations

electrical 4-3

receiver timing 2-61, 2-62

timings 2-57

transmitter timing 2-60

EXTAL jitter 4-5

external address bus 1-6

external bus control 1-6, 1-7

external clock operation 2-6

external data bus 1-6

PLL 4-5

power consumption 4-4

thermal 4-1

external interrupt timing (negative edge-

triggered) 2-15

external level-sensitive fast interrupt timing 2-14

external memory access (DMA Source) timing 2-

16

Digital Audio Transmitter 1-1

Direct Memory Access v

DMA v

DRAM

out of page

MOTOROLA

DSP56364 Advance Information

Index - i

Index

External Memory Expansion Port 1-6, 2-17

PCU v

Peripheral modules vi

Phase Lock Loop v, 2-8

PLL v, 1-1, 1-5, 2-8

Characteristics 2-8

F

functional signal groups 1-1

performance issues 4-5

PLL design considerations 4-5

PLL performance issues 4-5

Port A 1-1, 1-6

G

GPIO timing 2-63

Ground 1-4

PLL 1-4

Port B 1-1

ground 1-1

Port C 1-1, 1-12

Power 1-2

H

power 1-1

HDI08 1-1

Host Interface 1-1

power consumption benchmark test A-1

power consumption design considerations 4-4

Program Control Unit v

I

R

internal clocks 2-6

interrupt and mode control 1-1, 1-8

interrupt control 1-8

recovery from Stop state using IRQA 2-15, 2-16

RESET 1-8

Reset timing 2-9, 2-13

interrupt timing 2-9

external level-sensitive fast 2-14

external negative edge-triggered 2-15

S

Serial Audio Interface (ESAI) vi

Serial Host Interface 1-1, 1-9

Serial Host Interface (SHI) vi

SHI 1-1, 1-9

J

Jitter 4-5

JTAG 1-16

JTAG Port

signal groupings 1-1

signals 1-1

timing 2-64, 2-65

JTAG/OnCE port 1-1

SRAM

read access 2-20

M

read and write accesses 2-17

write access 2-21

maximum ratings 2-1, 2-2

mechanical drawings 3-6

Memory v

Memory Configuration v

Mfax system 3-6

mode control 1-8

Mode select timing 2-9

Stop state

recovery from 2-15, 2-16

Stop timing 2-9

supply voltage 2-2

T

Test Access Port timing diagram 2-65

Test Clock (TCLK) input timing diagram 2-64

thermal characteristics 2-2

thermal design considerations 4-1

Timer 1-1

O

OnCE module 1-16

operating mode select timing 2-15

ordering drawings 3-6

Timing

ordering information 5-1

Enhanced Serial Audio Interface (ESAI) 2-

59

General Purpose I/O (GPIO) Timing 2-57

OnCE™ (On Chip Emulator) Timing 2-57

P

package

TQFP description 3-1, 3-3

Index - ii

DSP56364 Advance Information

MOTOROLA

Index

Serial Host Interface (SHI) SPI Protocol

Timing 2-46

Serial Host Interface (SHI) Timing 2-46

timing

interrupt 2-9

mode select 2-9

Reset 2-9

Stop 2-9

TQFP

pin list by number 3-3

pin-out drawing (top) 3-1

TQFP package drawing 3-6

MOTOROLA

DSP56364 Advance Information

Index - iii

DSP56364

iv

DSP56364 Advance Information

MOTOROLA

Symphony and OnCE are registered trademarks of Motorola, Inc.

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no

warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does

Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims

any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which

may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual

performance may vary over time. All operating parameters, including “Typicals” must be validated for each

customer application by customer’s technical experts. Motorola does not convey any license under its patent rights

nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in

systems intended for surgical implant into the body, or other applications intended to support life, or for any other

application in which the failure of the Motorola product could create a situation where personal injury or death may

occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application,

Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors

harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or

indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such

claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and ꢀ are

registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.

How to reach us:

USA/Europe/Locations Not Listed:

Technical Resource Center:

Internet:

1 (800) 521-6274

http://dspaudio.motorola.com

Motorola Literature Distribution

P.O. Box 5405

DSP Helpline

dsphelp@dsp.sps.mot.com

Denver, Colorado 80217

1 (800) 441-2447

1 (303) 675-2140

Japan:

Asia/Pacific:

Nippon Motorola Ltd.

Motorola Semiconductors H.K. Ltd.

8B Tai Ping Industrial Park

51 Ting Kok Road

Tai Po, N.T., Hong Kong

852-26629298

SPD, Strategic Planning Office

4-32-1, Nishi- Gotanda

Shinagawa-ku, Tokyo 141, Japan

81-3-5487-8488


型号：	DSPB56364FU100
厂家：	MOTOROLA
描述：	Digital Signal Processor, 8-Ext Bit, 100MHz, CMOS, PQFP100, TQFP-100
文件：	总141页 (文件大小：1651K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DSPB56364FU100 [MOTOROLA]

相关型号：

DSPB56366AG120

DSPB56366AG120

DSPB56366AG120

DSPB56367AG150

DSPB56367AG150

DSPB56367AG150

DSPB56367PV150

DSPB56367PV150

DSPB56371AF150

DSPB56374AE

DSPB56374AF

DSPB56374AFC