MC145423DW [FREESCALE]
Universal Digital Loop Transceiver (UDLT-3); 通用数字环路收发器（ UDLT - 3 ）
| 型号： | MC145423DW |
| 厂家： | 
Freescale |
| 描述： | Universal Digital Loop Transceiver (UDLT-3) |
| 文件： | 总30页 (文件大小：797K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Freescale Semiconductor, Inc.
MC145423
Errata
Universal Digital Loop Transceiver (UDLT-3)
Pin Selectable Master/Slave
Limited Distance Modem
This errata applies only to the following:
• Preproduction silicon marked “XCSAMPLE”.
• When setup to operate in UDLT1 mode triangle wave output.
Do to differences in device geometries and process, the LO1 and LO2 output impedance of the MC145423 is
higher during non-burst time than the MC145422 and MC145426 devices it replaces. To compensate for this
difference, the line interface requires a slight modification to optimize transmission performance.
The following partial schematic highlights these differences by placing the modifications inside dashed boxes.
These changes are:
• R19 changes from 110 Ω to 75 Ω.
• R21 changes from 110 Ω to 75 Ω.
• R23 is an added component with a value of 1400 Ω.
For all other device configurations, the original interface as found in the datasheet (page 25, BASIC DIGITAL
TELSET) can be used.
V
DD
75 Ω D1
LO1
R19
D2
1400 Ω
R23
V
DD
75 Ω D3
110 Ω
See Note
LO2
LI
R22
D4
R21
To
Twisted
Pair
To
Battery
1 µF
V
DD
See Note
V
DD
V
REF
NOTE: Battery feed limiting resistors;
value up to user discretion.
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Order Number: MC145423/D
Rev. 0, 8/24/00
MC145423
Product Preview
Universal Digital Loop
Transceiver (UDLT-3)
Pin Selectable Master/Slave
Limited Distance Modem
DW SUFFIX
SOIC
CASE 751F
The MC145423 is a CMOS integrated circuit designed to be one
of the major building blocks in digital subscriber voice/data
telephone systems and remote data acquisition and control systems.
The UDLT-3 incorporates into one device, all the functionality of
the MC145421 (ISDN UDLT-2 master), MC145425 (ISDN UDLT-2
slave), MC145422 (UDLT-1 master), and MC145426 (UDLT-1
slave).
DT SUFFIX
TSSOP
CASE 1168
ORDERING INFORMATION
Since these modes/functions are pin selectable, the MC145423
can be used in telephone switch line cards, as well as remote digital
telsets or data terminals.
MC145423DW SOIC Package
MC145423DT
TSSOP Package
• V
= 4.5 V to 5.5 V
DD
• 28-Pin SOIC and TSSOP Packages
• Protocol Independent
• Pin Controlled Power-Down
• LI Sensitivity Control in Master Mode
• 2.048 MHz Output in Slave Mode
UDLT-2 Features
• Synchronous Full Duplex 160 kbps Voice and Data
Communications in a 2B+2D Format for ISDN Compatibility
• Provides CCITT Basic Access Data Transfer Rate (2B+D) for
ISDNs on a Single Twisted Pair Up to 1 km on 26 AWG or
Larger Cable
UDLT-1 Features
• Pin Controlled Loopback
• Automatic Power-Up/Down (Slave)
• Full Duplex Synchronous 64 kbps Voice/Data Channel and Two
8 kbps Signaling Data Channels Over One 26 AWG Wire Pair Up
to 2 km
Freescale Semiconductor, Inc.
MC145423
PIN ASSIGNMENT
V
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
DD
MASTER/SLAVE
SS
V
2
ref
LI
3
LO1
LB
4
LO2
VD
5
Rx
SDI1
6
RE2/BCLK
RE1/CLKOUT
LI SENS/2.048 MHz
SDI2
7
FRAME 10/20
SDCLK/8kHz
SDO1
8
9
TDC-RDC/XTAL
out
CCI/XTAL
10
11
12
13
14
in
SDO2
MSI/TONE
EN1-TE1
SE/(Mu/A)
PD
EN2-TE2/SIE/B1B2
Tx
MOD TRI/SQ
28-PIN SOIC/TSSOP PACKAGES
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Freescale Semiconductor, Inc.
MC145423
BLOCK DIAGRAM
SDCLK/8kHz
LO1
LO2
B1
B2
D1 D2
T RO
A
D U L
SDI2
SDI1
D2 BUFFER
D1 BUFFER
O
M
SE
LATCH
REGISTER
LOGIC
RE2/
BCLK
B2 BUFFER
B1 BUFFER
Rx
CCI/XTAL
In
(TDC-RDC)/
RE1/
CLKOUT
OSC
XTAL
out
CLKOUT
BCLK
SE/
(Mu/A)
Mu/A
LB
SE
LATCH
MSI/TONE
MOD TRI/SQ
FRAME 10/20
EN2-TE2
EN1-TE1
SEQUENCE
AND
CONTROL
PD
SE
LATCH
MASTER/
SLAVE
SE
LATCH
LI SENS/
2.048 MHz
TDC/RDC
VD
CONTROL
VD
LI
SDO2
SDO1
D2 BUFFER
D1 BUFFER
D2
D1
REGISTER
LOGIC
B2
B1
B2 BUFFER
B1 BUFFER
Tx
V
ref
EN2-TE2/
SIE
EN1-TE1
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Freescale Semiconductor, Inc.
MC145423
ABSOLUTE MAXIMUM RATINGS (Voltage Referenced to V
)
SS
This device contains circuitry to protect
the inputs against damage due to high static
voltages or electric fields; however, it is
advised that normal precautions be taken
to avoid applications of any voltage higher
than maximum rated voltages to this high-
impedance circuit. For proper operation, it
Rating
DC Supply Voltage
Voltage, Any Pin to V
Symbol
Value
Unit
V
– V
–0.5 to 6
V
V
DD
SS
V
I
–0.5 to V + 0.5
DD
SS
DC Current, Any Pin (Excluding
, V
±10
mA
V
)
DD SS
Operating Temperature
Storage Temperature
T
–40 to 85
°C
°C
is recommended that V and V
be
A
in out
constrained to the range V
≤ (V or V
)
SS
in out
T
–85 to 150
stg
≤ V . Reliability of operation is enhanced
DD
if unused inputs are tied to an appropriate
logic level (e.g., either V
or V ).
SS
DD
RECOMMENDED OPERATING CONDITIONS (T = –40° to 85°C)
A
Parameter
Pins
Min
Typ
—
Max
5.5
80
Unit
V
DC Supply Voltage
V
V
V
4.5
—
DD
DD
DD
Power Dissipation (PD = V
Power Dissipation (PD = V
Frame Rate
)
V
V
= 5 V
= 5 V
—
mW
mW
kHz
MHz
DD
DD
)
—
—
80
SS
DD
MSI
CCI
7.9
8.0
8.1
CCI CLK Frequency (MSI = 8 kHz)
UDLT-1 (CCI = 256 x MSI)
UDLT-2
—
—
2.048
8.192
—
8.29
Frame Rate Slip*
—
—
0.25
%
Data Clock Rate (Master Mode)
TDC-RDC
LO1, LO2
kHz
UDLT-1
UDLT-2
64
128
—
—
4100
4100
SDCLK (UDLT-2 Only)
16
—
4100
kHz
kHz
Modulation Baud Rate
UDLT-1
—
—
—
—
256
512
UDLT-2
* The slave’s crystal frequency divided by 512 (UDLT-1) or 1024 (UDLT-2), must equal the master’s MSI frequency ±0.25% for optimum
operation.
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Freescale Semiconductor, Inc.
MC145423
DIGITAL CHARACTERISTICS (V
= 5 V ±10%, T = –40° to 85°C, Unless Otherwise Stated)
A
DD
Parameter
Min
x 0.7
Max
Unit
Input High Level
V
—
V
DD
Input Low Level
—
—
V
x 0.3
V
DD
Input Current (Digital Pins)
Input Current LI
±1.0
±100
7.5
µA
µA
pF
mA
—
Input Capacitance
—
Output High Current (Excluding Tx and PD)
Output Current Low (Excluding Tx and PD)
V
V
= V
– 0.5 V
= 0.4V
–1.6
—
OH
DD
V
—
OL
1.6
mA
mA
Tx Output High Current
V
= V
= 2.5 V
– 0.5 V
–3.4
–2.5
—
—
OH
OH
DD
Tx Output Low Current
V
V
= 0.4 V
= 0.8 V
2.5
3.5
—
—
mA
µA
µA
OL
OL
PD Output High Current — Slave Mode*
PD Output Low Current — Slave Mode*
V
= 2.5 V
– 0.5 V
DD
–90
–10
—
—
OH
= V
V
OH
OH
V
OL
V
OL
= 0.8 V
= 0.4 V
100
60
—
—
Tx, SDO1, SDO2, and VD Three-State Current
XTAL Output High Current
—
±10.0
—
µA
µA
µA
V
= V
– 0.5 V
= 0.4 V
–450
450
DD
XTAL Output Low Current
V
—
OL
* To overdrive PD from a low level to 3.5 V, or a high level to 1.5 V requires a minimum of ±800 µA drive capability.
ANALOG CHARACTERISTICS (V
= 5 V ±10%, T = –40° to 85°C)
A
DD
Parameter
Modulation Differential Amplitude (RL = 440 Ω)
Modulation Differential Offset
Min
4.5
0
Max
6.0
40
Unit
Vp-p
mV
LO1 to LO2
V
Voltage, Typically 9/20 x (V
– V
)
2.0
–22
0.05
50
2.5
–18
2.5
300
V
ref
DD SS
PCM Tone Level
dBm
Vpeak
kΩ
Demodulator Input Amplitude*
Demodulator Input Impedance (LI to V
)
ref
* The input level into the demodulator to reliably demodulate incoming bursts. Input referenced to V
.
ref
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Freescale Semiconductor, Inc.
MC145423
MASTER SWITCHING CHARACTERISTICS (V
= 5 V ±10%, T = –40° to 85°C, C = 50 pF)
DD
A
L
Figure
No.
Parameter
Input Rise Time: All Digital Inputs
Input Fall Time: All Digital Inputs
Pulse Width:
TDC, RDC, RE1, RE2, MSI, SDCLK (UDLT-2)
CCI Duty Cycle
Propagation Delay:
Symbol
Min
Max
2
Unit
µs
t
—
—
r
t
f
2
µs
t
ns
p
90
45
—
t
55
%
w2(H,L)
t
t
,
ns
PLH
MSI to SDO1, SDO2, VD (PD = V
)
—
—
50
50
DD
TDC to Tx
PHL
MSI, TE1, TE2, RE1, RE2 to TDC-RDC Setup Time
TDC-RDC to MSI, TE1, TE2, RE1, RE2, Hold Time
Rx to TDC-RDC Setup Time
t
20
50
30
30
30
30
—
—
—
—
—
—
—
50
ns
ns
ns
ns
ns
ns
ns
su3
t
h5
t
su5
Rx to TDC-RDC Hold Time
t
h1
SDI1, SDI2 to MSI Setup Time
t
su2
SDI1, SDI2 to MSI Hold Time
t
h2
MSI Rising Edge to First SDCLK Falling Edge
(UDLT-2 Only)
t
P1LH
TE Rising Edge to First Tx Data Bit Valid
t
t
—
—
—
—
50
50
ns
ns
ns
ns
su6
TDC-RDC Rising Edge to Tx Data Bits 2 – 8 Valid
TE1,TE2 Falling Edge to Tx High Impedance
su7
t
70
dly
SDCLK Rising Edge to SDO1, SDO2 Bit Valid
(UDLT-2 Only)
t
135
su8
SDI1, SDI2 Data Setup (Data Valid Before SDCLK
Falling Edge) (UDLT-2 Only)
t
50
20
—
—
ns
ns
su9
SDI1, SDI2 Data Hold (Data Valid After SDCLK
Falling Edge) (UDLT-2 Only)
t
h3
PD, LB Setup (PD, LB Valid Before MSI Rising Edge)
PD, LB Hold (PD, LB Valid After MSI Rising Edge)
t
50
20
—
—
ns
ns
su10
t
h4
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Freescale Semiconductor, Inc.
MC145423
SLAVE SWITCHING CHARACTERISTICS (V
= 5 V ±10%, T = –40° to 85°C, C = 50 pF)
DD
A
L
Figure
No.
Parameter
Input Rise Time: All Digital Inputs
Input Fall Time: All Digital Inputs
Clock Output Pulse Width: BCLK
Crystal Frequency
Symbol
Min
—
Max
2
Unit
µs
t
r
t
f
—
2
µs
t
3.66
4.086
4.15
4.1
µs
w(H,L)
f
MHz
ns
x1
Propagation Delay Times:
EN1, EN2, TE1 Rising to BCLK (TONE = V
EN1, EN2, TE1 Rising to BCLK (TONE = V
)
)
t
t
t
t
t
t
t
t
–50
300
—
175
400
20
20
50
400
50
50
DD
SS
p1
p1
p2
p3
p4
p4
p5
p6
BCLK to EN1, EN2, TE1 Falling
RE1 Rising to BCLK (UDLT-1)
—
RE1 Falling to BCLK (TONE = V ) (UDLT-1)
–50
300
—
DD
RE1 Falling to BCLK (TONE = V ) (UDLT-1)
SS
BCLK to Tx
TE1,TE2 to SDO1, SDO2
—
Rx to BCLK Setup Time
t
30
30
30
30
—
—
—
31
31
—
10
—
—
ns
ns
ns
ns
ns
ns
ns
µs
µs
ns
ns
su5
Rx to BCLK Hold Time
t
h1
SDI1, SDI2 to TE Setup Time
t
—
su6
SDI1, SDI2 to TE Hold Time
t
—
h2
EN1, EN2 Rising Edge to DCLK Rising Edge (UDLT-2)
EN1, EN2 Rising Edge to First Tx Data Bit Valid
BCLK Rising Edge to Tx Data Bits 2 – 8 Valid
DCLK Pulse Width High (UDLT-2)
t
±30
30
PHL
t
dly1
t
–40
31.5
31.5
30
su7
t
w(H)
DCLK Pulse Width Low (UDLT-2)
t
w(L)
DCLK Rising Edge to SDO1, SDO2 (UDLT-2)
t
dly2
SDI1, SDI2 Setup (SDI1, SDI2 Valid Before DCLK
Falling Edge) (UDLT-2)
t
—
su9
SDI1, SDI2 Hold (SDI1, SDI2 Valid After DCLK
Falling Edge) (UDLT-2)
t
—
—
30
30
ns
ns
h3
EN1, TE1 Rising Edge to VD Valid
t
dly3
SE PIN TIMING
Figure
No.
Parameter
Symbol
Min
Max
Unit
LB, PD Hold
(LB, PD Valid After SE Falling Edge)
t
10
—
ns
h
SDO1, SDO2, VD High Impedance After SE Falling Edge
SDO1, SDO2, VD Valid After SE Rising Edge
t
—
30
25
40
—
—
ns
ns
ns
dly1
t
dly2
LB, PD Setup
(LB, PD Valid Before SE Rising Edge)
t
su
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MC145423
8
1
p
t
7
1
1
1
t
1
Figure 1. UDLT-1 Slave Timing Nonsynchronous
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Freescale Semiconductor, Inc.
MC145423
p
t
E
C
’
Figure 2. UDLT-1 Slave Timing Synchronous
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MC145423
1
1
1
1
8
8
2
2
7
2
2
)
(
t
2
2
2
2
2
)
2
Figure 3. UDLT-2 Slave Timing
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MC145423
h
t
D
A
E
’
O
N
A
E
8
MI
1
I
H
1
Figure 4. UDLT-1 Master Timing
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MC145423
E
C
N
O
2
t
8
1
1
2
2
y
Figure 5. UDLT-2 Master Timing
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MC145423
SE
LB, PD
t
t
su
h
PREVIOUS STATE
INTERNALLY LATCHED
SDO1, SDO2, VD
t
t
dly2
dly1
Figure 6. SE Pin Timing
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MC145423
SOIC PACKAGE PINOUT COMPARISON
UDLT-3 PINOUT VERSUS MC145421DW/22DW/25DW/26DW
(UDLT-1/UDLT-2 MASTER/SLAVE) PINOUT
UDLT-3
MC145423
UDLT-1 Master
MC145422
UDLT-1 Slave
MC145426
UDLT-2 Master
MC145421
UDLT-2 Slave
MC145425
Pin
No.
Pin
Name
Pin
No.
Pin
Name
Pin
No.
Pin
Name
Pin
No.
Pin
Name
Pin
No.
Pin
Name
1
2
V
1
V
1
2
3
5
6
7
9
V
1
V
1
2
3
4
5
6
7
V
SS
SS
SS
SS
SS
V
2
V
V
2
V
V
ref
ref
ref
ref
ref
3
LI
LB
3
LI
LI
3
LI
LI
4
5
LB
LB
4
LB
LB
5
VD
6
VD
SI1
SI2
VD
SI1
SI2
5
VD
D1I
D2I
VD
DI1
DI2
6
SDI1
7
6
7
SDI2
9
7
8
FRAME 10/20
SDCLK/8kHz
SDO1
Logic 0
Logic 0
SDCLK
SO1
Logic 1
Logic 1
9
High Impedance
SO1
8
DCLK
D1O
D2O
SE
8
DCLK
D1O
10
11
12
13
14
15
16
8
8
9
9
SDO2
10
11
12
SO2
SE
10
11
12
SO2
Mu/A
PD
10
11
12
10
11
12
D2O
SE/(Mu/A)
PD
(Mu/A)
PD
PD
PD
MOD TRI/SQ
Tx
Logic 0
Logic 0
Tx
B1B2
Logic 0
TE1
(Tone) TE
(XTAL ) X1
Logic 1
Logic 1
16
14
Tx
15
13
14
Tx
13
14
Tx
EN2-TE2/SIE/
B1B2
SIE
TE2
EN2
17
18
19
20
EN1-TE1
15
13
17
18
TE1
MSI
14
13
16
17
15
16
17
18
TE1
MSI
15
16
17
18
EN1
MSI/TONE
TONE
CCI/XTAL
CCI
CCI
(XTAL ) CCI
in
in
TDC-RDC/
XTAL
in
(XTAL ) X2
TDC/RDC
TDC/RDC
(XTAL ) XTL
out
out
out
21
LI SENS/
2.048 MHz
Logic 0
LI SENS
2.048 MHz Out
Logic 0
LI SENS
2.048 MHz Out
22
23
24
25
26
27
RE1/CLKOUT
RE2/BCLK
Rx
20
RE1
20
18
19
22
23
RE1
(BCLK) CLK
Rx
19
20
21
22
23
RE1
19
20
21
22
23
CLKOUT
BCLK
Rx
High Impedance
RE2
Rx
19
Rx
LO2
22
23
LO2
LO1
LO2
LO2
LO1
LO2
LO1
LO1
LO1
MASTER/
SLAVE
Logic 0
Logic 1
Logic 0
Logic 1
28
V
24
V
24
V
24
V
24
V
DD
DD
DD
DD
DD
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MC145423
MC145423 UDLT-3 PIN STATES FOR UDLT-1 SLAVE MODE
UDLT-1 Slave Mode Powered-Down
TONE = 0, Off TONE = 1, On
No Valid Valid No Valid Valid
Burst Rec’d Burst Rec’d Burst Rec’d Burst Rec’d
Power Supply Power Supply Power Supply Power Supply Power Supply Power Supply
UDLT-1 Slave Mode
Powered-Up
MC145423
Pin
No.
Pin
Name
In/out
Normal
LB Low
1
V
Power
SS
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
2
V
ref
Analog
Ref
AGND
AGND
AGND
AGND
AGND
AGND
V
/2
V
/2
V
/2
V
/2
V
/2
V
/2
DD
DD
DD
DD
DD
DD
3
4
5
6
LI
LB
Input
Input
Analog In
1
Analog In
0
Analog In
Don’t Care
VD = 0
Analog In
Don’t Care
VD = 1
Analog In
Don’t Care
VD = 0
Analog In
Don’t Care
VD = 1
VD
Output
Input
Digital Out
Digital Out
SDI1
8 kbps
Data In
8 kbps
Data In
Don’t Care
Don’t Care
Don’t Care
Don’t Care
7
8
SDI2
Input
Input
8 kbps
Data In
8 kbps
Data In
Don’t Care
0
Don’t Care
0
Don’t Care
0
Don’t Care
0
FRAME
10/20
0
0
9
SDCLK/
8kHz
Output
Output
Output
Input
SDCLK/8kHz SDCLK/8kHz
High-Z,
Not Used
High-Z,
Not Used
High-Z,
Not Used
High-Z,
Not Used
10
11
SDO1
8 kbps
8 kbps
Data Not
Changed
8 kbps
Data Out
Data Not
Changed
8 kbps
Data Out
Data Out
Data Out
SDO2
8 kbps
8 kbps
Data Not
Changed
8 kbps
Data Out
Data Not
Changed
8 kbps
Data Out
Data Out
Data Out
12 SE/(Mu/A)
1= Mu,
0 = A
1= Mu,
0 = A
1= Mu,
0 = A
1= Mu,
0 = A
1= Mu,
0 = A
1= Mu,
0 = A
13
14
PD
I/O
1
0
1
0
0
0
0
0
0
0
0
0
MOD
Input
TRI/SQ
15
16
Tx
Output
Input
64 kbps
Data Out
64 kbps
Data Out
High
Impedance
64 kbps
Data Out
64 kbps
PCM Tone
64 kbps
PCM Tone
EN2-TE2/
SIE/B1B2
1/0 B1B2
1/0 B1B2
1/0 B1B2
1/0 B1B2
1/0 B1B2
1/0 B1B2
17
18
EN1-TE1
Output
Input
EN1 = 8 kHz EN1 = 8 kHz
1/0 TONE 1/0 TONE
EN1 = 0
EN1 = 8 kHz EN1 = 8 kHz EN1 = 8 kHz
TONE = 0 TONE = 1 TONE = 1
MSI/
TONE = 0
TONE
19
CCI/
XTAL
Input
XTAL
XTAL
XTAL
XTAL
in
XTAL
in
XTAL
in
in
4.096 MHz
in
4.096 MHz
in
4.096 MHz
4.096 MHz
4.096 MHz
4.096 MHz
in
20 TDC-RDC/ Output
XTAL
XTAL
out
4.096 MHz
XTAL
out
4.096 MHz
XTAL
out
4.096 MHz
XTAL
XTAL
XTAL
out
out
out
4.096 MHz
4.096 MHz
4.096 MHz
out
21
LI SENS/
Output
2.048 MHz
2.048 MHz
2.048 MHz
2.048 MHz
2.048 MHz
2.048 MHz
2.048 MHz
22
RE1/
Output
RE1 = 8 kHz RE1 = 8 kHz
RE1 = 1
RE1 = 8 kHz RE1 = 8 kHz RE1 = 8 kHz
CLKOUT
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MC145423
MC145423 UDLT-3 PIN STATES FOR UDLT-1 SLAVE MODE (continued)
UDLT-1 Slave Mode Powered-Down
TONE = 0, Off TONE = 1, On
No Valid Valid No Valid Valid
Burst Rec’d Burst Rec’d Burst Rec’d Burst Rec’d
UDLT-1 Slave Mode
Powered-Up
MC145423
Pin
No.
Pin
Name
In/out
Normal
LB Low
23
24
25
26
27
28
RE2/
BCLK
Output
BCLK =
128 kHz
BCLK = 0
BCLK =
128 kHz
BCLK =
128 kHz
BCLK =
128 kHz
BCLK =
128 kHz
Rx
Input
Output
Output
Input
64 kbps
Data In
Don’t Care
Don’t Care
LO2 = LO1
LO1 = LO2
1
Don’t Care
LO2 = LO1
LO1 = LO2
1
Don’t Care
LO2 = LO1
LO1 = LO2
1
Don’t Care
LO2 = LO1
LO1 = LO2
1
LO2
LO1
Modulator
Out
Modulator
Out
Modulator
Out
Modulator
Out
MASTER/
SLAVE
1
1
V
Power
+V
+V
+V
+V
+V
+V
DD
MC145423 UDLT-3 PIN STATES FOR UDLT-1 MASTER MODE
UDLT-1 Master Mode
UDLT-1 Master Mode
Powered-Down
MC145423
Powered-Up
Pin
No.
Pin
Name
In/out
Normal
LB Low
SE Low
Normal
SE Low
1
V
Power
Power Supply
Gnd
Power Supply
Gnd
Power Supply
Gnd
Power Supply
Gnd
Power Supply
Gnd
SS
2
V
ref
Analog
Ref
AGND V /2
DD
AGND V /2
DD
AGND V /2
DD
AGND V /2
DD
AGND V /2
DD
3
4
LI
LB
Input
Input
Output
Input
Input
Input
Analog In
1
Don’t Care
0
Analog In
State Latched
High Impedance
State Latched
State Latched
0
Analog In
Don’t Care
Digital out
8 kbps Data In
8 kbps Data In
0
Analog In
Don’t Care
High Impedance
State Latched
State Latched
0
5
VD
Digital out
8 kbps Data In
8 kbps Data In
0
Digital out
8 kbps Data In
8 kbps Data In
0
6
SDI1
7
SDI2
8
FRAME 10/20
SDCLK
SDO1
SDO2
SE/(Mu/A)
PD
9
Don’t Care High Impedance High Impedance High Impedance High Impedance High Impedance
10
11
12
13
14
Output
Output
Input
8 kbps Data Out 8 kbps Data Out High Impedance 8 kbps Data Out High Impedance
8 kbps Data Out 8 kbps Data Out High Impedance 8 kbps Data Out High Impedance
1
1
0
1
1
0
0
1
0
0
0
Input
State Latched
0
State Latched
0
MOD
Input
TRI/SQ
15
16
Tx
Output
Input
64 kbps
Data Out
64 kbps
Data Out
64 kbps
Data Out
64 kbps
Data Out
64 kbps
Data Out
EN2-TE2/
SIE/B1B2
SIE Digital In
SIE Digital In
SIE Digital In
SIE Digital In
SIE Digital In
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MC145423
MC145423 UDLT-3 PIN STATES FOR UDLT-1 MASTER MODE (continued)
UDLT-1 Master Mode
UDLT-1 Master Mode
Powered-Down
MC145423
Powered-Up
Pin
No.
Pin
Name
In/out
Input
Input
Input
Normal
TE1 8 kHz
MSI 8 kHz
LB Low
TE1 8 kHz
MSI 8 kHz
SE Low
TE1 8 kHz
MSI 8 kHz
Normal
SE Low
TE1 8 kHz
MSI 8 kHz
17
18
19
EN1-TE1
MSI/TONE
CCI/
TE1 8 kHs
MSI 8 kHz
CCI 2.048 MHz CCI 2.048 MHz CCI 2.048 MHz CCI 2.048 MHz CCI 2.048 MHz
XTAL
in
TDC-RDC/
XTAL
20
21
22
23
Input
Input
Input
TDC-RDC
Data Clk
TDC-RDC
Data Clk
TDC-RDC
Data Clk
TDC-RDC
Data Clk
TDC-RDC
Data Clk
out
LI SENS/
2.048 MHz
Digital In
LI Sensitivity
Digital In
LI Sensitivity
Digital In
LI Sensitivity
Digital In
LI Sensitivity
Digital In
LI Sensitivity
RE1/
CLKOUT
RE1 8 kHz
RE1 8 kHz
RE1 8 kHz
RE1 8 kHz
RE1 8 kHz
RE2/
Don’t Care High Impedance High Impedance High Impedance High Impedance High Impedance
BCLK
24
25
26
27
Rx
Input
Output
Output
Input
64 kbps Data In 64 kbps Data In 64 kbps Data In
Don’t Care
LO2 = LO1
LO1 = LO2
0
Don’t Care
LO2 = LO1
LO1 = LO2
0
LO2
LO1
Modulator Out
Modulator Out
0
LO2 = LO1
LO1 = LO2
0
No Effect
No Effect
0
MASTER/
SLAVE
28
V
Power
+V
+V
+V
+V
+V
DD
MC145423 UDLT-3 PIN STATES FOR UDLT-2 SLAVE MODE
UDLT-2 Slave Mode
Powered-Down
UDLT-2 Slave Mode
MC145423
Powered-Up
TONE = 0, Off
No Valid Valid
Burst Rec’d Burst Rec’d Burst Rec’d Burst Rec’d
Power Supply Power Supply Power Supply Power Supply Power Supply Power Supply
TONE = 1, On
Pin
No.
Pin
Name
No Valid Valid
In/out
Normal
LB Low
1
V
Power
SS
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
2
V
Analog
Ref
AGND
AGND
AGND
AGND
AGND
AGND
ref
V
/2
V
/2
V
/2
V
/2
V
/2
V
/2
DD
DD
DD
DD
DD
DD
3
4
5
6
LI
LB
Input
Input
Analog In
1
Analog In
0
Analog In
Don’t Care
VD = 0
Analog In
Don’t Care
VD = 1
Analog In
Don’t Care
VD = 0
Analog In
Don’t Care
VD = 1
VD
Output
Input
Digital Out
Digital Out
SDI1
16 kbps
Data In
16 kbps
Data In
Don’t Care
Don’t Care
Don’t Care
Don’t Care
7
8
9
SDI2
Input
Input
16 kbps
Data In
16 kbps
Data In
Don’t Care
1
Don’t Care
1
Don’t Care
1
Don’t Care
1
FRAME
10/20
1
1
SDCLK
Output
16 kHz
16 kHz
16 kHz
16 kHz
16 kHz
16 kHz
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MC145423
MC145423 UDLT-3 PIN STATES FOR UDLT-2 SLAVE MODE (continued)
UDLT-2 Slave Mode
Powered-Down
UDLT-2 Slave Mode
Powered-Up
MC145423
TONE = 0, Off
TONE = 1, On
Pin
No.
Pin
Name
No Valid Valid
Burst Rec’d Burst Rec’d Burst Rec’d Burst Rec’d
No Valid Valid
In/out
Normal
LB Low
10
11
12
SDO1
SDO2
Output
16 kbps
Data Out
16 kbps
Data Out
Data Not
Changed
16 kbps
Data Out
Data Not
Changed
16 kbps
Data Out
Output
Input
16 kbps
Data Out
16 kbps
Data Out
Data Not
Changed
16 kbps
Data Out
Data Not
Changed
16 kbps
Data Out
SE/
1/0
1/0
1/0
1/0
1/0
1/0
(Mu/A)
Mu/A
Mu/A
Mu/A
Mu/A
Mu/A
Mu/A
13
14
PD
I/O
1
1
1
1
0
1
0
1
0
1
0
1
MOD
Input
TRI/SQ
15
16
Tx
Output
Output
128 kbps
Data Out*
128 kbps
Data Out*
High
Impedance
64 kbps
Data Out
500 Hz
Tone Out
500 Hz
Tone Out
EN2-TE2/
SIE/B1B2
EN2 8 kHz
EN2 8 kHz
EN2 = 0
EN2 = 0
EN2 8 kHz
EN2 8 kHz
17
18
EN1-TE1
Output
Input
EN1 8 kHz
1/0 Tone
EN1 8 kHz
1/0 Tone
EN1 = 0
EN1 = 0
EN1 8 kHz
1 No Tone
EN1 8 kHz
1 Tone
MSI/
0 No Tone
0 No Tone
TONE
19
CCI/
Input
XTAL
XTAL
XTAL
XTAL
XTAL
XTAL
XTAL
8.192 MHz
8.192 MHz
8.192 MHz
8.192 MHz
8.192 MHz
8.192 MHz
in
20 TDC-RDC/ Output
XTAL
XTAL
8.192 MHz
XTAL
8.192 MHz
XTAL
8.192 MHz
XTAL
8.192 MHz
XTAL
8.192 MHz
XTAL
8.192 MHz
out
21
22
23
24
25
26
27
28
LI SENS/
2.048 MHz
Output
Output
Output
Input
2.048 MHz
RE1 8 kHz
2.048 MHz
RE1 8 kHz
BCLK = 0
Don’t Care
2.048 MHz
RE1 0
2.048 MHz
RE1 0
2.048 MHz
RE1 8 kHz
2.048 MHz
RE1 8 kHz
RE1/
CLKOUT
RE2/
BCLK
BCLK
128 kHz
BCLK
128 kHz
BCLK
128 kHz
BCLK
128 kHz
BCLK
128 kHz
Rx
128 kbps
Data In
Don’t Care
LO2 = LO1
LO2 = LO1
1
Don’t Care
LO2 = LO1
LO2 = LO1
1
128 kbps
Data In
128 kbps
Data In
LO2
LO1
Output
Output
Input
Modulator
Out
Modulator
Out
LO2 = LO1
LO2 = LO1
Modulator
Out
Modulator
Out
LO1 = LO2
LO1 = LO2
MASTER/
SLAVE
1
1
1
1
V
DD
Power
+V
+V
+V
+V
+V
+V
* Tx is high impedance when TE1 and TE2 are both low, simultaneously.
Tx is undefined when TE1 and TE2 are both high, simultaneously.
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MC145423
MC145423 UDLT-3 PIN STATES FOR UDLT-2 MASTER MODE
MC145423
UDLT-2 Master Powered-Up
UDLT-2 Master Powered-Down
Pin
No.
Pin
Name
In/out
Normal
LB Low
SE Low
Normal
SE Low
1
V
Power
Power Supply
Gnd
Power Supply
Gnd
Power Supply
Gnd
Power Supply
Gnd
Power Supply
Gnd
SS
2
3
4
5
6
7
8
V
Analog Ref AGND V /2
DD
AGND V /2
DD
AGND V /2
DD
AGND V /2
DD
AGND V /2
DD
ref
LI
Input
Input
Output
Input
Input
Input
Analog In
1
Don’t Care
0
Analog In
Analog In
Don’t Care
Digital Out
Analog In
Don’t Care
LB
State Latched
High Impedance
VD
Digital Out
Digital Out
High Impedance
SDI1
SDI2
16 kbps Data In 16 kbps Data In State Latched 16 kbps Data In State Latched
16 kbps Data In 16 kbps Data In State Latched 16 kbps Data In State Latched
FRAME 10/
20
1
1
1
1
1
9
SDCLK
SDO1
Input
16 kHz
16 kHz
16 kHz
16 kHz
16 kHz
10
Output
16 kbps Data
Out
16 kbps Data High Impedance 16 kbps Data High Impedance
Out Out
11
SDO2
Output
16 kbps Data
Out
16 kbps Data High Impedance 16 kbps Data High Impedance
Out
Out
12
13
SE/(Mu/A)
PD
Input
Input
1
1
1
1
0
1
0
1
State Latched
1
0
State Latched
1
14 MOD TRI/SQ
Input
1
1
15
Tx
Output
128 kbps*
Data Out
128 kbps*
Data Out
128 kbps*
Data Out
128 kbps*
Data Out
128 kbps*
Data Out
16
EN2-TE2/
SIE/B1B2
Input
TE2 8 kHz
TE2 8 kHz
TE2 8 kHz
TE2 8 kHz
TE2 8 kHz
17
18
19
EN1-TE1
Input
Input
Input
TE1 8 kHz
8 kHz
TE1 8 kHz
8 kHz
TE1 8 kHz
8 kHz
TE1 8 kHz
8 kHz
TE1 8 kHz
8 kHz
MSI/TONE
CCI/XTAL
CCI
4.096 MHz
CCI
4.096 MHz
CCI
4.096 MHz
CCI
4.096 MHz
CCI
4.096 MHz
in
20
21
22
TDC-RDC/
XTAL
Input
Input
Input
TDC-RDC
Data Clk
TDC-RDC
Data Clk
TDC-RDC
Data Clk
TDC-RDC
Data Clk
TDC-RDC
Data Clk
out
LI SENS/
2.048 MHz
Digital In
Sensitivity
Digital In
Sensitivity
Digital In
Sensitivity
Digital In
Sensitivity
Digital In
Sensitivity
RE1/
RE1 8 kHz
RE1 8 kHz
RE1 8 kHz
RE1 8 kHz
RE1 8 kHz
CLKOUT
23
24
25
26
27
RE2/BCLK
Rx
Input
Input
RE2 8 kHz
RE2 8 kHz
RE2 8 kHz
RE2 8 kHz
Don’t Care
LO2 = LO1
LO1 = LO2
0
RE2 8 kHz
Don’t Care
LO2 = LO1
LO1 = LO2
0
128 kbps Data In 128 kbps Data In 128 kbps Data In
LO2
Output
Output
Input
Modulator Out
Modulator Out
0
LO2 = LO1
LO1 = LO2
0
No Effect
No Effect
0
LO1
MASTER/
SLAVE
28
V
Power
+V
+V
+V
+V
+V
DD
* Tx is high impedance when TE1 and TE2 are both low, simultaneously.
Tx is undefined when TE1 and TE2 are both high, simultaneously.
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MC145423
PIN DESCRIPTIONS
synchronization and the absence of detected bit errors.
VD is a CMOS output and is high impedance when SE
is low.
V
SS
Negative Supply (Pin 1)
Master Mode: VD changes state on the rising
edge of MSI, when PD is high. When PD is low, VD
changes state at the end of demodulation of a
transmission burst and does not change again until
three MSI rising edges have occurred, at which time it
goes low, or until the next demodulation of a burst.
Slave Mode: If no transmissions from the master
have been received within the last 250 µs, as
determined by an internal oscillator, VD will go low.
This is the most negative power pin, and should be
tied to system ground (0 V).
V
ref
Voltage Reference Output (Pin 2)
This is the output from the internal reference supply
(mid-supply) and should be bypassed to both V and
V
SS
with 0.1 µF capacitors. This pin usually serves
DD
as an analog ground reference for transformer
coupling of the device’s incoming bursts from the line.
No external load should be placed on this pin.
SDI1 and SDI2
D Channel Signaling Data Bit Inputs 1 and 2
(Pins 6 and 7)
LI
Master Mode (UDLT-1): These inputs are the
8 kbps serial data inputs in UDLT-1 mode. Data on
these pins is loaded on the rising edge of MSI for
transmission to the slave. The state of these pins is
latched if SE is held low.
Line Input (Pin 3)
This pin is the input to the demodulator for the
incoming bursts. This input has an internal 240 kΩ
resistor tied to the V pin, so an external capacitor or
line transformer may be used to couple the input signal
to the device with no dc offset.
ref
Slave Mode (UDLT-1): These inputs are the
8 kbps serial data inputs in UDLT-1 mode. Data on
these pins is loaded on the rising edge of TE1 for
transmission to the master. If no transmissions from
the master are being received and PD is high, data on
these pins will be loaded into the part on an internal
signal. Therefore, data on these pins should be steady
until synchronous communication with the master has
been established, as indicated by the high on VD.
Master Mode (UDLT-2): These inputs are the
16 kbps serial data inputs in UDLT-2 mode. Two bits
should be clocked into each of these inputs between
the rising edges of the MSI frame reference clock. The
first bit of each D channel is clocked into an
intermediate buffer on the first falling edge of the
SDCLK following the rising edge of MSI. The second
bit of each D channel is clocked in on the next
negative transition of the SDCLK. If further SDCLK
negative edges occur, new information is serially
clocked into the buffer replacing the previous data,
one bit at a time. Buffered D channel bits are burst to
the slave on the next rising edge of the MSI frame
reference clock. The state of these pins is latched if SE
is held low.
LB
Loopback Low Input (Pin 4)
Master Mode: A low on this pin ties the internal
modulator output to the internal demodulator input,
which loops the entire burst for testing purposes.
During the loopback operation, the LI input is ignored,
and the LO1 and LO2 outputs are driven to equal
voltages. The state of the LB pin is internally latched if
the SE pin is held low. This feature is only active when
the PD input is high.
Slave Mode: When this pin is low and PD is high,
the incoming B channels from the master are burst
back to the master, instead of the Rx B channel input
data. The SDI1 and SDI2 functions operate normally
in this mode, and the BCLK (pin 23) is held low.
Additionally, for both the UDLT-1 and UDLT-2 mode,
when the TONE (pin 18) and loopback functions are
active simultaneously, the loopback function overrides
the TONE function.
VD
Slave Mode (UDLT-2): These inputs are the
16 kbps serial data inputs in UDLT-2 mode. The D
channel data bits are clocked in serially on the
negative edge of the 16 kbps SDCLK output pin.
Valid Data Output (Pin 5)
A high level on this pin indicates that a valid line
transmission has been demodulated. A valid line
transmission burst is determined by proper
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MC145423
FRAME 10/20
(Pin 8)
tells the D channel data shift register to produce the
second D channel bit on the next rising edge of the
SDCLK. Further rising edges of the SDCLK
recirculate the D channel output buffer information.
Master Mode (UDLT-1): These outputs are
received signaling bits from the slave UDLT and
change state on the rising edge of MSI, if PD is high;
or at the end of demodulation, if PD is low.
Slave Mode (UDLT-2): These two pins are the
outputs for the 16 kbps D channels. These pins are
updated on the rising edges of the slave SDCLK
output pin.
The UDLT series of transceivers are designed to
operate using a ping-pong transmission scheme with
an 8 kHz burst rate. Each frame the master device
“pings” a burst of data to the slave, which responds
with a “pong” burst of data. This pin selects whether
this 8 kHz frame will have a 10-bit data burst for
UDLT-1 compatibility or a 20-bit data burst for
UDLT-2 compatibility.
A logic low (0 V) selects the UDLT-1 (MC145422/
MC145426) mode. This sets the device to operate with
one 64 kbps voice/data channel and two 8 kbps
Slave Mode (UDLT-1): These outputs are
received signaling bits from the master UDLT and
change state on the rising edge of TE1.
signaling channels. A logic high (V ) on this pin
DD
selects the UDLT-2 (MC145421/MC145425) mode.
This sets the device to operate with two 64 kbps
channels and two 16 kbps channels (2B+2D).
SE/(Mu/A)
Signaling Enable Input or Tone Format Input
(Pin 12)
SDCLK
D Channel Signaling Data Clock Input (Pin 9)
Master Mode (SE): A low on this pin causes the
state of LB, PD, SDI1, and SDI2 to be stored.
Additionally, output pins VD, SDO1, and SDO2 will
be high impedance. This allows the device to be
bussed with other UDLTs using a common control bus.
A high on this pin returns the device to normal
operation.
Slave Mode (Mu/A): This pin allows the user to
select the PCM code format for the pacifier tone. A
high on this pin selects Mu-Law. A low on this pin
selects A-Law. The state of this pin determines the
PCM code sequence for the 500 Hz square wave tone
generated when the TONE pin input is high.
Master Mode (UDLT-2): This is the transmit and
receive data clock input for both D channels. See
SDO1 and SDO2 pin descriptions for more
information.
Master Mode (UDLT-1): High impedance.
Slave Mode (UDLT-2): This is the transmit and
receive data clock output for both D channels. It starts
on demodulation of a burst from the master device.
This signal is rising-edge aligned with the EN1 and
BCLK signals. After the demodulation of a burst, the
SDCLK line completes two cycles and then remains
low until the next burst from the master is
demodulated. In this manner, synchronization with the
master is established and any clock slip between
master and slave is absorbed each frame.
PD
Power Down Low (Pin 13)
Master Mode: When this pin is held low, the
device powers down, except for the circuitry necessary
to demodulate an incoming burst and to output VD
and the B and D channel data bits. When this pin is
brought high, the device waits for three positive MSI
edges or until the end of an incoming transmission
from the slave and then begins transmitting every MSI
period to the slave UDLT on the next rising edge of
MSI.
Slave Mode: This is a bidirectional pin with a
weak output driver that can be externally overdriven.
When this pin is floating and a burst from the master is
demodulated, the weak output drivers will try to force
PD high. The drivers will try to force PD low, if
Slave Mode (UDLT-1): This pin outputs 8 kHz
equivalent to TE1.
SDO1 and SDO2
D Channel Signaling Data Outputs 1 and 2
(Pins 10 and 11)
Master Mode (UDLT-2): These serial outputs
provide the 16 kbps D channel signaling information
from the incoming burst. Two data bits should be
clocked out of each of these two outputs between the
rising edges of the MSI frame reference clock. The
rising edge of MSI produces the first bit of each
D channel on its respective pin. Circuitry then
searches for a negative D channel clock edge. This
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MC145423
250 µs have elapsed without a burst from the master
being successfully demodulated. This allows the slave
device to self power-up and power-down in demand
powered loop systems. When held low, the device
powers down and the only active circuitry, is that
which is necessary for the demodulation of data. When
held high, the device is powered up and transmits
normally in response to received bursts from the
master.
of the incoming word at the Rx pin will be transmitted
to the slave. The PCM word to the slave will have LSB
forced low in this mode. In this manner, signal bit 2 to/
from the slave UDLT is inserted into the PCM words
the master sends and receives from the backplane, for
routing through the PABX for simultaneous voice/data
communication. The state of this pin is internally
latched if the SE pin is brought and held low.
Slave Mode (UDLT-1): In this mode, this pin is
an input and selects the timeslot used for transferring
the receive data word. When this pin is low, the device
uses the RE1 pin timing the same as the MC145426
UDLT-1 slave. When this pin is a logic 1, the receive
word is latched in during the TE1 timeslot,
simultaneously with the transmit word transfer. The
RE1 pin timing is not affected by this selection.
Master Mode (EN2-TE2 UDLT-2): In this mode,
this pin functions as EN2-TE2. This pin, along with
TE1 pin-17 control the output of data for their
respective B-channel on the Tx output pin. When both
TE1 and TE2 are low, the Tx pin is high impedance.
The rising edge of the respective enable produces the
first bit of the selected B-channel data on the Tx pin.
Internal circuitry then scans for the next negative
transition of the TDC-RDC clock. Following this
event, the next seven bits of the selected B-channel
data are output on the next seven rising edges of the
TDC-RDC data clock. When TE1 and TE2 are high
simultaneously, data on the Tx pin is undefined. TE1
and TE2 should be approximately leading-edge
aligned with the TDC-RDC data clock. To keep the Tx
pin out of the high impedance state, these enable lines
should be high while the respective B channel data is
being output.
MOD TRI/SQ
Modulation Select (Pin 14)
A logic low (0 V) on this pin selects the MDPSK
modulation which has a slew controlled voltage output
for reduced EMI/RFI. This output looks like a triangle
waveform that is modulated with different angles for
the peaks. A logic high (V ) on this pin, selects
DD
square wave output for maximum power to the line.
Tx
Transmit Data Output (Pin 15)
Master Mode (UDLT-1): This pin is high
impedance when TE1 is low. When TE1 is high, this
pin presents new 8-bit B channel data on rising edges
of TDC-RDC.
Slave Mode (UDLT-1): B channel data is output
on this pin on the rising edge of BCLK, while TE1 is
high. This pin is high impedance when TE1 is low.
Master Mode (UDLT-2): This pin is high
impedance when both TE1 and TE2 are low. This pin
serves as an output for B channel information received
from the slave device. The B channel data is under
control of TE1 and TE2 and TDC-RDC.
Slave Mode (UDLT-2): This pin is an output for
the B channel data received from the master.
B channel 1 data is output on the first eight cycles of
the BCLK output when EN1 is high. B channel 2 data
is output on the next eight cycles of the BCLK, when
EN2 is high. B channel data bits are clocked out on the
rising edge of the BCLK output pin.
Slave Mode (EN2-TE2 UDLT-2): Functioning as
EN2-TE2, this pin is an output and serves as an 8 kHz
enable signal for the input and output of the B channel
2 data. While EN2 is high, B channel 2 data is clocked
out on the Tx pin on the eight rising edges of the
BCLK. During this same time, B channel 2 input data
is clocked in on the Rx pin, on the eight falling edges
of the BCLK.
EN2-TE2/SIE/B1B2
B Channel 2 Enable Output or
Signal Insert Enable (Pin 16)
EN1-TE1
B Channel 1 Enable Output (Pin 17)
Master Mode (SIE UDLT-1): In this mode, this
pin functions as SIE. When held high, this pin causes
signal bit 2, as received from the slave, to be inserted
into the LSB of the outgoing PCM word at the Tx pin.
The SDI2 pin will be ignored, and in its place, the LSB
This pin is the logical inverse of EN2-TE2, and
serves to control B channel 1 data. See the above pin
description for more information. EN1 serves as the
slave device’s 8 kHz frame reference signal. The VD
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pin is also updated on the rising edge of the EN1
signal.
desired. XTAL should be left open if an external
out
signal is used on this input.
MSI/TONE
Master Sync Input or Tone Enable Input
(Pin 18)
TDC-RDC/Xtal
Transmit and Receive Data Clock or Crystal
Output (Pin 20)
out
Master Mode (MSI): This pin is the master 8 kHz
frame reference input. The rising edge of MSI loads
B and D channel data, which had been input during the
previous frame, into the modulator section of the
device, and initiates the outbound burst onto the
twisted pair cable. The rising edge of MSI also
initiates the buffering of the B and D channel data
demodulated during the previous frame. MSI should
be approximately leading edge aligned with the TDC-
RDC data clock input signal.
Master Mode (TDC-RDC): This input is the
transmit and receive data clock for the B channel data.
Output data changes state on the rising edge of this
signal, and input data is read on the falling edges of
this signal. TDC-RDC should be roughly leading edge
aligned with MSI.
Slave Mode (XTAL
out pin. It is capable of driving one external CMOS
input and 15 pF of additional capacitance. See pin
): This pin is the crystal
out
description for XTAL (pin 19).
in
Slave Mode (TONE): A high on this pin causes a
500 Hz square wave PCM tone to be inserted in place
of the demodulated data. This feature allows the
designer to provide audio feedback for telset keyboard
depressions.
LI SENS/2.048 MHz
Line Input Sensitivity or 2.048 MHz Output
(Pin 21)
Master Mode: By applying a logic 1 on this pin,
the sensitivity of LI is reduced by 15 dB. This reduces
the effects of crosstalk, and false detects that would be
picked up and demodulated when the LI pin is
connected to an open loop.
Slave Mode: This pin outputs a 2.048 MHz signal
for use with a PCM codec-filter. All other device
clocks are generated from the rising edge of this clock.
The 8 kHz enables are derived by dividing this
2.048 MHz clock by a nominal ratio of 256. Phase
synchronization to the master UDLT’s burst is
achieved by dividing this clock by the ratios of either
255, 256, or 257.
CCI/XTAL
in
Convert Clock Input or Crystal Input (Pin 19)
Master Mode (CCI UDLT-1): A 2.048 MHz
clock signal should be applied to this pin. This signal
is used for internal sequencing and control. This signal
should be frequency and phase coherent with MSI for
optimum performance.
Slave Mode (XTAL UDLT-1): A 4.096 MHz
in
crystal is tied between this pin and XTAL
(pin 20).
and
to V
out
A 10 MΩ resistor across this pin and XTAL
out
25 pF capacitors from this pin and XTAL
out
are required for stability and to ensure start-up. This
pin may be driven from an external source. XTAL
SS
RE1/CLKOUT
Receive Data Enable 1 Input or Clock Output
(Pin 22)
out
should be left open if an external signal is used on this
input.
Master Mode (CCI UDLT-2): An 8.192 MHz
clock should be supplied to this input. The 8.192 MHz
input should be 50% duty cycle. This signal may free
run with respect to all other clocks without
performance degradation.
Master Mode (RE1 UDLT-1): A rising edge on
this pin will enable data on the Rx pin to be loaded
into the receive data register on the next eight falling
edges of the TDC-RDC data clock. RE1 and TDC-
RDC should be approximately leading edge aligned.
Slave Mode (RE1 UDLT-1): This B series
CMOS output is the inverse of TE1 (see TE1 pin
description).
Master Mode (RE1 UDLT-2): This input along
with RE2 (pin 23) control the input of B channel data
on the Rx pin. The rising edge of the respective enable
signal causes the device to load the selected receive
Slave Mode (XTAL UDLT-2): Normally, an
in
8.192 MHz crystal is tied between this pin and the
XTAL
XTAL and XTAL
XTAL and XTAL
stability and start-up. XTAL may also be driven with
in
an external 8.192 MHz signal if a crystal is not
(pin 20). A 10 MΩ resistor between
out
in
in
and 25 pF capacitors from
out
out
to V are required to ensure
SS
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data buffer with data from the Rx pin on the next eight
falling edges of the TDC-RDC clock. The RE1 and
RE2 enables should be roughly leading edge aligned
with the TDC-RDC data clock. These enables are
rising edge sensitive and need not be high for the
entire B channel input period.
which is simultaneous with the transfer of the transmit
word. See the pin descriptions for EN2-TE2/SIE/
B1B2 and EN1-TE2 for more information.
Master Mode (UDLT-2): B channel data is input
on this pin and controlled by the RE1, RE2, and TDC-
RDC pins.
Slave Mode (CLKOUT UDLT-2): This pin
serves as a buffered output of the crystal frequency
divided by two.
Slave Mode (UDLT-2): This pin is an input for
the B channel data. B channel 1 data is clocked in on
the first eight falling edges of the BCLK output
following the rising edge of the EN1 output. B channel
2 data is clocked in on the next eight falling edges of
the BCLK following the rising edge of the EN2
output.
RE2/BCLK
Receive Data Enable Input 2 or B Channel
Data Clock Output (Pin 23)
Master Mode (UDLT-1): This pin is high
impedance.
LO2
Line Drive Output (Pin 25)
Master Mode (RE2 UDLT-2): See pin
description for RE1 (pin 22).
The LO2 pin, along with LO1 (pin 26) form a push-
pull output, to drive the twisted pair transmission line.
The UDLT-1 drives the twisted pair with a 10-bit,
256 kHz modified DPSK (MDPSK) burst, or a square
wave (set by pin 14 MOD TRI/SQ) burst, each 125 µs.
The UDLT-2 drives the twisted pair with a 20-bit
512 kHz modulated burst. When these pins are idle
and set for square wave modulation, they rest at the
positive power supply voltage. When these pins are
Slave Mode (BCLK UDLT-1 and UDLT-2):
This output provides the data clock for the telset
codec-filter. This clock signal is 128 kHz and begins
operating upon the successful demodulation of a burst
from the master. At this time, EN1-TE1 goes high and
BCLK starts toggling. BCLK remains active for
16 periods, at the end of which time it remains low
until another burst is received from the master. In this
manner, synchronization between the master and slave
is established and any clock slippage is absorbed each
frame. If TONE (pin 18) is brought high, then EN1-
TE1/RE1 are generated from an internal oscillator
until TONE is brought low, or an incoming burst from
the master is received. BCLK is disabled when LB is
held low.
idle and set for MDPSK, they rest at V . For power
ref
supply voltages less than 4.5 V, squarewave
modulation must be used.
LO1
Line Driver Output (Pin 26)
See the pin description for LO2 (pin 25).
Rx
MASTER/SLAVE
Master/Slave Mode (Pin 27)
Receive Data Input (Pin 24)
Master Mode (UDLT-1): The 8-bit B channel
data is clocked into the device on this pin, on the
falling edges of TDC-RDC, under the control of RE1.
Slave Mode (UDLT-1): The 8-bit B channel data
from the telset PCM codec-filter is input on this pin on
the eight falling edges of BCLK after RE1 goes high,
when EN2-TE2/SIE/B1B2, pin 16 is low. When EN2-
TE2/SIE/B1B2, pin16 is high, the receive data word is
latched in during the high period of EN1-TE1, pin 17
A logic low (0 V) on this pin selects master and a
logic high (V ) selects slave.
DD
V
DD
Positive Supply (Pin 28)
This is the most positive power supply pin.
Acceptable operating voltages are from 4.5 V to 5.5 V.
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G
T
R
5
.
5
0
N
N
Ω
0
3
2W
4
2
Ω
Ω
Ω
k
0
F
N
0
N
µ
1
1
4 7.
0
Ω
Ω
Ω
0
0
7
1
1
4
5
5
5
0M
V
8
V
A
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MC145423
MULTICHANNEL DIGITAL LINE CARD
POWER
SUPPLY
V
MSI/TONE
8 kHz FRAME SYNC
TRANSMIT DATA BUS
RECEIVE DATA BUS
DD
LO1
TO
BACK-
PLANE
Tx
TIP
V
Rx
ref
TDC/RDC/XTAL
2.048 MHz DATA CLOCK
LO2
out
CCI/XTAL
in
LI
PD
SDI1 UDLT-3
MASTER
MODE
SDO1
RE1/CLKOUT
EN1-TE1 (I/O)
EN2-TE2(I/O)/SIE
SE/(Mu/A)
SDI2
SDO2
SDCLK
MASTER/SLAVE
MOD SELECT
FRAME 10/20
RE2/BCLK
LI SENS/2.048 MHz
LB
V
SS
VD
RING
TO
BACK-
PLANE
POWER
SUPPLY
TIMING
AND
CONTROL
V
MSI/TONE
Tx
DD
LO1
TIP
V
Rx
ref
TDC/RDC/XTAL
LO2
LI
out
CCI/XTAL
in
PD
SDI1 UDLT-3
MASTER
MODE
RE1/CLKOUT
EN1-TE1 (I/O)
SDI2
SDO1
EN2-TE2(I/O)/SIE
SDO2
SDCLK
SE/(Mu/A)
MASTER/SLAVE
MOD SELECT
FRAME 10/20
RE2/BCLK
LI SENS/2.048 MHz
LB
V
VD
SS
RING
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MC145423
PACKAGE DIMENSIONS
DW SUFFIX
SOIC PACKAGE
CASE 751F-05
D
NOTES:
A
1. DIMENSIONS ARE IN MILLIMETERS.
28
15
2. INTERPRET DIMENSIONS AND TOLERANCES PER
ASME Y14.5M, 1994.
M
B
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSIONS.
M
4. MAXIMUM MOLD PROTRUSION 0.015 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT
MAXIMUM MATERIAL CONDITION.
H
E
5
0 2.
1
14
MILLIMETERS
B
PIN 1 IDENT
DIM MIN
MAX
2.65
0.29
0.49
0.32
A
A1
B
C
D
E
e
H
L
2.35
0.13
0.35
0.23
17.80 18.05
7.40 7.60
1.27 BSC
10.05 10.55
L
0.10
e
0.41
0.90
C
θ
0
8
°
°
SEATING
PLANE
B
C
θ
M
S
S
B
0.025
C A
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DT SUFFIX
TSSOP PACKAGE
CASE 1168-01
B
D
A
A
b1
C
28
15
c
c1
E/2
E
(b)
E1
SECTION A-A
1
14
0.2
A
B
C
NOTES:
PIN 1
INDEX
1. DIMENSIONS AND TOLERANCING PER ASME
Y14.5M, 1994.
2. DIMENSIONS IN MILLIMETERS.
2X e/2
END
VIEW
2X 14 TIPS
26X
e
VIEW A
TOP VIEW
3. DIMENSION D DOES NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE MOLD PROTRUSION IS
0.15 PER SIDE.
4. DIMENSION E1 DOES NOT INCLUDE INTERLEAD
FLASH OR MOLD PROTRUSION. INTERLEAD FLASH
OR PROTRUSION SHALL NOT EXCEED 0.25 PER
SIDE.
0.05
5. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSIONS. DAMBAR PROTRUSION SHALL NOT
CAUSE THE LEAD WIDTH TO EXCEED 0.38.
(D)
28X
0.2
A
MILLIMETERS
SEATING PLANE
DIM MIN
MAX
1.20
0.15
1.05
0.30
0.25
0.20
0.16
9.80
A
A1
A2
b
b1
c
---
0.05
0.80
0.19
0.19
0.09
0.09
9.60
A
28X
b
A
(θ 1°)
M
0.1
A
B C
GAGE
PLANE
SIDE VIEW
A1 A2
c1
D
e
E
0.65 BSC
6.40 BSC
0.25
E1
L
4.30
0.50
4.50
0.70
θ°
L
θ
θ 1
0
8
°
°
VIEW A
14 REF
°
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