MC33977DW_技术文档

Document Number: MC33977

Rev. 2.0, 1/2007

Freescale Semiconductor

Technical Data

Single Gauge Driver

33977

The 33977 is a Serial Peripheral Interface (SPI) Controlled, stepper

motor gauge driver Integrated Circuit (IC). This monolithic IC consists

of a dual H-Bridge coil driver and its associated control logic. The H-

Bridge drivers are used to automatically control the speed, direction,

and magnitude of current through the coils of a two-phase

instrumentation stepper motor, similar to an MMT-licensed AFIC 6405

of Switec MS-X156.xxx motor.

SINGLE GAUGE DRIVER

The 33977 is ideal for use in instrumentation systems requiring

distributed and flexible stepper motor gauge driving. The device also

eases the transition to stepper motors from air core motors by

emulating the damped air core pointer movement.

Features

• MMT-Licensed Two-Phase Stepper Motor Compatible

• Switec MS-X15.xxx Stepper Motor Compatible

• Minimal Processor Overhead Required

• Fully Integrated Pointer Movement and Position State Machine

with Air Core Movement Emulation

• 4096 Possible Steady State Pointer Positions

• 340° Maximum Pointer Sweep

• Maximum Acceleration of 4500°/s²

DW SUFFIX

EG SUFFIX (Pb-FREE)

98ASB42344B

24-PIN SOICW

• Maximum Pointer Velocity of 400°/s

ORDERING INFORMATION

Temperature

• Analog Microstepping (12 Steps/Degrees of Pointer Movement)

• Pointer Calibration and Return to Zero (RTZ)

• Controlled via 16-Bit SPI Messages

Device

Package

Range (T )

A

• Internal Clock Capable of Calibration

• Low Sleep Mode Current

• Pb-Free Packaging Designated by suffix code EG

MC33977DW/R2

-40°C to 125°C

24 SOICW

MCZ33977EG/R2

V

PWR

33977

VPWR

V

DD

5.0 V

Regulator

VDD

SIN+

SIN-

Motor

RTZ

RST

CS

COS+

COS-

MCU

SCLK

SI

SO

GND

Figure 1. 33977 Simplified Application Diagram

Freescale Semiconductor, Inc. reserves the right to change the detail specifications,

as may be required, to permit improvements in the design of its products.

INTERNAL BLOCK DIAGRAM

VPWR

VDD

CS

INTERNAL

REGULATOR

COS+

COS-

COS

SCLK

SO

SPI

SI

LOGIC

RST

STATE

MACHINE

H-BRIDGE

AND

SIN+

SIN-

UNDER-

AND

ILIM

CONTROL

OVERVOLTAGE

DETECT

OVERTEMPERATURE

DETECT

SIN

VDD

SIGMA-DELTA

ADC

MULTIPLEXER

OSCILLATOR

AGND

RTZ

GND (8)

Figure 2. 33977 Simplified Internal Block Diagram

33977

Analog Integrated Circuit Device Data

Freescale Semiconductor

2

PIN CONNECTIONS

COS+

COS-

SIN+

SIN-

GND

CS

NC

GND

VPWR

RST

VDD

RTZ

SCLK

SO

SI

Figure 3. 33977 Pin Connections

Table 1. 33977 Pin Definitions

A functional description of each pin can be found in the Functional Pin Description section beginning onpage 10.

Pin Name Pin Function

Formal Name

Definition

(MS Motor

Pin #)

H-Bridge Outputs 0

Each pin is the output of a half-bridge, designed to source or sink current.

Output

COS+ (MS #4)

COS- (MS #3)

SIN+ (MS #1)

SIN- (MS #2)

1

2

3

4

5 to 8,

17 to 20

GND

Ground

Ground pins

N/A

Input

Output

Input

9

Chip Select

Serial Clock

Serial Output

Serial Input

Return to Zero

This pin is connected to a chip select output of a Large Scale Integration

(LSI) Master IC and controls which device is addressed.

CS

10

11

12

13

SCLK

This pin is connected to the SCLK pin of the master device and acts as a

bit clock for the SPI port.

SO

SI

This pin is connected to the SPI Serial Data Input pin of the Master device

or to the SI pin of the next device in a daisy chain.

This pin is connected to the SPI Serial Data Output pin of the Master

device from which it receives output command data.

RTZ

This is a multiplexed output pin for the non-driven coil, during a Return to

Zero (RTZ) event.

Multiplexed

Output

14

15

VDD

RST

Voltage

Reset

This SPI and logic power supply input will work with 5.0 V supplies.

Input

This pin is connected to the Master and is used to reset the device, or

place it into a sleep state by driving it to Logic [1]. When this pin is driven

to Logic [0], all internal logic is forced to the default state. This input has

an internal active pull-up.

16

VPWR

NC

Battery Voltage

No Connect

Power supply

Input

–

21, 22, 23, 24

These pins are not connected to any internal circuitry, or any other pin,

and may be connected to the board where convenient.

33977

Analog Integrated Circuit Device Data

Freescale Semiconductor

3

ELECTRICAL CHARACTERISTICS

MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

MAXIMUM RATINGS

Table 2. Maximum Ratings

All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or

permanent damage to the device.

Ratings

Symbol

Value

Unit

ELECTRICAL RATINGS

Power Supply Voltage

Steady-State

V

PWRSS

-0.3 to 41

-0.3 to 7.0

40

Input Pin Voltage ⁽¹⁾

V

mA

V

IN

SIN± COSI± Continuous Current Per Output ⁽²⁾

I

OUTMAX

ESD Voltage ⁽³⁾

V

ESD

Human Body Model (HBM)

Machine Model (MM)

Charge Device Model (CDM)

±2000

±200

THERMAL RATINGS

Operating Temperature

Ambient

°C

T_A

T_J

-40 to 125

-40 to 150

Junction

Storage Temperature

T_STG

-55 to 150

°C

Thermal Resistance

Junction-to-Ambient

Junction-to-Lead

°C/W

R_ΘJA

R_ΘJL

60

20

(5)

Peak Package Reflow Temperature During Reflow ⁽⁴⁾

,

T_PPRT

Note 5

°C

Notes

1. Exceeding voltage limits on Input pins may cause permanent damage to the device.

2. Output continuous output rating so long as maximum junction temperature is not exceeded. Operation at 125°C ambient temperature

will require maximum output current computation using package thermal resistances.

3. ESD testing is performed in accordance with the Human Body Model (HBM) (C_ZAP= 100 pF, R_ZAP= 1500 Ω), the Machine Model (MM)

(C_ZAP= 200 pF, R_ZAP= 0 Ω), and the Charge Device Model (CDM).

4. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may

cause malfunction or permanent damage to the device.

5. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow

Temperature and Moisture Sensitivity Levels (MSL),

Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e.

MC33xxxD enter 33xxx), and review parametrics.

33977

Analog Integrated Circuit Device Data

Freescale Semiconductor

4

ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

Table 3. Static Electrical Characteristics

Characteristics noted under conditions 4.75 V < VDD < 5.25 V, and -40°C < TA< 125°C, unless otherwise noted. Typical

values noted reflect the approximate parameter means at T_A= 25°C under nominal conditions unless otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

POWER INPUT (VDD)

Battery Supply Voltage Range

Fully Operational

V_PWR

V

6.5

4.0

–

26

Limited Operation ^{(6), (7)}

V_PWRSupply Current

I_PWR

mA

Gauge Outputs ON, No Output Loads

–

4.0

6.0

VPWR Supply Current (All Outputs Disabled)

Reset = Logic [0], V_DD= 5.0 V

µA

I_PWRSLP1

I_PWRSLP2

–

42

15

60

25

Reset = Logic [0], V_DD= 0 V

Overvoltage Detection Level ⁽⁸⁾

V_PWROV

V_PWRUV

V_DD

26

5.0

4.5

–

32

5.6

5.0

–

38

6.2

5.5

4.5

V

Undervoltage Detection Level ⁽⁹⁾

Logic Supply Voltage Range (5.0 V Nominal Supply)

Under V_DDLogic Reset

V_DDUV

VDD Supply Current

Sleep: Reset Logic [0]

Outputs Enabled

I_DDOFF

I_DDON

–

40

65

µV

1.0

1.8

mA

POWER OUTPUT (SIN-, SIN+, COS-, COS+)

Microstep Output (Measured Across Coil Outputs)

SIN± (COS±) (Refer to Pin Definitions onpage 3)

R_OUT= 200 Ω, PE6 = 0

V

Steps

Pin Definitions

V_ST6

V_ST5

V_ST4

V_ST3

V_ST2

V_ST1

V_ST0

4.82

5.3

6.0

6, 18,

0, 12

0.94 V_ST60.97 V_ST6

1.0 V_ST6

5, 7, 17, 19

4, 8, 16, 20

3, 9, 15, 21

2, 10, 14, 22

1, 11, 13, 23

0, 12

1, 11, 13, 23

2, 10, 14, 22

3, 9, 15, 21

5, 7, 17, 19

6, 18

0.84 V_ST60.87 V_ST60.96 V_ST6

0.68 V_ST60.71 V_ST60.8 V_ST6

0.47 V_ST60.50 V_ST60.57 V_ST6

0.23 V_ST60.26 V_ST60.31 V_ST6

0.1

0.0

0.1

Full Step Active Output (Measured Across Coil Outputs) ⁽¹⁰⁾

SIN± (COS±), Steps 1,3 (Pin Definitions 0 and 2)

V_FS

V

4.9

5.3

6.0

Notes

6. Outputs and logic remain active; however, the larger coil voltage levels may be clipped. The reduction in drive voltage may result in a

loss of position control.

7. The logic will reset at some level below the specified Limited Operational minimum.

8. Outputs will disable and must be re-enabled via the PECCR command.

9. Outputs remain active; however, the reduction in drive voltage may result in a loss of position control.

10. See Figure 7.

33977

Analog Integrated Circuit Device Data

Freescale Semiconductor

5

ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

Table 3. Static Electrical Characteristics (continued)

Characteristics noted under conditions 4.75 V < VDD < 5.25 V, and -40°C < TA< 125°C, unless otherwise noted. Typical

values noted reflect the approximate parameter means at T_A= 25°C under nominal conditions unless otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

POWER OUTPUT (SIN-, SIN+, COS-, COS+) (Continued)

Microstep Full Step Output (Measured from Coil Low Side to Ground)

SIN± (COS±) I_OUT= 30 mA

V_LS

V

0.0

0.1

0.3

Output Flyback Clamp ⁽¹¹⁾

V_FB

I_LIM

–

V_ST6+ 0.5 V_ST6+ 1.0

V

Output Current Limit (Output - V_ST6

Overtemperature Shutdown ⁽¹²⁾

Overtemperature Hysteresis ⁽¹²⁾

)

40

100

–

170

180

16

mA

°C

T_SD

155

8.0

T_HYST

–

CONTROL I/O (SI, SCLK, CS, RST, SO)

Input Logic High Voltage ⁽¹²⁾

V_IH

V_IL

2.0

–

0.8

–

V

Input Logic Low Voltage ⁽¹²⁾

–

Input Logic Voltage Hysteresis ⁽¹²⁾

Input Logic Pull-Down Current (SI, SCLK)

Input Logic Pull-Up Current (CS, RST)

SO High State Output Voltage (I_OH= 1.0 mA)

SO Low State Output Voltage (I_OL= 1.6 mA)

SO Tri-State Leakage Current (CS = 3.5 V)

Input Capacitance ⁽¹³⁾

V_INHYST

I_DWN

I_UP

–

3.0

5.0

0.8 V_DD

–

100

–

mV

µA

V

20

–

V_SOH

V_SOL

I_SOLK

C_IN

–

0.2

0.0

4.0

–

0.4

5.0

12

20

V

-5.0

–

µA

pF

SO Tri-State Capacitance ⁽¹³⁾

C_SO

–

ANALOG TO DIGITAL CONVERTER (RTZ ACCUMULATOR COUNT)

ADC Gain ^{(12), (14)}

G

100

188

270

Counts/V/

ms

ADC

Notes

11. Outputs remain active; however, the reduction in drive voltage may result in a loss of position control.

12. This parameter is guaranteed by design; however, it is not production tested.

13. Capacitance not measured. This parameter is guaranteed by design; however, it is not production tested.

14. Reference RTZ Accumulator (Typical) on page 30

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Analog Integrated Circuit Device Data

Freescale Semiconductor

6

ELECTRICAL CHARACTERISTICS

DYNAMIC ELECTRICAL CHARACTERISTICS

Table 4. Dynamic Electrical Characteristics

Characteristics noted under conditions 4.75 V < VDD < 5.25 V, and -40°C < TA < 125°C, unless otherwise noted. Typical

values noted reflect the approximate parameter means at T_A= 25°C under nominal conditions unless otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

POWER OUTPUT AND CLOCK TIMINGS (SIN+, SIN-, COS+, COS-) CS

SIN± (COS±) Output Turn ON Delay Time (Time from Rising CS

Enabling Outputs to Steady State Coil Voltages and Currents) ⁽¹⁵⁾

t_DLYON

ms

–

1.0

SIN± (COS±) Output Turn OFF Delay Time (Time from Rising CS

Disables Outputs to Steady State Coil Voltages and Currents) ⁽¹⁵⁾

t_DLYOFF

–

1.0

1.7

Uncalibrated Oscillator Cycle Time

t_CLU

t_CLC

0.65

1.0

µs

Calibrated Oscillator Cycle Time

Calibration Pulse = 8.0 µs, PECCR D4 = Logic [0]

Calibration Pulse = 8.0 µs, PECCR D4 = Logic [1]

1.0

0.9

1.1

1.0

1.2

1.1

Maximum Pointer Speed ⁽¹⁶⁾

V_MAX

A_MAX

–

400

°/s

Maximum Pointer Acceleration ⁽¹⁶⁾

4500

°/s²

SPI INTERFACE TIMING (CS, SCLK, SO, SI, RST) ⁽¹⁷⁾

Recommended Frequency of SPI Operation

f_SPI

t_LEAD

t_LAG

–

167

–

1.0

–

2.0

–

MHz

ns

Falling Edge of CS to Rising Edge of SCLK (Required Setup Time) ⁽¹⁸⁾

Falling Edge of SCLK to Rising Edge of CS (Required Setup Time) ⁽¹⁸⁾

SI to Falling Edge of SCLK (Required Setup Time) ⁽¹⁸⁾

Falling Edge of SCLK to SI (Required Hold Time) ⁽¹⁸⁾

–

ns

t_SISU

25

83

ns

t_SIHOLD

–

ns

SO Rise Time

C_L= 200 pF

t_RSO

ns

–

25

50

t_FSO

SO Fall Time

C_L= 200 pF

ns

–

25

50

SI, CS, SCLK, Incoming Signal Rise Time ⁽¹⁹⁾

t_RSI

t_FIS

–

50

ns

µs

SI, CS, SCLK, Incoming Signal Fall Time ⁽¹⁹⁾

Falling Edge of RST to Rising Edge of RST (Required Setup Time) ⁽¹⁸⁾

Rising Edge of CS to Falling Edge of CS (Required Setup Time) ^{(18), (20)}

Falling Edge of RST to Rising Edge of CS (Required Setup Time) ⁽¹⁸⁾

Notes

t

3.0

5.0

WRST

t_CS

t_EN

15. Maximum specified time for the 33977 is the minimum guaranteed time needed from the microcontroller.

16. The minimum and maximum value will vary proportionally to the internal clock tolerance. These numbers are based on an ideally

calibrated clock frequency of 1.0 MHz. These are not 100 percent tested.

17. The 33977 shall meet all SPI interface timing requirements specified in the SPI Interface Timing section of this table, over the specified

temperature range. Digital interface timing is based on a symmetrical 50 percent duty cycle SCLK Clock Period of 33 ns. The device shall

be fully functional for slower clock speeds. Reference Figure 4 and 5.

18. The required setup times specified for the 33977 are the minimum time needed from the microcontroller to guarantee correct operation.

19. Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.

20. The value is for a 1.0 MHz calibrated internal clock. The value will change proportionally as the internal clock frequency changes.

33977

Analog Integrated Circuit Device Data

Freescale Semiconductor

7

ELECTRICAL CHARACTERISTICS

DYNAMIC ELECTRICAL CHARACTERISTICS

Table 4. Dynamic Electrical Characteristics (continued)

Characteristics noted under conditions 4.75 V < VDD < 5.25 V, and -40°C < TA < 125°C, unless otherwise noted. Typical

values noted reflect the approximate parameter means at T_A= 25°C under nominal conditions unless otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

SPI INTERFACE TIMING (CS, SCLK, SO, SI, RST) ^‘(CONTINUED)

Time from Falling Edge of CS to SO Low Impedance ⁽²²⁾

Time from Falling Edge of CS to SO High Impedance ⁽²³⁾

t_SOEN

t_SODIS

t_VALID

–

145

4.0

ns

µs

ns

1.3

Time from Rising Edge of SCLK to SO Data Valid ⁽²⁴⁾

0.2 V_DD= SO = 0.8 V_DD, C_L= 200 pF

–

90

150

Notes

21. The 33977 shall meet all SPI interface timing requirements specified in the SPI Interface Timing section of this table, over the specified

temperature range. Digital interface timing is based on a symmetrical 50 percent duty cycle SCLK Clock Period of 33 ns. The device shall

be fully functional for slower clock speeds.

22. Time required for output status data to be terminated at SO 1.0 kΩ load on SO.

23. Time required for output status data to be available for use at SO 1.0 kΩ load on SO.

24. Time required to obtain valid data out from SO following the rise of SCLK.

33977

Analog Integrated Circuit Device Data

8

Freescale Semiconductor

ELECTRICAL CHARACTERISTICS

TIMING DIAGRAMS

V

IN

IL

RST

CS

0.2 V

DD

^tWRST

t

CS

0.7 V

V

DD

IH

IL

0.7 V

DD

t

LAG

LEAD

RSI

V

IH

0.7 V

DD

0.2 V

SCLK

SI

t

FIS

t

SISU

t

SI(HOLD)

Don’t Care

0.7 V

DD

Don’t Care

Valid

Don’t Care

0.2 V

DD

Figure 4. Input Timing Switching Characteristics

t

FIS

t

RSI

V

OH

3.5V

50%

SCLK

1.0V

OL

t

SO(EN)

V

OH

OL

V

0.7 DD

V

0.2 DD

SO

Low-to-High

t

RSO

t

VALID

t

RSO

SO

V

OH

OL

High-to-Low

V

0.7 DD

V

0.2 DD

t

SO(DIS)

Figure 5. Valid Data Delay Time and Valid Time Waveforms

33977

Analog Integrated Circuit Device Data

Freescale Semiconductor

9

FUNCTIONAL DESCRIPTION

FUNCTIONAL PIN DESCRIPTION

FUNCTIONAL DESCRIPTION

INTRODUCTION

This 33977 is a single-packaged, Serial Peripheral

INterface (SPI) controlled, single stepper motor gauge driver

integrated circuit (IC). This monolithic stepper IC consists of

[deleted two per D. Mortensen] a dual output H-Bridge coil

driver [deleted plural s for accurate tense] and the

associated control logic. The dual H-Bridge driver is used to

automatically control the speed, direction, and magnitude of

current through the coils of a two-phase instrumentation

stepper motor, similar to an MMT-licensed AFIC 6405 of

Switec MS-X 156.xxx motor.

FUNCTIONAL PIN DESCRIPTION

SCLK has an internal pull down (l_DWN), as specified in the

section of the Static Electrical Characteristics Table. When

CS is logic [1], signals at the SCLK and SI pins are ignored

and SO is tri-stated (high impedance). Refer to the data

transfer Timing Diagrams on page 9.

COSINE POSITIVE (COS0+)

The H-Bridge pins linearly drive the sine and cosine coils

of a stepper motor, providing four-quadrant operation.

COSINE NEGATIVE (COS0-)

The H-Bridge pins linearly drive the sine and cosine coils

of a stepper motor, providing four-quadrant operation.

SERIAL OUTPUT (SO)

The SO data pin is a tri-stateable output from the Shift

register. The Status register bits are the first 16 bits shifted

out. Those bits are followed by the message bits clocked in

FIFO, when the device is in a daisy chain connection or being

sent words that are multiples of 16 bits. Data is shifted on the

rising edge of the SCLK signal. The SO pin will remain in a

high impedance state until the CS pin is put into a logic low

state.

SINE POSITIVE (SIN+)

The H-Bridge pins linearly drive the sine and cosine coils

of a stepper motor, providing four-quadrant operation.

SINE NEGATIVE (SIN-)

The H-Bridge pins linearly drive the sine and cosine coils

of a stepper motor, providing four-quadrant operation.

SERIAL INPUT (SI)

GROUND (GND)

The SI pin is the input of the SPI. Serial input information

is read on the falling edge of SCLK. A 16-bit stream of serial

data is required on the SI pin, beginning with the most

significant bit (MSB). Messages that are not multiples of 16

bits (e.g., daisy chained device messages) are ignored. After

transmitting a 16-bit word, the CS pin must be de-asserted

(logic [1]) before transmitting a new word. SI information is

ignored when CS is in a logic high state.

Ground pins.

CHIP SELECT (CS)

The pin enables communication with the master device.

When this pin is in a logic [0] state, the 33977 is capable of

transferring information to, and receiving information from,

the master. The 33977 latches data in from the Input Shift

registers to the addressed registers on the rising edge of CS.

RETURN TO ZERO (RTZ)

The output driver on the SO pin is enabled when CS is

logic [0]. When CS is logic high, signals at the SCLK and SI

pins are ignored and the SO pin is tri-stated (high

This is a multiplexed output pin for the non-driven coil,

during a Return to Zero (RTZ) event.

impedance). CS will only be transitioned from a logic [1] state

to a logic [0] state when SCLK is logic [0]. CS has an internal

pull-up (I_UP) connected to the pin, as specified in the section

of the Static Electrical Characteristics Table.

VOLTAGE (VDD)

The SPI and logic power supply input will work with 5.0 V

supplies.

SERIAL CLOCK (SCLK)

RESET (RST)

SCLK clocks the Internal Shift registers of the 33977

device. The SI pin accepts data into the Input Shift register on

the falling edge of the SCLK signal, while the Serial Output

pin (SO) shifts data information out of the SO Line Driver on

the rising edge of the SCLK signal. It is important that the

SCLK pin be in a logic [0] state whenever the CS makes any

transition.

If the master decides to reset the device, or place it into a

sleep state, the RST pin is driven to a Logic [0]. A Logic [0] on

the RST pin forces all internal logic to the known default state.

This input has an internal active pull-up.

VOLTAGE POWER (VPWR)

This is the power supply pin.

33977

Analog Integrated Circuit Device Data

Freescale Semiconductor

10

FUNCTIONAL DESCRIPTION

FUNCTIONAL INTERNAL BLOCK DESCRIPTION (OPTIONAL)

Internal

SPI

Logic

Oscillator

RTZ

Reference

Under and

Overvoltage

Detect

H-Bridge

and Control

Figure 6. Functional Internal 33977 Block Illustration

SERIAL PERIPHERAL INTERFACE (SPI)

OSCILLATOR

This circuitry manages incoming messages and outgoing

status data.

The internal oscillator generates the internal clock for all

timing critical features.

LOGIC

H-BRIDGE AND CONTROL

This design element includes internal logic including state

machines and message decoding.

This circuitry contains the output coil drivers and the

multiplexers necessary for four quadrant operation and RTZ

sequencing. This circuitry is repeated for the Sine and Cosine

coils.

INTERNAL REFERENCE

• Overtemperature — Each output includes an

overtemperature sensing circuit

This design element is used for step value levels.

• ILIM — Each output is current limited

UNDER AND OVERVOLTAGE DETECTION

This design element detects when V_PWRis out of the

normal operating range.

RETURN TO ZERO (RTZ)

This circuitry outputs the voltage present on the non-driven

coil during RTZ operation.

33977

Analog Integrated Circuit Device Data

Freescale Semiconductor

11

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

STATE MACHINE OPERATION

The 33977 is ideal for use in instrumentation systems

requiring distributed and flexible stepper motor gauge driving.

The device also eases the transition to stepper motors from

air core motors by emulating the air core pointer movement

with little additional processor bandwidth utilization. The two-

phase stepper motor has maximum allowable velocities and

acceleration and deceleration. The purpose of the stepper

motor state machine is to drive the motor with the maximum

performance while remaining within the motor’s voltage,

velocity, and acceleration constraints.

A requirement of the state machine is to ensure the

deceleration phase begins at the correct time and pointer

position. When commanded, the motor [will deleted PV]

accelerates constantly to the maximum velocity, and then it

moves toward the commanded position at the maximum

velocity. Eventually, the pointer reaches the calculated

location where the movement has to decelerate, safely

slowing to a stop at the desired position. During the

deceleration phase, the motor does [will deleted PV] not

exceed the maximum deceleration.

During normal operation, both stepper motor rotors are

microstepped at 24 steps per electrical revolution, illustrated

in Figure 7. A complete electrical revolution results in two

degrees of pointer movement. There is a second smaller

[parentheses removed-unnecessary] state machine in the IC

controlling these microsteps. The smaller state machine

receives clockwise or counter-clockwise index commands at

timed intervals, thereby stepping the motor in the appropriate

direction by adjusting the current in each coil. Normalized

values are provided in Table 5.

Figure 7. Clockwise Microsteps

Table 5. Coil Step Value

SINE

(Angle)*

COS (Angle -30)* COS (Angle -30)*

Step

Angle

PE6=0

PE6=1

0.866

0.966

1.0

0

1

0.0

15

0.0

1.0

0.259

0.5

0.965

0.866

0.707

0.5

2

30

3

45

0.707

0.866

0.966

1.0

0.966

0.866

0.707

0.500

0.259

0.0

4

60

5

75

0.259

0.0

6

90

7

105

120

135

150

0.966

0.866

0.707

0.5

-0.259

-0.5

8

9

-0.707

-0.866

-0.259

-0.500

10

33977

Analog Integrated Circuit Device Data

Freescale Semiconductor

12

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

Table 5. Coil Step Value

and solving for v in terms of u, s, and t gives:

11

12

13

14

15

16

17

18

19

20

21

22

23

165

180

195

210

225

240

255

270

285

300

315

330

345

0.259

0.0

-0.966

-1.0

-0.707

-0.866

-0.966

-1.0

v = ²/_t- u

The correct value of t to use in the equation is the

quantized value obtained above.

-0.259

-0.5

-0.966

-0.867

-0.707

-0.5

From these equations, a set of recursive equations can be

generated to give the allowed time step between motor

indexes when the motor is accelerating from a stop to its

maximum velocity.

-0.707

-0.866

-0.966

-1.0

-0.966

-0.866

-0.707

-0.500

-0.259

0.0

-0.259

0.0

Starting from a position p of 0 and a velocity v of 0, these

equations define the time interval between steps at each

position. To drive the motor at maximum performance, index

commands are given to the motor at these intervals. A table

is generated giving the time step *t at an index position n.

-0.966

-0.866

-0.707

-0.5

0.259

0.5

0.707

0.866

0.966

0.259

0.500

0.707

p₀= 0

v₀= 0

-0.259

* Denotes normalized values

⎡

2

⎤

-v_{n -1}+ √

v

_{n -1}+ 2a

The motor is stepped by providing index commands at

intervals. The time between steps defines the motor velocity

and the changing time defines the motor acceleration.

∆t_n=

a

The state machine uses a table to define the allowed time

and the maximum velocity. A useful side effect of the table is

that it also allows the direct determination of the position at

which the velocity should reduce to stop the motor at the

desired position.

where ⎡ ⎤ indicates rounding up

v_n= ²/_∆tn- V_{n -1}

p_n= n

Motor motion equations follow: [reworded for efficient use

of space]

Note: [chgd for format consistency AND deleted that as PV]

For p_n= n, on the nth step, the motor [has deleted as PV]

indexed by n positions and has been accelerating steadily at

the maximum allowed rate. This is critical because it also

indicates the minimum distance the motor must travel while

decelerating to a stop. For example, the stopping distance is

also equal to the current value of n.

(The units of position are steps and velocity and

acceleration are in steps/second and steps/second².)

From an initial position of 0 with an initial velocity (u), the

motor position (s) at a time (t) is:

s = ut + ¹/₂at ²

The algorithm of pointer movement can be summarized in

two steps:

1. The pointer is at the previously commanded position

and is not moving.

For unit steps, the time between steps is:

2. A command to move to a pointer position (other than

the current position) has been received. Timed index

pulses are sent to the motor driver at an ever-

increasing rate, according to the time steps in Table 6,

until:

- u + √ u²+ 2a

⇒

t =

a

This defines the time increment between steps when the

motor is initially traveling at a velocity u. In the ROM, this time

is quantized to multiples of the system clock by rounding

upwards, ensuring acceleration never exceeds the allowed

value. The actual velocity and acceleration is calculated from

the time step actually used. Using:

aThe maximum velocity (default or selected) is

reached after which the step time intervals will no

longer decrease.

bThe distance in steps that remain to travel are less

than the current step time index value. The motor

then decelerates by increasing the step times

according to Table 6 until the commanded

position is reached. The state machine controls

the deceleration so that the pointer reaches the

commanded position efficiently.

v²= u²+ 2as

and

v = u + at

An example of the velocity table for a particular motor is

provided in Table 6. This motor’s maximum speed is 4800

33977

Analog Integrated Circuit Device Data

Freescale Semiconductor

13

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

microsteps/s (at 12 microsteps/degrees), and its maximum

acceleration is 54000 microsteps/s². The table is quantized

to a 1.0 MHz clock.

Table 6. Velocity Table

Velocity Time Between

Velocity

Velocity Time Between

Velocity

Velocity Time Between

Velocity

Position

Steps (µs)

(µSteps/s)

Position

Steps (µs)

(µSteps/s)

Position

Steps (µs)

(µSteps/s)

0

0.0

27217

13607

11271

7970

5858

4564

3720

3132

2701

2373

2115

1908

1737

1594

1473

1369

1278

1199

1129

1066

1010

960

0.00

36.7

76

77

380

377

374

372

369

366

364

361

358

356

354

351

349

347

344

342

340

338

336

334

332

330

328

326

324

322

321

319

317

315

314

312

310

309

307

306

2631.6

2652.5

2673.8

2688.2

2710.0

2732.2

2747.3

2770.1

2793.3

2809.0

2824.9

2849.0

2865.3

2881.8

2907.0

2924.0

2941.2

2958.6

2976.2

2994.0

3012.0

3030.3

3048.8

3067.5

3086.4

3105.6

3115.3

3134.8

3154.6

3174.6

3184.7

3205.1

3225.8

3236.2

3257.3

3268.0

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

180

181

182

183

184

185

186

187

257

256

255

254

253

252

251

250

249

248

247

246

245

244

243

242

241

240

239

238

237

236

265

235

234

233

232

231

230

3891.1

3906.3

3921.6

3937.0

3952.6

3968.3

3984.1

4000.0

4016.1

4032.3

4048.6

4065.0

4081.6

4098.4

4115.2

4132.2

4149.4

4166.7

4184.1

4201.7

4219.4

4237.3

4255.3

4273.5

4291.8

4310.3

4329.0

4347.8

1

2

73.5

78

3

88.7

79

4

125.5

170.7

219.1

268.8

319.3

370.2

421.4

472.8

524.1

575.7

627.4

678.9

730.5

782.5

834.0

885.7

938.1

990.1

1041.7

1091.7

1140.3

1187.6

1231.5

1275.5

1315.8

1356.9

1396.6

1434.7

1470.6

1508.3

1543.2

1577.3

80

5

81

6

82

7

83

8

84

9

85

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

86

87

88

89

90

91

92

93

94

95

96

97

98

916

99

877

100

101

102

103

104

105

106

107

108

109

110

111

842

812

784

760

737

716

697

680

663

648

634

33977

Analog Integrated Circuit Device Data

Freescale Semiconductor

14

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

Table 6. Velocity Table (continued)

Velocity Time Between

Velocity

Velocity Time Between

Velocity

Velocity Time Between

Velocity

Position

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

Steps (µs)

(µSteps/s)

Position

Steps (µs)

(µSteps/s)

Position

Steps (µs)

(µSteps/s)

621

608

596

585

575

565

555

546

538

529

521

514

507

500

493

487

481

475

469

464

458

453

448

444

439

434

430

426

422

418

414

410

406

403

399

396

393

389

386

383

1610.3

1644.7

1677.9

1709.4

1739.1

1769.9

1801.8

1831.5

1858.7

1890.4

1919.4

1945.5

1972.4

2000.0

2028.4

2053.4

2079.0

2105.3

2132.2

2155.2

2183.4

2207.5

2232.1

2252.3

2277.9

2304.1

2325.6

2347.4

2369.7

2392.3

2415.5

2439.0

2463.1

2481.4

2506.3

2525.3

2544.5

2570.7

2590.7

2611.0

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

304

303

301

300

298

297

295

294

293

291

290

289

287

286

285

284

282

281

280

279

278

277

275

274

273

272

271

270

269

268

267

266

265

264

263

262

261

260

259

258

3289.5

3300.3

3322.3

3333.3

3355.7

3367.0

3389.8

3401.4

3413.0

3436.4

3448.3

3560.2

3484.3

3496.5

3508.8

3521.1

3546.1

3558.7

3571.4

3584.2

3597.1

3610.1

3636.4

3649.6

3663.0

3676.5

3690.0

3703.7

3717.5

3731.3

3745.3

3759.4

3773.6

3787.9

3802.3

3816.8

3831.4

3846.2

3861.0

3876.0

188

189

190

191

192

193

194

195

196

197

198

199

200

201

202

203

204

205

206

207

208

209

210

211

212

213

214

215

216

217

218

219

220

221

222

223

224

225

229

228

227

226

225

224

223

222

221

220

219

218

217

216

215

214

213

212

211

210

209

208

4366.8

4386.0

4405.3

4424.8

4444.4

4464.3

4484.3

4504.5

4524.9

4545.5

4566.2

4587.2

4608.3

4629.6

4651.2

4672.9

4694.8

4717.0

4739.3

4761.9

4784.7

4807.7

33977

Analog Integrated Circuit Device Data

Freescale Semiconductor

15

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

3. A third, and even more expensive approach requires

the use of an additional crystal, or resonator.

INTERNAL CLOCK CALIBRATION

Timing-related functions on the 33977 (e.g., pointer,

velocities, acceleration, and Return to Zero Pointer speeds)

depend upon a precise, consistent time reference to control

the pointer accurately and reliably. Generating accurate time

references on an integrated circuit can be accomplished.

There are three methods to generate accurate time

references on an integrated circuit:

The internal clock in the 33977 is temperature

independent and area efficient; however, it can vary up to 70

percent due to process variation. Using the existing SPI

inputs and the precision timing reference already available to

the microcontroller, the 33977 allows more accurate clock

calibration to within ±10 percent without requiring extra pins,

components, or costly circuitry.

1. One option is trimming; however, timing tends to be

costly due to the large amount of die area required for

trim pads.

Calibrating the internal 1.0 MHz clock is initiated by writing

Logic [1] to PECCR bit PE3, illustrated in Figure 8.

2. Another, but expensive possibility is an externally

generated clock signal. This option requires a

dedicated pin on the device and controller.

Figure 8. Gauge Enable and Clock Calibration Example

fall below 1.0 MHz. The frequency range of the calibrated

clock is always below 1.0 MHz if PECCR bit PE4 is Logic [0]

prior to initiating a calibration command, followed by an 8.0 µs

reference pulse. The frequency is centered at 1.0 MHz if bit

D4 is written Logic [1].

The 8.0 µs calibration pulse is then provided by the

controller to result in a nominal internal 33977 clock speed of

1.0 MHz. The pulse is sent on the CS pin immediately after

the SPI calibration command is sent. During the calibration,

The 33977 can be fooled into calibrating faster or slower

than the optimal frequency by sending a calibration pulse

longer or shorter than the intended 8.0 µs. As long as the

calibration divisor remains between four and 15 there is no

calibration flag. For applications requiring a slower calibrated

clock, e.g., a motor designed with a gear ratio of 120:1

(8 microsteps/deg), users will have to provide a longer

calibration pulse. The internal oscillator can be slowed with

the PECCR command, so the calibration divisor safely falls

within the four to 15 range when calibrating with a longer time

reference. Fro example, for the 120:1 motor, the pulse would

be 12 µs instead of 8.0 µs. The result of this slower calibration

is longer step times resulting in generating pointer

no other SPI lines should be toggled. At the moment the CS

pin transitions from Logic [1] to Logic [0], an internal 7-bit

counter counts the number of cycles of an internal, 8.0 MHz

clock. The counter stops when the CS pin transitions from

Logic [0] to Logic [1]. The value in the counter represents the

number of cycles of the 8.0 MHz clock occurring in the 8.0 µs

window; it should range from 32 to 119. An offset is added to

this number to help center, or skew, the calibrated result to

generate a desired maximum, or normal frequency. The

modified counter value is truncated by four bits to generate

the calibration divisor, potentially ranging from four to 15. The

8.0 MHz clock is divided by the calibration divisor, resulting in

a calibrated 1.0 MHz clock. If the calibration divisor lies

outside the range of four to 15, the 33977 flags the CAL bit in

the device Status register, indicating the calibration

movements capable of meeting acceleration and velocity

requirements. The resolution of the pointer positioning

decreases from 0.083 deg/microstep (180:1) to 0.125

deg/microstep (120:1) while the pointer sweep range

increases from approximately 340° to over 500°.

procedure was not successful. A clock calibration is allowed

only if the gauge is disabled, or the pointer is not moving as

indicated by the Status bit of MOV, illustrated in Table 16

section of this document.

Note: A fast calibration could result in violations of the

motor acceleration and a velocity maximums, resulting in

missed steps.

Some applications may require a guaranteed maximum

pointer velocity and acceleration. Guaranteeing these

maximums requires the nominal internal clock frequency to

33977

Analog Integrated Circuit Device Data

Freescale Semiconductor

16

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

position step values as the pointer decelerates. The default

movement in the 33977 uses this ramp modification feature.

An example is illustrated in Figure 9. If the maximum

acceleration and deceleration of the pointer is desired, the

repetitive steps can be disabled by writing Logic [1] to the

PECCR bit PE5.

POINTER DECELERATION

Constant acceleration and deceleration of the pointer

produces relatively choppy movements when compared to

those of an air core gauge. Modification of the velocity

position ramp during deceleration can create the desired

damped movement. This modification is accomplished in the

33977 by adding repetitive steps at several of the last velocity

.

Velocity

Position

24

23

22

21

20

21

20

19

18

17

16

15

14

13

12

11

10

19

18

17

16

15

14

13

12

11

10

Hold Counts

9

8

7

6

5

4

3

2

1

=

0

Position

0

Microsteps

Figure 8. Deceleration Ramp

Figure 9. Deceleration Ramp

determines an RTZ sequence is not working properly, for

example, the RTZ taking too long; it can disable the

command via the RTZR bit RZ1. [Altered for better read flow]

RETURN TO ZERO CALIBRATION

Many stepper motor applications require [that deleted as

PV] the IC detect when the stepper motor stalls after

commanded to return to the zero position for calibration

purposes. In instrumentation applications, the stalling occurs

when the pointer hits the end stop on the gauge bezel,

[which is deleted as PV] usually at the zero position. It is

important to know [that PV] when the pointer reaches the end

stop, it immediately stops without bouncing away. The 33977

device provides the ability to automatically and independently

return the pointer to the zero position via the RTZR and

RTZCR SPI commands. An automatic RTZ is initiated, using

the RZ1 and RZ2 bits, provided the RZ4 is Logic [1]. During

an RTZ event, all commands related to the gauge being

returned are ignored until the pointer has successfully

zeroed, or the RTZR bit RZ1 is written to disable the event.

Once an RTZ event is initiated, the device reports back via

the SO pin an RTZ event is underway.

RTZCR bits RC10:RC5 are written to preload the

accumulator with a predetermined value assuring accurate

pointer stall detection. This preloaded value can be

determined during application development by disabling the

automatic shutdown feature of the device with the RTZR bit

RZ4. This operating mode allows the master to monitor the

RTZ event, using the accumulator information available via

the SO if the device is configured to provide the RTZ

Accumulator Status. The unconditional RTZ event can be

turned OFF using the RTZR bit RZ1.

If the Position 0 location bit, RZ2, is in the default Logic [0]

mode, then during an RTZ event the pointer is returned

counterclockwise (CCW) using full steps at a constant speed

determined by the RTZCR RC3:RC0 and RC12:RC11 bits

written during RTZ configuration, see Figure 10. Full steps

are used during an RTZ so only coil of the motor is being

driven at any time. The coil not being driven is used to

determine if the pointer is moving. If the pointer is moving, the

flux present in the non-driven coil is processed by integrating

the back EMF signal present on the opened pin of the coil

while applying a fixed potential to the other end.

The RTZCR command is used to set the RTZ pointer

speed, choose an appropriate blanking time, and preload the

integration accumulator with an appropriate offset. On

reaching the end stop, the device reports back to the

microcontroller via the status message [that PV] the RTZ was

successful. The RTZ automatically disables, [that will PV]

allowing other commands to be valid. In the event the master

33977

Analog Integrated Circuit Device Data

Freescale Semiconductor

17

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

I

I_M_m_A_ax_X

+

0

I_coil

I_COIL

SINE

_

I_MAX

I_max

0

1

2

3

0

I

MAX

max

COSINE

+

I_COIL

I_coil

0

_

I_MAX

I_max

0

1

2

3

0

Figure 9. FULLSTEPS (Counter Clockwise)

Figure 10. Full Steps (Counterclockwise)

The IC automatically prepares the non-driven coil at each

step, waits for a predetermined blanking time, and then

processes the signal for the duration of the full step. When

the pointer reaches the stop and not longer moves, the

dissipating flux is detected. The processed results are placed

in the RTZ accumulator, and then compared to a decision

threshold. If the signal exceeds the decision threshold, the

pointer is assumed to be moving. If the threshold value is not

exceeded, the drive sequence is stopped if RTZR bit RZ4 is

Logic [0]. If bit RZ4 is Logic [1], the RTZ movement will

continue indefinitely until the RTZR bit RZ1 is used to stop the

RTZ event.

held constant. The full steps are evenly spaced, resulting in

equidistant movement as the motor is full stepped.

In comparison, motors [that have deleted PV] whose coils

aligned at a 60° angle [will deleted PV] results in two distinct

flux values as a the coils are driven in the same full step

fashion. This lack of symmetry in the measured flux is due to

the difference in the electrical angles between full steps.

Clearly stated, the distance the rotor moves changes from full

step to full step. This difference can be observed in Figure 7

and Table 5.

In Figure 7, where PE6 = 0, the difference in microsteps

between alternating full steps (one coil at maximum current

while the other is at zero) is always six. In contrast, the same

figure illustrates PE6 = 1 showing the difference in

microsteps between full steps of the 60° coils alternating

between four and eight. These expected differences should

be taken into account when setting the RTZ threshold.

A pointer [that is PV] not on a full step location, or [that

PV] is in magnetic alignment prior to the RTZ event may

cause a false RTZ detection. More specifically, an RTZ event

beginning from a non-full step position may result in an

abbreviated flux value potentially interpreted as a stalled

pointer. Advancing the pointed by at least 12 microsteps

clockwise (if PE7 = 0) to the nearest full step position (e.g., 0,

6, 12, 18, 24, etc.) prior to initiating an RTZ ensures the

magnetic fields line up and increases the chances of a

successful pointer stall detection. It is important that the

pointer be in a static, or commanded, position before starting

the RTZ event. Because the time duration and the number of

steps the pointer moves prior to reaching the commanded

position can vary depending upon its status at the time a

position change is communicated, the master should make

sure that the rotor is not moving prior to starting an RTZ.

Cessation of movement can be inferred by monitoring the

CMD and/or the MOV status bits.

After completion of an RTZ, the 33977 automatically

assigns the zero step position to the full step position at the

end-stop location. Because the actual zero position could lie

anywhere within the full step where the zero was detected,

the assigned zero position could be within a window of ±0.5°.

An RTZ can be used to detect stall, even if the pointer rests

on the end-stop when RTZ sequence is initiated. However, it

is recommended to advance the pointer by at least 12

microsteps to the nearest full step prior to initiating the RTZ.

RTZ OUTPUT

During an RTZ event the non-driven coil is analyzed to

determine the state of the motor. The 33977 multiplexes the

coil voltages, [chgd PV and provides to read as active voice]

providing signal from the non-driven coil to the RTZ pin.

It should be pointed out, the flux value, for an ideal motor

with the coils perfectly aligned at 90°, will vary little from full

step to full step if all other variables, such as temperature, are

33977

Analog Integrated Circuit Device Data

Freescale Semiconductor

18

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

continues to be set until the gauge is successfully re-enacted,

provided the junction temperature has fallen below the

hysteresis level.

DEFAULT MODE

Default mode refers to the state of the 33977 after an

internal or external reset prior to SPI communication. An

internal reset occurs during V_DDpower-up or if V_PWRfalls

below 4.0 V. An external reset is initiated by the RST pin

driven to Logic [0]. With the exception of the RTZCR full step

time, all of the specific pin functions and internal registers will

operate as though all of the addressable configuration

register bits were set to Logic [0]. This means, for example,

[deleted PV that] the outputs will be disabled after a power-

up or external reset, and SO flag OD6 and OD8 are set,

indicating an undervoltage event. Anytime an external reset

is exerted and the default is restored, all configuration

parameters [replaced e.g. with such as] such as clock

calibration, maximum speed, and RTZ parameters are lost

and must be reloaded.

OVERVOLTAGE FAULT REQUIREMENTS

The device is capable of surviving V_PWRvoltages within

the maximum specified in Maximum Ratings, Table 2. V_PWR

levels resulting in an overvoltage shutdown condition can

result in uncertain pointer positions. Therefore, the pointer

position should be re-calibrated. The master will be notified of

an overvoltage event via the SO pin if the device status is

selected. Overvoltage detection and notification occurs

regardless of whether the gauge(s) are enabled or disabled.

OVERCURRENT FAULT REQUIREMENTS

Outcome currents are limited to safe levels allowing the

device to rely on thermal shutdown to protect itself.

FAULT LOGIC REQUIREMENTS

The 33977 device indicates each of the following faults as

they occur:

UNDERVOLTAGE FAULT REQUIREMENTS

Undervoltage V_PWRconditions may result in uncertain

pointer positions. Therefore, the internal clock and the pointer

position may require re-calibration. The state machine

continues to operate with V_PWRvoltage levels as low as 4.0

V; however, the coil voltages may be clipped. Notification of

an undervoltage event is provided via the SO pin.

• Overtemperature fault

• Undervoltage V_PWR

• Overvoltage V_PWR

• Clock Out of Specification [Formalized spec]

These fault bits remain enabled until they are clocked out

of the SO pin with a valid SPI message.

RESET (SLEEP MODE)

Overcurrent faults are not reports directly; however, it is

likely an overcurrent condition will become a thermal issue

and be reported.

The device can reset internally or externally. If the V_DD

level falls below the V_DDUVlevel, the device resets and

powers up in the Default mode. See Static Electrical

Characteristics table under the sub-heading: Power Input in

Table 3. Similarly, if the RST pin is driven to Logic [0], then

the device resets to its default state. The device consumes

the least amount of current (I_DDand I_PWR) when the RST pin

is Logic [0]. This is also referred to as the Sleep mode.

OVERTEMPERATURE FAULT REQUIREMENTS

The 33977 incorporates overtemperature protection

circuitry, shutting off the gauge driver when an excessive

temperature is detected. In the event of a thermal overload,

the gauge driver is automatically disabled and the fault is

flagged via the OT device status bit. The indicating flag

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FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

Figure 11 and Figure 12. [figure numbers changed due to

SPI PROTOCOL DESCRIPTION

template formatting]

The SPI interface has a full-duplex, three-wire

synchronous,16-bit serial synchronous interface data

transfer and four I/O lines associated with it: Chip Select

(CS), Serial Clock (SCLK), Serial Input (SI), and Serial Output

(SO). The SI/SO pins of the 33977 follow a first in/first out

(D15/D0) protocol with both input and output words

transferring the most significant bit first. All inputs are

compatible with 5.0 V CMOS logic levels.

It transitions one time per bit transferred at an operating

frequency, f_SPI, defined in the SPI Interface Timing section of

the Dynamic Electrical Characteristics Table 4. It is idle

between command transfers. The pin is 50 percent duty

cycle, with CMOS logic levels. This signal is used to shift data

to and from the device.

SERIAL OUTPUT (SO)

CHIP SELECT (CS)

The SO data pin is a tri-stateable output from the Shift

register. This output will remain tri-stated unless the device is

selected by a low CS signal. The output signal generated will

have CMOS logic levels and the output will transition on the

rising edges of SCLK. The serial output data provides status

feedback and fault information for each output and is returned

MSB first when the device is addressed.

The CS pin enables communication with the master

device.

When this pin is in a Logic [0] state, the 33977 is capable

of transferring information to, and receiving information from,

the master. The 33977 latches data in from the Input Shift

registers to the addressed registers on the rising edge of CS.

The output driver on the SO pin is enabled when CS is Logic

[0]. When CS is logic high, signals at the SCLK and SI pins

are ignored and the SO pin is tri-stated (high impedance). CS

will only be transitioned from a Logic [1] state to a Logic [0]

The Status register bits are the first 16 bits shifted out.

Those bits are followed by the message bits clocked in FIFO,

when the device is in a daisy chain connection, or being sent

words [that are deleted as PV] multiples of 16 bits. Data is

shifted on the rising edge of the SCLK signal. The SO pin

[will deleted as PV] remains in a high impedance state until

the CS pin is put into a logic low state.

state when SCLK is Logic [0]. CShas an internal pull-up (I_UP

)

connected to the pin, as specified in the section of the Static

Electrical Characteristics table entitled CONTROL I/O,

[which is found on page...deleted for consistent format]

Table 3. This pin is also used to calibrate the internal clock.

SERIAL INPUT (SI)

The SI pin is the input of the SPI. This input has an internal

active pull-down requiring CMOS logic levels. The serial data

transmitted on this line is a 16-bit control command sent MSB

first, controlling the gauge functions. The master ensures

data is available on the falling edge of SCLK.

SERIAL CLOCK (SCLK)

SCLK clocks the Internal Shift registers of the 33977

device. The SI pin accepts data into the Input Shift register on

the falling edge of the SCLK signal, while the Serial Output

pin (SO) shifts data information out of the SO line driver on

the rising edge of the SCLK signal. It is important the SCLK

pin be in a Logic [0] state whenever the CS makes any

transition. SCLK has an internal pull-down (l_DWN), as

specified in the section Control I/O of the Static Electrical

Characteristics, [which is found on page...deleted for

consistent format] Table 3. When CS is Logic [1], signals at

the SCLK and SI pins are ignored and SO is tri-stated (high

impedance). Refer to the data transfer timing diagrams in

Serial input information is read on the falling edge of

SCLK. A 16-bit stream of serial data is required on the SI pin,

beginning with the most significant bit (MSB). Messages [that

are deleted as PV] not multiples of 16 bits (e.g., daisy

chained device messages) are ignored. After transmitting a

16-bit word, the CSpin must be de-asserted (Logic [1]) before

transmitting a new word. SI information is ignored when CS

is in a logic high state.

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20

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

This section provides a description of the 33977 SPI

behavior. To follow the explanation below, please refer to

Table 7 and to the timing diagrams illustrated in Figure 11

and Figure 12.

Table 7. Data Transfer Timing

Description

CS (1-to-0)

CS (0-to-1)

SO

SO pin is enabled

33977 configuration and desired output states are transferred and executed according to the data in the Shift registers

Will change state on the rising edge of the SCLK pin signal

SI

Will accept data on the falling edge of the SCLK pin signal

CS

Output Shift register is loaded here

Note: SO is tri-stated when CS is Logic [1]

Figure 11. Single 16-Bit Word SPI Communication

CS

SCLK

SI

D2

D12 D11

0D12 OD

SO

Notes:

1. SO is tri-stated when CS is Logic [1].

2. D15, D14, D13, , and D0 refer to the first 16 bits of data into the 33977.

3. D15*, D14*, D13*,. . . ., and D0* refer to the most recent entry of program data into the 33977.

4. OD15, OD14, OD13, . . .,and OD0 refer to the first 16 bits of fault and status data out of the 33977.

Figure 12. Multiple 16-Bit Word SPI Communication

DATA INPUT

DATA OUTPUT

The Input Shift register captures data at the falling edge of

the SCLK. The SCLK pulses exactly 16 times only inside the

transmission windows (CS in a Logic [1] state). By the time

the CS signal goes to Logic [1] again, the contents of the

Input Shift register are transferred to the appropriate internal

register addressed in bits 15:13. The minimum time CS

should be kept high depends on the internal clock speed,

specified in the SPI Interface Timing section of the [Static

replaced with Dynamic - correcting table location] Dynamic

Electrical Characteristics, Table 4. It must be long enough so

the internal clock is able to capture the data from the Input

Shift register and transfer it to the internal registers.

At the first rising edge of the SCLK [clock deleted to

eliminate redundancy], with CS at Logic [1], the contents of

the selected Status Word register are transferred to the

Output Shift register. The first 16 bits clocked out are the

status bits. If data continues to clock in before the CS

transitions to Logic [1], the device begins to shift out the data

previously clocked in FIFO after the CS first transitioned to

Logic[1].

COMMUNICATION MEMORY MAPS AND

REGISTER DESCRIPTIONS

The 33977 device is capable of interfacing directly with a

microcontroller via the 16-bit SPI protocol specified below.

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FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

The device is controlled by the microprocessor and reports

back status information via the SPI. This section provides a

detailed description of all registers accessible via serial

interface. The various registers control the behavior of this

device.

• Battery overvoltage

• Battery undervoltage

• Pointer zeroing status

• Internal clock status

• Confirmation of pointer movement commands

• Real time pointer position information

• Real time pointer velocity step information

• Pointer movement direction

• Command pointer position status

• RTZ accumulator value

A message is transmitted by the master beginning with the

MSB (D15) and ending with the LSB (D0). Multiple messages

can be transmitted in succession to accommodate those

applications where daisy chaining is desirable, or to confirm

transmitted data, as long as the messages are all multiples of

16 bits. Data is transferred through daisy-chained devices, as

illustrated in Figure 12. If an attempt is made to latch in a

message smaller than 16 bits wide, it is ignored.

REGISTER DESCRIPTIONS

The following section describes the registers, their

addresses, and their impact on device operation.

Table 8 lists the five registers the 33977 uses to configure

the device, control the state of the [Chgd to two per D.

Mortensen] two H-bridge outputs, and determine the type of

status information [that is deleted PV] clocked back to the

master. The registers are addressed via D15:D13 of the

incoming SPI word.

ADDRESS 000 - POWER, ENABLE, CALIBRATION,

AND CONFIGURATION REGISTER (PECCR)

The Power, Enable, Calibration, and Configuration

Register is illustrated in Table 9. A write to the 33977 using

this register allows the master to:

Table 8. Module Memory Map

Address

• Enable or disable the output drivers of the gauge

controller

• Calibrate the internal clock

Register

Name

See

[15:13]

000

Power, Enable, Calibration, and

Configuration Register

PECCR

Table

9

• Disable the air core emulation

• Select the direction of the pointer movement during

pointer positioning and zeroing

• Configure the device for the desired status information

to be clocked out into the SO pin, or

• Send a null command for the purpose of reading the

status bits.

001

010

Maximum Velocity Register

VELR

POSR

Table

10

Gauge Position Register

Table

11

011

100

Not Used

–

This register is also used to place the 33977 into a low

current consumption mode.

Return to Zero Register

RTZR

Table

12

The gauge drivers can be enabled by writing Logic [1] to

the assigned address bits, PE0. This feature could be used

to disable a driver if it is failing. The device can be placed into

a standby current mode by writing Logic [0] to PE0. During

this state, most current consuming circuits are biased off.

When in the Standby mode, the internal clock will remain ON.

101

Return to Zero Configuration

Register

RTZCR

Table

13

110

111

Not Used

RMPSELR

–

Reserved for Test

The internal state machine utilizes a ROM table of step

times defining the duration that the motor will spend at each

microstep as it accelerates or decelerates to a commanded

position. The accuracy of the acceleration and velocity of the

motor is directly related to the accuracy of the internal clock

Although the accuracy of the internal clock is temperature

independent, the non-calibrated tolerance is +70% to -35%.

The 33977 was designed with a feature allowing the internal

clock to be software calibrated to a tighter tolerance of ±10%,

using the CS pin and a reference time pulse provided by the

microcontroller.

[The word Zero omitted above in 101 my error]

MODULE MEMORY MAP

Various registers of the 33977 SPI module are addressed

by the three MSBs of the 16-bit word received serially.

Functions to be controlled include:

• Individual gauge drive enabling

• Power-up/down

• Internal clock calibration

• Gauge pointer position and velocity

• Gauge pointer zeroing

Calibration of the internal clock is initiated by writing Logic

[1] to PE3. The calibration pulse, which must be 8.0 µs for an

internal clock speed of 1.0 MHz, will be sent on the CS pin

immediately after the SPI word is sent. No other SPI lines will

be toggled. A clock calibration will be allowed only if the

gauge is disabled or the pointer is not moving, as indicated

• Air core motor movement emulation

• Status information

Status reporting includes:

• Individual gauge overtemperature condition

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FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

by status bits MOV0. Additional details are provided in the

Internal clock Calibration section.

Similarly, this bit must always be written as Logic [1] when

being used to control Switec style motors.

Some applications may require a guaranteed maximum

pointer velocity and acceleration. Guaranteeing these fall

below 1.0 MHz. The frequency range of the calibrated clock

maximums requires [that deleted PV] the nominal internal

clock frequency will always be below 1.0 MHz if bit PE4 is

Logic [0] when initiating a calibration command, followed by

an 8.0 µs reference pulse. The frequency will be centered at

1.0 MHz if bit PE4 is Logic [1]. Some applications may require

a slower calibrated clock due to a lower motor gear reduction

ratio. Writing Logic [1] to bit PE2 will slow the internal

oscillator by one-third. Slowing the oscillator accommodates

a longer calibration pulse without overrunning the internal

counter - a condition designed to generate a CAL fault

indication. For example, calibration for a clock frequency of

667 kHz would require a calibration pulse of 12 µs. Unless the

internal oscillator is slowed by writing PE2 to Logic [1], a 12

µs calibration pulse may overrun the counter and generate a

CAL fault indication.

The default Pointer Position 0 (PE7 = 0) will be the farthest

counter-clockwise position. A Logic [1] written to bit PE7 will

change the location of the position 0 for the gauge to the

farthest clockwise position. The pointer will always move

towards position 0 when executing an RTZ. Exercise care

when writing to PECCR bit PE7 in order to prevent an

accidental change of the position 0 location.

Bits PE11:PE9 determine the content of the bits clocked

out of the SO pin. When bit PE11 is at Logic [0], the clocked

out bits will provide device status. If Logic [1] is written to bit

PE11, the bits clocked out of the SO pin, depending upon the

state of bits PE10:PE9, provides either:

• Accumulator information and detection status during

the RTZ (PE10 Logic [0])

• Real time pointer position location at the time CS goes

low (PE10 Logic [1] and PE9 Logic [0]), or

• The real time step position of the pointer as described

in the velocity Table 6 (PE10 and PE9 Logic [1]).

Some applications may require faster pointer positioning

than is provided with the air core motor emulation feature.

Writing Logic [1] to bit PE5 will disable the air core emulation

for both gauges and provide an acceleration and deceleration

at the maximum that the velocity position ramp can provide.

Bit PE6 must always be written Logic [0] during all PECCR

writes if the device is being used to drive an MMT style motor.

Additional details are provided in the SO Communication

section.

If bit PE12 is Logic [1] during a PECCR command, the

state of PE11:PE0 is ignored. This is referred to as the null

command and can be used to read device status without

affecting device operation.

Table 9. Power, Enable, Calibration, and Configuration Register (PECCR)

Address 000

Bits

D12

–

D11

–

D10

–

D9

–

D8

–

D7

–

D6

–

D5

–

D4

–

D3

–

D2

–

D1

–

D0

–

Read

Write

PE12

PE11

PE10

PE9

0

PE7

PE6

PE5

PE4

PE3

PE2

0

PE0

Pointer Position or Pointer Speed Select (PE9) Bit D9

The bits in Table 9 are write-only.

This bit is recognized only if PE11 and PE10 = 1.

Null Command for Status Read (PE12) Bit D12

• 0 = Gauge Pointer Position

• 1 = Gauge Pointer Speed

• 0 = Disable

• 1 = Enable

(PE8) Bit D8

Status Select (PE11) Bit D11

This bit must be transmitted as Logic [0] for valid PECCR

commands.

This bit selects the information clocked out of the SO pin.

• 0 = Device Status (the logic states of PE10, and PE9

are don’t cares)

Position 0 Location Select (PE7) Bit D7

• 1 = RTZ Accumulator Value, Gauge Pointer position, or

Gauge Velocity ramp position (depending upon the

logic states of PE10, and PE9)

This bit determines the Position 0 of the gauge. RTZ

direction will always be to the position 0.

• 0 = Position 0 is the most CCW (counterclockwise)

position

• 1 = Position 0 is the most CW (clockwise) position

RTZ Accumulator or Pointer Status Select (PE10) Bit D10

This bit is recognized only when PE11 = 1.

Motor Type Selection (PE6) Bit D6

• 0 = RTZ Accumulator Value and status

• 1 = Pointer Position or Speed

• 0 = MMT Style (coil phase difference = 90°)

• 1 = Switec Style (coil phase difference = 60°)

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FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

Air Core Motor Emulation (PE5) Bit D5

Gauge Enable (PE0) Bit D0

This bit is enabled or disabled (acceleration and

deceleration is constant if disabled).

This bit enables or disables the output drivers of the

Gauge.

• 0 = Enable

• 1 = Disable

• 0 = Disable

• 1 = Enable

Clock Calibration Frequency Selector (PE4) Bit D4

ADDRESS 001 - MAXIMUM VELOCITY REGISTER

(VELR)

• 0 = Maximum f =1.0 MHz (for 8.0 µs calibration pulse)

• 1 = Nominal f =1.0 MHz (for 8.0 µs calibration pulse)

The Gauge Maximum Velocity Register is used to set a

maximum velocity for the gauge (refer to Table 4). Bits V7:V0

contain a position value from 1 - 225 representative of the

velocity position value described in the Velocity Table,

Table 6. The table value becomes the maximum velocity until

it is changed to another value. If a maximum value is chosen

that is greater than the maximum velocity of the acceleration

Clock Calibration Enable (PE3) Bit D3

This bit enables or disables the clock calibration.

• 0 = Disable

• 1 = Enable

table, the maximum table value becomes the maximum

velocity.

Oscillator Adjustment (PE2) Bit D2

• 0 = t_CLU

• 1 = 0.66 x t_CLU

If the motor is turning at a speed greater than the new

maximum, the motor immediately moves down the velocity

ramp until the speed falls equal to or below it. Bit V8 must be

written to a Logic [1] when changing the maximum velocity of

the motor. Bits V12:V10 must be at Logic [0] for valid VELR

commands.

(PE1) Bit D1

This bit must be transmitted as Logic [0] for valid PECCR

commands

.

Table 10. Maximum Velocity Register (VELR)

Address 001

Bits

D12

–

D11

–

D10

–

D9

–

D8

–

D7

–

D6

–

D5

–

D4

–

D3

–

D2

–

D1

–

D0

–

Read

Write

0

V8

V7

V6

V5

V4

V3

V2

V1

V0

(V7:V0) Bits D7:D0

The bits in Table 10 are write-only.

These bits can be used to program the device to limit the

maximum velocity of the pointer movement. to one of over

200 speeds listed in the Velocity Table 6. This velocity will

remain the maximum of the intended gauge until changed by

command. Velocities can range from position 1 (00000001)

to position 225 (11111111).

(V12:V9) Bits D12:D9

These bits must be transmitted as Logic [0] for valid VELR

commands.

Gauge Velocity (V8) Bit D8

Enables the maximum velocity as determined in the V7:

V0.

ADDRESSES 010 - GAUGE POSITION REGISTER

(POSR)

• 0 = Velocity change disabled

• 1 = Velocity change enabled

SI Address 010 (Gauge Position Register) register bits

PO11: PO0 are written to when communicating the desired

pointer positions. Commanded positions can range from 0 to

4095

Table 11. Gauge Position Register (POSR)

Address 010

Bits

D12

–

D11

–

D10

–

D9

–

D8

–

D7

–

D6

–

D5

–

D4

–

D3

–

D2

–

D1

–

D0

–

Read

Write

0

P011

P010

P09

P08

P07

P06

P05

P04

P03

P02

P01

P00

The bits in Table 11 are write-only.

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FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

PO012 (D12)

steps, where only one coil is driven at any point in time. The

back electromotive force (EMF) signal present on the non-

driven coil is integrated and its results are stored in an

accumulator. A Logic [1] written to bit RZ1 enables a Return

to Zero for the Gauge if RZ0 is Logic [0]. A Logic [0] written to

This bits must be transmitted as Logic [0] for valid POSR

commands.

P011:P00 (D11:D0)

bit RZ1 disables a Return to Zero for the Gauge when RZ0 is

Logic [0].

Desired pointer position of Gauge. Pointer positions can

range from 0 (000000000000) to position 4095

(111111111111). For a stepper motor requiring 12

microsteps per degree of pointer movement, the maximum

pointer sweep is 341.25° (4095 ÷ 12).

Bits D12:D5 and D3:D2 must be written Logic [0] for valid

RTZR commands. An unconditional RTZ event can be

enabled or disabled with Bit RZ4. Writing Logic [0] results in

a typical RTZ event, automatically providing a Stop when a

stall condition is detected. A Logic [1] will result in RTZ

movement, causing a Stop if a Logic [0] is written to bit RZ0.

This feature is useful during development and

ADDRESS 100 - GAUGE RETURN TO ZERO

REGISTER (RTZR)

Gauge Return to Zero Register (RTZR), Table 12 below,

is written to return the gauge pointers to the zero position.

During an RTZ event, the pointer is returned to zero using full

characterization of RTZ requirements.

Table 12. Gauge Return to Zero Register (RTZR)

Address 100

Bits

D12

–

D11

–

D10

–

D9

–

D8

–

D7

–

D6

–

D5

–

D4

–

D3

–

D2

–

D1

–

D0

–

Read

Write

0

RZ4

0

RZ2

RZ1

0

(RZ0) Bit D0

Return to Zero Enable. This bit must always be written

Logic [0].

The register bits in Table 12 are write-only.

(RZ12:RZ5) Bits D12:D5

These bits must be transmitted as Logic [0] for valid

commands.

ADDRESS 101 - GAUGE RETURN TO ZERO

CONFIGURATION REGISTER

(RZ4) Bit D4

Gauge Return to Zero Configuration Register (RTZCR) is

used to configure the Return to Zero Event, Table 13. It is

written to modify the: [listed as bullets for reading ease]

This bit is used to enable an unconditional RTZ event.

• 0 = Automatic Return to Zero

• 1 = Unconditional Return to Zero

• Step time, or rate at which the pointer moves during an

RTZ event

• Integration blanking time, which is the time immediately

following the transition of a coil from a driven state to an

open state in the RTZ mode

(RZ3) Bit D3

This bit must be transmitted as Logic [0] for valid

commands.

• Threshold of the RTZ integration register

Values used for this register should be selected during

development to optimize the RTZ for each application.

Selecting an RTZ step rate resulting in consistently

successful zero detections depends on a clear understanding

of the motor characteristics. Specifically, resonant

frequencies exist due to the interaction between the motor

and the pointer. This command allows for the selection of an

RTZ pointer speed away from these frequencies. Also, some

motors require a significant amount of time for the pointer to

settle to a steady state position when moving from one full

step position to the next. Consistent and accurate integration

values require that the pointer be stationary at the end of the

full step time.

(RZ2) Bit D2

Return to Zero Direction bit. This bit is used to properly

sequence the integrator, depending upon the desired zeroing

direction.

• 0 = Return to Zero will occur in the CCW direction

(PE7 = 0)

• 1 = Return to Zero will occur in the CW direction

(PE7 =1)

(RZ1) Bit D1

Return to Zero Enable. This bit commands the gauge to

return the pointer to zero position.

Bits RC3:RC0, RC12:RC11, and RC4 determine the time

spent at each full step during an RTZ event. Bits RC3:RC0

are used to select a ∆t ranging from 0 ms (0000) to 61.44 ms

• 0 = Return to Zero Disabled

• 1 = Return to Zero Enabled

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FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

(1111) in increments of 4.096 ms (refer to Table 14). The ∆t

is multiplied by the factor M, defined by bits RC12:RC11. The

product is then added to the blanking time, selected using bit

RC4, to generate the full step time. The multiplier selected

with RC12:RC11 will be 1 (00), 2 (01), or 4 (10) as illustrated

in the equations below. Note that the RC12:RC11 value of 8

(11) is not recommended for use in a product design

application, because of the potential for an RTZ accumulator

internal overflow, due to the long time step. The blanking time

is either 512 µs when RC4 is Logic [0], or 768 µs when it is

Logic [1].The full step time is calculated using the following

equations:

and is compared to a threshold. Values above the threshold

indicate a pointer is moving. Values below the threshold

indicate a stalled pointer, thereby resulting in the cessation of

the RTZ event.

The RTZ accumulator bits are signed and represented in

two’s complement. After a full step of integration, a sign bit of

0 is the indicator of an accumulator exceeding the decision

threshold of 0, and the pointer is assumed to still be moving.

Similarly, if the sign bit is Logic [1] after a full step of

integration, the accumulator value is negative and the pointer

is assumed to be stopped. The integrator and accumulator

are initialized after each full step. If the PECCR command is

written to clock out the RTZ accumulator values via the SO,

the OD14 bit corresponds to the sign bit of the RTZ

accumulator.

When D3:D0 (RC3:RC0) = 0000

Full Step (t) = ∆t x M+ blanking (t)

(1)

When D3:D0 (RC3:RC0) = 0000

Accurate pointer stall detection depends on a correctly

preloaded accumulator for specific gauge, pointer, and full

step combinations. Bits RC10:RC5 are used to offset the

initial RTZ accumulator value, properly detecting a stalled

motor. The initial accumulator value at the start of a full step

of integration is negative. If the accumulator was correctly

preloaded, a free moving pointer will result in a positive value

at the end of the integration time, and a stalled pointer will

result in a negative value. The preloaded values associated

with each combination of bits RC10:RC5 are illustrated in

Table 15. The accumulator should be loaded with a value

resulting in an accumulator MSB to Logic [1] when the motor

is stalled. For the default mode, after a power-up or any reset,

the 33977 device sets the accumulator value to -1.

Full Step (t) = blanking (t) + 2.048 ms (2)

Note: In equation (2), a 2.048 ms offset is added to the full

step time when the RC3:RC0 = 0000. The full step time

default value after a logic reset is 12.80 ms (RC12:RC11 =

00, RC4 = 0, and RC3:RC0 = 0011).

If there are two full steps per degree of pointer movement,

the pointer speed is 1/(Full Step x 2) deg/s.

Detecting pointer movement is accomplished by

integrating the EMF present in the non-driven coil during the

RTZ event. The integration circuitry is implemented using a

Sigma-Delta converter resulting in the placement of a value

in the 15-bit RTZ accumulator at the end of each full step. The

value in the RTZ accumulator represents the change in flux

Table 13. Return to Zero Register Configuration Register (RTZCR)

Address 101

Bits

D12

–

D11

–

D10

–

D9

–

D8

–

D7

–

D6

–

D5

–

D4

–

D3

–

D2

–

D1

–

D0

–

Read

Write

RC12

RC11

RC10

RC9

RC8

RC7

RC6

RC5

RC4

RC3

RC2

RC1

RC0

The bits in Table 13 are write-only.

Values range from -1 (00000000) to -1009 (11111111) as

shown in Table 15, the default value = 000000.

(RC12:RC11) Bits D12:D11

(RC4) Bit D4

These bits, along with RC3:RC0 (D3:D0) and RC4 (D4),

determine the full step time and, therefore, the rate at which

the pointer will move during an RTZ event. The values of

D12:D11 determine the multiplier (M) used in equation (1)

(refer to the previous page).

This bit determines the RTZ blanking time (blanking (t)).

The default value = 0

• 0 = 512 µs

• 1 = 768 µs

RC12:RC11 = M; default value = 00

(RC3:RC0) Bits D3:D0

• 00 = 1

• 01 = 2

• 10 = 4

These bits, along with RC12:RC11 (D12:D11) and RC4

(D4), determine the time variables used to calculate the full

step times with equations (1) or (2) illustrated above.

RC3:RC0 determines the ∆t time. The ∆t values range from 0

(0000) to 61.440 ms (1111) and are shown in Table 14. The

default ∆t is 0 (0011).

• 11 = 8 (Not to be used for design)

(RC10:RC5) Bits D10:D5

These bits determine the value preloaded into the RTZ

integration accumulator to adjust the detection threshold.

Note: Equation (2) (refer to the preceding page) is only

used to calculate the full step time if RC3:RC0 = 0000. Use

equation (1) for all other combinations of RC3:RC0.

33977

Analog Integrated Circuit Device Data

Freescale Semiconductor

26

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

Table 14. RTZCR Full Step Time

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

32.768

36.864

40.960

45.056

49.152

53.248

57.344

61.440

RC3

0

RC2

0

RC1

0

RC0

0

∆t (ms)

0.0

0

1

4.096

0

1

0

8.192

0

1

12.288

16.384

20.480

24.576

28.672

0

1

0

1

0

1

0

1

0

1

Table 15. RTZCR Accumulator Offset

RC10

RC9

RC8

RC7

RC6

RC5

Preload Value

Initial Accumulator Value = (-16xPV) -1

0

.

0

1

0

.

0

1

0

1

0

.

0

1

2

3

4

.

-1

-17

-33

-49

-65

.

1

.

1

63

-1009

33977

Analog Integrated Circuit Device Data

Freescale Semiconductor

27

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

PECCR command determines the nature of the status data

that is clocked out of the SO pin. There are four different

types of status information available:

SO COMMUNICATION

When the CS pin is pulled low, the internal status register,

as configured with the PECCR command bits PE11:PE8, is

loaded into the output register and the data is clocked out

MSB (OD15) first. Following a CS transition 0 to 1, the device

determines if the shifted-in message was of a valid length (a

valid message length is one that is greater than 0 bits and a

multiple of 16 bits) and, if so, latches the incoming data into

the appropriate registers. At this time, the SO pin is tri-stated

and the status register is now able to accept new status

information. Fault status information will be latched and held

until the Device Status Output register is selected and it is

clocked out via the SO. If the message length was

1. Device Status (Table 16)

2. RTZ Accumulator Status (Table 17)

3. Gauge Pointer Position Status (Table 18)

4. Gauge Pointer Velocity Status (Table 19)

Once a specific status type is selected, it will not change

until either the PECCR command bits PE11:PE8 (D11:D8)

are written to select another or the device is reset. Each of the

Status types and the PECCR bit necessary to select them ar

described in the following paragraphs.

determined to be invalid, the fault information will not be

cleared and will be transmitted again during the next valid SPI

message. Pointer status information bits (e.g., pointer

position, velocity, and commanded position status) will

always reflect the real time state of the pointer. Any bits

clocked out of the SO pin after the first 16 are representative

of the initial message bits clocked into the SI pin since the CS

pin first transitioned to a Logic [0]. This feature is useful for

daisy-chaining devices as well as message verification. As

described above, the last valid write to bits PE11:PE8 of the

DEVICE STATUS INFORMATION

Most recent valid PECCR command resulting in the Device

Status output:

D11

D10

D9

D8

0

x

x = Don’t Care

Table 16. Device Status Output Register

Bits

OD15 OD14 OD13 OD12 OD11 OD10 OD9

OD8

UV

–

OD7

OD6

OD5

OD4

OD3

ST3

–

OD2

OD1

ST1

–

OD0

OT

–

Read

Write

ST15

–

DIR

–

ST13 0POS ST11 CMD

OV

–

CAL OVUV ST5

MOV

–

RTZ

–

The bits in Table 16 are read-only bits.

• 0 = At commanded position

• 1 = Not at commanded position

(ST15) Bit OD15

Overvoltage Indication (OV) Bit OD9

This bit has no meaning.

A Logic [1] on this bit indicates V_PWRvoltage exceeded the

upper limit of V_PWROVsince the last SPI communication.

Refer to the Static Electrical Characteristics Table 3 under

POWER INPUT.

(DIR) Bit OD14

This bit indicates the direction that the Gauge is moving.

• 0 = Toward position 0

An overvoltage event will automatically disable the driver

outputs. Because the pointer may not be in the expected

position, the master may want to re-calibrate the pointer

position with an RTZ command after the voltage returns to a

normal level. For an overvoltage event, both gauges must be

re-enabled as quickly as this flag returns to Logic [0]. The

state machine will continue to operate properly as long as

V_DDis within the normal range.

• 1 = Away from position 0

(ST13) Bit OD13

This bit has no meaning.

(0POS) Bit OD12

This bit indicates the configured Position 0 for the Gauge.

• 0 = Normal range

• 1 = Battery voltage exceeded V_PWROV

• 0 = Farthest CCW

• 1 = Farthest CW

Undervoltage Indication (UV) Bit OD8

(ST11) Bit OD11

A Logic [1] on this bit indicates the V_PWRvoltage fell below

V_PWRUVsince the last SPI communication. Refer to the Static

Electrical Characteristics Table 3 under the heading of

POWER INPUT. An undervoltage event is just flagged;

however, at some voltage level below 4.0 V, the outputs turn

OFF and the state machine resets. Because the pointer may

This bit has no meaning.

(CMD) Bit OD10

This bit indicates if the Gauge is at the most recently

commanded position.

33977

Analog Integrated Circuit Device Data

Freescale Semiconductor

28

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

not be in the expected position, the master may want to re-

calibrate the pointer position with an RTZ command after the

voltage returns to a normal level. For an undervoltage vent,

both gauges may need to be re-enabled as quickly as this

flag returns to Logic [0]. The state machine will continue to

operate properly as long as V_DDis within the normal range.

This bit may also be used to determine if the Gauge is

enabled or disabled.

• 0 = Gauge position has not changed since the last SPI

command

• 1 = Gauge pointer position has changed since the last

SPI command

• 0 = Normal range

• 1 = Battery voltage fell below V_PWRUV

ST3 (OD3) - This bit has no meaning

Calibrated Clock out of Specification (CAL) Bit OD7

RTZ0 Is Enabled or Disabled (RTZ) Bit OD2

Reading Logic [1] on this bit indicates the clock count

calibrated to a value outside the expected range given the

tolerance specified by t_CLCin the Dynamic Electrical

Characteristics Table 4 under POWER OUTPUT and

CLOCK TIMING.

A Logic [1] on this bit indicates the gauge is in the process

of returning to the zero position as requested with the RTZ

command. This bit continues to indicate Logic [1] until the SPI

message following a detection of the zero position, or the

RTZ feature is commanded OFF using the RTZ message.

• 0 = Clock within specification

• 1 = Clock out of specification

• 0 = Return to Zero disabled

• 1 = Return to Zero enabled successfully

Undervoltage or Overvoltage Indication (OVUV) Bit OD6

(ST1) Bit OD1

A Logic [1] on this bit indicates V_PWRvoltage fell to a level

below the V_PWRUVsince the last SPI communication. Refer

to the Static Electrical Characteristics table, Table 3 under

the subheading INPUT POWER. An undervoltage event is

just flagged, while an overvoltage event automatically

disables the drive outputs. Because the pointer may not be in

the expected position, the master may want to re-calibrate

the pointer with an RTZ command after the voltage returns to

normal level. For an overvoltage event, both gauges must be

re-enabled as soon as this flag returns to Logic [0]. The state

machine will continue to operate properly as long as V_DDis

within the normal range.

This bit has no meaning.

Gauge Driver Junction Overtemperature (OT) Bit OD0

A Logic [1] on this bit indicates that the coil drive circuitry

has exceeded the maximum allowable junction temperature

since the last SPI communication and that the Gauge has

been disabled. It is recommended that the pointer be re-

calibrated using the RTZ command after re-enabling the

gauge using the PECCR command. This bit remains Logic [1]

until the gauge is re-enabled.

• 0 = Temperature within range

• 1 = Maximum allowable junction temperature condition

is reached

• 0 = Normal range

• 1 = Battery voltage fell below V_PWRUVor exceeded

V_PWROV

RTZ ACCUMULATOR STATUS INFORMATION

Most recent valid PECCR command resulting in the RTZ

Accumulator status output:

(ST5) Bit OD5

This bit has no meaning

D11

D10

D9

D8

Gauge Movement Since last SPI Communication (MOV)

Bit OD4

1

0

x

x = Don’t Care

A Logic [1] on this bit indicates the Gauge pointer position

has changed since the last SPI command. This information

allows the master to confirm the pointer is moving as

commanded.

[Used headings to distinguish bits and accompanying text.]

Table 17. RTZ Accumulator Status Output Register

Bits

OD15 OD14 OD13 OD12 OD11 OD10 OD9

OD8

OD7

OD6

OD5

OD4

OD3

OD2

OD1

OD0

Read

Write

RTZ ACC14 ACC13 ACC12 ACC11 ACC10 ACC9 ACC8 ACC7 ACC6 ACC5 ACC4 ACC3 ACC2 ACC1 ACC0

–

The bits in Table 17 are read-only bits.

(RTZ) Bit OD15

RTZ Bit Is Enabled or Disabled. Reading Logic [1] on this

bit indicates that the Gauge is in the process of returning to

the zero position as requested with the RTZ command. This

33977

Analog Integrated Circuit Device Data

Freescale Semiconductor

29

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

bit will continue to indicate Logic [1] until the SPI message

following a detection of the zero position, or after the RTZ

feature is commanded OFF using the RTZ message.

The analog-to-digital converter's linear input range covers

the expected magnitude of motor back e.m.f. signals, which

is usually less than 500mV. Input signals greater than this will

not cause any damage (the circuit is connected to the motor

H-Bridge drivers, and thus is exposed to the full magnitude of

the drive voltages), but may cause some small loss of

linearity. A typical plot of output vs. input is shown in

Figure 13 for 4ms step times.

• 0 = Return to Zero disabled

• 1 = Return to Zero enabled successfully

[Corrected original entry above to ACC2]

(ACC14:ACC0) Bits OD14:OD0

These 15 bits are from the RTZ accumulator. They

represent the integrated signal present on the non-driven coil

during an RTZ event. These bits are Logic [0] after power-on

reset, or after the RST pin transitions from Logic [0] to [1].

After an RTZ event, they will represent the last RTZ

accumulator result before the RTZ was stopped.

GAUGE POINTER POSITION STATUS

INFORMATION

Most recent valid PECCR command resulting in the

Gauge Pointer Position status output:

ACC14 is the MSB and is the sign bit used for zero

detection. Negative numbers have MSB Logic [1] and are

coded in twos complement.

D11

D10

D9

D8

1

0

omitted “don’t care--because N/A

Figure 13. RTZ Accumulator (Typical)

Table 18. Gauge Pointer Position Status Output Register

Bits

OD15 OD14 OD13 OD12 OD11 OD10 OD9

OD8

OD7

OD6

OD5

OD4

OD3

OD2

OD1

OD0

Read

Write

ENB

–

DIR

–

DIRC CMD POS11 POS10 POS9 POS8 POS7 POS5 POS5 POS4 POS3 POS2 POS1 POS0

–

(DIRC) Bit OD13

The bits in Table 18 are read-only bits.

This bit is used to determine whether the direction of the

most recent pointer movement is toward the last commanded

position or away from it.

(ENB) Bit OD15

This bit indicates whether the Gauge is enabled.

• 0 = Direction of the pointer movement is toward the

commanded position

• 1 = Direction of the pointer movement is away from the

commanded position

• 0 = Disabled

• 1 = Enabled

(DIR) Bit OD14

This bit indicates the direction the Gauge is moving.

(CMD) Bit OD12

• 0 = Toward position 0

• 1 = Away from position 0

This bit indicates whether the gauge is at the most recently

commanded position.

• 0 = At commanded position

• 1 = Not at commanded position

33977

Analog Integrated Circuit Device Data

Freescale Semiconductor

30

FUNCTIONAL DEVICE OPERATION

(POS11:POS0) Bits OD11:OD0

D11

D10

D9

D8

These 12 bits represent the actual position of the pointer

at the time CS transitions to a Logic [0].

1

x

x = Don’t Care

GAUGE POINTER VELOCITY STATUS

INFORMATION

Most recent valid PECCR command resulting in the

Gauge and 1 Pointer Velocity status output:

Table 19. Gauge Pointer Velocity STatus Output Register

Bits

OD15 OD14 OD13 OD12 OD11 OD10 OD9

OD8

V8

–

OD7

V7

–

OD6

OD5

V5

–

OD4

OD3

V3

–

OD2

OD1

V1

–

OD0

V0

–

Read

Write

V15

–

V14

–

V13

–

V12

–

V11

–

V10

–

V9

–

V6

–

V4

–

V2

–

(V7:V0) Bits OD7:OD0

The bits in Table 19 are read-only bits.

These eight bits represent the step table value, [that

deleted PV] indicating the actual velocity step location (refer

to Table 19) of the Gauge pointer at the time that the CS

transitions to a Logic [0].

(V15:V8) Bits OD15:OD8

These eight bits have no meaning. Velocity position that

identifies it in the un-truncated ramp (e.g., if RS = 2, then the

velocity step location will be 3 when the pointer is at the

commanded position).

33977

Analog Integrated Circuit Device Data

Freescale Semiconductor

31

TYPICAL APPLICATIONS

The 33977 is an extremely versatile device that can be

used in a variety of applications, Figure 1. The acceleration

and deceleration ramps have been designed for applications

where smooth movement is of the highest priority. These

ramps are fixed and the characteristics can be seen in the

following figures. For applications where configurable pointer

response and damping are desirable, consider the features

of the MC33976. Figure 14 shows the characteristics of the

acceleration ramp.

6000

5000

76ms

4000

Ideal

Acceleration

(4500 deg/s^2)

3000

2000

1000

0

MC33977

Acceleration

0

20000

40000

60000

80000

100000

120000

140000

160000

180000

TIME (us)

Figure 14. Acceleration Response Characteristics

33977

Analog Integrated Circuit Device Data

Freescale Semiconductor

32

TYPICAL APPLICATIONS

Figure 15 illustrates the deceleration damping characteristics of the device with the hold counts enabled and disabled.

1250

1200

1150

1100

1050

1000

950

MC33977

without

Hold Counts

MC33977

with

Hold Counts

900

850

800

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Time (s)

Figure 15. Deceleration Damping Response Examples

Table 20 provides a step-by-step example of configuring

and using many of the features designed into the IC This

example is intended to familiarize users with some of the

device features.

Table 20. 33977 Setup, Configuration, and Usage Example

Reference Table

and/or Figure

Step

Command

Description

a) Enables the gauge

Bit PE0: Gauge enable bit

•

b) Clock calibration

Table 9,

Figure 8

1

PECCR

•

Bit PE3: Enables calibration procedure

Bit PE4: Set clock f = 1.0 MHz maximum or nominal

c) Send 8.0 µs pulse on CS to calibrate 1.0 MHz clock

a) Set RTZ full step time

Table 13

Table 14

•

Bit RC3:RC0

b) Set RTZ blanking time

Bits RC4

c) Preload RTZ accumulator

Bits RC12:RC11 and RC10:RC5

d) Check SO for an out-of-range clock calibration

Is Bit CAL Logic [1}? If so, repeat Steps 1 and 2

Table 15

Table 9

•

2

RTZCR

Table 16

•

a) Move pointer to position 12 prior to RTZ

Table 11

Table 9

4

5

POSR

b) Check SO to determine if gauge has moved

Table 16

•

Is bit MOV (OD4) Logic [1]? If so, the gauge moved to the first microstep

a) Send null command to determine if gauges moved

Bit PE12

b) Check SO to determine if the gauge has moved

•

Table 9

Table 16

PECCR

•

Is bit MOV (OD4) Logic [1]? If so, the gauge moved another microstep since the last

SPI message. Keep track of movement and if 12 steps are finished, and both gauges

are at a static position, the RTZ. Otherwise, repeat steps a) and b).

•

Bit CMD (OD10) could also be monitored to determine if the pointer is static.

33977

Analog Integrated Circuit Device Data

Freescale Semiconductor

33

TYPICAL APPLICATIONS

Table 20. 33977 Setup, Configuration, and Usage Example

Reference Table

and/or Figure

Step

Command

Description

a) Return the gauge to the zero stop using the RTZ command

•

Bit RZ1 enables or disables an RTZ

Bits RZ2 and PE7 select the direction

Table 12

Table 9

6

RTZ

b) Select the RTZ accumulator bits to clock out on the SO bits using bits PE11:PE10.

These will be used if characterizing the RTZ.

Table 15

a) Check the status of the RTZ by sending the null command to monitor bit RTZ of the

Device Status SO.

Table 9

Table 16

•

Bit PE12 is the null command

7

PECCR

VELR

b) Is RTZ (OD2) Logic [1]? If not, the gauge is still returning and null command should be

resent.

a) Change the maximum velocity of the gauge

•

Table 9

Table 6

Bit V8 enables a change to the maximum velocity

Bits V7:V10 determine the maximum velocity position from Table 6, Velocity Table

10

a) Position gauge pointer

Bits P011:P00: Desired pointer position

•

b) Check SO for out-of-range V_PWR

•

Is bit OVUV (OD6) Logic [1] If so, use UV (OD8) and OV (OD9) to decide whether to

RTZ after valid V_PWR

Table 11

Table 6

11

POSR

c) Check SO for overtemperature

•

Is bit OT Logic [1]? If so, enable driver again. If OT continues to indicate

overtemperature, shut down the gauge.

•

Once OT returns to normal, re-establish the zero reference by RTZ command.

a) Return the pointer close to zero position using POSR

13

15

POSR

Table 11

b) Move pointer position at least 12 microsteps CW to the nearest full step prior to RTZ

f) Send null command to see if gauges moved

•

Bit PE12

g) Check SO to determine if the gauge moved.

Table 9

Table 16

PECCR

•

Is bit MOV (OD4) Logic [1]? If so, the gauge moved another microstep since the last

SPI message. Keep track of movement and if 12 steps are finished, and both gauges

are at a static position, then RTZ. Otherwise, repeat steps a) and b).

•

Bit CMD (OD10) could also be monitored to determine the pointer is static.

a) Return the gauge to the zero stop using the RTZ command.

•

Bit RZ1 enables or disables an RTZ

Bits RZ2 and PE7 select the direction

TABLE 9

TABLE 12

TABLE 16

RTZ

16

b) Select the RTZ accumulator bits clocking out on the SO bits using bits PE11:PE10

These will be used if characterizing the RTZ.

a) Check the status of the RTZ by sending the null command to monitor SO bit RTZ

TABLE 9

TABLE 16

•

Bit PE12 is the null command

PECCR

17

20

b) Is RTZ Logic [0]? If not, the gauge is still returning and null command should be resent

a) Disable the gauge driver and go to standby

•

Bit PE0:PE1 disable the gauge

b) Put the device to sleep

RST pin is pulled to Logic [0]

TABLE 9

•

33977

Analog Integrated Circuit Device Data

Freescale Semiconductor

34

PACKAGING

PACKAGE DIMENSIONS

PACKAGING

PACKAGE DIMENSIONS

For the most current revision of the package, visit www.freescale.com and do a keyword search using the “98A” number listed

below.

DW SUFFIX

EG SUFFIX (PB-FREE)

24-PIN

PLASTIC PACKAGE

98ASB42344B

ISSUE F

33977

Analog Integrated Circuit Device Data

Freescale Semiconductor

35

REVISION HISTORY

REVISION

1.0

DATE

8/2006

1/2007

DESCRIPTION OF CHANGES

• Initial release

• Updated to the current Freescale format

2.0

• Revised Internal Block Diagram to enhance readability

• Added parameter Peak Package Reflow Temperature During Reflow ⁽⁴⁾

and notes ⁽⁴⁾and ⁽⁵⁾

,

⁽⁵⁾on page 4

• Made wording additions to Address 101 - Gauge Return to Zero Configuration Register

on page 25 and (RC12:RC11) Bits D12:D11 on page 26

,

• Added ADC Gain ^{(12) (14)}to Static Electrical Characteristics table

• Added RTZ Accumulator (Typical) on page 30 and accompanying text

33977

Analog Integrated Circuit Device Data

Freescale Semiconductor

36

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MC33977

Rev. 2.0

1/2007


型号：	MC33977DW
厂家：	Freescale
描述：	Single Gauge Driver 单计驱动器驱动器仪表
文件：	总37页 (文件大小：1775K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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