MCF51AG96VQH [FREESCALE]
MCF51AG128 ColdFire Microcontroller; MCF51AG128的ColdFire微控制器
| 型号： | MCF51AG96VQH |
| 厂家： | 
Freescale |
| 描述： | MCF51AG128 ColdFire Microcontroller |
| 文件： | 总50页 (文件大小：1625K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Freescale Semiconductor
Data Sheet: Technical Data
Document Number: MCF51AG128
Rev. 5, 6/2010
MCF51AG128
80 LQFP
64 LQFP
MCF51AG128 ColdFire
Microcontroller
Covers: MCF51AG128 and
MCF51AG96
14 mm × 14 mm
10 mm × 10 mm
48 LQFP
7 mm x 7mm
64 QFP
14 mm × 14 mm
®
The MCF51AG128 is a member of the ColdFire family of
– Low-voltage detection with reset or interrupt
– Separate low voltage warning with selectable trip points
– Illegal opcode and illegal address detection with reset
– Flash block protection for each array to prevent
accidental write/erasure
32-bit variable-length reduced instruction set (RISC)
microcontroller. This document provides an overview of the
MCF51AG128 series MCUs, focusing on its highly
integrated and diverse feature set.
– Hardware CRC module to support fast cyclic
redundancy checks
• Debug Support
The MCF51AG128 derivative are low-cost, low-power, and
high-performance 32-bit ColdFire V1 microcontroller units
(MCUs) designed for industrial and appliance applications. It
is an ideal upgrade for designs based on the MC9S08AC128
series of 8-bit microcontrollers.
– Single-wire back ground debug interface
– Real-time debug support, with six hardware breakpoints
(4 PC, 1 address pair and 1 data) that can be configured
into a 1- or 2-level trigger
– On-chip trace buffer provides programmable start/stop
recording conditions
The MCF51AG128 features the following functional units:
®
• 32-bit Version 1 ColdFire central processor unit (CPU)
– Up to 50.33 MHz ColdFire CPU from 2.7 V to 5.5 V
– Provide 0.94 Dhrystone 2.1 DMIPS per MHz
performance when running from internal RAM (0.76
DMIPS per MHz when running from flash)
– Implements Coldfire Instruction Set Revision C
(ISA_C)
– Support for real-time program (and optional partial data)
trace using the debug visibility bus
• DMA Controller
– Four independently programmable DMA channels
provide the means to directly transfer data between
system memory and I/O peripherals
– DMA enabled peripherals include IIC, SCI, SPI, FTM,
HSCMP, ADC, RTC, and eGPIO, and the DMA request
from these peripherals can be configured as DMA
source or as an iEvent input
• On-chip memory
– Up to 128 KB flash memory read/program/erase over
full operating voltage and temperature
– Up to 16 KB random access memory (RAM)
– Security circuitry to prevent unauthorized access to
RAM and flash contents
• CF1_INTC
• Power-Saving Modes
– Support of 44 peripheral I/O interrupt requests and seven
software (one per level) interrupt requests
– Fixed association between interrupt request source, level
and priority, up to two requests can be remapped to the
highest maskable level and priority
– Unique vector number for each interrupt source
– Support for service routine interrupt acknowledge
(software IACK) read cycles for improved system
performance
– Three ultra-low power stop modes and reduced power
wait mode
– Peripheral clock enable register can disable clocks to
unused modules, thereby reducing currents
• System Protection
– Advanced independent clocked watchdog (WDOG)
with features like, robust refresh mechanism, windowed
mode, high granulation timeout, fast test of timeout, and
always forces a reset
– Additional external watchdog monitor (EWM) to help
reset external circuits
– Ability to mask any individual or all interrupt sources
Freescale reserves the right to change the detail specifications as may be required to permit
improvements in the design of its products.
© Freescale Semiconductor, Inc., 2010. All rights reserved.
• System Clock Sources
– Oscillator (XOSC) — Loop-control pierce oscillator; crystal or ceramic resonator range of 31.25 kHz to 38.4 kHz or 1
MHz to 16 MHz
– Internal Clock Source (ICS) — Frequency-locked-loop (FLL) controlled by internal or external reference; trimmable
internal reference allows 0.2% resolution and 2% deviation (1% across 0 to 70 ºC)
• Peripherals
– ADC — 24 analog inputs with 12 bits resolution; output formatted in 12-, 10- or 8-bit right-justified format; single or
continuous conversion (automatic return to idle after single conversion); interrupt or DMA request when conversion
complete; operation in low-power modes for lower noise operation; asynchronous clock source for lower noise operation;
selectable asynchronous hardware conversion triggers from RTC, PDB, or iEvent; dual samples based on hardware
triggers during ping-pong mode; on-chip temperature sensor
– PDB — 16-bit of resolution with prescaler; seven possible trigger events input; positive transition of trigger event signal
initiates the counter; support continuous trigger or single shot, bypass mode; supports two triggered delay outputs or ORed
together; pulsed output could be used for HSCMP windowing signal
– iEvent — User programmable combinational boolean output using the four selected iEvent input channels for use as
interrupt requests, DMA transfer requests, or hardware triggers
– FTM — Two 6-channel flexible timer/PWM modules with DMA request option; deadtime insertion is available for each
complementary channel pair; channels operate as pairs with equal outputs, pairs with complimentary outputs or
independent channels (with independent outputs); 16-bit free-running counter; the load of the FTM registers which have
write buffer can be synchronized; write protection for critical registers; backwards compatible with TPM
– TPM — 16-bit free-running or modulo up/down count operation; two channels, each channel may be input capture, output
compare, or edge-aligned PWM; one interrupt per channel plus terminal count interrupt
16
12
– CRC — High speed hardware CRC generator circuit using 16-bit shift register; CRC16-CCITT compliancy with x + x
5
+ x + 1 polynomial; error detection for all single, double, odd, and most multi-bit errors; programmable initial seed value
– HSCMP — Two analog comparators with selectable interrupt on rising edge, falling edge, or either edges of comparator
output; the positive and negative inputs of the comparator are both driven from 4-to-1 muxes; programmable voltage
reference from two internal DACs; support DMA transfer
– IIC — Compatible with IIC bus standard and SMBus version 2 features; up to 100 kbps with maximum bus loading;
multi-master operation; software programmable for one of 64 different serial clock frequencies; programmable slave
address and glitch input filter; interrupt driven byte-by-byte data transfer; arbitration lost interrupt with automatic mode
switching from master to slave; calling address identification interrupt; bus busy detection; broadcast and 10-bit address
extension; address matching causes wake-up when MCU is in Stop3 mode; DMA support
– SCI — Two serial communications interface modules with optional 13-bit break; full-duplex, standard non-return-to-zero
(NRZ) format; double-buffered transmitter and receiver with separate enables; 13-bit baud rate selection with /32
fractional divide; interrupt-driven or polled operation; hardware parity generation and checking; programmable 8-bit or
9-bit character length; receiver wakeup by idle-line or address-mark; address match feature in receiver to reduce
address-mark wakeup ISR overhead; 1/16 bit-time noise detection; DMA transmission for both transmit and receive
– SPI — Two serial peripheral interfaces with full-duplex or single-wire bidirectional option; double-buffered transmitter
and receiver; master or slave mode operation; selectable MSB-first or LSB-first shifting; 8-bit or 16-bit data modes;
programmable transmit bit rate; receive data buffer hardware match feature; DMA transmission for transmit and receive
• Input/Output
– Up to 69 GPIOs and one Input-only pin
– Interrupt or DMA request with selectable polarity on all input pins
– Programmable glitch filter, hysteresis and configurable pull up/down device on all input pins
– Configurable slew rate and drive strength on all output pins
– Independent pin value register to read logic level on digital pin
– Up to 16 rapid general purpose I/O (RGPIO) pins connected to the processor’s local 32-bit platform bus with set, clear,
and faster toggle functionality
MCF51AG128 ColdFire Microcontroller, Rev. 5
2
Freescale Semiconductor
Table of Contents
1
2
MCF51AG128 Family Configurations . . . . . . . . . . . . . . . . . . . .4
Table 8. ESD and Latch-Up Protection Characteristics. . . . . . . 17
Table 10. Supply Current Characteristics. . . . . . . . . . . . . . . . . . 21
Table 11.HSCMP Electrical Specifications. . . . . . . . . . . . . . . . . 23
Table 12.5V 12-bit ADC Operating Conditions. . . . . . . . . . . . . . 23
Table 13.5 V 12-bit ADC Characteristics (VREFH = VDDA, VREFL
1.1 Device Comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.2 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
1.4 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Preliminary Electrical Characteristics . . . . . . . . . . . . . . . . . . .14
2.1 Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . .14
2.2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . .14
2.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .15
2.4 Electrostatic Discharge (ESD) Protection Characteristics
16
2.5 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
2.6 Supply Current Characteristics . . . . . . . . . . . . . . . . . . .21
2.7 High Speed Comparator (HSCMP) Electricals . . . . . . .23
2.8 Digital to Analog (DAC) Characteristics . . . . . . . . . . . .23
2.9 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .23
2.10 External Oscillator (XOSC) Characteristics . . . . . . . . .27
2.11 ICS Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
2.12 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
2.12.1 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . .30
2.12.2 Timer (TPM/FTM) Module Timing . . . . . . . . . . .31
2.12.3 SPI Characteristics . . . . . . . . . . . . . . . . . . . . . .32
2.13 Flash Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . .34
2.14 EMC Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
2.14.1 Radiated Emissions. . . . . . . . . . . . . . . . . . . . . .35
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Package Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Mechanical Outline Drawings . . . . . . . . . . . . . . . . . . . . . . . . .37
5.1 80-pin LQFP Package. . . . . . . . . . . . . . . . . . . . . . . . . .37
5.2 64-pin LQFP Package. . . . . . . . . . . . . . . . . . . . . . . . . .40
5.3 64-pin QFP Package. . . . . . . . . . . . . . . . . . . . . . . . . . .43
5.4 48-pin LQFP Package. . . . . . . . . . . . . . . . . . . . . . . . . .46
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
=
V
SSA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 14.Oscillator Electrical Specifications (Temperature Range =
–40 to 105 °C Ambient) . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 15.ICS Frequency Specifications (Temperature Range = –40
to 105 °C Ambient) . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 16.Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 17.TPM/FTM Input Timing . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 18.SPI Timing Characteristics . . . . . . . . . . . . . . . . . . . . . 32
Table 19.Flash Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 20.Orderable Part Number Summary. . . . . . . . . . . . . . . . 36
Table 21.Package Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 22.Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
List of Figures
Figure 1.MCF51AG128 Series MCUs Block Diagram . . . . . . . . . 6
Figure 2.80-Pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 3.64-Pin QFP and LQFP . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 4.48-Pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 5.Typical IOH vs. VDD – VOH (Low Drive,PTxDSn = 0) . . 19
Figure 6.Typical IOH vs. VDD – VOH (High Drive, PTxDSn = 1) . 19
Figure 7.Typical IOL vs. VOL (Low Drive, PTxDSn = 0) . . . . . . . 20
Figure 8.Typical IOL vs. VOL (High Drive, PTxDSn = 1) . . . . . . . 20
Figure 9.Run Current at Different Conditions. . . . . . . . . . . . . . . 22
Figure 10.ADC Input Impedance Equivalency Diagram. . . . . . . 25
Figure 11.Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 12.IRQ/KBIPx Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 13.Timer External Clock . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 14.Timer Input Capture Pulse. . . . . . . . . . . . . . . . . . . . . 31
Figure 15.SPI Master Timing (CPHA = 0) . . . . . . . . . . . . . . . . . 33
Figure 16.SPI Master Timing (CPHA = 1) . . . . . . . . . . . . . . . . . 33
Figure 17.SPI Slave Timing (CPHA = 0) . . . . . . . . . . . . . . . . . . 34
Figure 18.SPI Slave Timing (CPHA = 1) . . . . . . . . . . . . . . . . . . 34
3
4
5
6
List of Tables
Table 1. MCF51AG128 Series Device Comparison. . . . . . . . . . .4
Table 2. MCF51AG128 Series Functional Units . . . . . . . . . . . . . .7
Table 3. Pin Availability by Package Pin-Count. . . . . . . . . . . . . .12
Table 4. Parameter Classifications . . . . . . . . . . . . . . . . . . . . . . .14
Table 5. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . .15
Table 6. Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .15
Table 7. ESD and Latch-up Test Conditions. . . . . . . . . . . . . . . .16
Table 9. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
MCF51AG128 ColdFire Microcontroller, Rev. 5
3
Freescale Semiconductor
MCF51AG128 Family Configurations
1
MCF51AG128 Family Configurations
1.1
Device Comparison
The following table compares the various device derivatives available within the MCF51AG128 series MCUs.
Table 1. MCF51AG128 Series Device Comparison
MCF51AG128
MCF51AG96
Feature
80-pin
64-pin
48-pin
80-pin
64-pin
48-pin
Flash memory size (KB)
RAM size (KB)
128
96
16
ColdFire V1 core with BDM
(background debug module)
Yes
HSCMP (analog comparator)
2
2
1
2
2
1
ADC (analog-to-digital converter)
channels (12-bit)
24
19
12
24
19
12
CRC (cyclic redundancy check)
DAC
Yes
2
2
1
2
2
1
DMA controller
4-ch
Yes
Yes
Yes
Yes
Yes
iEvent (intelligent Event module)
EWM (External Watchdog Monitor)
WDOG (Watchdog timer)
RTC
DBG (debug module)
IIC (inter-integrated circuit)
IRQ (interrupt request input)
INTC (interrupt controller)
LVD (low-voltage detector)
ICS (internal clock source)
OSC (crystal oscillator)
Port I/O1
1
1
No
1
1
No
Yes
Yes
Yes
Yes
Yes
69
16
53
16
39
15
69
16
53
16
39
15
RGPIO (rapid general-purpose I/O)
SCI (serial communications interface)
SPI1 (serial peripheral interface)
SPI2 (serial peripheral interface)
FTM1 (flexible timer module) channels
FTM2 channels
2
Yes
Yes
No
No
Yes
No
No
62
62
MCF51AG128 ColdFire Microcontroller, Rev. 5
4
Freescale Semiconductor
MCF51AG128 Family Configurations
Table 1. MCF51AG128 Series Device Comparison (continued)
MCF51AG128
64-pin
MCF51AG96
64-pin
Feature
80-pin
48-pin
80-pin
48-pin
TPM3 (timer pulse-width modulator)
channels
2
Debug Visibility Bus
Yes
No
No
Yes
No
No
1
2
Up to 16 pins on Ports E and F are shared with the ColdFire Rapid GPIO module.
Some pins of FTMx might not be bonded on small package, therefore these channels could be used as soft timer only.
1.2
Block Diagram
Figure 1 shows the connections between the MCF51AG128 series pins and modules.
MCF51AG128 ColdFire Microcontroller, Rev. 5
Freescale Semiconductor
5
MCF51AG128 Family Configurations
PTA7/ADP23
PTA6/MCLK
PTA5/C2IN3
PTA4/C2IN2
PTA3/CMP2OUT
PTA2/CIN1
PTA1/EWM_out
PTA0/EWM_in
PTB7/ADP11
PTB6/ADP12
PTB5/ADP13
PTB4/ADP14
PTB3/ADP15
VREFH
VREFL
VDDA
VSSA
VREFH
VREFL
VDDA
VSSA
Port D:
CMP1OUT
CIN1
Port C,D,G:
ADP10-
ADP0
C1IN2
C1IN3
HSCMP1
Port J:
DDATA3-
DDATA0
PST3-
PST0
Port G:
PSTCLK
Port B:
ADP18-
ADP11
DBG
ADC
Port A:
CMP2OUT
CIN1
Port H:
VBUS
ADP22-
ADP19
Port A:
BKGD/MS
HSCMP2
C2IN2
C2IN3
BDM
BKPT
PTB2ADP16
PTB1/ADP17/TPM3CH1
PTB0/ADP18/TPM3CH0
ADP23
PTC6/FTM2FLT
PTC5/RxD2
PTC4/SS2
PTC3/TxD2
PTC2/ADP8
PTC1/SDA
FTM1CLK
FTM2CLK
TPMCLK
Port F:
FTM1CH5
FTM1CH4
FTM1CH3
FTM1CH2
Port E:
Port E:
RXD1
TXD1
ColdFire V1 core
+ DMA + iEvent
SCI1
SCI2
RESET
*
FTM1
Port C:
RXD2
TXD2
FTM1CH1
FTM1CH0
PTC0/SCL
SIM
PTD7/ADP7
PTD6/FTM1CLK/ADP0
PTD5/ADP1
PTD4/FTM2CLK/ADP2
PTD3/ADP5
PTD2/ADP6/CMP1OUT
PTD1/ADP9/C1IN3
PTD0/ADP10/C1IN2
PTE7/RGPIO7/SPSCK1
PTE6/RGPIO6/MOSI1
PTE5/RGPIO5/MISO1
PTE4/RGPIO4/SS1
PTE3/RGPIO3/FTM1CH1
PTE2/RGPIO2/FTM1CH0
PTE1/RGPIO1/RxD1
PTE0/RGPIO0/TxD1
IRQ/
TPMCLK
Port J:
FTM2CH5
FTM2CH4
FTM2CH3
FTM2CH2
Port F:
FTM2CH1
FTM2CH0
Port E:
SS1
SPSCK1
MOSI1
MISO1
WDOG LVD
IRQ
*
FTM2
SPI1
SPI2
FLASH
128 or 96 KB
Port H:
SS2
SPSCK2
MOSI2
MISO2
Port B:
or Port G:
RAM
16 KB
TPM3
TPM3CH1
TPM3CH0
Port F:
PTF7/RGPIO15
RGPIO15
RGPIO14
RGPIO13
RGPIO12
RGPIO11
RGPIO10
RGPIO9
PTF6/RGPIO14/FTM1FLT
PTF5/RGPIO13/FTM2CH1
PTF4/RGPIO12/FTM2CH0
PTF3/RGPIO11/FTM1CH5
PTF2/RGPIO10/FTM1CH4
PTF1/RGPIO9/FTM1CH3
PTF0/RGPIO8/FTM1CH2
RGPIO8
PTG6/XTAL
PTG5/EXTAL
PTG4/ADP3
PTG3/ADP4
PTG2/BKPT
PTG1/PSTCLK1/TPM3CH1
PTG0/PSTCLK0/TPM3CH0
RGPIO
Port E:
RGPIO7
RGPIO6
RGPIO5
RGPIO4
RGPIO3
RGPIO2
RGPIO1
RGPIO0
Port G:
EXTAL
XTAL
CRC
RTC
ICS
OSC
PTH6/MISO2
PTH5/MOSI2
PTH4/SPSCK2
Port C:
SDA
SCL
PTH3/ADP19/FTM2CH5
PTH2/ADP20/FTM2CH4
PTH1/ADP21/FTM2CH3
PTH0/ADP22/FTM2CH2
VDD
VSS
VSS
IIC
DAC1
DAC2
VREG
EWM
PTJ7/DDATA3/FTM2CH2
PTJ6/DDATA2/FTM2CH3
PTJ5/DDATA1/FTM2CH4
PTJ4/DDATA0//FTM2CH5
PTJ3/PST3
PTJ2/PST2
PTJ1/PST1
EWM_in
EWM_out
PTJ0/PST0
Figure 1. MCF51AG128 Series MCUs Block Diagram
MCF51AG128 ColdFire Microcontroller, Rev. 5
6
Freescale Semiconductor
MCF51AG128 Family Configurations
1.3
Features
Table 2 describes the functional units of the MCF51AG128 series.
Table 2. MCF51AG128 Series Functional Units
Functional Unit
Function
CF1Core (V1 ColdFire core)
BDM (background debug module)
DBG (debug)
Executes programs and interrupt handlers
Provides single pin debugging interface (part of the V1 ColdFire core)
Provides debugging and emulation capabilities (part of the V1 ColdFire core)
Allows for real-time program traces (part of the V1 ColdFire core)
Controls resets and chip level interfaces between modules
Provides storage for program code, constants, and variables
Provides storage for program variables
VBUS (debug visibility bus)
SIM (system integration module)
Flash (flash memory)
RAM (random-access memory)
RGPIO (rapid general-purpose input/output) Allows for I/O port access at CPU clock speeds
VREG (voltage regulator)
LVD (low-voltage detect)
Controls power management across the device
Monitors internal and external supply voltage levels, and generates a reset or
interrupt when the voltages are too low
CF1_INTC (interrupt controller)
ADC (analog-to-digital converter)
Controls and prioritizes all device interrupts
Measures analog voltages at up to 12 bits of resolution
Provide a variety of timing-based features
FTM1, FTM2 (flexible timer/pulse-width
modulators)
TPM3 (timer/pulse-width modulator)
CRC (cyclic redundancy check)
Provides a variety of timing-based features
Accelerates computation of CRC values for ranges of memory
HSCMP1, HSCMP2 (analog comparators) Compare two analog inputs
DAC1, DAC2 (digital-to-analog converter)
IIC (inter-integrated circuit)
Provide programmable voltage reference for HSCMPx
Supports standard IIC communications protocol
ICS (internal clock source)
Provides clocking options for the device, including a frequency-locked loop
(FLL) for multiplying slower reference clock sources
OSC (crystal oscillator)
Allows a crystal or ceramic resonator to be used as the system clock source
or reference clock for the FLL
SCI1, SCI2 (serial communications
interfaces)
Serial communications UARTs capable of supporting RS-232 and LIN
protocols
SPI1, SPI2 (8/16-bit serial peripheral
interfaces)
Provide 8/16-bit 4-pin synchronous serial interface
DMA
Provides the means to directly transfer data between system memory and I/O
peripherals
iEvent
Highly programmable module for creating combinational boolean outputs for
use as interrupt requests, DMA transfer requests, or hardware triggers
EWM (External Watchdog Monitor)
Additional watchdog system to help reset external circuits
MCF51AG128 ColdFire Microcontroller, Rev. 5
Freescale Semiconductor
7
MCF51AG128 Family Configurations
Table 2. MCF51AG128 Series Functional Units (continued)
Functional Unit
Function
WDOG (Watchdog timer)
RTC (Real Time Counter)
keeps a watch on the system functioning and resets it in case of its failure
Provides a constant time-base with optional interrupt
MCF51AG128 ColdFire Microcontroller, Rev. 5
8
Freescale Semiconductor
MCF51AG128 Family Configurations
1.4
Pin Assignments
This section describes the pin assignments for the available packages.
Figure 2 shows the pinout of the 80-pin LQFP.
PTG3/ADP4
PTD3/ADP5
PTD2/ADP6/CMP1OUT
PTD7/ADP7
PTC2/ADP8
PTD1/ADP9/C1IN3
PTD0/ADP10/C1IN2
PTB7/ADP11
PTB6/ADP12
PTB5/ADP13
PTB4/ADP14
PTB3/ADP15
PTB2/ADP16
PTB1/ADP17/TPM3CH1
PTB0/ADP18/TPM3CH0
PTH3/ADP19/FTM2CH5
PTH2/ADP20/FTM2CH4
PTH1/ADP21/FTM2CH3
PTH0/ADP22/FTM2CH2
PTA7/ADP23
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
1
2
3
4
5
6
7
8
PTC0/SCL
PTC1/SDA
IRQ/TPMCLK
PTF0/RGPIO8/FTM1CH2
PTF1/RGPIO9/FTM1CH3
PTF2/RGPIO10/FTM1CH4
PTF3/RGPIO11/FTM1CH5
PTF4/RGPIO12/FTM2CH0
PTC6/FTM2FLT
9
80-Pin
LQFP
10
11
12
13
14
15
16
17
18
19
20
PTF7/RGPIO15
PTF5/RGPIO13/FTM2CH1
PTF6/RGPIO14/FTM1FLT
PTJ0/PST0
PTJ1/PST1
PTJ2/PST2
PTJ3/PST3
PTE0/RGPIO0/TxD1
PTE1/RGPIO1/RxD1
PTE2/RGPIO2/FTM1CH0
PTE3/RGPIO3/FTM1CH1
Note: Pin names in bold
are not available in lower
pin count packages.
Figure 2. 80-Pin LQFP
MCF51AG128 ColdFire Microcontroller, Rev. 5
Freescale Semiconductor
9
MCF51AG128 Family Configurations
Figure 3 shows the pinout of the 64-pin LQFP and QFP.
PTC0/SCL
PTC1/SDA
IRQ/TPMCLK
PTF0/RGPIO8/FTM1CH2
PTF1/RGPIO9/FTM1CH3
PTF2/RGPIO10/FTM1CH4
PTF3/RGPIO11/FTM1CH5
PTF4/RGPIO12/FTM2CH0
PTC6/FTM2FLT
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
PTG3/ADP4
PTD3/ADP5
PTD2/ADP6/CMP1OUT
PTD7/ADP7
PTC2/ADP8
PTD1/ADP9/C1IN3
PTD0/ADP10/C1IN2
PTB7/ADP11
PTB6/ADP12
PTB5/ADP13
PTB4/ADP14
PTB3/ADP15
PTB2/ADP16
PTB1/ADP17/TPM3CH1
PTB0/ADP18/TPM3CH0
PTA7/ADP23
64-Pin QFP
64-Pin LQFP
PTF7/RGPIO15
PTF5/RGPIO13/FTM2CH1
PTF6/RGPIO14/FTM1FLT
PTE0/RGPIO0/TxD1
PTE1/RGPIO1/RxD1
PTE2/RGPIO2/FTM1CH0
PTE3/RGPIO3/FTM1CH1
Figure 3. 64-Pin QFP and LQFP
MCF51AG128 ColdFire Microcontroller, Rev. 5
10
Freescale Semiconductor
MCF51AG128 Family Configurations
Figure 4 shows the pinout of the 48-pin LQFP.
36
35
34
33
32
31
30
29
28
27
26
25
PTD2/ADP6/CMP1OUT
1
2
IRQ/TPMCLK
PTF0/RGPIO8/FTM1CH2
PTF1/RGPIO9/FTM1CH3
PTF2/RGPIO10/FTM1CH4
PTF3/RGPIO11/FTM1CH5
PTF4/RGPIO12/FTM2CH0
PTC6/FTM2FLT
PTD1/ADP9/CMP1IN3
PTD0/ADP10/CMP1IN2
PTB7/ADP11
3
4
5
PTB6/ADP12
48 LQFP
6
7
8
9
PTB5/ADP13
PTB4/ADP14
PTF7/RGPIO15
PTF5/RGPIO13/FTM2CH1
PTF6/RGPIO14/FTM1FLT
PTB3/ADP15
PTB2/ADP16
10
11
12
PTB1/ADP17/TPM3CH1
PTB0/ADP18/TPM3CH0
PTA3
PTE0/RGPIO0/TXD1
PTE1/RGPIO1/RXD1
Figure 4. 48-Pin LQFP
MCF51AG128 ColdFire Microcontroller, Rev. 5
Freescale Semiconductor
11
MCF51AG128 Family Configurations
Table 3 shows the package pin assignments.
Table 3. Pin Availability by Package Pin-Count
Pin Number
64
Lowest <-- Priority --> Highest
Port Pin Alt 1 Alt 2
80
48
1
1
—
—
1
PTC0
PTC1
IRQ
SCL
SDA
2
2
3
3
TPMCLK1
RGPIO8
RGPIO9
RGPIO10
RGPIO11
RGPIO12
FTM2FLT
RGPIO15
RGPIO13
RGPIO14
PST0
4
4
2
PTF0
PTF1
PTF2
PTF3
PTF4
PTC6
PTF7
PTF5
FTM1CH2
FTM1CH3
FTM1CH4
FTM1CH5
FTM2CH0
5
5
3
6
6
4
7
7
5
8
8
6
9
9
7
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
10
11
12
—
—
—
—
13
14
15
16
17
18
19
20
—
—
21
22
23
24
25
—
—
26
27
28
29
30
31
32
8
9
FTM2CH1
FTM1FLT
10 PTF6
—
—
—
—
PTJ0
PTJ1
PTJ2
PTJ3
PST1
PST2
PST3
11 PTE0
12 PTE1
13 PTE2
RGPIO0
RGPIO1
RGPIO2
RGPIO3
RGPIO4
RGPIO5
RGPIO6
RGPIO7
DDATA0
DDATA1
DDATA2
DDATA3
PSTCLK0
TxD1
RxD1
FTM1CH0
FTM1CH1
SS1
—
PTE3
14 PTE4
15 PTE5
16 PTE6
17 PTE7
MISO1
MOSI1
SPSCK1
FTM2CH5
FTM2CH4
FTM2CH3
FTM2CH2
TPM3CH0
—
—
PTJ4
PTJ5
18 PTJ6
19 PTJ7
20 PTG0
21 VSS
22 VDD
—
—
PTG1
PTG2
PSTCLK1
BKPT
TPM3CH1
23 PTA0
24 PTA1
EWM_in
EWM_out
CIN1
—
PTA2
25 PTA3
CMP2OUT
C2IN2
—
—
—
PTA4
PTA5
PTA6
C2IN3
MCLK
MCF51AG128 ColdFire Microcontroller, Rev. 5
12
Freescale Semiconductor
MCF51AG128 Family Configurations
Table 3. Pin Availability by Package Pin-Count (continued)
Pin Number
64
Lowest <-- Priority --> Highest
Port Pin Alt 1 Alt 2
PTA7 ADP23
80
48
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
33
—
—
—
—
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
—
49
50
51
—
52
53
54
55
56
57
58
59
60
61
—
62
—
63
64
—
—
—
—
—
PTH0
PTH1
PTH2
PTH3
ADP22
ADP21
ADP20
ADP19
ADP18
ADP17
ADP16
ADP15
ADP14
ADP13
ADP12
ADP11
ADP10
ADP9
FTM2CH2
FTM2CH3
FTM2CH4
FTM2CH5
TPM3CH0
26 PTB0
27 PTB1
28 PTB2
29 PTB3
30 PTB4
31 PTB5
32 PTB6
33 PTB7
34 PTD0
35 PTD1
TPM3CH1
C1IN2
C1IN3
—
—
PTC2
PTD7
ADP8
ADP7
36 PTD2
ADP6
CMP1OUT
—
—
—
—
—
PTD3
PTG3
PTG4
PTD4
PTD5
ADP5
ADP4
ADP3
FTM2CLK
ADP1
ADP2
ADP0
37 PTD6
PTC4
FTM1CLK
SS2
—
38 VSSA
38 VREFL
39 VREFH
39 VDDA
40 VDD
41 VSS
42 PTG5
43 PTG6
44 BKGD
45 RESET
EXTAL
XTAL
MS
—
PTH4
46 PTH5
PTH6
SPSCK2
MOSI2
MISO2
TxD2
—
47 PTC3
48 PTC5
RxD2
MCF51AG128 ColdFire Microcontroller, Rev. 5
Freescale Semiconductor
13
Preliminary Electrical Characteristics
1
TPMCLK, FTM1CLK, and FTM2CLK options are configured via software; out of
reset, FTM1CLK, FTM2CLK, and TPMCLK are available to FTM1, FTM2, and
TPM3 respectively.
2
Preliminary Electrical Characteristics
This section contains electrical specification tables and reference timing diagrams for the MCF51AG128 series MCUs,
including detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications.
The electrical specifications are preliminary and are from previous designs or design simulations. These specifications may not
be fully tested or guaranteed at this early stage of the product life cycle. These specifications will, however, be met for
production silicon. Finalized specifications will be published after complete characterization and device qualifications have
been completed.
NOTE
The parameters specified in this data sheet supersede any values found in the module
specifications.
2.1
Parameter Classification
The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better
understanding the following classification is used and the parameters are tagged accordingly in the tables where appropriate:
Table 4. Parameter Classifications
Those parameters are guaranteed during production testing on each individual device.
P
C
Those parameters are achieved by the design characterization by measuring a statistically relevant
sample size across process variations.
Those parameters are achieved by design characterization on a small sample size from typical devices
under typical conditions unless otherwise noted. All values shown in the typical column are within this
category.
T
Those parameters are derived mainly from simulations.
D
NOTE
The classification is shown in the column labeled “C” in the parameter tables where
appropriate.
2.2
Absolute Maximum Ratings
Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the
limits specified in Table 5 may affect device reliability or cause permanent damage to the device. For functional operating
conditions, refer to the remaining tables in this section.
This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised
that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this
high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for
instance, either V or V ).
SS
DD
MCF51AG128 ColdFire Microcontroller, Rev. 5
14
Freescale Semiconductor
Preliminary Electrical Characteristics
Table 5. Absolute Maximum Ratings
Rating Symbol
Value
Unit
Supply voltage
Input voltage
V
–0.3 to 5.8
V
V
DD
V
–0.3 to VDD + 0.3
In
Instantaneous maximum current
ID
IDD
±25
mA
Single pin limit (applies to all port pins)1, 2, 3
Maximum current into V
Storage temperature
120
mA
DD
T
–55 to 150
°C
stg
1
Input must be current limited to the value specified. To determine the value of the required
current-limiting resistor, calculate resistance values for positive (VDD) and negative (VSS) clamp
voltages, then use the larger of the two resistance values.
2
3
All functional non-supply pins are internally clamped to VSS and VDD
.
Power supply must maintain regulation within operating VDD range during instantaneous and
operating maximum current conditions. If positive injection current (VIn > VDD) is greater than
IDD, the injection current may flow out of VDD and could result in external power supply going
out of regulation. Ensure external VDD load will shunt current greater than maximum injection
current. This will be the greatest risk when the MCU is not consuming power. Examples are: if
no system clock is present, or if the clock rate is very low which would reduce overall power
consumption.
2.3
Thermal Characteristics
This section provides information about operating temperature range, power dissipation, and package thermal resistance. Power
dissipation on I/O pins is usually small compared to the power dissipation in on-chip logic and it is user-determined rather than
being controlled by the MCU design. To take P into account in power calculations, determine the difference between actual
I/O
pin voltage and V or V and multiply by the pin current for each I/O pin. Except in cases of unusually high pin current
SS
DD
(heavy loads), the difference between pin voltage and V or V is very small.
SS
DD
Table 6. Thermal Characteristics
Rating
Symbol
Value
Unit
Operating temperature range (packaged)
Maximum junction temperature
Thermal resistance 1,2,3,4
TA
TJ
–40 to 105
150
°C
°C
80-pin LQFP
64-pin QFP
64-pin LQFP
48-pin LQFP
1s
2s2p
56
45
1s
2s2p
54
41
θJA
°C/W
1s
2s2p
67
49
1s
2s2p
69
51
MCF51AG128 ColdFire Microcontroller, Rev. 5
Freescale Semiconductor
15
Preliminary Electrical Characteristics
1
Junction temperature is a function of die size, on-chip power dissipation, package thermal
resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation
of other components on the board, and board thermal resistance.
2
3
4
Junction to Ambient Natural Convection
1s — Single layer board, one signal layer
2s2p — Four layer board, 2 signal and 2 power layers
The average chip-junction temperature (T ) in °C can be obtained from:
J
T = T + (P × θ )
JA
Eqn. 1
J
A
D
where:
T = Ambient temperature, °C
A
θ
= Package thermal resistance, junction-to-ambient, °C/W
JA
P = P + P
D
int
I/O
P
P
= I × V , Watts — chip internal power
DD DD
= Power dissipation on input and output pins — user determined
int
I/O
For most applications, P << P and can be neglected. An approximate relationship between P and T (if P is neglected)
I/O
int
D
J
I/O
is:
P = K ÷ (T + 273 °C)
Eqn. 2
D
J
Solving Equation 1 and Equation 2 for K gives:
K = P × (T + 273°C) + θ × (P )
2
Eqn. 3
D
A
JA
D
where K is a constant pertaining to the particular part. K can be determined from Equation 3 by measuring P (at equilibrium)
D
for a known T . Using this value of K, the values of P and T can be obtained by solving Equation 1 and Equation 2 iteratively
A
D
J
for any value of T .
A
2.4
Electrostatic Discharge (ESD) Protection Characteristics
Although damage from static discharge is much less common on these devices than on early CMOS circuits, normal handling
precautions should be used to avoid exposure to static discharge. Qualification tests are performed to ensure that these devices
can withstand exposure to reasonable levels of static without suffering any permanent damage.
All ESD testing is in conformity with CDF-AEC-Q00 Stress Test Qualification for Automotive Grade Integrated Circuits.
(http://www.aecouncil.com/) This device was qualified to AEC-Q100 Rev E.
A device is considered to have failed if, after exposure to ESD pulses, the device no longer meets the device specification
requirements. Complete dc parametric and functional testing is performed per the applicable device specification at room
temperature followed by hot temperature, unless specified otherwise in the device specification.
Table 7. ESD and Latch-up Test Conditions
Model
Description
Symbol
Value
Unit
Human Body
Series Resistance
R1
C
1500
100
3
Ω
pF
—
Storage Capacitance
Number of Pulse per pin
—
MCF51AG128 ColdFire Microcontroller, Rev. 5
16
Freescale Semiconductor
Preliminary Electrical Characteristics
Table 7. ESD and Latch-up Test Conditions (continued)
Model
Latch-up
Description
Minimum input voltage limit
Maximum input voltage limit
Symbol
Value
Unit
—
—
–2.5
7.5
V
V
Table 8. ESD and Latch-Up Protection Characteristics
Num
Rating
Human Body Model (HBM)
Symbol
Min
Max
Unit
1
2
3
VHBM
VCDM
ILAT
2000
500
—
—
—
V
V
Charge Device Model (CDM)
Latch-up Current at TA = 85°C
100
mA
2.5
DC Characteristics
This section includes information about power supply requirements, I/O pin characteristics, and power supply current in various
operating modes.
Table 9. DC Characteristics
Num C
1 — Operating voltage
Parameter
Symbol
Min
Typical1
Max
Unit
2.7
—
5.5
V
Output high voltage — Low Drive (PTxDSn = 0)
5 V, ILoad = –5 mA
VDD – 1.5
VDD – 0.8
VDD – 0.4
VDD – 0.4
—
—
—
—
—
—
—
—
3 V, ILoad = –1.5 mA
5V, ILoad = –3 mA, PTC0 and PTC1
3V, ILoad = –1.5 mA, PTC0 and PTC1
VOH
Output high voltage — High Drive (PTxDSn = 1)
5 V, ILoad = –20 mA
VDD – 1.5
—
—
—
—
—
—
—
—
2
P
V
3 V, ILoad = –8 mA
5V, ILoad = –12 mA, PTC0 and PTC1
3V, ILoad = –8 mA, PTC0 and PTC1
VDD – 0.8
VDD – 0.4
VDD – 0.4
Output low voltage — Low Drive (PTxDSn = 0)
5 V, ILoad = 5 mA
—
—
—
—
—
—
—
—
1.5
0.8
0.4
0.4
3 V, ILoad = 1.5 mA
5V, ILoad = 3 mA, PTC0 and PTC1
3V, ILoad = 1.5 mA, PTC0 and PTC1
VOL
Output low voltage — High Drive (PTxDSn = 1)
5 V, ILoad = 20 mA
—
—
—
—
—
—
—
—
1.5
0.8
0.4
0.4
3
P
V
3 V, ILoad = 8 mA
5V, ILoad = 12 mA, PTC0 and PTC1
3V, ILoad = 8 mA, PTC0 and PTC1
Output high current — Max total IOH for all ports
4
5
C
C
5V IOHT
3V
—
—
—
—
100
60
mA
mA
Output low current — Max total IOL for all ports
5 V IOLT
3 V
—
—
—
—
100
60
MCF51AG128 ColdFire Microcontroller, Rev. 5
Freescale Semiconductor
17
Preliminary Electrical Characteristics
Table 9. DC Characteristics (continued)
Num C
Parameter
Symbol
Min
Typical1
Max
Unit
6
7
8
9
P Input high voltage; all digital inputs
VIH
VIL
0.65 × VDD
—
—
—
V
P Input low voltage; all digital inputs
D Input hysteresis; all digital inputs
P Input leakage current; input only pins2
—
0.35 × VDD
Vhys
|IIn|
0.06 × VDD
—
—
1
mV
μA
μA
—
—
0.1
0.1
10 P High Impedance (off-state) leakage current2
Internal pullup resistors3
|IOZ
|
1
20
10
45
22
65
32
11
P
RPU
kΩ
Internal pullup resistorsPTC0 and PTC1
12 P Internal pulldown resistors4
13 C Input Capacitance; all non-supply pins
14 P POR rearm voltage
RPD
CIn
20
—
45
—
65
8
kΩ
pF
V
VPOR
tPOR
0.9
10
1.4
—
2.0
—
15 D POR rearm time
μs
Low-voltage detection threshold —
high range
16
17
18
19
20
21
P
P
P
P
P
P
VLVD1
VLVD0
VLVW3
VLVW2
VLVW1
VLVW0
V
V
V
V
V
V
VDD falling
VDD rising
3.9
4.0
4.0
4.1
4.1
4.2
Low-voltage detection threshold —
low range
VDD falling
VDD rising
2.48
2.54
2.56
2.62
2.64
2.70
Low-voltage warning threshold —
high range 1
VDD falling
VDD rising
4.5
4.6
4.6
4.7
4.7
4.8
Low-voltage warning threshold —
high range 0
VDD falling
VDD rising
4.2
4.3
4.3
4.4
4.4
4.5
Low-voltage warning threshold
low range 1
VDD falling
VDD rising
2.84
2.90
2.92
2.98
3.00
3.06
Low-voltage warning threshold —
low range 0
VDD falling
VDD rising
2.66
2.72
2.74
2.80
2.82
2.88
Low-voltage inhibit reset/recover hysteresis
22
23
T
5 V Vhys
3 V
—
—
100
60
—
—
mV
V
RAM retention voltage
D
VRAM
—
0.6
1.0
DC injection current5 6 7 8 (single pin limit)
VIN >VDD
VIN <VSS
0
0
—
—
2
–0.2
mA
24
D
IIC
DC injection current (Total MCU limit, includes
sum of all stressed pins)
mA
V
IN >VDD
0
0
—
—
25
–5
VIN <VSS
MCF51AG128 ColdFire Microcontroller, Rev. 5
18
Freescale Semiconductor
Preliminary Electrical Characteristics
1
2
3
4
5
Typical values are based on characterization data at 25°C unless otherwise stated.
Measured with VIn = VDD or VSS
Measured with VIn = VSS
Measured with VIn = VDD
.
.
.
Power supply must maintain regulation within operating VDD range during instantaneous and operating
maximum current conditions. If positive injection current (VIn > VDD) is greater than IDD, the injection current may
flow out of VDD and could result in external power supply going out of regulation. Ensure external VDD load will
shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not
consuming power. Examples are: if no system clock is present, or if clock rate is very low (which would reduce
overall power consumption).
6
7
All functional non-supply pins are internally clamped to VSS and VDD
.
Input must be current limited to the value specified. To determine the value of the required current-limiting
resistor, calculate resistance values for positive and negative clamp voltages, then use the larger of the two
values.
8
The RESET pin does not have a clamp diode to VDD. Do not drive this pin above VDD
.
Typical VDD - VOH vs. IOH AT VDD=3V
Typical V - VOH vs. IOH AT V = 5V
DD
DD
0.8
0.6
0.4
0.2
0.0
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
Hot (105°C)
Room (25°C)
Cold (-40°C)
Hot (105°C)
Room (25°C)
Cold (-40°C)
0
-1
-2
-3
-4
-5
0
-1
-2
IOH (mA)
IOH (mA)
Figure 5. Typical I vs. V – V (Low Drive,PTxDSn = 0)
OH
DD
OH
Typical VDD - VOH vs. IOH AT VDD = 5V
Typical VDD - VOH vs. IOH AT VDD=3V
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
Hot (105°C)
Room (25°C)
Cold (-40°C)
0.8
0.6
0.4
0.2
0.0
Hot (105°C)
Room (25°C)
Cold (-40°C)
0
-1
-2
-3
-4
-5
-6
-7
-8
IOH (mA)
IOH (mA)
Figure 6. Typical I vs. V – V (High Drive, PTxDSn = 1)
OH
DD
OH
MCF51AG128 ColdFire Microcontroller, Rev. 5
Freescale Semiconductor
19
Preliminary Electrical Characteristics
Typical VOL vs. IOL AT VDD = 3V
Typical VOL vs. IOL AT VDD = 5V
1.40
1.20
1.00
0.80
0.60
0.40
0.20
0.00
Hot (105°C)
Room (25°C)
Cold (-40°C)
0.80
0.60
0.40
0.20
0.00
Hot (105°C)
Room (25°C)
Cold (-40°C)
0
1
2
0
1
2
3
4
5
IOL (mA)
IOL (mA)
Figure 7. Typical I vs. V (Low Drive, PTxDSn = 0)
OL
OL
Typical VOL vs. IOL AT VDD = 3V
Typical VOL vs. IOL AT VDD = 5V
1.40
Hot (105°C)
Room (25°C)
Cold (-40°C)
0.80
0.60
0.40
0.20
0.00
1.20
1.00
0.80
0.60
0.40
0.20
0.00
Hot (105°C)
Room (25°C)
Cold (-40°C)
0
1
2
3
4
5
6
7
8
IOL (mA)
IOL (mA)
Figure 8. Typical I vs. V (High Drive, PTxDSn = 1)
OL
OL
MCF51AG128 ColdFire Microcontroller, Rev. 5
20
Freescale Semiconductor
Preliminary Electrical Characteristics
2.6
Supply Current Characteristics
Table 10. Supply Current Characteristics
Num
C
Parameter
Symbol
VDD (V)
Typical1
Max2
Unit
1
C
Run supply current3 measured at 4 MHz CPU
clock (All Peripheral Clocks are ON)
RIDD
5
3
5
3
5
3
5
3
5
3
5
3
5
3
5
3
5
3
5
3
5
3
5
3
5.8
5.7
7
mA
7
2
C
C
P
C
C
C
C
C
C
C
C
Run supply current3 measured at 16 MHz CPU
clock (All Peripheral Clocks are ON)
21
25
25
50
50
70
70
6
mA
mA
20.9
39.2
39.1
57.9
57.8
4.7
3
Run supply current3 measured at 32 MHz CPU
clock (All Peripheral Clocks are ON)
4
Run supply current3 measured at 50MHz CPU
clock (All Peripheral Clocks are ON)
mA
mA
5
Run supply current3 measured at 4 MHz CPU
clock (All Peripheral Clocks are OFF4)
RIDD
WIDD
S2IDD
4.6
6
6
Run supply current3 measured at 16 MHz CPU
clock (All Peripheral Clocks are OFF4)
16.1
15.9
29
20
20
35
35
50
50
5
mA
mA
7
Run supply current3 measured at 32 MHz CPU
clock (All Peripheral Clocks are OFF4)
28.9
44.1
44.0
3.2
8
Run supply current3 measured at 50 MHz CPU
clock (All Peripheral Clocks are OFF4)
mA
mA
mA
mA
mA
9
Wait supply current3 measured at 4 MHz CPU
clock
3.2
5
10
11
12
13
Wait supply current3 measured at 16 MHz
CPU clock
10.1
10
13
13
25
25
40
40
Wait supply current3 measured at 32 MHz
CPU clock
19
18.8
29.2
29
Wait supply current3 measured at 50 MHz
CPU clock
Stop2 mode supply current
C
P
C
–40 °C
25 °C
105 °C
5
1.17
1.35
28.6
3
3
40
μA
μA
1.0
1.34
26.8
3
3
40
C
P
C
–40 °C
25 °C
105 °C
3
MCF51AG128 ColdFire Microcontroller, Rev. 5
Freescale Semiconductor
21
Preliminary Electrical Characteristics
Table 10. Supply Current Characteristics
Num
C
Parameter
Symbol
VDD (V)
Typical1
Max2
Unit
14
Stop3 mode supply current
S3IDD
C
P
C
–40 °C
25 °C
105 °C
5
1.2
1.7
43.3
3
3
60
μA
μA
1.04
1.6
45.5
3
3
60
C
P
C
–40 °C
25 °C
105 °C
3
5
15
Stop4 mode supply current
–40 °C
25 °C
S4IDD
C
P
C
106
109
155
130
130
170
μA
μA
105 °C
95
98
142
130
130
170
C
P
C
–40 °C
25 °C
105 °C
3
16
17
C
RTC adder to stop2 or stop35, 25 °C
S23IDDRTC
5
3
300
300
5
—
—
—
nA
nA
μA
C
Adder to stop3 for oscillator enabled6
(ERCLKEN = 1 and EREFSTEN = 1)
S3IDDOSC
5, 3
1
2
3
4
5
6
Typicals are measured at 25 °C.
Values given here are preliminary estimates prior to completing characterization.
Code run from flash, FEI mode, and does not include any dc loads on port pins. Bus CLK= (CPU CLK/2)
GPIO filters are working on LPO clock.
Most customers are expected to use auto-wakeup from stop2 or stop3 instead of the higher current wait mode.
Values given under the following conditions: low range operation (RANGE = 0), low power mode (HGO = 0).
Figure 9. Run Current at Different Conditions
MCF51AG128 ColdFire Microcontroller, Rev. 5
22
Freescale Semiconductor
Preliminary Electrical Characteristics
2.7
High Speed Comparator (HSCMP) Electricals
Table 11. HSCMP Electrical Specifications
Num
C
Rating
Symbol
Min
Typical
Max
Unit
1
2
—
T
Supply voltage
VDD
2.7
—
—
5.5
—
V
Supply current, high speed mode (EN = 1,
PMODE = 1)
IDDAHS
200
μA
3
T
Supply current, low speed mode (EN = 1,
PMODE = 0)
IDDALS
—
20
—
μA
4
5
6
7
—
D
D
D
Analog input voltage
VAIN
VAIO
VH
VSS – 0.3
—
5
VDD
40
V
Analog input offset voltage
Analog Comparator hysteresis
—
3.0
—
mV
mV
ns
9.0
70
20.0
120
Propagation delay, high speed mode (EN = 1,
PMODE = 1)
tDHS
8
9
D
D
Propagation delay, low speed mode (EN = 1,
PMODE = 0)
tDLS
—
—
400
400
600
—
ns
ns
Analog Comparator initialization delay
tAINIT
2.8
Digital to Analog (DAC) Characteristics
Num
C
Rating
Symbol
Min
Typical
Max
Unit
1
2
3
D
D
D
Supply voltage
VDDA
IDDAC
IDDACS
2.7
—
—
—
—
5.5
20
V
Supply current (enabled)
Supply current (stand-by)
μA
nA
—
150
4
5
6
7
8
D
D
D
D
P
DAC reference input voltage
DAC setup delay
Vin1,Vin2
tPRGST
Vstep
VSSA
—
—
1000
Vin/32
—
VDDA
—
V
nS
V
DAC step size
3Vin/128
Vin/32
1.18
5Vin/128
Vin
DAC output voltage range
Vdacout
VBG
V
Bandgap voltage reference
1.20
1.21
V
factory trimmed at VDD = 5 V, Temp = 25 °C
2.9
ADC Characteristics
Table 12. 5V 12-bit ADC Operating Conditions
Characterist
ic
Typic
Num
C
Conditions
Symb
Min
Max
Unit
Comment
al1
1
D
Supply
voltage
Absolute
Delta to VDD
VDDA
2.7
—
0
5.5
V
—
—
ΔVDDA
–100
100
mV
2
(VDD–VDDA
)
2
D
Ground
voltage
Delta to VSS
ΔVSSA
–100
0
100
mV
—
2
(VSS–VSSA
)
MCF51AG128 ColdFire Microcontroller, Rev. 5
Freescale Semiconductor
23
Preliminary Electrical Characteristics
Table 12. 5V 12-bit ADC Operating Conditions (continued)
Characterist
ic
Typic
al1
Num
C
Conditions
Symb
Min
Max
Unit
Comment
3
D
Ref Voltage
High
—
VREFH
2.7
VDDA
VDDA
V
—
4
D
Ref Voltage
Low
—
VREFL
VSSAD
VSSA
VSSA
V
—
5
6
D
C
Input Voltage
—
—
VADIN
CADIN
VREFL
—
—
VREFH
5.5
V
—
—
Input
4.5
pF
Capacitance
7
8
C
C
Input
Resistance
—
RADIN
—
3
5
kΩ
kΩ
—
Analog
Source
Resistance
12 bit mode
ADCK > 4 MHz
fADCK < 4 MHz
RAS
External to
MCU
f
—
—
—
—
2
5
C
10 bit mode
fADCK > 4 MHz
fADCK < 4 MHz
—
—
—
—
5
10
C
D
D
8 bit mode (all valid fADCK
)
—
—
—
—
10
8.0
4.0
9
ADC
Conversion
Clock Freq.
High Speed (ADLPC = 0)
Low Power (ADLPC = 1)
fADCK
0.4
0.4
MHz
—
—
1
2
Typical values assume VDDA = 5.0 V, Temp = 25 °C, fADCK = 1.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
DC potential difference.
MCF51AG128 ColdFire Microcontroller, Rev. 5
24
Freescale Semiconductor
Preliminary Electrical Characteristics
SIMPLIFIED
INPUT PIN EQUIVALENT
CIRCUIT
Z
ADIN
SIMPLIFIED
CHANNEL SELECT
Pad
Z
AS
leakage
due to
input
CIRCUIT
ADC SAR
ENGINE
R
R
AS
ADIN
protection
+
V
ADIN
–
C
AS
V
+
AS
–
R
R
R
ADIN
ADIN
ADIN
INPUT PIN
INPUT PIN
INPUT PIN
C
ADIN
Figure 10. ADC Input Impedance Equivalency Diagram
Table 13. 5 V 12-bit ADC Characteristics (V
= V
, V
= V
)
SSA
REFH
DDA
REFL
Max
—
Num
C
Characteristic
Conditions
Symb
Min
Typical1
Unit
Comment
1
T
Supply Current
ADLPC = 1
ADLSMP = 1
ADCO = 1
—
IDDAD
—
181
μA
—
—
—
—
—
2
3
4
5
T
T
D
T
Supply Current
ADLPC = 1
ADLSMP = 0
ADCO = 1
—
—
—
IDDAD
IDDAD
IDDAD
IDDAD
—
—
—
—
334
385
—
—
1
μA
μA
mA
μA
Supply Current
ADLPC = 0
ADLSMP = 1
ADCO = 1
Supply Current
ADLPC = 0
ADLSMP = 0
ADCO = 1
0.717
0.065
Supply Current
Stop, Reset,
Module Off
1
MCF51AG128 ColdFire Microcontroller, Rev. 5
Freescale Semiconductor
25
Preliminary Electrical Characteristics
Table 13. 5 V 12-bit ADC Characteristics (V
= V
, V
= V ) (continued)
SSA
REFH
DDA
REFL
Num
C
Characteristic
Conditions
Symb
Min
Typical1
Max
Unit
Comment
6
P
ADC
Asynchronous
Clock Source
High Speed
(ADLPC = 0)
fADACK
2
3.3
5
3.3
—
—
—
—
MHz
tADACK
1/fADACK
=
Low Power
(ADLPC = 1)
1.25
—
2
20
7
8
P
T
Conversion
Time (Including
sample time)
Short Sample
(ADLSMP = 0)
tADC
ADCK See Table 10 for
cycles
conversion time
variances
Long Sample
(ADLSMP = 1)
—
40
Sample Time
Short Sample
(ADLSMP = 0)
tADS
—
3.5
23.5
ADCK
cycles
Long Sample
—
(ADLSMP = 1)
9
T
P
T
T
P
T
T
P
T
T
P
T
T
P
T
D
Total
Unadjusted
Error
12 bit mode
10 bit mode
8 bit mode
12 bit mode
10 bit mode3
8 bit mode5
12 bit mode
10 bit mode
8 bit mode
12 bit mode
10 bit mode
8 bit mode
12 bit mode
10 bit mode
8 bit mode
12 bit mode
10 bit mode
8 bit mode
12 bit mode
10 bit mode
8 bit mode
ETUE
DNL
INL
EZS
EFS
EQ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
±3.0
±1
—
±2.5
±1.0
—
LSB2
LSB2
LSB2
LSB2
LSB2
LSB2
LSB2
Includes
quantization
±0.5
±1.75
±0.5
±0.3
±1.5
±0.5
±0.3
±1.5
±0.5
±0.5
±1
10
11
12
13
14
15
Differential
Non-Linearity
—
±1.0
±0.5
—
Integral
Non-Linearity
—
±1.0
±0.5
—
Zero-Scale
Error
VADIN = VSSAD
VADIN = VDDAD
—
±1.5
±0.5
—
Full-Scale Error
±0.5
±0.5
–1 to 0
—
±1
±0.5
—
Quantization
Error
±0.5
±0.5
—
—
D
Input Leakage
Error
EIL
±1
Pad leakage4 *
RAS
±0.2
±0.1
±2.5
±1
MCF51AG128 ColdFire Microcontroller, Rev. 5
26
Freescale Semiconductor
Preliminary Electrical Characteristics
Table 13. 5 V 12-bit ADC Characteristics (V
= V
, V
= V ) (continued)
SSA
REFH
DDA
REFL
Num
C
Characteristic
Conditions
25 °C
Symb
Min
Typical1
Max
Unit
Comment
16
D
Temp Sensor
Voltage
VTEMP25
—
1.396
—
mV
—
17
D
Temp Sensor
Slope
–40 °C — 25 °C
25 °C — 85 °C
m
—
—
3.266
3.638
—
—
mV/°C
—
1
Typical values assume VDDA = 5.0 V, Temp = 25 °C, fADCK = 1.0 MHz unless otherwise stated. Typical values are for reference
only and are not tested in production.
2
3
4
1 LSB = (VREFH - VREFL)/2N
Monotonicity and No-Missing-Codes guaranteed in 10 bit and 8 bit modes
Based on input pad leakage current. Refer to pad electricals.
2.10 External Oscillator (XOSC) Characteristics
Table 14. Oscillator Electrical Specifications (Temperature Range = –40 to 105 °C Ambient)
Num
C
Rating
Symbol
Min
Typical1
Max
Unit
Oscillator crystal or resonator (EREFS = 1, ERCLKEN = 1)
Low range (RANGE = 0)
flo
fhi
fhi-hgo
fhi-lp
32
1
1
—
—
—
—
38.4
16
16
8
kHz
MHz
MHz
MHz
1
C
High range (RANGE = 1) FEE or FBE mode 2
High range (RANGE = 1, HGO = 1) FBELP mode
High range (RANGE = 1, HGO = 0) FBELP mode
1
C1
C2
See crystal or resonator
manufacturer’s recommendation.
2
3
—
—
Load capacitors
Feedback resistor
Low range (32 kHz to 100 kHz)
High range (1 MHz to 16 MHz)
RF
10
1
—
MΩ
Series resistor
Low range, low gain (RANGE = 0, HGO = 0)
Low range, high gain (RANGE = 0, HGO = 1)
High range, low gain (RANGE = 1, HGO = 0)
High range, high gain (RANGE = 1, HGO = 1)
—
—
—
0
100
0
—
—
—
4
—
RS
kΩ
≥ 8 MHz
4 MHz
1 MHz
—
—
—
0
0
0
0
10
20
Crystal start-up time 3
t
Low range, low gain (RANGE = 0, HGO = 0)
Low range, high gain (RANGE = 0, HGO = 1)
High range, low gain (RANGE = 1, HGO = 0)4
High range, high gain (RANGE = 1, HGO = 1)3
—
—
—
—
1500
2000
3
—
—
—
—
CSTL-LP
t
5
6
T
T
CSTL-HGO
ms
t
CSTH-LP
t
7
CSTH-HGO
Square wave input clock frequency (EREFS = 0, ERCLKEN =
1)
—
—
—
FEE mode 2
FBE mode2
FBELP mode
fextal
0.03125
50.33
50.33
50.33
MHz
0
0
1
Data in Typical column was characterized at 5.0 V, 25 °C or is typical recommended value.
MCF51AG128 ColdFire Microcontroller, Rev. 5
Freescale Semiconductor
27
Preliminary Electrical Characteristics
2
When MCG is configured for FEE or FBE mode, input clock source must be divisible using RDIV to within the range of
31.25 kHz to 39.0625 kHz.
3
This parameter is characterized and not tested on each device. Proper PC board layout procedures must be followed to
achieve specifications.
4
4 MHz crystal
MCU
EXTAL
XTAL
RS
RF
C1
Crystal or Resonator
C2
2.11 ICS Specifications
Table 15. ICS Frequency Specifications (Temperature Range = –40 to 105 °C Ambient)
Num C
Rating
Symbol
Min
Typical1
Max
Unit
1
C Internal reference frequency - factory trimmed at VDD
fint_ft
—
32.768
—
kHz
= 5 V and temperature = 25 °C
2
3
4
C Average internal reference frequency – untrimmed
fint_ut
tirefst
31.25
—
—
60
39.06
100
20
kHz
μs
T Internal reference startup time
C DCO output frequency
Low range (DRS = 00)
Mid range (DRS = 01)
High range (DRS = 10)
Low range (DRS = 00)
Mid range (DRS = 01)
High range (DRS = 10)
fdco_ut
16
32
48
—
—
MHz
range - untrimmed 2
C
—
40
C
—
60
5
P DCO output frequency2
fdco_DMX32
16.82
33.69
50.48
±0.1
—
MHz
Reference =32768Hz
and DMX32 = 1
P
P
—
—
—
—
6
7
8
9
D Resolution of trimmed DCO output frequency at fixed
voltage and temperature (using FTRIM)
Δfdco_res_t
Δfdco_res_t
Δfdco_t
—
±0.2
%fdco
%fdco
%fdco
%fdco
D Resolution of trimmed DCO output frequency at fixed
voltage and temperature (not using FTRIM)
—
—
—
±0.2
±0.4
±2
D Total deviation of trimmed DCO output frequency over
full voltage and temperature range
0.5
–1.0
D Total deviation of trimmed DCO output frequency over
Δfdco_t
±0.5
±1
fixed voltage and temperature range of 0 –70 °C
MCF51AG128 ColdFire Microcontroller, Rev. 5
28
Freescale Semiconductor
Preliminary Electrical Characteristics
Table 15. ICS Frequency Specifications (continued)(Temperature Range = –40 to 105 °C Ambient)
Num C
Rating
Symbol
Min
Typical1
Max
Unit
10 D FLL acquisition time 3
tfll_acquire
CJitter
—
—
—
1
ms
11 D Long term Jitter of DCO output clock (averaged over
2ms interval) 4
0.02
0.2
%fdco
12 D Loss of external clock minimum freq. (RANGE = 0)
• ext. clock freq: above (3/5)fint, never reset
• ext. clock freq: between (2/5)fint and (3/5)fint, maybe
reset (phase dependency)
floc_low
(3/5) x fint
—
—
—
—
kHz
kHz
• ext. clock freq: below (2/5)fint, always reset
13 D Loss of external clock minimum freq. (RANGE = 1)
• ext. clock freq: above (16/5)fint, never reset
• ext. clock freq: between (15/5)fint and (16/5)fint,
maybe reset (phase dependency)
floc_high
(16/5) x fint
• ext. clock freq: below (15/5)fint, always reset
1
2
3
Data in Typical column was characterized at 3.0 V, 25 °C or is typical recommended value
The resulting bus clock frequency should not exceed the maximum specified bus clock frequency of the device.
This specification applies to any time the FLL reference source or reference divider is changed, trim value changed or
changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the
reference, this specification assumes it is already running.
4
Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fBUS
.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the FLL circuitry by VDD and VSS and variation in crystal oscillator frequency increase the CJitter percentage for
a given interval.
MCF51AG128 ColdFire Microcontroller, Rev. 5
Freescale Semiconductor
29
Preliminary Electrical Characteristics
2.12 AC Characteristics
This section describes ac timing characteristics for each peripheral system.
2.12.1 Control Timing
Table 16. Control Timing
Num
C
Parameter
Symbol
Min
Typ1
Max
Unit
1
2
3
D
D
D
Bus frequency (tcyc = 1/fBus
)
Internal low-power oscillator period
External reset pulse width2
fBus
dc
—
—
24
MHz
tLPO
800
1500
μs
textrst
100
—
—
ns
(tcyc = 1/fSelf_reset
)
4
5
6
7
D
D
D
D
Reset low drive
trstdrv
tMSSU
tMSH
66 x tcyc
500
—
—
—
—
—
—
ns
ns
ns
Active background debug mode latch setup time
Active background debug mode latch hold time
IRQ pulse width
100
Asynchronous path2
tILIH, IHIL
t
100
1.5 x tcyc
—
—
ns
Synchronous path3
Port rise and fall time (load = 30 pF for SPI, rest 50 pF)4
Slew rate control disabled (PTxSE = 0) High drive
Slew rate control enabled (PTxSE = 1) High drive
Slew rate control disabled (PTxSE = 0) Low drive
Slew rate control enabled (PTxSE = 1) Low drive
11
35
40
75
tRise, tFall
8
—
—
ns
1
2
Typical values are based on characterization data at VDD = 5.0 V, 25 °C unless otherwise stated.
This is the shortest pulse that is guaranteed to be recognized as a RESET pin request. Shorter pulses are not guaranteed to
override reset requests from internal sources.
3
4
This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or
may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case.
Timing is shown with respect to 20% VDD and 80% VDD levels. Temperature range –40°C to 105°C.
textrst
RESET PIN
Figure 11. Reset Timing
MCF51AG128 ColdFire Microcontroller, Rev. 5
30
Freescale Semiconductor
Preliminary Electrical Characteristics
tIHIL
IRQ/KBIPx
IRQ/KBIPx
tILIH
Figure 12. IRQ/KBIPx Timing
2.12.2 Timer (TPM/FTM) Module Timing
Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that can be used as the
optional external source to the timer counter. These synchronizers operate from the current bus rate clock.
Table 17. TPM/FTM Input Timing
NUM
C
Function
Symbol
Min
Max
Unit
1
2
3
4
5
—
—
D
External clock frequency
External clock period
fTPMext
tTPMext
tclkh
DC
4
fBus/4
—
MHz
tcyc
tcyc
tcyc
tcyc
External clock high time
External clock low time
Input capture pulse width
1.5
1.5
1.5
—
D
tclkl
—
D
tICPW
—
tTPMext
tclkh
TPMxCLK
tclkl
Figure 13. Timer External Clock
tICPW
TPMxCHn
TPMxCHn
tICPW
Figure 14. Timer Input Capture Pulse
MCF51AG128 ColdFire Microcontroller, Rev. 5
Freescale Semiconductor
31
Preliminary Electrical Characteristics
2.12.3 SPI Characteristics
Table 18 and Figure 15 through Figure 18 describe the timing requirements for the SPI system.
Table 18. SPI Timing Characteristics
No.
C
Function
Operating frequency
Symbol
Min
Max
Unit
—
D
Master
Slave
fop
fBus/2048
0
fBus/2
fBus/4
Hz
SPSCK period
Master
Slave
1
2
3
4
5
6
D
D
D
D
D
D
tSPSCK
tLead
tLag
2
4
2048
—
tcyc
tcyc
Enable lead time
Master
Slave
1/2
1
—
—
tSPSCK
tcyc
Enable lag time
Master
Slave
1/2
1
—
—
tSPSCK
tcyc
Clock (SPSCK) high or low time
Master
Slave
tWSPSCK
tcyc – 30
tcyc – 30
1024 tcyc
—
ns
ns
Data setup time (inputs)
Master
Slave
tSU
30
30
—
—
ns
ns
Data hold time (inputs)
Master
Slave
tHI
10
10
—
—
ns
ns
Slave access time
—
—
tcyc
7
8
D
D
ta
Slave MISO disable time
—
—
tcyc
tdis
Data valid time ( maximum delay after
SPCLK edge to Data output)
Master
Slave
1
9
D
D
tV
—
—
25
70
ns
ns
Data hold time ( minimum delay after
SPCLK edge to Data output)
Master
Slave
1
10
tHO
10
10
—
—
ns
ns
1
SPI Output Load = 30 pf
MCF51AG128 ColdFire Microcontroller, Rev. 5
32
Freescale Semiconductor
Preliminary Electrical Characteristics
SS1
(OUTPUT)
1
2
3
SPSCK
(CPOL = 0)
4
(OUTPUT)
4
SPSCK
(CPOL = 1)
(OUTPUT)
5
6
MISO
(INPUT)
MSB IN2
LSB IN
BIT 6 . . . 1
9
9
10
MOSI
(OUTPUT)
MSB OUT2
BIT 6 . . . 1
LSB OUT
NOTES:
1. SS output mode (DDS7 = 1, SSOE = 1).
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 15. SPI Master Timing (CPHA = 0)
SS(1)
(OUTPUT)
1
2
3
SPSCK
(CPOL = 0)
(OUTPUT)
4
4
SPSCK
(CPOL = 1)
(OUTPUT)
5
6
MISO
(INPUT)
MSB IN(2)
BIT 6 . . . 1
BIT 6 . . . 1
LSB IN
9
10
MOSI
(OUTPUT)
MASTER MSB OUT(2)
PORT DATA
MASTER LSB OUT
PORT DATA
NOTES:
1. SS output mode (DDS7 = 1, SSOE = 1).
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 16. SPI Master Timing (CPHA = 1)
MCF51AG128 ColdFire Microcontroller, Rev. 5
Freescale Semiconductor
33
Preliminary Electrical Characteristics
SS
(INPUT)
3
1
SPSCK
(CPOL = 0)
(INPUT)
2
4
4
SPSCK
(CPOL = 1)
(INPUT)
8
7
10
9
10
MISO
(OUTPUT)
SEE
NOTE
BIT 6 . . . 1
SLAVE LSB OUT
MSB OUT
SLAVE
6
5
MOSI
(INPUT)
BIT 6 . . . 1
MSB IN
LSB IN
NOTE:
1. Not defined but normally MSB of character just received
Figure 17. SPI Slave Timing (CPHA = 0)
SS
(INPUT)
1
3
2
SPSCK
(CPOL = 0)
(INPUT)
4
4
SPSCK
(CPOL = 1)
(INPUT)
9
10
8
MISO
(OUTPUT)
SEE
BIT 6 . . . 1
BIT 6 . . . 1
SLAVE LSB OUT
LSB IN
SLAVE
MSB OUT
NOTE
5
6
7
MOSI
(INPUT)
MSB IN
NOTE:
1. Not defined but normally LSB of character just received
Figure 18. SPI Slave Timing (CPHA = 1)
2.13 Flash Specifications
This section provides details about program/erase times and program-erase endurance for the Flash memory.
Program and erase operations do not require any special power sources other than the normal V supply. For more detailed
DD
information about program/erase operations, see MCF51AG128 Reference Manual.
MCF51AG128 ColdFire Microcontroller, Rev. 5
34
Freescale Semiconductor
Preliminary Electrical Characteristics
Table 19. Flash Characteristics
Num
C
Characteristic
Symbol
Min
Typical1
Max
Unit
1
2
3
4
5
6
7
8
9
—
—
—
—
—
—
—
—
C
Supply voltage for program/erase
Supply voltage for read operation
Internal FCLK frequency2
Vprog/erase
VRead
fFCLK
tFcyc
2.7
2.7
150
5
5.5
5.5
V
V
200
6.67
kHz
μs
Internal FCLK period (1/FCLK)
Byte program time (random location)2
Byte program time (burst mode)2
Page erase time3
tprog
9
4
tFcyc
tFcyc
tFcyc
tFcyc
cycles
tBurst
tPage
4000
20,000
Mass erase time2
tMass
Program/erase endurance4
TL to TH = –40 °C to 105 °C
T = 25 °C
10,000
—
—
100,000
—
—
10
C
Data retention5
tD_ret
15
100
—
years
1
2
3
Typical values are based on characterization data at VDD = 5.0 V, 25 °C unless otherwise stated.
The frequency of this clock is controlled by a software setting.
These values are hardware state machine controlled. User code does not need to count cycles. This information
supplied for calculating approximate time to program and erase.
4
5
Typical endurance for flash was evaluated for this product family on the HC9S12Dx64. For additional information
on how Freescale Semiconductor defines typical endurance, please refer to Engineering Bulletin EB619/D, Typical
Endurance for Nonvolatile Memory.
Typical data retention values are based on intrinsic capability of the technology measured at high temperature and
de-rated to 25 °C using the Arrhenius equation. For additional information on how Freescale Semiconductor defines
typical data retention, please refer to Engineering Bulletin EB618/D, Typical Data Retention for Nonvolatile Memory.
2.14 EMC Performance
Electromagnetic compatibility (EMC) performance is highly dependant on the environment in which the MCU resides. Board
design and layout, circuit topology choices, location and characteristics of external components as well as MCU software
operation all play a significant role in EMC performance. The system designer should consult Freescale applications notes such
as AN2321, AN1050, AN1263, AN2764, and AN1259 for advice and guidance specifically targeted at optimizing EMC
performance.
2.14.1 Radiated Emissions
Microcontroller radiated RF emissions are measured from 150 kHz to 1 GHz using the TEM/GTEM Cell method in accordance
with the IEC 61967-2 and SAE J1752/3 standards. The measurement is performed with the microcontroller installed on a
custom EMC evaluation board while running specialized EMC test software. The radiated emissions from the microcontroller
are measured in a TEM cell in two package orientations (North and East). For more detailed information concerning the
evaluation results, conditions and setup, please refer to the EMC Evaluation Report for this device.
MCF51AG128 ColdFire Microcontroller, Rev. 5
Freescale Semiconductor
35
Ordering Information
3
Ordering Information
This section contains ordering information for MCF51AG128 devices.
MCF
AG 128
XX
V
51
Status
Package designator
(MCF = Fully Qualified ColdFire)
(PCF = Product Engineering)
Temperature range
(V = –40 °C to 105 °C, C = –40°C to 85 °C )
Core
Family
Memory size designator
Table 20. Orderable Part Number Summary
Flash / SRAM
Freescale Part Number
Description
(KB)
Package
Temperature
MCF51AG128VLK
MCF51AG128VLH
MCF51AG128VQH
MCF51AG128VLF
MCF51AG96VLK
MCF51AG96VLH
MCF51AG96VQH
MCF51AG96VLF
MCF51AG128 ColdFire Microcontroller
128 / 16
128 / 16
128 / 16
128 / 16
96 / 16
96 / 16
96 / 16
96 / 16
80 LQFP
64 LQFP
64 QFP
–40°C to 105°C
–40°C to 105°C
–40°C to 105°C
–40°C to 105°C
–40°C to 105°C
–40°C to 105°C
–40°C to 105°C
–40°C to 105°C
MCF51AG128 ColdFire Microcontroller
MCF51AG128 ColdFire Microcontroller
MCF51AG128 ColdFire Microcontroller
MCF51AG96 ColdFire Microcontroller
MCF51AG96 ColdFire Microcontroller
MCF51AG96 ColdFire Microcontroller
MCF51AG96 ColdFire Microcontroller
48 LQFP
80 LQFP
64 LQFP
64 QFP
48 LQFP
4
Package Information
Table 21. Package Descriptions
Pin Count
Package Type
Abbreviation
Designator
Case No.
Document No.
80
64
64
48
Low Quad Flat Package
Low Quad Flat Package
Quad Flat Package
LQFP
LQFP
QFP
LK
LH
QH
LF
917A
840F
840B
932
98ASS23237W
98ASS23234W
98ASB42844B
98ASH00962A
Low Quad Flat Package
LQFP
MCF51AG128 ColdFire Microcontroller, Rev. 5
36
Freescale Semiconductor
Mechanical Outline Drawings
5
Mechanical Outline Drawings
5.1
80-pin LQFP Package
MCF51AG128 ColdFire Microcontroller, Rev. 5
Freescale Semiconductor
37
Mechanical Outline Drawings
MCF51AG128 ColdFire Microcontroller, Rev. 5
38
Freescale Semiconductor
Mechanical Outline Drawings
MCF51AG128 ColdFire Microcontroller, Rev. 5
Freescale Semiconductor
39
Mechanical Outline Drawings
5.2
64-pin LQFP Package
MCF51AG128 ColdFire Microcontroller, Rev. 5
40
Freescale Semiconductor
Mechanical Outline Drawings
MCF51AG128 ColdFire Microcontroller, Rev. 5
Freescale Semiconductor
41
Mechanical Outline Drawings
MCF51AG128 ColdFire Microcontroller, Rev. 5
42
Freescale Semiconductor
Mechanical Outline Drawings
5.3
64-pin QFP Package
MCF51AG128 ColdFire Microcontroller, Rev. 5
Freescale Semiconductor
43
Mechanical Outline Drawings
MCF51AG128 ColdFire Microcontroller, Rev. 5
44
Freescale Semiconductor
Mechanical Outline Drawings
MCF51AG128 ColdFire Microcontroller, Rev. 5
Freescale Semiconductor
45
Mechanical Outline Drawings
5.4
48-pin LQFP Package
MCF51AG128 ColdFire Microcontroller, Rev. 5
46
Freescale Semiconductor
Mechanical Outline Drawings
MCF51AG128 ColdFire Microcontroller, Rev. 5
Freescale Semiconductor
47
Revision History
6
Revision History
Table 22. Revision History
Description
Rev. No.
Date
11/2008
1
2
3
4
Initial Draft Release.
4/2009
5/2009
12/2009
Internal Release.
Alpha Customer Release.
• Added 48-pin LQFP information;
• Updated Section 2.5/17 and 2.6/21.
• Provided the supply current in Section 2.7/23, and setup delay in Section 2.8/23.
5
6/2010
• Updated Table 10.
• Added Figure 9.
• Corrected pin names of PTG6 and PTG5 in 48-pin LQFP.
• Standardized Generation 2008 Watchdog to Watchdog.
• In Table 9, updated Output high/low voltage — Low Drive (PTxDSn = 0) 3 V, ILoad value.
MCF51AG128 ColdFire Microcontroller, Rev. 5
48
Freescale Semiconductor
THIS PAGE INTENTIONALLY BLANK
MCF51AG128 ColdFire Microcontroller, Rev. 5
Freescale Semiconductor
49
Information in this document is provided solely to enable system and software
implementers to use Freescale Semiconductor products. There are no express or
implied copyright licenses granted hereunder to design or fabricate any integrated
circuits or integrated circuits based on the information in this document.
How to Reach Us:
Home Page:
www.freescale.com
Web Support:
http://www.freescale.com/support
Freescale Semiconductor reserves the right to make changes without further notice to
any products herein. Freescale Semiconductor makes no warranty, representation or
guarantee regarding the suitability of its products for any particular purpose, nor does
Freescale Semiconductor assume any liability arising out of the application or use of any
product or circuit, and specifically disclaims any and all liability, including without
limitation consequential or incidental damages. “Typical” parameters that may be
provided in Freescale Semiconductor data sheets and/or specifications can and do vary
in different applications and actual performance may vary over time. All operating
parameters, including “Typicals”, must be validated for each customer application by
customer’s technical experts. Freescale Semiconductor does not convey any license
under its patent rights nor the rights of others. Freescale Semiconductor products are
not designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life,
or for any other application in which the failure of the Freescale Semiconductor product
could create a situation where personal injury or death may occur. Should Buyer
purchase or use Freescale Semiconductor products for any such unintended or
unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and
its officers, employees, subsidiaries, affiliates, and distributors harmless against all
claims, costs, damages, and expenses, and reasonable attorney fees arising out of,
directly or indirectly, any claim of personal injury or death associated with such
unintended or unauthorized use, even if such claim alleges that Freescale
USA/Europe or Locations Not Listed:
Freescale Semiconductor, Inc.
Technical Information Center, EL516
2100 East Elliot Road
Tempe, Arizona 85284
+1-800-521-6274 or +1-480-768-2130
www.freescale.com/support
Europe, Middle East, and Africa:
Freescale Halbleiter Deutschland GmbH
Technical Information Center
Schatzbogen 7
81829 Muenchen, Germany
+44 1296 380 456 (English)
+46 8 52200080 (English)
+49 89 92103 559 (German)
+33 1 69 35 48 48 (French)
www.freescale.com/support
Japan:
Freescale Semiconductor Japan Ltd.
Headquarters
Semiconductor was negligent regarding the design or manufacture of the part.
ARCO Tower 15F
1-8-1, Shimo-Meguro, Meguro-ku,
Tokyo 153-0064
RoHS-compliant and/or Pb-free versions of Freescale products have the functionality
and electrical characteristics as their non-RoHS-compliant and/or non-Pb-free
counterparts. For further information, see http://www.freescale.com or contact your
Freescale sales representative.
Japan
0120 191014 or +81 3 5437 9125
support.japan@freescale.com
Asia/Pacific:
Freescale Semiconductor China Ltd.
Exchange Building 23F
No. 118 Jianguo Road
Chaoyang District
For information on Freescale’s Environmental Products program, go to
http://www.freescale.com/epp.
Beijing 100022
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc.
All other product or service names are the property of their respective owners.
© Freescale Semiconductor, Inc. 2010. All rights reserved.
China
+86 10 5879 8000
support.asia@freescale.com
For Literature Requests Only:
Freescale Semiconductor Literature Distribution Center
1-800-441-2447 or 303-675-2140
Fax: 303-675-2150
LDCForFreescaleSemiconductor@hibbertgroup.com
Document Number: MCF51AG128
Rev. 5
6/2010
相关型号：
MCF51CN128CLK
32-BIT, FLASH, 50.33 MHz, MICROCONTROLLER, PQFP80, 14 X 14 MM, 1.40 MM HEIGHT, 0.65 MM PITCH, LQFP-80
ROCHESTER
MCF51EM256_1
MCF51EM256-based Poly Phase Energy Meter Reference Design 110V Technical Specifications
FREESCALE
MCF51EM256_2
MCF51EM256-based Poly Phase Energy Meter Reference Design 220V Technical Specifications
FREESCALE
©2020 ICPDF网 联系我们和版权申明