MCF51JU64VLF [FREESCALE]
Advance Information Temperature range (ambient): -40°C to 105°C; 超前信息温度范围（环境） ： -40°C至105℃
| 型号： | MCF51JU64VLF |
| 厂家： | 
Freescale |
| 描述： | Advance Information Temperature range (ambient): -40°C to 105°C |
| 文件： | 总71页 (文件大小：1008K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Document Number: MCF51JU128
Rev. 0, 05/2011
Freescale Semiconductor
Data Sheet: Advance Information
MCF51JU128
MCF51JU128 Advance
Information
Supports the MCF51JU128VLH,
MCF51JU128VHX, MCF51JU128VHS,
MCF51JU64VLF, MCF51JU64VHS,
MCF51JU32VHS, MCF51JU32VFM
Features
Analog
– 12-bit SAR ADC
– 12-bit DAC
– Analog comparator (CMP) containing a 6-bit DAC
and programmable reference input
– Voltage reference (VREF)
•
•
•
Operating characteristics
– Voltage range: 1.71 V to 3.6 V
•
– Flash write voltage range: 1.71 V to 3.6 V
– Temperature range (ambient): -40°C to 105°C
Core
•
– Up to 50 MHz V1 ColdFire CPU
– Dhrystone 2.1 performance: 1.10 DMIPS per MHz
when executing from internal RAM, 0.99 DMIPS
per MHz when executing from flash memory
Timers
– Programmable delay block (PDB)
– Motor control/general purpose/PWM timers (FTM)
– 16-bit low-power timers (LPTMRs)
– 16-bit modulo timer (MTIM)
– Carrier modulator transmitter (CMT)
System
•
•
– DMA controller with four programmable channels
– Integrated ColdFire DEBUG_Rev_B+ interface with
single-wire BDM connection
Communication interfaces
– UARTs with Smart Card support and FIFO
– SPI modules, one with FIFO
– Inter-Integrated Circuit (I2C) modules
– USB full/low speed On-the-Go controller with on-
chip transceiver
– Integrated Interchip Sound (I2S) / Serial Audio
Interface (SAI) to support full-duplex serial
interfaces with frame sync such as AC97 and
CODEC
Power management
– 10 low power modes to provide power optimization
based on application requirements
– Low-leakage wakeup unit (LLWU)
– Voltage regulator (VREG)
Clocks
•
– Crystal oscillators (two, each with range options): 1
kHz to 32 kHz (low), 1 MHz to 8 MHz (medium), 8
MHz to 32 MHz (high)
Human-machine interface
– Up to 48 EGPIO pins
– Up to 16 rapid general purpose I/O (RGPIO) pins
– Low-power hardware touch sensor interface (TSI)
– Interrupt request pin (IRQ)
•
– Multipurpose clock generator (MCG)
Memories and memory interfaces
•
•
– Flash memory, FlexNVM, FlexRAM, and RAM
– Serial programming interface (EzPort)
– Mini-FlexBus external bus interface
Security and integrity
– Hardware CRC module to support fast cyclic
redundancy checks
– 128-bit unique identification (ID) number per chip
This document contains information on a new product. Specifications and
information herein are subject to change without notice.
© 2011 Freescale Semiconductor, Inc.
Preliminary
Table of Contents
1 Ordering parts...........................................................................3
5.4.1 Thermal operating requirements...........................19
5.4.2 Thermal attributes.................................................19
6 Peripheral operating requirements and behaviors....................20
6.1 Core modules....................................................................20
6.1.1 Debug specifications.............................................20
6.2 System modules................................................................20
6.3 Clock modules...................................................................21
6.3.1 MCG specifications...............................................21
6.3.2 Oscillator electrical specifications.........................23
6.4 Memories and memory interfaces.....................................26
6.4.1 Flash (FTFL) electrical specifications....................26
6.4.2 EzPort Switching Specifications............................30
6.4.3 Mini-Flexbus Switching Specifications..................31
6.5 Security and integrity modules..........................................33
6.6 Analog...............................................................................34
6.6.1 ADC electrical specifications.................................34
6.6.2 CMP and 6-bit DAC electrical specifications.........37
6.6.3 12-bit DAC electrical characteristics.....................39
6.6.4 Voltage reference electrical specifications............42
6.7 Timers................................................................................43
6.8 Communication interfaces.................................................44
6.8.1 USB electrical specifications.................................44
6.8.2 USB DCD electrical specifications........................44
6.8.3 USB VREG electrical specifications......................44
6.8.4 SPI switching specifications..................................45
6.8.5 I2S/SAI Switching Specifications..........................49
6.9 Human-machine interfaces (HMI)......................................51
6.9.1 TSI electrical specifications...................................51
7 Dimensions...............................................................................52
7.1 Obtaining package dimensions.........................................52
8 Pinout........................................................................................53
8.1 Signal Multiplexing and Pin Assignments..........................53
8.2 Pinout diagrams.................................................................55
8.3 Module-by-module signals.................................................59
9 Revision History........................................................................70
1.1 Determining valid orderable parts......................................3
2 Part identification......................................................................3
2.1 Description.........................................................................3
2.2 Format...............................................................................3
2.3 Fields.................................................................................3
2.4 Example............................................................................4
3 Terminology and guidelines......................................................4
3.1 Definition: Operating requirement......................................4
3.2 Definition: Operating behavior...........................................5
3.3 Definition: Attribute............................................................5
3.4 Definition: Rating...............................................................5
3.5 Result of exceeding a rating..............................................6
3.6 Relationship between ratings and operating
requirements......................................................................6
3.7 Guidelines for ratings and operating requirements............6
3.8 Definition: Typical value.....................................................7
4 Ratings......................................................................................8
4.1 Thermal handling ratings...................................................8
4.2 Moisture handling ratings..................................................8
4.3 ESD handling ratings.........................................................9
4.4 Voltage and current operating ratings...............................9
5 General.....................................................................................9
5.1 Typical Value Conditions...................................................9
5.2 Nonswitching electrical specifications...............................10
5.2.1 Voltage and Current Operating Requirements......10
5.2.2 LVD and POR operating requirements.................11
5.2.3 Voltage and current operating behaviors..............12
5.2.4 Power mode transition operating behaviors..........12
5.2.5 Power consumption operating behaviors..............13
5.2.6 EMC radiated emissions operating behaviors.......16
5.2.7 Designing with radiated emissions in mind...........16
5.2.8 Capacitance attributes..........................................16
5.3 Switching electrical specifications.....................................17
5.3.1 General Switching Specifications..........................17
5.4 Thermal specifications.......................................................19
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
2
Freescale Semiconductor, Inc.
Preliminary
Ordering parts
1 Ordering parts
1.1 Determining valid orderable parts
Valid orderable part numbers are provided on the web. To determine the orderable part
numbers for this device:
1. Go to http://www.freescale.com.
2. Perform a part number search for the following partial device numbers: PCF51JU
and MCF51JU.
2 Part identification
2.1 Description
Part numbers for the chip have fields that identify the specific part. You can use the
values of these fields to determine the specific part you have received.
2.2 Format
Part numbers for this device have the following format:
Q CCCC DD MMM T PP
2.3 Fields
This table lists the possible values for each field in the part number (not all combinations
are valid):
Field
Description
Qualification status
Values
Q
• M = Fully qualified, general
market flow
• P = Prequalification
CCCC
DD
Core code
CF51 = ColdFire V1
Device number
JF, JU, QF, QH, QM, QU
Table continues on the next page...
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
Freescale Semiconductor, Inc.
3
Preliminary
Terminology and guidelines
Field
Description
Values
• 32 = 32 KB
Memory size (program flash memory)1
MMM
• 64 = 64 KB
• 128 = 128 KB
T
Temperature range, ambient (°C)
Package identifier
V = –40 to 105
PP
• FM = 32 QFN (5 mm x 5 mm)
• HS = 44 Laminate QFN (5 mm x 5
mm)
• LF = 48 LQFP (7 mm x 7 mm)
• HX = 64 Laminate QFN (9 mm x 9
mm)
• LH = 64 LQFP (10 mm x 10 mm)
1. All parts also have FlexNVM, FlexRAM, and RAM.
2.4 Example
This is an example part number:
MCF51JU128VLH
3 Terminology and guidelines
3.1 Definition: Operating requirement
An operating requirement is a specified value or range of values for a technical
characteristic that you must guarantee during operation to avoid incorrect operation and
possibly decreasing the useful life of the chip.
3.1.1 Example
This is an example of an operating requirement, which you must meet for the
accompanying operating behaviors to be guaranteed:
Symbol
Description
Min.
Max.
Unit
VDD
1.0 V core supply
voltage
0.9
1.1
V
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
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Freescale Semiconductor, Inc.
Preliminary
Terminology and guidelines
3.2 Definition: Operating behavior
An operating behavior is a specified value or range of values for a technical
characteristic that are guaranteed during operation if you meet the operating requirements
and any other specified conditions.
3.2.1 Example
This is an example of an operating behavior, which is guaranteed if you meet the
accompanying operating requirements:
Symbol
Description
Min.
Max.
Unit
IWP
Digital I/O weak pullup/ 10
pulldown current
130
µA
3.3 Definition: Attribute
An attribute is a specified value or range of values for a technical characteristic that are
guaranteed, regardless of whether you meet the operating requirements.
3.3.1 Example
This is an example of an attribute:
Symbol
Description
Min.
Max.
Unit
CIN_D
Input capacitance:
digital pins
—
7
pF
3.4 Definition: Rating
A rating is a minimum or maximum value of a technical characteristic that, if exceeded,
may cause permanent chip failure:
• Operating ratings apply during operation of the chip.
• Handling ratings apply when the chip is not powered.
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
Freescale Semiconductor, Inc.
5
Preliminary
Terminology and guidelines
3.4.1 Example
This is an example of an operating rating:
Symbol
Description
Min.
Max.
Unit
VDD
1.0 V core supply
voltage
–0.3
1.2
V
3.5 Result of exceeding a rating
40
30
The likelihood of permanent chip failure increases rapidly as
soon as a characteristic begins to exceed one of its operating ratings.
20
10
0
Operating rating
Measured characteristic
3.6 Relationship between ratings and operating requirements
Fatal
range
Normal
operating
range
Fatal
range
- Probable permanent failure
- No permanent failure
- Possible decreased life
- Possible incorrect operation
- No permanent failure
- Correct operation
- No permanent failure
- Possible decreased life
- Possible incorrect operation
- Probable permanent failure
Handling range
- No permanent failure
–∞
∞
3.7 Guidelines for ratings and operating requirements
Follow these guidelines for ratings and operating requirements:
• Never exceed any of the chip’s ratings.
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
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Freescale Semiconductor, Inc.
Preliminary
Terminology and guidelines
• During normal operation, don’t exceed any of the chip’s operating requirements.
• If you must exceed an operating requirement at times other than during normal
operation (for example, during power sequencing), limit the duration as much as
possible.
3.8 Definition: Typical value
A typical value is a specified value for a technical characteristic that:
• Lies within the range of values specified by the operating behavior
• Given the typical manufacturing process, is representative of that characteristic
during operation when you meet the typical-value conditions or other specified
conditions
Typical values are provided as design guidelines and are neither tested nor guaranteed.
3.8.1 Example 1
This is an example of an operating behavior that includes a typical value:
Symbol
Description
Min.
Typ.
Max.
Unit
IWP
Digital I/O weak
pullup/pulldown
current
10
70
130
µA
3.8.2 Example 2
This is an example of a chart that shows typical values for various voltage and
temperature conditions:
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
Freescale Semiconductor, Inc.
7
Preliminary
Ratings
5000
4500
4000
3500
3000
2500
2000
1500
1000
500
TJ
150 °C
105 °C
25 °C
–40 °C
0
0.90
0.95
1.00
1.05
1.10
VDD (V)
4 Ratings
4.1 Thermal handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
TSTG
Storage temperature
–55
150
260
245
°C
1
TSDR
Solder temperature, lead-free
Solder temperature, leaded
—
—
°C
2
1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
4.2 Moisture handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
MSL
Moisture sensitivity level
—
3
—
1
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
8
Freescale Semiconductor, Inc.
Preliminary
General
4.3 ESD handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
VHBM
Electrostatic discharge voltage, human body model
-2000
+2000
V
1
VCDM
ILAT
Electrostatic discharge voltage, charged-device model
Latch-up current at ambient temperature of 105°C
-500
-100
+500
+100
V
2
mA
1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body
Model (HBM).
2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
4.4 Voltage and current operating ratings
Symbol
Description
Min.
Max.
Unit
VDD
Digital supply voltage
–0.3
3.8
V
IDD
VDIO
VAIO
ID
Digital supply current
—
120
VDD + 0.3
VDD + 0.3
25
mA
V
Digital input voltage (except RESET, EXTAL, and XTAL)
Analog, RESET, EXTAL, and XTAL input voltage
–0.3
–0.3
–25
V
Instantaneous maximum current single pin limit (applies to all
port pins)
mA
VDDA
IDDA
Analog supply voltage
Analog supply current
USB_DP input voltage
USB_DM input voltage
USB Regulator input
VDD – 0.3
—
VDD + 0.3
TBD
V
mA
V
VUSB_DP
VUSB_DM
VREGIN
–0.3
3.63
–0.3
3.63
V
–0.3
6.0
V
5 General
5.1 Typical Value Conditions
Typical values assume you meet the following conditions (or other conditions as
specified):
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
Freescale Semiconductor, Inc.
9
Preliminary
Nonswitching electrical specifications
Symbol
Description
Value
Unit
TA
Ambient temperature
3.3 V supply voltage
25
°C
V
VDD
3.3
5.2 Nonswitching electrical specifications
5.2.1 Voltage and Current Operating Requirements
Table 1. Voltage and current operating requirements
Symbol
Description
Min.
Max.
Unit
Notes
VDD
Supply voltage
1.71
3.6
V
VDDA
Analog supply voltage
1.71
–0.1
–0.1
3.6
0.1
0.1
V
V
V
VDD – VDDA VDD-to-VDDA differential voltage
VSS – VSSA VSS-to-VSSA differential voltage
VIH
VIL
IIC
Input high voltage
1
2
3
3
• 2.7 V ≤ VDD ≤ 3.6 V
• 1.7 V ≤ VDD ≤ 2.7 V
0.7 × VDD
—
—
V
V
0.75 × VDD
Input low voltage
• 2.7 V ≤ VDD ≤ 3.6 V
• 1.7 V ≤ VDD ≤ 2.7 V
—
—
0.35 × VDD
0.3 × VDD
V
V
DC injection current — single pin
• VIN > VDD
0
0
2
mA
mA
–0.2
• VIN < VSS
DC injection current — total MCU limit, includes sum
of all stressed pins
0
0
25
–5
mA
mA
• VIN > VDD
• VIN < VSS
VRAM
VDD voltage required to retain RAM
1.2
—
V
1. The device always interprets an input as a 1 when the input is greater than or equal to VIH (min.) and less than or equal to
VIH (max.), regardless of whether input hysteresis is turned on.
2. The device always interprets an input as a 0 when the input is less than or equal to VIL (max.) and greater than or equal to
VIL (min.), regardless of whether input hysteresis is turned on.
3. All functional non-supply pins are internally clamped to VSS and VDD. Input must be current limited to the value specified.
To determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp
voltages, then use the larger of the two values. Power supply must maintain regulation within operating VDD range during
instantaneous and operating maximum current conditions. If positive injection current (VIn > VDD) is greater than IDD, the
injection current may flow out of VDD and could result in external power supply going out of regulation. Ensure external
VDD load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
10
Freescale Semiconductor, Inc.
Preliminary
Nonswitching electrical specifications
consuming power. Examples are: if no system clock is present, or if clock rate is very low (which would reduce overall
power consumption).
5.2.2 LVD and POR operating requirements
Table 2. LVD and POR operating requirements
Symbol Description
Min.
Typ.
Max.
Unit
Notes
VPOR
Falling VDD POR detect voltage
TBD
1.1
TBD
V
VLVDH
Falling low-voltage detect threshold — high
range (LVDV=01)
TBD
2.56
TBD
V
Low-voltage warning thresholds — high range
• Level 1 falling (LVWV=00)
1
VLVW1H
VLVW2H
VLVW3H
VLVW4H
TBD
TBD
TBD
TBD
2.70
2.80
2.90
3.00
TBD
TBD
TBD
TBD
V
V
V
V
• Level 2 falling (LVWV=01)
• Level 3 falling (LVWV=10)
• Level 4 falling (LVWV=11)
VHYSH
Low-voltage inhibit reset/recover hysteresis —
high range
60
TBD
TBD
mV
V
VLVDL
Falling low-voltage detect threshold — low range
(LVDV=00)
TBD
1.60
Low-voltage warning thresholds — low range
• Level 1 falling (LVWV=00)
1
VLVW1L
VLVW2L
VLVW3L
VLVW4L
TBD
TBD
TBD
TBD
1.80
1.90
2.00
2.10
TBD
TBD
TBD
TBD
V
V
V
V
• Level 2 falling (LVWV=01)
• Level 3 falling (LVWV=10)
• Level 4 falling (LVWV=11)
VHYSL
Low-voltage inhibit reset/recover hysteresis —
low range
40
TBD
mV
VBG
tLPO
Bandgap voltage reference
TBD
TBD
1.00
TBD
TBD
V
Internal low power oscillator period
factory trimmed
1000
μs
1. Rising thresholds are falling threshold + hysteresis voltage
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
Freescale Semiconductor, Inc.
11
Preliminary
Nonswitching electrical specifications
5.2.3 Voltage and current operating behaviors
Table 3. Voltage and current operating behaviors
Symbol
Description
Min.
Max.
Unit
Notes
VOH
Output high voltage — high drive strength
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = -10 mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = -3 mA
VDD – 0.5
VDD – 0.5
—
—
V
V
Output high voltage — low drive strength
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = -2 mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = -0.6 mA
VDD – 0.5
VDD – 0.5
—
—
V
V
IOHT
VOL
Output high current total for all ports
—
100
mA
Output low voltage — high drive strength
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 10 mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 3 mA
—
—
0.5
0.5
V
V
Output low voltage — low drive strength
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 2 mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 0.6 mA
—
—
0.5
0.5
V
V
IOLT
IIN
Output low current total for all ports
—
100
mA
Input leakage current (per pin)
• @ full temperature range
• @ 25 °C
—
—
TBD
TBD
μA
μA
IOZ
RPU
RPD
Hi-Z (off-state) leakage current (per pin)
Internal pullup resistors
—
20
20
TBD
50
μA
kΩ
kΩ
1
2
Internal pulldown resistors
50
1. Measured at Vinput = VSS
2. Measured at Vinput = VDD
5.2.4 Power mode transition operating behaviors
All specifications except tPOR and VLLSx-RUN recovery times in the following table
assume this clock configuration:
• CPU and system clocks = 50 MHz
• Bus clock (and flash and Mini-FlexBus clocks) = 25 MHz
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
12
Freescale Semiconductor, Inc.
Preliminary
Nonswitching electrical specifications
Table 4. Power mode transition operating behaviors
Symbol
Description
Min.
Max.
Unit
Notes
tPOR
After a POR event, amount of time from the point VDD
reaches 1.8 V to execution of the first instruction
across the operating temperature range of the chip.
—
300
μs
1
RUN → VLLS1 → RUN
• RUN → VLLS1
1
1
1
—
—
4.4
μs
μs
• VLLS1 → RUN
TBD
RUN → VLLS2 → RUN
• RUN → VLLS2
—
—
4.6
μs
μs
• VLLS2 → RUN
TBD
RUN → VLLS3 → RUN
• RUN → VLLS3
—
—
4.4
μs
μs
• VLLS3 → RUN
TBD
RUN → LLS → RUN
• RUN → LLS
—
—
4.4
6.5
μs
μs
• LLS → RUN
RUN → VLPS → RUN
• RUN → VLPS
—
—
4.4
4.6
μs
μs
• VLPS → RUN
RUN → STOP → RUN
• RUN → STOP
—
—
4.4
4.6
μs
μs
• STOP → RUN
1. Normal boot (FTFL_FOPT[LPBOOT] is 1)
5.2.5 Power consumption operating behaviors
Table 5. Power consumption operating behaviors
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
IDDA
Analog supply current
—
—
TBD
mA
1
IDD_RUN
Run mode current — all peripheral clocks
disabled, code executing from RAM
2
• @ 1.8 V
• @ 3.0 V
—
—
13.5
14
TBD
TBD
mA
mA
Table continues on the next page...
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
Freescale Semiconductor, Inc.
13
Preliminary
Nonswitching electrical specifications
Table 5. Power consumption operating behaviors (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
IDD_RUN
Run mode current — all peripheral clocks
disabled, code executing from flash memory with
page buffering disabled
2
—
—
16.6
17
TBD
TBD
mA
mA
• @ 1.8 V
• @ 3.0 V
IDD_RUN
Run mode current — all peripheral clocks
enabled, code executing from RAM, exercising
flash memory
3
4
—
—
20
20
TBD
TBD
mA
mA
• @ 1.8 V
• @ 3.0 V
IDD_RUN_MAX
Run mode current — all peripheral clocks
enabled and peripherals active, code executing
from flash memory
—
—
TBD
TBD
TBD
TBD
mA
mA
• @ 1.8 V
• @ 3.0 V
IDD_WAIT
Wait mode current at 3.0 V — all peripheral
clocks disabled
—
—
6.6
TBD
TBD
mA
mA
5
6
IDD_WAIT
Wait mode current at 3.0 V — all peripheral
clocks disabled
TBD
IDD_STOP
IDD_VLPR
Stop mode current at 3.0 V
—
—
0.34
0.63
TBD
TBD
mA
mA
Very-low-power run mode current at 3.0 V — all
peripheral clocks disabled
7
8
IDD_VLPR
Very-low-power run mode current at 3.0 V — all
peripheral clocks enabled
—
0.78
TBD
mA
IDD_VLPW
IDD_VLPS
IDD_LLS
Very-low-power wait mode current at 3.0 V
Very-low-power stop mode current at 3.0 V
—
—
0.15
12
TBD
TBD
mA
μA
9
10
Low leakage stop mode current at 3.0 V
• @ –40 to 25 °C
10,11,12
—
—
—
3.0
TBD
TBD
TBD
μA
μA
μA
• @ 70 °C
TBD
TBD
• @ 105 °C
IDD_VLLS3
Very low-leakage stop mode 3 current at 3.0 V
10,11,12
10,11
• @ –40 to 25 °C
• @ 70 °C
—
—
—
2.0
TBD
TBD
TBD
μA
μA
μA
TBD
TBD
• @ 105 °C
IDD_VLLS2
Very low-leakage stop mode 2 current at 3.0 V
• @ –40 to 25 °C
• @ 70 °C
—
—
—
1.5
TBD
TBD
TBD
μA
μA
μA
TBD
TBD
• @ 105 °C
Table continues on the next page...
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
14
Freescale Semiconductor, Inc.
Preliminary
Nonswitching electrical specifications
Table 5. Power consumption operating behaviors (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
IDD_VLLS1
Very low-leakage stop mode 1 current at 3.0 V
10,11
• @ –40 to 25 °C
• @ 70 °C
—
—
—
1.3
TBD
TBD
TBD
μA
μA
μA
TBD
TBD
• @ 105 °C
IDD_OSC
Average current for OSC enabled with 32 kHz
crystal at 3.0 V
—
—
—
0.7
—
—
—
μA
μA
μA
• @ –40 to 25 °C
• @ 70 °C
TBD
TBD
• @ 105 °C
1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See
each module's specification for its supply current.
2. 50 MHz core and system clocks, and 25 MHz bus clock. MCG configured for FEI mode. All peripheral clocks disabled.
3. 50 MHz core and system clocks, and 25 MHz bus clock. MCG configured for FEI mode. All peripheral clocks enabled, but
peripherals are not in active operation.
4. 50 MHz core and system clocks, and 25 MHz bus clock. MCG configured for FEI mode. All peripheral clocks enabled, and
peripherals are in active operation.
5. 25 MHz core and system clocks, and 12.5 MHz bus clock. MCG configured for FEI mode.
6. 50 MHz core and system clocks, and 25 MHz bus clock. MCG configured for FEI mode.
7. 2 MHz core and system clocks, and 1 MHz bus clock. MCG configured for BLPE mode. All peripheral clocks disabled.
Code executing from flash memory.
8. 2 MHz core and system clocks, and 1 MHz bus clock. MCG configured for fast IRCLK mode. All peripheral clocks enabled,
but peripherals are not in active operation. Code executing from flash memory.
9. 2 MHz core and system clocks, and 1 MHz bus clock. MCG configured for fast IRCLK mode. All peripheral clocks disabled.
10. OSC clocks disabled.
11. All pads disabled.
12. Data reflects devices with 32 KB of RAM. For devices with 16 KB of RAM, power consumption is reduced by 500 nA. For
devices with 8 KB of RAM, power consumption is reduced by 750 nA.
5.2.5.1 Diagram: Typical IDD_RUN operating behavior
The following data was measured under these conditions:
• MCG in FEI mode (39.0625 kHz IRC), except for 1 MHz core (FBE)
• All peripheral clocks disabled except FTFL
• LVD disabled, USB voltage regulator disabled
• No GPIOs toggled
• Code execution from flash memory
DIAGRAM TBD
Figure 1. Run mode supply current vs. core frequency — all peripheral clocks disabled
The following data was measured under these conditions:
• MCG in FEI mode (39.0625 kHz IRC), except for 1 MHz core (FBE)
• All peripheral clocks enabled, but peripherals are not in active operation
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
Freescale Semiconductor, Inc.
15
Preliminary
Nonswitching electrical specifications
• LVD disabled, USB voltage regulator disabled
• No GPIOs toggled
• Code execution from flash memory
DIAGRAM TBD
Figure 2. Run mode supply current vs. core frequency — all peripheral clocks enabled
5.2.6 EMC radiated emissions operating behaviors
Table 6. EMC radiated emissions operating behaviors
Symbol
Description
Frequency
band (MHz)
Typ.
Unit
Notes
VRE1
VRE2
VRE3
VRE4
Radiated emissions voltage, band 1
Radiated emissions voltage, band 2
Radiated emissions voltage, band 3
Radiated emissions voltage, band 4
0.15–50
50–150
TBD
TBD
TBD
TBD
TBD
dBμV
1, 2
150–500
500–1000
0.15–1000
VRE_IEC_SAE IEC and SAE level
—
2, 3
1. Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions, 150
kHz to 1 GHz Part 1: General Conditions and Definitions, IEC Standard 61967-2, Integrated Circuits - Measurement of
Electromagnetic Emissions, 150 kHz to 1 GHz Part 2: Measurement of Radiated Emissions—TEM Cell and Wideband
TEM Cell Method, and SAE Standard J1752-3, Measurement of Radiated Emissions from Integrated Circuits—TEM/
Wideband TEM (GTEM) Cell Method.
2. VDD = 3 V, TA = 25 °C, fOSC = 16 MHz (crystal), fBUS = 25 MHz
3. Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and Wideband
TEM Cell Method, and Appendix D of SAE Standard J1752-3, Measurement of Radiated Emissions from Integrated
Circuits—TEM/Wideband TEM (GTEM) Cell Method.
5.2.7 Designing with radiated emissions in mind
To find application notes that provide guidance on designing your system to minimize
interference from radiated emissions:
1. Go to http://www.freescale.com.
2. Perform a keyword search for “EMC design.”
5.2.8 Capacitance attributes
Table 7. Capacitance attributes
Symbol
Description
Min.
Max.
Unit
CIN_A
Input capacitance: analog pins
—
7
pF
CIN_D
Input capacitance: digital pins
—
7
pF
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
16
Freescale Semiconductor, Inc.
Preliminary
Nonswitching electrical specifications
5.3 Switching electrical specifications
Table 8. Device clock specifications
Symbol
Description
Min.
Max.
Unit
Notes
Normal run mode
fSYS
fSYS_USB
fBUS
System and core clock
—
20
—
—
—
50
—
25
25
25
MHz
MHz
MHz
MHz
MHz
System and core clock when USB in operation
Bus clock
FB_CLK
fLPTMR
Mini-FlexBus clock
LPTMR clock
VLPR mode
fSYS
fBUS
System and core clock
Bus clock
—
—
—
—
2
1
MHz
MHz
MHz
MHz
FB_CLK
fLPTMR
Mini-FlexBus clock
LPTMR clock
1
25
5.3.1 General Switching Specifications
These general purpose specifications apply to all signals configured for EGPIO, MTIM,
CMT, PDB, IRQ, and I2C signals. The conditions are 50 pf load, VDD = 1.71 V to 3.6 V,
and full temperature range. The GPIO are set for high drive, no slew rate control, and no
input filter, digital or analog, unless otherwise specified.
Table 9. EGPIO General Control Timing
Symbol
G1
Description
Min.
Max.
Unit
Bus clock from CLK_OUT pin high to GPIO output valid
—
1
32
—
ns
ns
G2
Bus clock from CLK_OUT pin high to GPIO output invalid
(output hold)
G3
G4
GPIO input valid to bus clock high
28
—
—
4
ns
ns
Bus clock from CLK_OUT pin high to GPIO input invalid
GPIO pin interrupt pulse width (digital glitch filter disabled)
Synchronous path1
1.5
—
Bus
clock
cycles
GPIO pin interrupt pulse width (digital glitch filter disabled,
analog filter enabled)
100
—
ns
Asynchronous path2
Table continues on the next page...
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
Freescale Semiconductor, Inc.
17
Preliminary
Nonswitching electrical specifications
Table 9. EGPIO General Control Timing (continued)
Symbol
Description
Min.
Max.
Unit
GPIO pin interrupt pulse width (digital glitch filter disabled,
analog filter disabled)
50
—
ns
ns
Asynchronous path2
External reset pulse width (digital glitch filter disabled)
Mode select (MS) hold time after reset deassertion
100
2
—
—
Bus
clock
cycles
1. The greater synchronous and asynchronous timing must be met.
2. This is the shortest pulse that is guaranteed to be recognized.
Bus clock
G1
G2
Data outputs
G3
G4
Data inputs
Figure 3. EGPIO timing diagram
The following general purpose specifications apply to all signals configured for RGPIO,
FTM, and UART. The conditions are 25 pf load, VDD = 3.6 V to 1.71 V, and full
temperature range. The GPIO are set for high drive, no slew rate control, and no input
filter, digital or analog, unless otherwise specified.
Table 10. RGPIO General Control Timing
Symbol
R1
Description
Min.
Max.
Unit
CPUCLK from CLK_OUT pin high to GPIO output valid
—
1
16
—
ns
ns
R2
CPUCLK from CLK_OUT pin high to GPIO output invalid
(output hold)
R3
R4
GPIO input valid to bus clock high
17
—
—
2
ns
ns
CPUCLK from CLK_OUT pin high to GPIO input invalid
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
18
Freescale Semiconductor, Inc.
Preliminary
Thermal specifications
Bus clock
R1
R2
Data outputs
Data inputs
R3
R4
Figure 4. RGPIO timing diagram
5.4 Thermal specifications
5.4.1 Thermal operating requirements
Table 11. Thermal operating requirements
Symbol
Description
Min.
Max.
Unit
TJ
Die junction temperature
–40
125
105
°C
TA
Ambient temperature
–40
°C
5.4.2 Thermal attributes
Board type Symbol
Description
64 LQFP
64
48 LQFP
44
32 QFN Unit Notes
Laminate
QFN
Laminate
QFN
Single-layer RθJA
(1s)
Thermal resistance,
junction to ambient
(natural convection)
73
54
61
48
108
79
55
66
48
108
98
33
81
28
°C/W
°C/W
°C/W
°C/W
1
1
1
1
Four-layer
(2s2p)
RθJA
Thermal resistance,
junction to ambient
(natural convection)
69
69
Single-layer RθJMA
(1s)
Thermal resistance,
junction to ambient
(200 ft./min. air speed)
91
91
Four-layer
(2s2p)
RθJMA
Thermal resistance,
junction to ambient
(200 ft./min. air speed)
63
63
Table continues on the next page...
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
Freescale Semiconductor, Inc.
19
Preliminary
Peripheral operating requirements and behaviors
Board type Symbol
Description
64 LQFP
64
48 LQFP
44
32 QFN Unit Notes
Laminate
QFN
Laminate
QFN
—
—
—
RθJB
RθJC
ΨJT
Thermal resistance,
junction to board
37
20
5.0
44
34
20
4.0
44
13
°C/W
°C/W
°C/W
2
3
4
Thermal resistance,
junction to case
31
31
2.2
6.0
Thermal
6.0
6.0
characterization
parameter, junction to
package top outside
center (natural
convection)
1. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions
—Natural Convection (Still Air), or EIA/JEDEC Standard JESD51-6, Integrated Circuit Thermal Test Method
Environmental Conditions—Forced Convection (Moving Air).
2. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental Conditions
—Junction-to-Board.
3. Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate
temperature used for the case temperature. The value includes the thermal resistance of the interface material between
the top of the package and the cold plate.
4. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions
—Natural Convection (Still Air).
6 Peripheral operating requirements and behaviors
6.1 Core modules
6.1.1 Debug specifications
Table 12. Background debug mode (BDM) timing
Number
Symbol
tMSSU
Description
Min.
500
Max.
Unit
1
2
BKGD/MS setup time after issuing background
debug force reset to enter user mode or BDM
—
—
ns
µs
tMSH
BKGD/MS hold time after issuing background
debug force reset to enter user mode or BDM1
100
1. To enter BDM mode following a POR, BKGD/MS should be held low during the power-up and for a hold time of tMSH after
VDD rises above VLVD
.
6.2 System modules
There are no specifications necessary for the device's system modules.
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
20
Freescale Semiconductor, Inc.
Preliminary
Clock modules
6.3 Clock modules
6.3.1 MCG specifications
Table 13. MCG specifications
Symbol Description
Min.
Typ.
Max.
Unit
Notes
fints_ft Internal reference frequency (slow clock) —
—
32.768
—
kHz
factory trimmed at nominal VDD and 25°C
fints_t
Internal reference frequency (slow clock) — user
trimmed
31.25
—
39.0625
kHz
Iints
Internal reference (slow clock) current
—
—
—
TBD
TBD
0.1
—
4
µA
µs
tirefsts
Internal reference (slow clock) startup time
Δfdco_res_t Resolution of trimmed DCO output frequency at
fixed voltage and temperature — using SCTRIM
and SCFTRIM
0.3
%fdco
1
1
Δfdco_res_t Resolution of trimmed DCO output frequency at
fixed voltage and temperature — using SCTRIM
only
—
0.2
0.5
%fdco
Δfdco_t
Total deviation of trimmed average DCO output
frequency over voltage and temperature
—
—
+ 0.5
- 1.0
0.5
3.5
%fdco
%fdco
1
1
Δfdco_t
Total deviation of trimmed average DCO output
frequency over fixed voltage and temperature
range of 0–70°C
TBD
fintf_ft
Internal reference frequency (fast clock) —
factory trimmed at nominal VDD and 25°C
3.4
3
—
—
4
5
MHz
MHz
fintf_t
Internal reference frequency (fast clock) — user
trimmed
Iintf
Internal reference (fast clock) current
—
—
TBD
TBD
—
—
TBD
—
µA
µs
tirefstf
floc_low
Internal reference startup time (fast clock)
Loss of external clock minimum frequency —
RANGE = 00
(3/5) x
fints_t
kHz
floc_high
Loss of external clock minimum frequency —
RANGE = 01, 10, or 11
(16/5) x
fints_t
—
—
—
kHz
kHz
FLL
ffll_ref
FLL reference frequency range
31.25
39.0625
Table continues on the next page...
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
Freescale Semiconductor, Inc.
21
Preliminary
Clock modules
Table 13. MCG specifications (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
fdco
DCO output
frequency range
Low range (DRS=00)
640 × ffll_ref
20
20.97
25
MHz
2, 3
Mid range (DRS=01)
1280 × ffll_ref
40
60
80
—
—
—
—
41.94
62.91
83.89
23.99
47.97
71.99
95.98
50
75
100
—
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Mid-high range (DRS=10)
1920 × ffll_ref
High range (DRS=11)
2560 × ffll_ref
fdco_t_DMX3 DCO output
Low range (DRS=00)
732 × ffll_ref
4, 5
frequency
2
Mid range (DRS=01)
1464 × ffll_ref
—
Mid-high range (DRS=10)
2197 × ffll_ref
—
High range (DRS=11)
2929 × ffll_ref
—
Jcyc_fll
Jacc_fll
FLL period jitter
—
—
TBD
TBD
TBD
TBD
ps
ps
6
6
FLL accumulated jitter of DCO output over a 1µs
time window
tfll_acquire FLL target frequency acquisition time
—
—
1
ms
7
PLL
fvco
Ipll
VCO operating frequency
48.0
—
—
100
—
MHz
µA
PLL operating current
8
8
1060
• PLL @ 96 MHz (fosc_hi_1 = 8 MHz, fpll_ref
2 MHz, VDIV multiplier = 48)
=
=
Ipll
PLL operating current
—
600
—
—
µA
• PLL @ 48 MHz (fosc_hi_1 = 8 MHz, fpll_ref
2 MHz, VDIV multiplier = 24)
fpll_ref
PLL reference frequency range
2.0
4.0
MHz
Jcyc_pll
PLL period jitter
• fvco = 48 MHz
• fvco = 100 MHz
9, 10
9, 10
—
—
120
50
—
—
ps
ps
Jacc_pll
PLL accumulated jitter over 1µs window
• fvco = 48 MHz
—
—
1350
600
—
—
ps
ps
• fvco = 100 MHz
Table continues on the next page...
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
22
Freescale Semiconductor, Inc.
Preliminary
Clock modules
Notes
Table 13. MCG specifications (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Dlock
Dunl
Lock entry frequency tolerance
1.49
—
2.98
%
Lock exit frequency tolerance
Lock detector detection time
4.47
—
—
—
5.97
%
tpll_lock
0.15 +
ms
11
1075(1/
fpll_ref
)
1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock
mode).
2. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=0.
3. The resulting system clock frequencies should not exceed their maximum specified values. The DCO frequency deviation
(Δfdco_t) over voltage and temperature should be considered.
4. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=1.
5. The resulting clock frequency must not exceed the maximum specified clock frequency of the device.
6. This specification was obtained at TBD frequency.
7. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed,
DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE,
FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running.
8. Excludes any oscillator currents that are also consuming power while PLL is in operation.
9. This specification was obtained using a Freescale developed PCB. PLL jitter is dependent on the noise characteristics of
each PCB and results will vary.
10. PLL period jitter is measured in RMS.
11. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled
(BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes
it is already running.
6.3.2 Oscillator electrical specifications
This section provides the electrical characteristics of the module.
6.3.2.1 Oscillator DC electrical specifications
Table 14. Oscillator DC electrical specifications
Symbol Description
Min.
Typ.
Max.
Unit
Notes
VDD
Supply voltage
1.71
—
3.6
V
IDDOSC
Supply current — low-power mode (HGO=0)
1
• 32 kHz
—
—
—
—
—
—
—
500
100
200
300
950
1.2
—
—
—
—
—
—
—
nA
μA
μA
μA
μA
mA
mA
• 1 MHz
• 4 MHz
• 8 MHz (only RANGE=01)
• 16 MHz
• 24 MHz
• 32 MHz
1.5
Table continues on the next page...
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
Freescale Semiconductor, Inc.
23
Preliminary
Clock modules
Table 14. Oscillator DC electrical specifications (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
IDDOSC
Supply current — high gain mode (HGO=1)
1
• 32 kHz
—
—
—
—
—
—
—
25
200
400
500
2.5
3
—
—
—
—
—
—
—
μA
μA
• 1 MHz
• 4 MHz
μA
• 8 MHz (only RANGE=01)
• 16 MHz
μA
mA
mA
mA
• 24 MHz
• 32 MHz
4
Cx
Cy
RF
EXTAL load capacitance
XTAL load capacitance
—
—
—
—
—
—
—
—
—
2, 3
2, 3
2, 4
Feedback resistor — low-frequency, low-power
mode (HGO=0)
MΩ
MΩ
MΩ
MΩ
kΩ
Feedback resistor — low-frequency, high-gain
mode (HGO=1)
—
—
—
—
—
—
10
—
—
—
—
—
—
—
Feedback resistor — high-frequency, low-power
mode (HGO=0)
Feedback resistor — high-frequency, high-gain
mode (HGO=1)
1
RS
Series resistor — low-frequency, low-power
mode (HGO=0)
—
Series resistor — low-frequency, high-gain mode
(HGO=1)
200
—
kΩ
Series resistor — high-frequency, low-power
mode (HGO=0)
kΩ
Series resistor — high-frequency, high-gain
mode (HGO=1)
• 1 MHz resonator
• 2 MHz resonator
• 4 MHz resonator
• 8 MHz resonator
• 16 MHz resonator
• 20 MHz resonator
• 32 MHz resonator
—
—
—
—
—
—
—
6.6
3.3
0
—
—
—
—
—
—
—
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
0
0
0
0
Table continues on the next page...
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
24
Freescale Semiconductor, Inc.
Preliminary
Clock modules
Notes
Table 14. Oscillator DC electrical specifications (continued)
Symbol Description
Min.
Typ.
Max.
Unit
5
Peak-to-peak amplitude of oscillation (oscillator
—
0.6
—
V
Vpp
mode) — low-frequency, low-power mode
(HGO=0)
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, high-gain mode
(HGO=1)
—
—
—
VDD
0.6
—
—
—
V
V
V
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, low-power mode
(HGO=0)
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, high-gain mode
(HGO=1)
VDD
1. VDD=3.3 V, Temperature =25 °C
2. See crystal or resonator manufacturer's recommendation
3. Cx,Cy can be provided by using either the integrated capacitors or by using external components.
4. When low power mode is selected, RF is integrated and must not be attached externally.
5. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to any
other devices.
6.3.2.2 Oscillator frequency specifications
Table 15. Oscillator frequency specifications
Symbol Description
Min.
Typ.
Max.
Unit
Notes
fosc_lo
Oscillator crystal or resonator frequency — low
32
—
40
kHz
frequency mode (MCG_C2[RANGE]=00)
fosc_hi_1
Oscillator crystal or resonator frequency — high
frequency mode (low range)
(MCG_C2[RANGE]=01)
1
8
—
—
8
MHz
MHz
fosc_hi_2
Oscillator crystal or resonator frequency — high
frequency mode (high range)
32
(MCG_C2[RANGE]=1x)
fec_extal
tdc_extal
tcst
Input clock frequency (external clock mode)
Input clock duty cycle (external clock mode)
—
40
—
—
50
50
60
—
MHz
%
1
Crystal startup time — 32 kHz low-frequency,
low-power mode (HGO=0)
750
ms
2, 3
Crystal startup time — 32 kHz low-frequency,
high-gain mode (HGO=1)
—
—
250
0.6
—
—
ms
ms
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), low-power mode
(HGO=0)
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), high-gain mode
(HGO=1)
—
1
—
ms
1. Other frequency limits may apply when external clock is being used as a reference for the FLL or PLL
2. Proper PC board layout procedures must be followed to achieve specifications.
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
Freescale Semiconductor, Inc.
25
Preliminary
Memories and memory interfaces
3. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S register
being set.
6.4 Memories and memory interfaces
6.4.1 Flash (FTFL) electrical specifications
This section describes the electrical characteristics of the FTFL module.
6.4.1.1 Flash timing specifications — program and erase
The following specifications represent the amount of time the internal charge pumps are
active and do not include command overhead.
Table 16. NVM program/erase timing specifications
Symbol Description
thvpgm4 Longword Program high-voltage time
thversscr Sector Erase high-voltage time
Min.
Typ.
Max.
Unit
Notes
—
20
TBD
μs
—
—
—
20
20
80
100
100
400
ms
ms
ms
1
1
1
thversblk32k Erase Block high-voltage time for 32 KB
thversblk128k Erase Block high-voltage time for 128 KB
1. Maximum time based on expectations at cycling end-of-life.
6.4.1.2 Flash timing specifications — commands
Table 17. Flash command timing specifications
Symbol Description
Read 1s Block execution time
Min.
Typ.
Max.
Unit
Notes
trd1blk32k
• 32 KB data flash
• 128 KB data flash
—
—
—
—
0.4
1.4
ms
ms
trd1blk128k
trd1sec1k
tpgmchk
trdrsrc
Read 1s Section execution time (flash sector)
Program Check execution time
—
—
—
—
—
—
—
50
40
35
μs
μs
μs
μs
1
1
1
Read Resource execution time
35
tpgm4
Program Longword execution time
TBD
Erase Flash Block execution time
• 32 KB data flash
2
2
tersblk32k
—
—
20
80
100
400
ms
ms
• 128 KB data flash
tersblk128k
tersscr
Erase Flash Sector execution time
—
20
100
ms
Table continues on the next page...
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
26
Freescale Semiconductor, Inc.
Preliminary
Memories and memory interfaces
Table 17. Flash command timing specifications (continued)
Symbol Description
Program Section execution time
Min.
Typ.
Max.
Unit
Notes
tpgmsec512
tpgmsec1k
• 512 B flash
• 1 KB flash
—
—
TBD
TBD
TBD
TBD
ms
ms
trd1all
Read 1s All Blocks execution time
Read Once execution time
—
—
—
—
—
—
—
1.8
35
ms
μs
μs
ms
μs
trdonce
1
tpgmonce Program Once execution time
50
100
—
TBD
500
35
tersall
Erase All Blocks execution time
2
1
tvfykey
Verify Backdoor Access Key execution time
Program Partition for EEPROM execution time
• 32 KB FlexNVM
tpgmpart32k
—
25
TBD
ms
Set FlexRAM Function execution time:
• 8 KB EEPROM backup
tsetram8k
—
—
TBD
TBD
TBD
TBD
ms
ms
• 32 KB EEPROM backup
tsetram32k
Byte-write to FlexRAM for EEPROM operation
teewr8bers Byte-write to erased FlexRAM location execution
time
—
100
TBD
μs
3
Byte-write to FlexRAM execution time:
teewr8b8k
teewr8b16k
teewr8b32k
• 8 KB EEPROM backup
• 16 KB EEPROM backup
• 32 KB EEPROM backup
—
—
—
TBD
TBD
TBD
TBD
TBD
1.5
ms
ms
ms
Word-write to FlexRAM for EEPROM operation
teewr16bers Word-write to erased FlexRAM location
execution time
—
100
TBD
μs
Word-write to FlexRAM execution time:
teewr16b8k
teewr16b16k
teewr16b32k
• 8 KB EEPROM backup
• 16 KB EEPROM backup
• 32 KB EEPROM backup
—
—
—
TBD
TBD
TBD
TBD
TBD
1.5
ms
ms
ms
Longword-write to FlexRAM for EEPROM operation
teewr32bers Longword-write to erased FlexRAM location
execution time
—
200
TBD
μs
Longword-write to FlexRAM execution time:
teewr32b8k
teewr32b16k
teewr32b32k
• 8 KB EEPROM backup
• 16 KB EEPROM backup
• 32 KB EEPROM backup
—
—
—
TBD
TBD
TBD
TBD
TBD
2.7
ms
ms
ms
1. Assumes 25MHz flash clock frequency.
2. Maximum times for erase parameters based on expectations at cycling end-of-life.
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
Freescale Semiconductor, Inc.
27
Preliminary
Memories and memory interfaces
3. For byte-writes to an erased FlexRAM location, the aligned word containing the byte must be erased.
6.4.1.3 Flash (FTFL) current and power specfications
Table 18. Flash (FTFL) current and power specfications
Symbol
Description
Typ.
Unit
IDD_PGM
Worst case programming current in program flash
10
mA
6.4.1.4 Reliability specifications
Table 19. NVM reliability specifications
Typ.1
Symbol Description
Min.
Program Flash
Max.
Unit
Notes
tnvmretp10k Data retention after up to 10 K cycles
tnvmretp1k Data retention after up to 1 K cycles
tnvmretp100 Data retention after up to 100 cycles
nnvmcycp Cycling endurance
5
10
TBD
TBD
TBD
TBD
—
—
—
—
years
years
years
cycles
2
2
2
3
15
10 K
Data Flash
tnvmretd10k Data retention after up to 10 K cycles
tnvmretd1k Data retention after up to 1 K cycles
tnvmretd100 Data retention after up to 100 cycles
nnvmcycd Cycling endurance
5
TBD
TBD
TBD
TBD
—
—
—
—
years
years
years
cycles
2
2
2
3
10
15
10 K
FlexRAM as EEPROM
tnvmretee100 Data retention up to 100% of write endurance
tnvmretee10 Data retention up to 10% of write endurance
tnvmretee1 Data retention up to 1% of write endurance
Write endurance
5
TBD
TBD
TBD
—
—
—
years
years
years
2
2
2
4
10
15
nnvmwree16
nnvmwree128
nnvmwree512
nnvmwree4k
nnvmwree8k
• EEPROM backup to FlexRAM ratio = 16
• EEPROM backup to FlexRAM ratio = 128
• EEPROM backup to FlexRAM ratio = 512
• EEPROM backup to FlexRAM ratio = 4096
• EEPROM backup to FlexRAM ratio = 8192
35 K
315 K
1.27 M
10 M
TBD
TBD
TBD
TBD
TBD
—
—
—
—
—
writes
writes
writes
writes
writes
20 M
1. Typical data retention values are based on intrinsic capability of the technology measured at high temperature derated to
25°C. For additional information on how Freescale defines typical data retention, please refer to Engineering Bulletin
EB618.
2. Data retention is based on Tjavg = 55°C (temperature profile over the lifetime of the application).
3. Cycling endurance represents number of program/erase cycles at -40°C ≤ Tj ≤ 125°C.
4. Write endurance represents the number of writes to each FlexRAM location at -40°C ≤Tj ≤ 125°C influenced by the cycling
endurance of the FlexNVM (same value as data flash) and the allocated EEPROM backup. Minimum value assumes all
byte-writes to FlexRAM.
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
28
Freescale Semiconductor, Inc.
Preliminary
Memories and memory interfaces
6.4.1.5 Write endurance to FlexRAM for EEPROM
When the FlexNVM partition code is not set to full data flash, the EEPROM data set size
can be set to any of several non-zero values.
The bytes not assigned to data flash via the FlexNVM partition code are used by the
FTFL to obtain an effective endurance increase for the EEPROM data. The built-in
EEPROM record management system raises the number of program/erase cycles that can
be attained prior to device wear-out by cycling the EEPROM data through a larger
EEPROM NVM storage space.
While different partitions of the FlexNVM are available, the intention is that a single
choice for the FlexNVM partition code and EEPROM data set size is used throughout the
entire lifetime of a given application. The EEPROM endurance equation and graph
shown below assume that only one configuration is ever used.
EEPROM – 2 × EEESIZE
Writes_FlexRAM =
× Write_efficiency × nnvmcycd
where
• Writes_FlexRAM — minimum number of writes to each FlexRAM location
• EEPROM — allocated FlexNVM based on DEPART; entered with Program
Partition command
• EEESIZE — allocated FlexRAM based on DEPART; entered with Program Partition
command
• Write_efficiency —
• 0.25 for 8-bit writes to FlexRAM
• 0.50 for 16-bit or 32-bit writes to FlexRAM
• nnvmcycd — data flash cycling endurance
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
Freescale Semiconductor, Inc.
29
Preliminary
Memories and memory interfaces
Figure 5. EEPROM backup writes to FlexRAM
6.4.2 EzPort Switching Specifications
Table 20. EzPort switching specifications
Num
Description
Min.
2.7
—
Max.
3.6
Unit
V
Operating voltage
EP1
EZP_CK frequency of operation (all commands except
READ)
fSYS/2
MHz
EP1a
EP2
EP3
EP4
EP5
EP6
EP7
EP8
EZP_CK frequency of operation (READ command)
EZP_CS negation to next EZP_CS assertion
EZP_CS input valid to EZP_CK high (setup)
EZP_CK high to EZP_CS input invalid (hold)
EZP_D input valid to EZP_CK high (setup)
EZP_CK high to EZP_D input invalid (hold)
EZP_CK low to EZP_Q output valid (setup)
EZP_CK low to EZP_Q output invalid (hold)
—
fSYS/8
—
MHz
ns
2 x tEZP_CK
15
0.0
15
—
ns
—
ns
—
ns
0.0
—
—
ns
25
—
ns
0.0
ns
Table continues on the next page...
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
30
Freescale Semiconductor, Inc.
Preliminary
Memories and memory interfaces
Table 20. EzPort switching specifications (continued)
Num
Description
Min.
Max.
Unit
EP9
EZP_CS negation to EZP_Q tri-state
—
12
ns
EZP_CK
EZP_CS
EP3
EP4
EP2
EP9
EP7
EP8
EZP_Q (output)
EZP_D (input)
EP5
EP6
Figure 6. EzPort Timing Diagram
6.4.3 Mini-Flexbus Switching Specifications
All processor bus timings are synchronous; input setup/hold and output delay are given in
respect to the rising edge of a reference clock, FB_CLK. The FB_CLK frequency may be
the same as the internal system bus frequency or an integer divider of that frequency.
The following timing numbers indicate when data is latched or driven onto the external
bus, relative to the Mini-Flexbus output clock (FB_CLK). All other timing relationships
can be derived from these values.
Table 21. Flexbus switching specifications
Num
Description
Min.
2.7
—
Max.
3.6
25
Unit
V
Notes
Operating voltage
Frequency of operation
Clock period
MHz
ns
FB1
FB2
FB3
FB4
FB5
20
—
Address, data, and control output valid
Address, data, and control output hold
Data and FB_TA input setup
Data and FB_TA input hold
TBD
1
20
ns
1
1
2
2
—
ns
20
—
ns
10
—
ns
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
Freescale Semiconductor, Inc.
31
Preliminary
Memories and memory interfaces
1. Specification is valid for all FB_AD[31:0], FB_CSn, FB_OE, FB_R/W, and FB_TS.
2. Specification is valid for all FB_AD[31:0].
Note
The following diagrams refer to signal names that may not be
included on your particular device. Ignore these extraneous
signals.
Also, ignore the AA=0 portions of the diagrams because this
setting is not supported in the Mini-FlexBus.
FB1
FB_CLK
FB3
FB5
FB_A[Y]
FB_D[X]
FB_RW
FB_TS
Address
FB4
FB2
Address
Data
FB_ALE
FB_CSn
FB_OEn
FB_BEn
FB_TA
AA=1
AA=0
FB4
FB5
AA=1
AA=0
FB_TSIZ[1:0]
TSIZ
Figure 7. Mini-FlexBus read timing diagram
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
32
Freescale Semiconductor, Inc.
Preliminary
Memories and memory interfaces
FB1
FB_CLK
FB_A[Y]
FB_D[X]
FB_RW
FB_TS
FB2
FB3
Address
Address
Data
FB_ALE
FB_CSn
FB_OEn
FB_BEn
FB_TA
AA=1
AA=0
FB4
FB5
AA=1
AA=0
FB_TSIZ[1:0]
TSIZ
Figure 8. Mini-FlexBus write timing diagram
6.5 Security and integrity modules
There are no specifications necessary for the device's security and integrity modules.
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
Freescale Semiconductor, Inc.
33
Preliminary
Analog
6.6 Analog
6.6.1 ADC electrical specifications
All ADC channels meet the 12-bit single-ended accuracy specifications.
6.6.1.1 12-bit ADC operating conditions
Table 22. 12-bit ADC operating conditions
Typ.1
Symbol Description
Conditions
Absolute
Min.
1.71
-100
Max.
3.6
Unit
V
Notes
VDDA
Supply voltage
Supply voltage
—
ΔVDDA
Delta to VDD (VDD
-
0
+100
mV
2
2
VDDA
)
ΔVSSA
Ground voltage
Delta to VSS (VSS
-
-100
0
+100
mV
VSSA
)
VREFH
ADC reference
voltage high
1.13
VSSA
VREFL
VDDA
VDDA
V
V
VREFL
Reference
voltage low
VSSA
VSSA
VADIN
CADIN
Input voltage
—
4
VREFH
5
V
Input
capacitance
• 8/10/12 bit
modes
—
—
—
pF
RADIN
RAS
Input resistance
2
5
5
kΩ
kΩ
Analog source
resistance
12 bit modes
fADCK < 4MHz
3
—
—
fADCK
ADC conversion ≤ 12 bit modes
clock frequency
4
5
1.0
—
—
18.0
MHz
Ksps
Crate
ADC conversion ≤ 12 bit modes
rate
No ADC hardware
averaging
20.000
818.330
Continuous
conversions enabled,
subsequent conversion
time
1. Typical values assume VDDA = 3.0 V, Temp = 25°C, fADCK = 1.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
2. DC potential difference.
3. This resistance is external to MCU. The analog source resistance should be kept as low as possible in order to achieve the
best results. The results in this datasheet were derived from a system which has <8 Ω analog source resistance. The RAS
/
CAS time constant should be kept to <1ns.
4. In order to use the maximum ADC conversion clock frequency ADHSC bit should be set and the ADLPC should be clear.
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
34
Freescale Semiconductor, Inc.
Preliminary
Analog
5. For guidelines and examples of conversion rate calculation please download the ADC calculator tool http://
cache.freescale.com/files/soft_dev_tools/software/app_software/converters/ADC_CALCULATOR_CNV.zip?fpsp=1
SIMPLIFIED
INPUT PIN EQUIVALENT
ZADIN
CIRCUIT
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
Pad
leakage
due to
input
protection
ZAS
ADC SAR
ENGINE
RAS
RADIN
VADIN
CAS
VAS
RADIN
RADIN
RADIN
INPUT PIN
INPUT PIN
INPUT PIN
CADIN
Figure 9. ADC input impedance equivalency diagram
6.6.1.2 12-bit ADC electrical characteristics
Table 23. 12-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA
)
Conditions1
Typ.2
Symbol Description
Min.
Max.
Unit
Notes
IDDA_ADC Supply current
0.215
—
1.7
mA
3
ADC
asynchronous
clock source
• ADLPC=1, ADHSC=0
1.2
3.0
2.4
4.4
2.4
4.0
5.2
6.2
3.9
7.3
6.1
9.5
tADACK = 1/
fADACK
MHz
MHz
MHz
MHz
• ADLPC=1, ADHSC=1
• ADLPC=0, ADHSC=0
• ADLPC=0, ADHSC=1
fADACK
Sample Time
See Reference Manual chapter for sample times
Conversion Time The ADC calculator tool can be used to determine ADC conversion times for different ADC
configurations: http://cache.freescale.com/files/soft_dev_tools/software/app_software/
converters/ADC_CALCULATOR_CNV.zip?fpsp=1
Table continues on the next page...
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
Freescale Semiconductor, Inc.
35
Preliminary
Analog
Table 23. 12-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
Conditions1
• 12 bit modes
Typ.2
0.8
Symbol Description
Min.
Max.
TBD
1
Unit
Notes
LSB4
TUE
Total unadjusted
error
ADC
conversion
clock
• <12 bit modes
0.5
<12MHz,
Max
hardware
averaging
(AVGE =
%1, AVGS
= %11)
LSB4
DNL
Differential non-
linearity
• 12 bit modes
• <12 bit modes
0.7
0.2
TBD
0.5
ADC
conversion
clock
<12MHz,
Max
hardware
averaging
(AVGE =
%1, AVGS
= %11)
LSB4
LSB4
INL
EFS
Integral non-
linearity
• 12 bit modes
• <12 bit modes
• 12 bit modes
• <12 bit modes
• 12 bit modes
0.5
0.4
TBD
0.5
Max
averaging
Full-scale error
VADIN
VDDA
=
LSB4
mV
EQ
EIL
Quantization
error
—
—
Input leakage
error
IIn × RAS
IIn =
leakage
current
(refer to
the MCU's
voltage
and
current
operating
ratings)
Temp sensor
slope
• –40°C to 25°C
• 25°C to 105°C
—
—
TBD
TBD
—
—
mV/°C
mV/°C
VTEMP25 Temp sensor
voltage
25°C
—
TBD
—
mV
1. All accuracy numbers assume the ADC is calibrated with VREFH = VDDA
2. Typical values assume VDDA = 3.0 V, Temp = 25°C, fADCK = 2.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and the ADLPC bit (low power).
For lowest power operation the ADLPC bit should be set, the HSC bit should be clear with 1MHz ADC conversion clock
speed.
1 LSB = (VREFH - VREFL)/2N
4.
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
36
Freescale Semiconductor, Inc.
Preliminary
Analog
Figure TBD
Figure 10. Typical TUE vs. ADC conversion rate 12-bit single-ended mode
6.6.2 CMP and 6-bit DAC electrical specifications
Table 24. Comparator and 6-bit DAC electrical specifications
Symbol
Description
Min.
Typ.
Max.
Unit
VDD
Supply voltage
1.71
—
3.6
V
μA
μA
V
IDDHS
IDDLS
VAIN
VAIO
VH
Supply current, High-speed mode (EN=1, PMODE=1)
Supply current, low-speed mode (EN=1, PMODE=0)
Analog input voltage
—
—
—
—
—
—
200
20
VSS – 0.3
—
VDD
20
Analog input offset voltage
mV
Analog comparator hysteresis1
• CR0[HYSTCTR] = 00
• CR0[HYSTCTR] = 01
• CR0[HYSTCTR] = 10
• CR0[HYSTCTR] = 11
—
—
—
—
5
—
—
—
—
mV
mV
mV
mV
10
20
30
VCMPOh
VCMPOl
tDHS
Output high
Output low
VDD – 0.5
—
—
50
—
0.5
200
V
V
—
Propagation delay, high-speed mode (EN=1,
PMODE=1)
20
ns
tDLS
Propagation delay, low-speed mode (EN=1,
PMODE=0)
120
250
600
ns
Analog comparator initialization delay2
6-bit DAC current adder (enabled)
6-bit DAC integral non-linearity
—
—
—
7
40
—
μs
IDAC6b
INL
μA
LSB3
LSB
–0.5
–0.3
—
—
0.5
0.3
DNL
6-bit DAC differential non-linearity
1. Typical hysteresis is measured with input voltage range limited to 0.6 to VDD-0.6V.
2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to DACEN,
VRSEL, PSEL, MSEL, VOSEL) and the comparator output settling to a stable level.
3. 1 LSB = Vreference/64
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
Freescale Semiconductor, Inc.
37
Preliminary
Analog
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0
HYSTCTR
Setting
00
01
10
11
0.1
0.4
0.7
1
1.3
1.6
1.9
2.2
2.5
2.8
3.1
Vinlevel (V)
Figure 11. Typical hysteresis vs. Vin level (VDD=3.3V, PMODE=0)
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
38
Freescale Semiconductor, Inc.
Preliminary
12-bit DAC electrical characteristics
0.18
0.16
0.14
0.12
0.1
HYSTCTR
Setting
00
01
10
11
0.08
0.06
0.04
0.02
0
0.1
0.4
0.7
1
1.3
1.6
1.9
2.2
2.5
2.8
3.1
Vinlevel (V)
Figure 12. Typical hysteresis vs. Vin level (VDD=3.3V, PMODE=1)
6.6.3 12-bit DAC electrical characteristics
6.6.3.1 12-bit DAC operating requirements
Table 25. 12-bit DAC operating requirements
Symbol
Desciption
Min.
Max.
Unit
Notes
VDDA
Supply voltage
1.71
3.6
V
VDACR
TA
Reference voltage
Temperature
1.13
−40
—
3.6
105
100
1
V
1
°C
pF
mA
CL
Output load capacitance
Output load current
2
IL
—
1. The DAC reference can be selected to be VDDA or the voltage output of the VREF module (VREF_OUT)
2. A small load capacitance (47 pF) can improve the bandwidth performance of the DAC
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
Freescale Semiconductor, Inc.
39
Preliminary
12-bit DAC electrical characteristics
6.6.3.2 12-bit DAC operating behaviors
Table 26. 12-bit DAC operating behaviors
Symbol Description
Min.
Typ.
Max.
Unit
Notes
IDDA_DACLP Supply current — low-power mode
—
—
150
μA
IDDA_DACH Supply current — high-speed mode
—
—
700
μA
P
tDACLP
Full-scale settling time (0x080 to 0xF7F) — low-
power mode
—
—
—
—
100
15
200
30
μs
μs
1
1
1
tDACHP
Full-scale settling time (0x080 to 0xF7F) — high-
power mode
tCCDACLP Code-to-code settling time (0xBF8 to 0xC08) —
low-power mode and high-speed mode
0.7
—
1
μs
Vdacoutl
DAC output voltage range low — high-speed
mode, no load, DAC set to 0x000
100
VDACR
mV
mV
Vdacouth DAC output voltage range high — high-speed
mode, no load, DAC set to 0xFFF
VDACR
−100
—
INL
DNL
DNL
Integral non-linearity error — high speed mode
Differential non-linearity error — VDACR > 2 V
—
—
—
—
—
—
8
1
1
LSB
LSB
LSB
2
3
4
Differential non-linearity error — VDACR
VREFO (1.15 V)
=
VOFFSET Offset error
0.4
0.1
60
—
—
—
0.8
0.6
90
—
%FSR
%FSR
dB
5
5
EG
PSRR
TCO
Gain error
Power supply rejection ratio, VDDA > = 2.4 V
Temperature coefficient offset voltage
Temperature coefficient gain error
3.7
μV/C
6
TGE
—
TBD
—
ppm of
FSR/C
AC
Rop
SR
Offset aging coefficient
—
—
—
—
TBD
250
μV/yr
Ω
Output resistance load = 3 kΩ
Slew rate -80h→ F7Fh→ 80h
V/μs
• High power (SPHP
)
1.2
1.7
—
—
0.05
0.12
• Low power (SPLP
)
CT
Channel to channel cross talk
3dB bandwidth
—
—
-80
dB
BW
kHz
• High power (SPHP
)
550
40
—
—
—
—
• Low power (SPLP
)
1. Settling within 1 LSB
2. The INL is measured for 0+100mV to VDACR−100 mV
3. The DNL is measured for 0+100 mV to VDACR−100 mV
4. The DNL is measured for 0+100mV to VDACR−100 mV with VDDA > 2.4V
5. Calculated by a best fit curve from VSS+100 mV to VREF−100 mV
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
40
Freescale Semiconductor, Inc.
Preliminary
12-bit DAC electrical characteristics
6. VDDA = 3.0V, reference select set for VDDA (DACx_CO:DACRFS = 1), high power mode(DACx_C0:LPEN = 0), DAC set
to 0x800, Temp range from -40C to 105C
Figure 13. Typical INL error vs. digital code
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
Freescale Semiconductor, Inc.
41
Preliminary
12-bit DAC electrical characteristics
Figure 14. Offset at half scale vs. temperature
6.6.4 Voltage reference electrical specifications
Table 27. VREF full-range operating requirements
Symbol
Description
Min.
Max.
Unit
Notes
VDDA
Supply voltage
1.71
3.6
V
TA
CL
Temperature
−40
—
105
100
°C
nF
Output load capacitance
Table 28. VREF full-range operating behaviors
Symbol Description
Min.
Typ.
Max.
Unit
Notes
Vout
Voltage reference output with factory trim at
TBD
1.2
TBD
V
nominal VDDA and temperature=25C
Vout
Voltage reference output with— factory trim
TBD
—
TBD
V
Table continues on the next page...
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
42
Freescale Semiconductor, Inc.
Preliminary
12-bit DAC electrical characteristics
Table 28. VREF full-range operating behaviors (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
Vout
Vstep
Vdrift
Voltage reference output — user trim
1.198
—
1.202
V
Voltage reference trim step
—
—
0.5
—
—
mV
mV
Temperature drift (Vmax -Vmin across the full
temperature range)
40
See
Figure 15
Ac
Ibg
Itr
Aging coefficient
—
—
—
—
—
—
TBD
TBD
1.1
ppm/year
µA
Bandgap only (MODE_LV = 00) current
Tight-regulation buffer (MODE_LV =10) current
mA
ΔVLOAD Load regulation (MODE_LV = 10)
• current = + 1.0 mA
mV
1
—
—
—
—
TBD
TBD
• current = - 1.0 mA
Tstup
DC
Buffer startup time
—
—
—
—
—
100
TBD
TBD
µs
mV
dB
Line regulation (power supply rejection)
–60
1. Load regulation voltage is the difference between the VREF_OUT voltage with no load vs. voltage with defined load
Table 29. VREF limited-range operating requirements
Symbol
Description
Min.
Max.
Unit
Notes
Notes
TA
Temperature
0
50
°C
Table 30. VREF limited-range operating behaviors
Symbol
Description
Min.
Max.
Unit
Vout
Voltage reference output with factory trim
TBD
TBD
V
TBD
Figure 15. Typical output vs.temperature
Figure 16. Typical output vs. VDD
TBD
6.7 Timers
See General Switching Specifications.
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
Freescale Semiconductor, Inc.
43
Preliminary
Communication interfaces
6.8 Communication interfaces
6.8.1 USB electrical specifications
The USB electricals for the USB On-the-Go module conform to the standards
documented by the Universal Serial Bus Implementers Forum. For the most up-to-date
standards, visit http://www.usb.org.
6.8.2 USB DCD electrical specifications
Table 31. USB DCD electrical specifications
Symbol
Description
Min.
Typ.
Max.
Unit
VDP_SRC
USB_DP source voltage (up to 250 μA)
TBD
TBD
TBD
V
VLGC
Threshold voltage for logic high
USB_DP source current
USB_DM sink current
0.8
7
—
10
2.0
13
V
IDP_SRC
IDM_SINK
μA
μA
kΩ
V
50
100
—
150
24.8
0.4
RDM_DWN D- pulldown resistance for data pin contact detect
VDAT_REF Data detect voltage
14.25
0.25
TBD
6.8.3 USB VREG electrical specifications
Table 32. USB VREG electrical specifications
Symbol Description
Min.
2.7
—
Typ.
—
Max.
5.5
Unit
Notes
VREGIN Input supply voltage
V
IDDon
IDDstby
IDDoff
Quiescent current — Run mode, load current
equal zero, input supply (VREGIN) > 3.6 V
120
TBD
μA
Quiescent current — Standby mode, load
current equal zero
—
1.1
TBD
μA
Quiescent current — Shutdown mode
• VREGIN = 5.0 V and temperature=25C
• Across operating voltage and temperature
—
—
500
—
—
nA
μA
TBD
ILOADrun Maximum load current — Run mode
ILOADstby Maximum load current — Standby mode
—
—
—
—
120
1
mA
mA
Table continues on the next page...
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
44
Freescale Semiconductor, Inc.
Preliminary
Communication interfaces
Table 32. USB VREG electrical specifications
(continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
VReg33out Regulator output voltage — Input supply
(VREGIN) > 3.6 V
• Run mode
3
3.3
2.8
—
3.6
3.6
3.6
V
V
V
• Standby mode
TBD
TBD
VReg33out Regulator output voltage — Input supply
(VREGIN) < 3.6 V, pass-through mode
1
COUT
ESR
External output capacitor
1.76
1
2.2
—
8.16
100
μF
External output capacitor equivalent series
resistance
mΩ
ILIM
Short circuit current
TBD
290
TBD
mA
1. Operating in pass-through mode: regulator output voltage equal to the input voltage minus a drop proportional to ILoad
.
6.8.4 SPI switching specifications
The Serial Peripheral Interface (SPI) provides a synchronous serial bus with master and
slave operations. Many of the transfer attributes are programmable. The following tables
provide timing characteristics for classic SPI timing modes. Refer to the SPI chapter of
the chip's Reference Manual for information about the modified transfer formats used for
communicating with slower peripheral devices. All timing is shown with respect to 20%
VDD and 70% VDD, unless noted, and 100 pF load on all SPI pins. All timing assumes
slew rate control is disabled and high drive strength is enabled for SPI output pins.
Table 33. SPI master mode timing
Num.
Symbol Description
Min.
Max.
Unit
Comment
1
fop
Frequency of operation
fBUS/2048
fBUS/2
Hz
fBUS is the
bus clock
as defined
in Table 8.
2
tSPSCK
SPSCK period
2 x tBUS
2048 x
tBUS
ns
tBUS = 1/
fBUS
3
4
5
tLead
tLag
Enable lead time
Enable lag time
1/2
1/2
—
—
tSPSCK
tSPSCK
ns
—
—
—
tWSPSCK Clock (SPSCK) high or low time
tBUS - 30
1024 x
tBUS
6
7
tSU
tHI
Data setup time (inputs)
Data hold time (inputs)
21
0
—
—
ns
ns
—
—
Table continues on the next page...
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
Freescale Semiconductor, Inc.
45
Preliminary
Communication interfaces
Table 33. SPI master mode timing (continued)
Num.
Symbol Description
Min.
Max.
Unit
Comment
8
tv
Data valid (after SPSCK edge)
Data hold time (outputs)
Rise time input
—
25
ns
—
9
tHO
tRI
0
—
ns
ns
—
—
10
—
tBUS - 25
tFI
Fall time input
11
tRO
tFO
Rise time output
—
25
ns
—
Fall time output
1
SS
(OUTPUT)
3
2
10
10
11
11
4
SPSCK
5
=
(CPOL 0)
(OUTPUT)
5
SPSCK
(CPOL 1)
=
(OUTPUT)
6
7
MISO
(INPUT)
2
BIT 6 . . . 1
8
MSB IN
LSB IN
9
MOSI
(OUTPUT)
2
BIT 6 . . . 1
LSB OUT
MSB OUT
1. If configured as an output.
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 17. SPI master mode timing (CPHA=0)
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
46
Freescale Semiconductor, Inc.
Preliminary
Communication interfaces
1
SS
(OUTPUT)
2
10
10
11
11
4
3
SPSCK
(CPOL 0)
=
(OUTPUT)
5
5
SPSCK
(CPOL 1)
=
(OUTPUT)
6
7
MISO
(INPUT)
2
MSB IN
BIT 6 . . . 1
LSB IN
9
8
MOSI
(OUTPUT)
2
PORT DATA
BIT 6 . . . 1
MASTER LSB OUT
PORT DATA
MASTER MSB OUT
1.If configured as output
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 18. SPI master mode timing (CPHA=1)
Table 34. SPI slave mode timing
Num.
Symbol Description
Min.
Max.
fBUS/4
Unit
Comment
1
fop
Frequency of operation
0
Hz
fBUS is the
bus clock
as defined
in Table 8.
2
tSPSCK
SPSCK period
4 x tBUS
—
ns
tBUS = 1/
fBUS
3
4
5
6
7
8
tLead
tLag
Enable lead time
Enable lag time
1
—
—
tBUS
tBUS
ns
—
—
—
—
—
1
tBUS - 30
19.5
0
tWSPSCK Clock (SPSCK) high or low time
—
tSU
tHI
ta
Data setup time (inputs)
Data hold time (inputs)
Slave access time
—
ns
—
ns
—
tBUS
ns
Time to
data active
from high-
impedanc
e state
9
tdis
Slave MISO disable time
—
tBUS
ns
Hold time
to high-
impedanc
e state
10
11
tv
Data valid (after SPSCK edge)
Data hold time (outputs)
—
0
27
—
ns
ns
—
—
tHO
Table continues on the next page...
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
Freescale Semiconductor, Inc.
47
Preliminary
Communication interfaces
Table 34. SPI slave mode timing (continued)
Num.
Symbol Description
Min.
Max.
tBUS - 25
Unit
Comment
12
tRI
tFI
tRO
tFO
Rise time input
Fall time input
Rise time output
Fall time output
—
ns
—
13
—
25
ns
—
SS
(INPUT)
2
12
12
13
13
4
SPSCK
(CPOL 0)
=
(INPUT)
5
5
3
SPSCK
=
(CPOL 1)
(INPUT)
9
8
10
11
11
MISO
(OUTPUT)
see
SEE
BIT 6 . . . 1
SLAVE LSB OUT
SLAVE MSB
7
note
NOTE
6
MOSI
(INPUT)
BIT 6 . . . 1
MSB IN
LSB IN
NOTE: Not defined!
Figure 19. SPI slave mode timing (CPHA=0)
SS
(INPUT)
4
2
12
12
13
13
3
SPSCK
=
(CPOL 0)
(INPUT)
5
5
SPSCK
=
(CPOL 1)
(INPUT)
11
9
10
SLAVE MSB OUT
MISO
(OUTPUT)
see
BIT 6 . . . 1
SLAVE LSB OUT
LSB IN
note
8
6
7
MOSI
(INPUT)
MSB IN
BIT 6 . . . 1
NOTE: Not defined!
Figure 20. SPI slave mode timing (CPHA=1)
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
48
Freescale Semiconductor, Inc.
Preliminary
Communication interfaces
6.8.5 I2S/SAI Switching Specifications
This section provides the AC timing for the I2S/SAI module in master mode (clocks are
driven) and slave mode (clocks are input). All timing is given for noninverted serial clock
polarity (TCR2[BCP] is 0, RCR2[BCP] is 0) and a noninverted frame sync (TCR4[FSP]
is 0, RCR4[FSP] is 0). If the polarity of the clock and/or the frame sync have been
inverted, all the timing remains valid by inverting the bit clock signal (BCLK) and/or the
frame sync (FS) signal shown in the following figures.
Table 35. I2S/SAI master mode timing
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
1.71
40
3.6
V
I2S_MCLK cycle time1
S1
S2
S3
ns
I2S_MCLK pulse width high/low
I2S_TX_BCLK cycle time (output)1
I2S_RX_BCLK cycle time (output)1
I2S_TX_BCLK pulse width high/low
45%
80
55%
—
MCLK period
ns
160
—
S4
S5
45%
—
55%
15
BCLK period
ns
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output valid
S6
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output invalid
0
—
ns
S7
S8
S9
I2S_TX_BCLK to I2S_TXD valid
I2S_TX_BCLK to I2S_TXD invalid
—
0
15
—
—
ns
ns
ns
I2S_RXD/I2S_RX_FS input setup before
I2S_RX_BCLK
25
S10
S11
I2S_RXD/I2S_RX_FS input hold after I2S_RX_BCLK
I2S_TX_FS input assertion to I2S_TXD output valid2
0
—
ns
ns
—
21
1. This parameter is limited in VLPx modes.
2. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
Freescale Semiconductor, Inc.
49
Preliminary
Communication interfaces
S1
S2
S2
I2S_MCLK (output)
S3
S4
I2S_TX_BCLK/
I2S_RX_BCLK (output)
S4
S5
S6
I2S_TX_FS/
I2S_RX_FS (output)
S10
S9
I2S_TX_FS/
I2S_RX_FS (input)
S7
S8
S7
S8
I2S_TXD
I2S_RXD
S9
S10
Figure 21. I2S/SAI timing — master modes
Table 36. I2S/SAI slave mode timing
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
1.71
80
3.6
—
V
S11
I2S_RX_BCLK cycle time (input)
I2S_TX_BCLK cycle time (input)
ns
160
—
S12
S13
S14
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
(input)
45%
10
2
55%
MCLK period
I2S_TX_FS/I2S_RX_FS input setup before
I2S_TX_BCLK/I2S_RX_BCLK
—
ns
ns
I2S_TX_FS/I2S_RX_FS input hold after
I2S_TX_BCLK/I2S_RX_BCLK
—
S15
S16
S17
S18
S19
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output invalid
I2S_RXD setup before I2S_RX_BCLK
—
0
29
—
—
—
21
ns
ns
ns
ns
ns
10
2
I2S_RXD hold after I2S_RX_BCLK
I2S_TX_FS input assertion to I2S_TXD output valid1
—
1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
50
Freescale Semiconductor, Inc.
Preliminary
Human-machine interfaces (HMI)
S11
S12
I2S_TX_BCLK/
S12
I2S_RX_BCLK (input)
S15
S16
I2S_TX_FS/
I2S_RX_FS (output)
S13
S14
I2S_TX_FS/
I2S_RX_FS (input)
S15
S16
S15
S16
I2S_TXD
I2S_RXD
S17
S18
Figure 22. I2S/SAI timing — slave modes
6.9 Human-machine interfaces (HMI)
6.9.1 TSI electrical specifications
Table 37. TSI electrical specifications
Symbol Description
VDDTSI Operating voltage
CELE
Min.
Typ.
Max.
Unit
Notes
1.71
—
3.6
V
Target electrode capacitance range
Reference oscillator frequency
1
—
20
5.5
500
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
—
pF
MHz
MHz
pF
1
2
3
fREFmax
fELEmax
CREF
Electrode oscillator frequency
—
0.5
Internal reference capacitor
TBD
TBD
—
1
VDELTA
IREF
Oscillator delta voltage
600
1.133
1.133
TBD
TBD
TBD
0.25
mV
μA
4
3, 5
3, 5
6
Reference oscillator current source base current
Electrode oscillator current source base current
Electrode capacitance measurement precision
Electrode capacitance measurement precision
IELE
—
μA
Pres5
Pres20
—
%
—
%
7
Pres100 Electrode capacitance measurement precision
—
%
8
MaxSens2 Maximum sensitivity @ 20 pF electrode
0
0.003
fF/count
9
MaxSens Maximum sensitivity
0.003
—
—
—
15
—
16
25
fF/count
bits
10
11
Res
Resolution
TCon20
Response time @ 20 pF
8
μs
Table continues on the next page...
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
Freescale Semiconductor, Inc.
51
Preliminary
Dimensions
Table 37. TSI electrical specifications (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
ITSI_RUN Current added in run mode
—
55
—
μA
ITSI_LP
Low power mode current adder
—
1.3
TBD
μA
12
1. The TSI module is functional with capacitance values outside this range. However, optimal performance is not guaranteed.
2. CAPTRM=7, DELVOL=7, and fixed external capacitance of 20 pF.
3. CAPTRM=0, DELVOL=2, and fixed external capacitance of 20 pF.
4. CAPTRM=0, EXTCHRG=9, and fixed external capacitance of 20 pF.
5. The programmable current source value is generated by multiplying the SCANC[REFCHRG] value and the base current.
6. Measured with a 5 pF electrode, reference oscillator frequency of 10 MHz, PS = 128, NSCN = 8; Iext = 16.
7. Measured with a 20 pF electrode, reference oscillator frequency of 10 MHz, PS = 128, NSCN = 2; Iext = 16.
8. Measured with a 20 pF electrode, reference oscillator frequency of 10 MHz, PS = 16, NSCN = 3; Iext = 16.
9. Measured with a 20 pF electrode, reference oscillator frequency of ~5 MHz (IREF = 5 μA, REFCHRG = 4), PS = 128,
NSCN = 2; Iext = 16 (EXTCHRG = 15).
10. Typical value depends on the configuration used.
11. Time to do one complete measurement of the electrode. Sensitivity resolution of 0.0133 pF, PS = 0, NSCN = 0, 1
electrode, DELVOL = 2, EXTCHRG = 15.
12. CAPTRM=7, DELVOL=2, REFCHRG=0, EXTCHRG=4, PS=7, NSCN=0F, LPSCNITV=F, LPO is selected (1 kHz), and
fixed external capacitance of 20 pF. Data is captured with an average of 7 periods window.
7 Dimensions
7.1 Obtaining package dimensions
Package dimensions are provided in package drawings.
To find a package drawing, go to http://www.freescale.com and perform a keyword
search for the drawing’s document number:
If you want the drawing for this package
32-pin QFN
Then use this document number
98ARE10566D
44-pin Laminate QFN
48-pin LQFP
98ASA00239D
98ASH00962A
98ASA00279D
98ASS23234W
64-pin Laminate QFN
64-pin LQFP
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
52
Freescale Semiconductor, Inc.
Preliminary
Pinout
8 Pinout
8.1 Signal Multiplexing and Pin Assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Mux Control module is
responsible for selecting which ALT functionality is available on each pin.
NOTE
• On PTB0, EZP_MS_b is active only during reset. Refer to
the detailed boot description.
• PTC1 is open drain.
64-
pin
48-
pin
44-
pin
32-
pin
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
1
2
3
4
5
—
—
—
—
1
—
—
—
—
—
—
—
—
—
—
VDD
VDD
VSS
VSS
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
PTC6
UART0_TX
I2C0_SCL
RGPIO6
RGPIO7
RGPIO8
SPI1_MOSI FBa_AD11
SPI1_MISO FBa_AD12
SPI1_SCLK FBa_AD13
PTC7
PTD0
UART0_RX I2C0_SDA
UART0_CT
S_b
I2C1_SDA
I2S0_MCLK
/
I2S0_CLKIN
6
7
2
3
—
1
—
1
Disabled
Disabled
Disabled
Disabled
PTD1
PTA0
UART0_RT
S_b
I2C1_SCL
I2C2_SCL
I2C2_SDA
RGPIO9
SPI1_SS
SPI0_SS
FBa_AD14
FBa_AD15
FBa_AD16
I2S0_RX_B
CLK
FTM1_CH0
I2S0_RX_F
S
8
9
4
5
6
2
3
4
2
3
4
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
PTA1
PTA2
PTA3
FTM1_CH1
FTM1_CH2
FTM1_CH3
I2S0_RXD
UART1_TX
UART1_RX
SPI1_SS
10
SPI1_SCLK
I2S0_TX_B
CLK
EZP_CLK
EZP_DI
11
12
7
8
5
6
5
6
ADC0_SE2
ADC0_SE3
ADC0_SE2
ADC0_SE3
PTA4
PTA5
UART1_CT
S_b
I2C2_SCL
I2C2_SDA
FTM1_CH4
FTM1_CH5
SPI1_MISO
I2S0_TX_F
S
UART1_RT
S_b
SPI1_MOSI CLKOUT
I2S0_TXD
EZP_DO
13
14
15
16
17
18
19
20
21
9
7
7
VDDA
VDDA
10
11
12
13
14
15
16
17
8
—
—
—
8
VREFH
VREFH
9
VREF_OUT VREF_OUT
10
11
12
13
14
15
VREFL
VSSA
VREFL
VSSA
9
DAC0_OUT DAC0_OUT
10
11
12
VREGIN
VOUT33
USB0_DM
VREGIN
VOUT33
USB0_DM
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
Freescale Semiconductor, Inc.
53
Preliminary
Pinout
64-
pin
48-
pin
44-
pin
32-
pin
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
22
23
24
25
18
19
20
21
16
17
18
19
13
14
—
15
USB0_DP
VSS
USB0_DP
VSS
VDD
VDD
ADC0_SE8/ ADC0_SE8/ PTA6
TSI0_CH0 TSI0_CH0
LPTMR_AL
T1
FTM_FLT1
FTM0_CH0
FTM0_CH1
FBa_D7
FBa_D6
FBa_AD17
26
27
28
29
30
31
32
33
—
22
—
—
23
24
—
—
—
20
—
—
21
22
—
—
—
—
—
—
16
—
—
—
ADC0_SE9/ ADC0_SE9/ PTD2
TSI0_CH1
FTM0_QD_ RGPIO10
PHA
TSI0_CH1
ADC0_SE1
ADC0_SE1
PTD3
PTD4
PTD5
PTA7
PTD6
PTD7
PTE0
FTM0_QD_ RGPIO11
PHB
FBa_AD0
FBa_D7
FBa_D6
FBa_D5
FBa_D4
FBa_D3
FBa_D2
FBa_D1
0/TSI0_CH2 0/TSI0_CH2
ADC0_SE1 ADC0_SE1
1/TSI0_CH3 1/TSI0_CH3
ADC0_SE1 ADC0_SE1
2/TSI0_CH4 2/TSI0_CH4
ADC0_SE1 ADC0_SE1
3/TSI0_CH5 3/TSI0_CH5
ADC0_SE1 ADC0_SE1
4/TSI0_CH6 4/TSI0_CH6
ADC0_SE1 ADC0_SE1
5/TSI0_CH7 5/TSI0_CH7
RGPIO12
RGPIO13
UART0_TX
FTM0_QD_
PHA
UART0_RX RGPIO14
UART0_CT
S_b
I2C3_SCL
I2C3_SDA
RGPIO15
TSI0_CH8
TSI0_CH8
UART0_RT
S_b
34
35
—
—
—
TSI0_CH9
TSI0_CH9
Disabled
PTE1
PTB0
SPI0_SS
FTM_FLT0
FTM_FLT2
25
23
17
IRQ/
EZP_MS_b
I2C0_SCL
IRQ/
EZP_MS_b
EZP_CS_b
36
26
24
18
TSI0_CH10 TSI0_CH10 PTB1
SPI0_SCLK I2C0_SDA
LPTMR_AL
T2
FTM0_QD_ FB_CLKOU
PHB
T
37
38
—
—
—
—
—
—
TSI0_CH11 TSI0_CH11 PTE2
I2C3_SCL
FBa_D0
FBa_OE_b
ADC0_SE1
6/
ADC0_SE1
6/
PTE3
PTB2
PTB3
PTE4
SPI0_MOSI I2C3_SDA
TSI0_CH12 TSI0_CH12
39
40
41
27
28
29
25
26
—
19
20
—
ADC0_SE1
7/
ADC0_SE1
7/
SPI0_MISO
SPI0_MOSI
FBa_CS0_b
TSI0_CH13 TSI0_CH13
ADC0_SE1
8/
ADC0_SE1
8/
FBa_CS1_b FBa_ALE
FBa_AD1
TSI0_CH14 TSI0_CH14
ADC0_SE1
9/
ADC0_SE1
9/
UART0_RT
S_b
LPTMR_AL
T3
SPI1_SS
TSI0_CH15 TSI0_CH15
42
43
44
30
—
31
—
—
27
—
—
—
ADC0_SE2
0
ADC0_SE2
0
PTE5
PTE6
PTE7
UART0_CT
S_b
I2C1_SCL
SPI1_SCLK
SPI1_MISO
FBa_AD2
FBa_AD3
ADC0_SE2
1
ADC0_SE2
1
UART0_RX I2C1_SDA
ADC0_SE2
2
ADC0_SE2
2
UART0_TX
BKGD/MS
PDB0_EXT
RG
SPI1_MOSI FBa_RW_b
FBa_AD4
45
46
32
33
28
29
21
22
BKGD/MS
XTAL2
Disabled
XTAL2
PTB4
PTB5
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
54
Freescale Semiconductor, Inc.
Preliminary
Pinout
64-
pin
48-
pin
44-
pin
32-
pin
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
47
48
49
50
34
35
36
37
30
31
32
33
23
24
25
26
EXTAL2
VDD
EXTAL2
VDD
PTB6
VSS
VSS
EXTAL1
EXTAL1
PTB7
PTC0
I2C1_SDA
I2C1_SCL
TMR_CLKI
N1
51
38
34
27
XTAL1
XTAL1
TMR_CLKI
N0
RGPIO0
52
53
54
55
56
57
39
—
—
—
40
41
35
—
—
—
36
37
28
—
—
—
—
29
RESET_b
CMP0_IN0
Disabled
Disabled
PTC1
PTF0
PTF1
PTF2
PTF3
PTC2
RESET_b
SPI0_SS
CMP0_IN0
Disabled
FBa_AD5
SPI0_SCLK
SPI0_MISO
SPI0_MOSI
CMP0_OUT FBa_AD6
FBa_AD7
CMP0_IN1
CMP0_IN2
CMP0_IN3
CMP0_IN1
CMP0_IN2
CMP0_IN3
RGPIO1
RGPIO2
FBa_AD8
I2S0_TXD
UART1_RT
S_b
SPI1_SS
FBa_AD18
I2S0_TX_F
S
58
42
38
—
Disabled
Disabled
PTF4
UART1_CT
S_b
SPI1_SCLK
FBa_D3
FBa_AD19
I2S0_TX_B
CLK
59
60
43
44
39
40
—
—
Disabled
Disabled
Disabled
Disabled
PTF5
PTF6
UART1_RX SPI1_MISO
FBa_D2
FBa_D1
FBa_RW_b
FBa_AD9
I2S0_RXD
UART1_TX
SPI1_MOSI
I2S0_RX_F
S
61
62
45
46
41
42
—
Disabled
Disabled
Disabled
Disabled
PTF7
PTC3
UART0_RT
S_b
SPI0_SS
FBa_D0
FBa_AD10
I2S0_RX_B
CLK
30
UART0_CT
S_b
RGPIO3
SPI0_SCLK CLKOUT
USB_CLKIN I2S0_MCLK
/
I2S0_CLKIN
63
64
47
48
43
44
31
32
Disabled
Disabled
Disabled
Disabled
PTC4
PTC5
UART0_RX RGPIO4
SPI0_MISO PDB0_EXT
RG
USB_SOF_
PULSE
UART0_TX
RGPIO5
SPI0_MOSI CMT_IRO
8.2 Pinout diagrams
The following diagrams show pinouts for the 64-pin, 48-pin, 44-pin, and 32-pin
packages.
For each pin, the diagrams show the default function or (when disabled is the default) the
ALT1 signal for a GPIO function. However, many signals may be multiplexed onto a
single pin.
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
Freescale Semiconductor, Inc.
55
Preliminary
Pinout
VDD
VSS
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
VDD
2
EXTAL2
PTC6
3
XTAL2
PTC7
4
BKGD/MS
PTD0
5
ADC0_SE22
PTD1
6
ADC0_SE21
PTA0
7
ADC0_SE20
PTA1
8
ADC0_SE19/TSI0_CH15
ADC0_SE18/TSI0_CH14
ADC0_SE17/TSI0_CH13
ADC0_SE16/TSI0_CH12
TSI0_CH11
PTA2
9
PTA3
10
11
12
13
14
15
16
ADC0_SE2
ADC0_SE3
VDDA
TSI0_CH10
VREFH
VREF_OUT
VREFL
IRQ/EZP_MS_b
TSI0_CH9
TSI0_CH8
Figure 23. 64-pin Laminate QFN (pinout identical for 64-pin LQFP)
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
56
Freescale Semiconductor, Inc.
Preliminary
Pinout
VSS
36
35
34
33
32
31
30
29
28
27
26
25
PTD0
PTD1
1
2
VDD
EXTAL2
PTA0
3
XTAL2
PTA1
4
BKGD/MS
PTA2
5
ADC0_SE22
ADC0_SE20
ADC0_SE19/TSI0_CH15
ADC0_SE18/TSI0_CH14
ADC0_SE17/TSI0_CH13
TSI0_CH10
PTA3
6
ADC0_SE2
ADC0_SE3
VDDA
7
8
9
VREFH
VREF_OUT
VREFL
10
11
12
IRQ/EZP_MS_b
Figure 24. 48-pin LQFP
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
Freescale Semiconductor, Inc.
57
Preliminary
Pinout
EXTAL1
33
32
31
30
29
28
27
26
25
PTA0
PTA1
1
2
VSS
VDD
PTA2
3
EXTAL2
PTA3
4
XTAL2
ADC0_SE2
ADC0_SE3
VDDA
5
BKGD/MS
6
ADC0_SE22
ADC0_SE18/TSI0_CH14
ADC0_SE17/TSI0_CH13
7
VREFH
VREF_OUT
VREFL
8
9
10
11
TSI0_CH10
24
23
VSSA
IRQ/EZP_MS_b
Figure 25. 44-pin Laminate QFN
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
58
Freescale Semiconductor, Inc.
Preliminary
Pinout
VDD
PTA0
PTA1
24
23
22
21
20
19
1
2
3
4
5
6
7
8
EXTAL2
XTAL2
PTA2
BKGD/MS
PTA3
ADC0_SE18/TSI0_CH14
ADC0_SE17/TSI0_CH13
TSI0_CH10
ADC0_SE2
ADC0_SE3
VDDA
18
17
VSSA
IRQ/EZP_MS_b
Figure 26. 32-pin QFN
8.3 Module-by-module signals
NOTE
• On PTB0, EZP_MS_b is active only during reset. Refer to
the detailed boot description.
• PTC1 is open drain.
Table 38. Module signals by GPIO port and pin
64-pin
48-pin
44-pin
32-pin
Port
Module signal(s)
Power and ground
1
VDD
VDD
24
20
18
Table continues on the next page...
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
Freescale Semiconductor, Inc.
59
Preliminary
Pinout
Table 38. Module signals by GPIO port and pin (continued)
64-pin
48
48-pin
44-pin
32-pin
Port
Module signal(s)
35
31
24
VDD
VSS
VSS
VSS
2
23
19
36
17
32
14
25
49
System
45
12
62
10
11
12
35
32
8
28
6
21
6
PTB4
PTA5
PTC3
PTA3
PTA4
PTA5
PTB0
BKGD/MS
CLKOUT
CLKOUT
EZP_CLK
EZP_DI
46
6
42
4
30
4
7
5
5
8
6
6
EZP_DO
25
23
17
IRQ/EZP_MS_b,
EZP_CS_b
52
39
35
28
PTC1
RESET_b
OSC
50
47
51
46
37
34
38
33
33
30
34
29
26
23
27
22
PTB7
PTB6
PTC0
PTB5
EXTAL1
EXTAL2
XTAL1
XTAL2
LLWU
4
PTC7
PTD1
PTA5
PTA7
PTD7
PTB0
PTB1
PTB2
PTE7
PTB4
PTF2
PTF3
PTC2
PTF5
PTC3
LLWU_P0
LLWU_P1
LLWU_P2
LLWU_P3
LLWU_P4
LLWU_P5
LLWU_P6
LLWU_P7
LLWU_P8
LLWU_P9
LLWU_P10
LLWU_P11
LLWU_P12
LLWU_P13
LLWU_P14
6
2
8
12
30
32
35
36
39
44
45
55
56
57
59
62
6
6
23
21
16
25
26
27
31
32
23
24
25
27
28
17
18
19
21
40
41
43
46
36
37
39
42
29
30
Table continues on the next page...
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
60
Freescale Semiconductor, Inc.
Preliminary
Pinout
Table 38. Module signals by GPIO port and pin (continued)
64-pin
48-pin
44-pin
32-pin
Port
Module signal(s)
63
47
43
31
PTC4
LLWU_P15
RGPIO
51
56
57
62
63
64
3
38
40
41
46
47
48
34
36
37
42
43
44
27
PTC0
PTF3
PTC2
PTC3
PTC4
PTC5
PTC6
PTC7
PTD0
PTD1
PTD2
PTD3
PTD4
PTD5
PTD6
PTD7
RGPIO0
RGPIO1
RGPIO2
RGPIO3
RGPIO4
RGPIO5
RGPIO6
RGPIO7
RGPIO8
RGPIO9
RGPIO10
RGPIO11
RGPIO12
RGPIO13
RGPIO14
RGPIO15
29
30
31
32
4
5
1
2
6
26
27
28
29
31
32
22
24
20
22
LPTMR
25
36
41
21
26
29
19
24
15
18
PTA6
PTB1
PTE4
LPTMR_ALT1
LPTMR_ALT2
LPTMR_ALT3
LPTMR-TOD
50
47
25
36
41
51
46
37
34
21
26
29
38
33
33
30
19
24
26
23
15
18
PTB7
PTB6
PTA6
PTB1
PTE4
PTC0
PTB5
EXTAL1
EXTAL2
LPTMR_ALT1
LPTMR_ALT2
LPTMR_ALT3
XTAL1
34
29
27
22
XTAL2
PTA
7
8
3
4
5
6
1
2
3
4
1
2
3
4
PTA0
PTA1
PTA2
PTA3
PTA0
PTA1
PTA2
PTA3
9
10
Table continues on the next page...
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
Freescale Semiconductor, Inc.
61
Preliminary
Pinout
Table 38. Module signals by GPIO port and pin (continued)
64-pin
11
48-pin
44-pin
32-pin
Port
PTA4
PTA5
PTA6
PTA7
Module signal(s)
PTA4
7
8
5
6
5
6
12
PTA5
25
21
23
19
21
15
16
PTA6
30
PTA7
PTB
PTC
PTD
PTE
35
36
39
40
45
46
47
50
25
26
27
28
32
33
34
37
23
24
25
26
28
29
30
33
17
18
19
20
21
22
23
26
PTB0
PTB1
PTB2
PTB3
PTB4
PTB5
PTB6
PTB7
PTB0
PTB1
PTB2
PTB3
PTB4
PTB5
PTB6
PTB7
51
52
57
62
63
64
3
38
39
41
46
47
48
34
35
37
42
43
44
27
28
29
30
31
32
PTC0
PTC1
PTC2
PTC3
PTC4
PTC5
PTC6
PTC7
PTC0
PTC1
PTC2
PTC3
PTC4
PTC5
PTC6
PTC7
4
5
1
2
PTD0
PTD1
PTD2
PTD3
PTD4
PTD5
PTD6
PTD7
PTD0
PTD1
PTD2
PTD3
PTD4
PTD5
PTD6
PTD7
6
26
27
28
29
31
32
22
24
20
22
33
34
38
PTE0
PTE1
PTE3
PTE0
PTE1
PTE2
Table continues on the next page...
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
62
Freescale Semiconductor, Inc.
Preliminary
Pinout
Table 38. Module signals by GPIO port and pin (continued)
64-pin
39
48-pin
27
44-pin
32-pin
Port
PTB2
PTE4
PTE5
PTE6
PTE7
Module signal(s)
PTE3
25
19
41
29
PTE4
42
30
PTE5
43
PTE6
44
31
27
PTE7
PTF
53
54
55
56
58
59
60
61
PTF0
PTF1
PTF2
PTF3
PTF4
PTF5
PTF6
PTF7
PTF0
PTF1
PTF2
PTF3
PTF4
PTF5
PTF6
PTF7
40
42
43
44
45
36
38
39
40
41
5 V VREG
USB0
20
19
16
15
14
13
11
10
VOUT33
VREGIN
63
62
21
22
20
19
47
46
17
18
16
15
43
42
15
16
14
13
31
30
12
13
11
10
PTC4
PTC3
USB_SOF_PULSE
USB_CLKIN
USB0_DM
USB0_DP
VOUT33
VREGIN
ADC0
11
12
25
26
27
28
29
30
31
32
7
8
5
6
5
6
PTA4
PTA5
PTA6
PTD2
PTD3
PTD4
PTD5
PTA7
PTD6
PTD7
ADC0_SE2
ADC0_SE3
ADC0_SE8
ADC0_SE9
ADC0_SE10
ADC0_SE11
ADC0_SE12
ADC0_SE13
ADC0_SE14
ADC0_SE15
21
19
15
22
20
23
24
21
22
16
Table continues on the next page...
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
Freescale Semiconductor, Inc.
63
Preliminary
Pinout
Table 38. Module signals by GPIO port and pin (continued)
64-pin
38
48-pin
44-pin
32-pin
Port
PTE3
PTB2
PTB3
PTE4
PTE5
PTE6
PTE7
Module signal(s)
ADC0_SE16
ADC0_SE17
ADC0_SE18
ADC0_SE19
ADC0_SE20
ADC0_SE21
ADC0_SE22
VDDA
39
27
28
29
30
25
26
19
20
40
41
42
43
44
31
9
27
7
13
7
14
10
12
13
8
VREFH
16
10
11
VREFL
17
8
9
VSSA
DAC0
VREF
CMP0
18
15
14
11
12
9
DAC0_OUT
VREF_OUT
53
55
56
57
54
PTF0
PTF2
PTF3
PTC2
PTF1
CMP0_IN0
CMP0_IN1
CMP0_IN2
CMP0_IN3
CMP0_OUT
40
41
36
37
29
32
CMT
I2S0
64
48
44
42
PTC5
CMT_IRO
5
1
PTD0
PTC3
I2S0_MCLK/
I2S0_CLKIN
62
46
30
I2S0_MCLK/
I2S0_CLKIN
6
2
45
3
PTD1
PTF7
PTA0
PTF6
PTA1
PTF5
PTA3
PTF4
I2S0_RX_BCLK
I2S0_RX_BCLK
I2S0_RX_FS
I2S0_RX_FS
I2S0_RXD
61
7
41
1
1
2
4
60
8
44
4
40
2
59
10
58
43
6
39
4
I2S0_RXD
I2S0_TX_BCLK
I2S0_TX_BCLK
42
38
Table continues on the next page...
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
64
Freescale Semiconductor, Inc.
Preliminary
Pinout
Table 38. Module signals by GPIO port and pin (continued)
64-pin
11
48-pin
44-pin
32-pin
Port
PTA4
PTC2
PTA5
PTF3
Module signal(s)
I2S0_TX_FS
I2S0_TX_FS
I2S0_TXD
7
41
8
5
37
6
5
29
6
57
12
56
40
36
I2S0_TXD
TSI0
25
26
27
28
29
30
31
32
33
34
36
37
38
39
40
41
21
22
19
20
15
16
18
PTA6
PTD2
PTD3
PTD4
PTD5
PTA7
PTD6
PTD7
PTE0
PTE1
PTB1
PTE2
PTE3
PTB2
PTB3
PTE4
TSI0_CH0
TSI0_CH1
TSI0_CH2
TSI0_CH3
TSI0_CH4
TSI0_CH5
TSI0_CH6
TSI0_CH7
TSI0_CH8
TSI0_CH9
TSI0_CH10
TSI0_CH11
TSI0_CH12
TSI0_CH13
TSI0_CH14
TSI0_CH15
23
24
21
22
26
24
27
28
29
25
26
19
20
PDB0
FTM0
44
63
31
47
27
43
PTE7
PTC4
PDB0_EXTRG
PDB0_EXTRG
31
34
25
36
PTE1
PTA6
PTB1
FTM_FLT0
FTM_FLT1
21
26
19
24
15
18
FTM_FLT2 /
FTM0_QD_PHB
26
27
PTD2
PTD3
FTM0_CH0/
FTM0_QD_PHA
22
20
FTM0_CH1 /
FTM0_QD_PHB
30
51
50
23
38
37
21
34
33
16
27
26
PTA7
PTC0
PTB7
FTM0_QD_PHA
TMR_CLKIN0
TMR_CLKIN1
Table continues on the next page...
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
Freescale Semiconductor, Inc.
65
Preliminary
Pinout
Table 38. Module signals by GPIO port and pin (continued)
64-pin
48-pin
44-pin
32-pin
Port
Module signal(s)
FTM1
34
25
36
7
PTE1
PTA6
PTB1
PTA0
PTA1
PTA2
PTA3
PTA4
PTA5
PTC0
PTB7
FTM_FLT0
FTM_FLT1
FTM_FLT2
FTM1_CH0
FTM1_CH1
FTM1_CH2
FTM1_CH3
FTM1_CH4
FTM1_CH5
TMR_CLKIN0
TMR_CLKIN1
21
26
3
19
24
1
15
18
1
8
4
2
2
9
5
3
3
10
11
12
51
50
6
4
4
7
5
5
8
6
6
38
37
34
33
27
26
MTIM
51
50
38
37
34
33
27
26
PTC0
PTB7
TMR_CLKIN0
TMR_CLKIN1
Mini-FlexBus
36
27
41
42
43
44
53
54
55
56
60
61
3
26
22
29
30
24
20
18
PTB1
PTD3
PTE4
PTE5
PTE6
PTE7
PTF0
PTF1
PTF2
PTF3
PTF6
PTF7
PTC6
PTC7
PTD0
PTD1
PTA0
PTA1
PTA6
FB_CLKOUT
FBa_AD0
FBa_AD1
FBa_AD2
FBa_AD3
FBa_AD4
FBa_AD5
FBa_AD6
FBa_AD7
FBa_AD8
FBa_AD9
FBa_AD10
FBa_AD11
FBa_AD12
FBa_AD13
FBa_AD14
FBa_AD15
FBa_AD16
FBa_AD17
31
27
40
44
45
36
40
41
4
5
1
2
6
7
3
1
2
1
2
8
4
25
21
19
15
Table continues on the next page...
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
66
Freescale Semiconductor, Inc.
Preliminary
Pinout
Table 38. Module signals by GPIO port and pin (continued)
64-pin
57
48-pin
41
44-pin
37
32-pin
Port
PTC2
PTF4
PTB3
PTB2
PTE2
PTE1
PTE0
PTD7
PTD6
PTA7
PTD5
PTD4
PTE3
PTF5
Module signal(s)
FBa_AD18
FBa_AD19
FBa_ALE
FBa_CS0_b
FBa_D0
29
58
42
38
40
28
26
20
19
39
27
25
37
34
FBa_D1
33
FBa_D2
32
FBa_D3
31
24
23
22
21
FBa_D4
30
16
FBa_D5
29
FBa_D6
28
FBa_D7
38
FBa_OE_b
FBa_RW_b
59
43
39
DATA_BUS
8
4
2
2
PTA1
PTB2
PTF7
PTF6
PTF5
PTF4
PTD6
PTA7
PTD3
PTA6
PTE7
FBa_AD16
FBa_CS0_b
FBa_D0
39
61
60
59
58
31
30
27
25
44
27
45
44
43
42
24
23
22
21
31
25
41
40
39
38
22
21
20
19
27
19
FBa_D1
FBa_D2
FBa_D3
FBa_D4
16
15
FBa_D5
FBa_D6
FBa_D7
FBa_RW_b
I2C0 and I2C1
3
35
4
PTC6
PTB0
PTC7
PTB1
PTD1
PTE5
PTC0
PTD0
I2C0_SCL
I2C0_SCL
I2C0_SDA
I2C0_SDA
I2C1_SCL
I2C1_SCL
I2C1_SCL
I2C1_SDA
25
23
24
17
18
36
6
26
2
42
51
5
30
38
1
34
27
Table continues on the next page...
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
Freescale Semiconductor, Inc.
67
Preliminary
Pinout
Table 38. Module signals by GPIO port and pin (continued)
64-pin
43
48-pin
44-pin
32-pin
Port
PTE6
PTB7
Module signal(s)
I2C1_SDA
50
37
33
26
I2C1_SDA
I2C2 and I2C3
7
3
7
4
8
1
5
2
6
1
5
2
6
PTA0
PTA4
PTA1
PTA5
PTD7
PTE2
PTE0
PTE3
I2C2_SCL
I2C2_SCL
I2C2_SDA
I2C2_SDA
I2C3_SCL
I2C3_SCL
I2C3_SDA
I2C3_SDA
11
8
12
32
37
33
38
SPI0
39
55
63
38
40
56
64
36
54
62
7
27
47
25
43
19
31
20
PTB2
PTF2
PTC4
PTE3
PTB3
PTF3
PTC5
PTB1
PTF1
PTC3
PTA0
PTE1
PTF0
PTF7
SPI0_MISO
SPI0_MISO
SPI0_MISO
SPI0_MOSI
SPI0_MOSI
SPI0_MOSI
SPI0_MOSI
SPI0_SCLK
SPI0_SCLK
SPI0_SCLK
SPI0_SS
28
40
48
26
26
36
44
24
32
18
46
3
42
1
30
1
34
53
61
SPI0_SS
SPI0_SS
45
41
SPI0_SS
SPI1
4
PTC7
PTA4
PTE6
PTF5
PTC6
PTA5
PTE7
PTF6
SPI1_MISO
SPI1_MISO
SPI1_MISO
SPI1_MISO
SPI1_MOSI
SPI1_MOSI
SPI1_MOSI
SPI1_MOSI
11
43
59
3
7
5
5
6
43
39
12
44
60
8
6
31
44
27
40
Table continues on the next page...
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
68
Freescale Semiconductor, Inc.
Preliminary
Pinout
Table 38. Module signals by GPIO port and pin (continued)
64-pin
5
48-pin
44-pin
32-pin
Port
PTD0
PTA3
PTE5
PTF4
PTD1
PTA2
PTE4
PTC2
Module signal(s)
SPI1_SCLK
SPI1_SCLK
SPI1_SCLK
SPI1_SCLK
SPI1_SS
1
6
10
42
58
6
4
38
3
4
30
42
2
9
5
3
SPI1_SS
41
57
29
41
SPI1_SS
37
29
SPI1_SS
UART0
5
1
PTD0
PTD7
PTE5
PTC3
PTD1
PTE0
PTE4
PTF7
PTC7
PTD6
PTE6
PTC4
PTC6
PTA7
PTE7
PTC5
UART0_CTS_b
UART0_CTS_b
UART0_CTS_b
UART0_CTS_b
UART0_RTS_b
UART0_RTS_b
UART0_RTS_b
UART0_RTS_b
UART0_RX
32
42
62
6
30
46
2
42
30
33
41
61
4
29
45
41
22
43
31
43
63
3
24
47
UART0_RX
UART0_RX
31
16
32
5
UART0_RX
UART0_TX
30
44
64
23
31
48
21
27
44
UART0_TX
UART0_TX
UART0_TX
UART1
11
58
12
57
10
59
9
7
42
8
5
38
6
PTA4
PTF4
PTA5
PTC2
PTA3
PTF5
PTA2
PTF6
UART1_CTS_b
UART1_CTS_b
UART1_RTS_b
UART1_RTS_b
UART1_RX
6
29
4
41
6
37
4
43
5
39
3
UART1_RX
3
UART1_TX
60
44
40
UART1_TX
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
Freescale Semiconductor, Inc.
69
Preliminary
Revision History
9 Revision History
The following table provides a revision history for this document.
Table 39. Revision History
Rev. No.
Date
Substantial Changes
0
05/2011
Initial released version
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
70
Freescale Semiconductor, Inc.
Preliminary
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Document Number: MCF51JU128
Rev. 0, 05/2011
Preliminary
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