MCZ33793AEFR2 [FREESCALE]
Distributed System Interface (DSI) Sensor Interface; 分布式系统接口（ DSI ）传感器接口
| 型号： | MCZ33793AEFR2 |
| 厂家： | 
Freescale |
| 描述： | Distributed System Interface (DSI) Sensor Interface |
| 文件： | 总27页 (文件大小：816K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Document Number: MC33793
Rev 13.0, 11/2006
Freescale Semiconductor
Technical Data
Distributed System Interface
(DSI) Sensor Interface
33793/A
The 33793 is a slave Distributed System Interface (DSI) device
that is optimized as a sensor interface. The device contains circuits
to power sensors such as accelerometers and to digitize the analog
level from the sensor. The device is controlled by commands over the
DSI bus and returns measured data over the bus.
DISTRIBUTED SYSTEM INTERFACE
Features
• Conforms to DSI Specification Version 1
• 4-Channel, 8-Bit Analog-to-Digital Converter (ADC)
• 4 Pins Configurable as Analog or Logic Inputs or as Logic
Outputs
• Provides Regulated +5.0 V Output for Sensor Power from Bus
• Additional High-Drive Logic Output
D SUFFIX
EF SUFFIX (Pb-FREE)
98ASB42566B
16-PIN SOICN
• Undervoltage Fault Detection and Signaling
• On-Board Clock (No External Elements Required)
• Field-Programmable Address
• Default and Field-Programmable as a DSI Daisy Chain Device
• Recognizes Reverse Initialization for Open Bus Fault Tolerance
• Detects Short to Battery on Bus Switch and Prevents Its Closure
• Pb-Free Packaging Designated by Suffix Code EF
ORDERING INFORMATION
Temperature
Device
Package
Range (T )
J
MC33793D/R2
MCZ33793EF/R2
MCZ33793AEF/R2
-40°C to 150°C
16 SOICN
33790
GND
DSIO
33793
X-Y
Multiple
Accelerometer
BUSIN
I/O0
BUSRTN
DSI Slaves
Error
Test
X
I/O1
33793
I/O2
I/O3
Y
BUSOUT
BusIN
H_Cap
REGOUT
LOGOUT
V
CC
GND
AGND
Figure 1. 33793 Simplified Application Diagram
Freescale Semiconductor, Inc. reserves the right to change the detail specifications, as
may be required, to permit improvements in the design of its products.
© Freescale Semiconductor, Inc., 2006. All rights reserved.
DEVICE VARIATIONS
DEVICE VARIATIONS
Table 1. Device Variations
Freescale Part No.
MCZ33793EF/R2
MCZ33793AEF/R2
Other Significant Device Variations
Existing capacity
Capacity expansion
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INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
HCAP
Rectifiers
BUSIN
Bus Switch
0 – 35 V Bi-Directional
BUSOUT
Reverse Receiver
Forward Receiver
Data
Data
Response
Current
0 –11 mA
7.0 mA/µS
Frame
Frame
BUSRTN
Received
Message
Bandgap
Reference
Bandgap
Reference
Bus Return
from MCU
Oscillator
4.0 MHz
Logic
Command Decode
State Machine
LOGOUT
Logic Out
HighCurrent
DataOut <3:0>
Response Generation
I/O Buffers
4
Buffer
Power
Management
5.0 V Regulator
BG Reference
Bias Currents
DataOut <0>
Address A<3:0>
4 Bits NVM
IO0
DataOut <1>
DataOut <2>
DataOut <3>
IO1
IO2
GND
SEL
Supply Comparators
POR
I/O0
I/O1
4:1
ADC
8 Bits
IO3
I/O2
I/O3
Undervoltage
Detector
MUX
I/O<3:0>
BG
Figure 2. 33793 Simplified Internal Block Diagram
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PIN CONNECTIONS
PIN CONNECTIONS
1
2
16
15
BUSRTN
I/O0
BUSOUT
NC
3
4
5
6
14
13
12
11
AGND
I/O1
BUSIN
NC
AGND
I/O3
H_CAP
REGOUT
NC
7
8
10
9
NC
I/O2
LOGOUT
Figure 3. 33793 Pin Connections
Table 2. 33793 Pin Definitions
A functional description of each pin can be found in the Functional Pin Description section beginning on page 10.
Pin Number Pin Name Pin Function
Formal Name
Definition
This pin provides the common return for power and signalling.
1
2
BUSRTN
I/O0
Power
Bus Return
Logic I/O
This pin can be used to provide a logic level output, a logic input, or an
analog-to-digital (A/D) input.
Input/Output
This pin is the low reference level and power return for the analog-to-
digital converter (ADC).
3, 5
4
AGND
I/O1
Ground
Analog Ground
Logic I/O
This pin can be used to provide a logic level output, a logic input, or an
A/D input.
Input/Output
Input/Output
This pin can be used to provide a logic level output, a logic input, or an
A/D input.
6
I/O3
Logic I/O
These pins have no internal connections.
7, 10, 13, 15
8
NC
No Connect
Input/Output
No Connect
Logic I/O
This pin can be used to provide a logic level output, a logic input, or an
A/D input.
I/O2
This is a logic output with higher pull-up drive capability than the standard
logic I/O.
9
LOGOUT
REGOUT
H_CAP
Output
Output
Output
Logic Out
This pin provides a regulated 5.0 V output. The power is derived from the
bus.
11
12
Regulator Output
Holding Capacitor
A capacitor attached to this pin is charged by the bus during bus idle and
supplies current to run the device and for external devices via the
REGOUT pin during non-idle periods.
This pin attaches to the bus and responds to initialization commands.
14
16
BUSIN
Input
DSI Bus Input
This pin attaches to the bus and responds to reverse initialization
commands.
BUSOUT
Output
DSI Bus Output
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ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 3. Maximum Ratings
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or
permanent damage to the device.
Ratings
Symbol
Value
Unit
ELECTRICAL RATINGS
I/O Pin Voltage
V
-0.3 to V
+ 0.5
V
mA
V
IO
REGOUT
5.0
I/O Pin Current
IIO
VIN
IIN
BUSIN, BUSOUT, BUSRTN, and H_CAP Voltage
-0.3 to 40
250
BUSIN, BUSOUT, BUSRTN, and H_CAP Current (Continuous)
mA
V
ESD Protection (1)
Human Body Model
Machine Model
V
V
ESD1
ESD2
±2000
±200
THERMAL RATINGS
Storage Temperature
TSTG
TJ
-55 to 150
-40 to 150
Note 3.
°C
Operating Junction Temperature
°C
Peak Package Reflow Temperature During Reflow (2)
Thermal Resistance Junction to Case
Notes
,
TPPRT
(3)
°C
R
150
°C/W
θJC
1. ESD1 performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 Ω), ESD2 performed in accordance with the
Machine Model (CZAP = 200 pF, RZAP = 0 Ω).
2. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.
3. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow
Temperature and Moisture Sensitivity Levels (MSL),
Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e.
MC33xxxD enter 33xxx), and review parametrics.
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ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 4. Static Electrical Characteristics
Characteristics noted under conditions -0.3 V ≤ VBUSIN or VBUSOUT ≤ 30 V, 5.5 V < VH_CAP < 30 V, -40°C < TA < 85°C unless
otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless
otherwise noted.
Characteristic
Internal Quiescent Current Drain
Symbol
Min
Typ
Max
Unit
IQ
mA
VH_CAP = 25 V, Logout = 0, I/O = Input
–
–
3.0
BUSIN or BUSOUT to H_CAP Rectifier Voltage Drop
VRECT
V
I
I
or I
or I
= 15 mA
–
–
0.75
0.9
1.0
1.2
BUSIN
BUSIN
BUSOUT
BUSOUT
= 100 mA
BUSIN + BUSOUT Bias Current
IBIAS
µA
VBUSIN or VBUSOUT = 8.0 V, VH_CAP = 9.0 V
VBUSIN or VBUSOUT = 0.5 V, VH_CAP = 25 V
-100
–
–
–
100
20
Rectifier Leakage Current
IRLKG
VREG
VRLINE
VRLD
VUVL
RSW
µA
V
VBUSIN or VBUSOUT = 5.0 V, VH_CAP = 25 V
-20
4.75
–
–
100
5.25
180
100
0.97
8.0
Reg0ut
5.5 V > VH_CAP > 25 V, IRO = 12 mA
5.0
71
RegOut Line Regulation
mV
mV
VRO
Ω
IRO = 12 mA, 5.5 V > VH_CAP > 25 V
RegOut Load Regulation
IRO = 0 to 12 mA, 5.5 V > VH_CAP > 25 V
–
2.3
0.95
4.0
11
Undervoltage Lockout
Proportional to unloaded V
REGOUT
0.93
–
Bus Switch Resistance
VBI = 8.0 V, IBO = -80 mA (Bus Switch Active)
I/O0 and I/O3 Pull-Down Current
0 < VBUSIN or VBUSOUT < 1.0 V
IPD
µA
µA
V
7.0
-7.0
13
I/O1 and I/O2 Pull-Up Current
IPU
VRO < VBUSIN or VBUSOUT < VRO - 1.0 V
-11
-13
BUSIN and BUSOUT Logic Thresholds
Low
V
2.8
5.5
3.0
6.0
3.2
6.5
THL
High
V
THH
Logic Duty Cycle (assured by design)
%
Logic 0
Logic 1
D
10
60
33
67
40
90
CL
D
CH
BUSIN + BUSOUT Response Current
VBUSIN and/or VBUSOUT = 4.0 V
IRSP
mA
9.9
11
12.1
ADC Code Conversion Error (INL)
ADC Full-scale Error
ADCINL
ADCFS
–
–
–
–
< 1.0
3
LSB
counts
VRO
I/O Logic Input Thresholds
Logic High
VIH
VIL
0.7
–
0.54
0.51
–
Logic Low
0.3
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ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 4. Static Electrical Characteristics (continued)
Characteristics noted under conditions -0.3 V ≤ VBUSIN or VBUSOUT ≤ 30 V, 5.5 V < VH_CAP < 30 V, -40°C < TA < 85°C unless
otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless
otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
I/O Logic Output Levels
Output Low (IL = 1.0 mA)
VOL
VOH
0
0.08
0.5
1.0
V
Output High (IL = -500 µA)
0.8
0.985
VRO
LOGOUT Output Levels
V
Output Low (IL = 500 µA)
VLOL
VLOH1
VLOH2
0
4.7
–
0.2
5.0
–
0.5
5.3
Output High (IL = -10 mA, 6.2 V < VH_CAP < 25 V)
Output High (IL = -100 µA, 6.2 V < VH_CAP < 25 V)
VRO+0.5
Programming Time
T
ms
V
PROG
From Positive Edge of BUSIN or BUSOUT > V
on Program
THH
Command to Following Command Negative Transition < V
100
200
–
1000
30
THH
NVM BUSIN or BUSOUT Programming Voltage
NVMVP
22.25
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ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 5. Dynamic Electrical Characteristics
Characteristics noted under conditions -0.3 V ≤ VBUSIN or VBUSOUT ≤ 30 V, 5.5 V ≤ VH_CAP ≤ 30 V, -40°C ≤ TA ≤ 85°C unless
otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless
otherwise noted.
Characteristic
Initialization to Bus Switch Closing
Symbol
Min
Typ
Max
Unit
t
100
150
200
µs
BS
Loss of Signal Reset Time
tTO
ms
Maximum Time Below Frame Threshold
–
–
–
–
100
27
ADC Code Conversion Time (Go, No-Go Test)
tADC
tITR
µs
BUSIN and BUSOUT Response Current Transition Time
1.0 mA to 9.0 mA Transition, 9.0 mA to 1.0 mA
mA/µs
–
7.0
10
BUSIN or BUSIN Timing to Response Current
µs
BUSIN or BUSOUT Negative Voltage Transition = 3.0 V to I
BUSIN or BUSOUT Negative Voltage Transition = 3.0 V to I
= 7.0 mA
= 5.0 mA
t
t
–
–
–
–
3.3
3.3
RSPH
RSPL
RSPH
RSPL
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ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
TIMING DIAGRAMS
Frame
Frame
Threshold
Threshold
BUSIN/BUSOUT
tTO
tBS
End of Initialization
Command
Closed
BUS Switch
Open
Internal Reset
Reset
Figure 4. Bus Switch and Reset Timing
9.0 mA
7.0 mA
1.0 mA
9.0 mA
5.0 mA
1.0 mA
RESPONSE
CURRENT
tITR
tITR
tRSPH
3.0 V
BUSIN/BUSOUT
3.0 V
Figure 5. Response Current Timing
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FUNCTIONAL DESCRIPTION
INTRODUCTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
The 33793 is designed to be used with a sensor at a
location that is remote from a centralized MCU. This device
provides power, measurement, and communications
between the remote sensor and the centralized MCU over a
DSI bus. Sensors such as accelerometers can be powered
from the regulated output of the device, and the resulting
analog value from the sensor can be converted from an
analog level to a digital value for transmission over the DSI
bus in response to a query from the MCU. Four I/O lines can
be configured by the central MCU over the DSI bus as analog
inputs, digital inputs, or digital outputs. This allows more than
one sensor to be remotely controlled and measured by a
single 33793. Additionally, a high drive logic output is
provided that can be used to power other low-power sensors.
supplies energy to power the device during low excursions of
BUSIN and BUSOUT.
The Regulator supplies an on-board regulated voltage for
internal use, and the Power on Reset (POR) circuit provides
a reset signal during low-voltage conditions and during power
up/down. Some current is available for low-power sensors.
Data from the Central Control Unit (CCU) is applied to the
BUSIN and/or BUSOUT pins as voltage levels that are
sensed by the Level Detection circuitry. The Serial Decoder
detects these transitions and decodes the incoming data.
The Control Logic provides overall control of the 33793. It
controls diagnostic testing and formats responses to
commands with the message encoder. Responses are
formed via a switched current source that is slew-rate
controlled.
Power is passed from BUSIN or BUSOUT through on-
board rectifiers to a storage capacitor (referred to as the
H_CAP). The H_CAP stores energy during the highest
voltage excursions of the BUSIN or BUSOUT pin (idle) and
The one-time programmable (OTP) memory array
provides the nonvolatile storage for the pre-programmed
address. It is accessed via the Read/Write NVM command. It
has a built-in hardware lock that only allows one write.
FUNCTIONAL PIN DESCRIPTION
BUS RETURN (BUSRTN)
REGULATOR OUTPUT (REGOUT)
This pin provides the common return for power and
signalling.
This pin provides a regulated 5.0 V output. The power is
derived from the bus.
INPUT/OUTPUT (I/O0, I/O1, I/O2, I/O3)
HOLDING CAPACITOR (H_CAP)
This pin can be used to provide a logic level output, a logic
input, or an analog-to-digital (A/D) input.
A capacitor attached to this pin is charged by the bus
during bus idle and supplies current to run the device and for
external devices via the REGOUT pin during non-idle
periods.
ANALOG GROUND (AGND)
This pin is the low reference level and power return for the
analog-to-digital converter (ADC).
DSI BUS INPUT (BUSIN)
This pin attaches to the bus and responds to initialization
commands.
LOGIC OUT (LOGOUT)
This is a logic output with higher pull-up drive capability
than the standard logic I/O.
DSI BUS OUTPUT (BUSOUT)
This pin attaches to the bus and responds to reverse
initialization commands.
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
Refer to Figure 2, 33793 Internal Block Diagram, page 3,
for a simplified representation of the 33793’s components.
voltage at H_CAP will not drop below the frame threshold
during signaling.
RECTIFIER
POR
This rectifier or switch peak detects the bus signal into an
external capacitor attached to H_CAP. The capacitor
supplies power during signaling while the input voltage is at a
lower level.
The 33793 leaves the reset state when the voltage on
H_CAP rises above the Power-ON Reset threshold.
TIMEOUT
The voltage waveform at BUSIN and/or BUSOUT and the
size of the filter capacitor at H_CAP must be such that the
A timeout timer keeps track of the length of the time when
the input is not in idle mode. If this time exceeds a limit, the
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FUNCTIONAL DESCRIPTION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
part is reset. The purpose of this is to allow the part to reset
itself if the connection to the master is lost or if power is
removed from the system.
circuit limits the rise and fall time of current loading the bus by
controlling the current sinking element.
SWITCHED CURRENT SOURCE
5.0 V REGULATOR
A "1" data return bit will be signaled by turning on a fixed
current source. During signaling time, the 33793 will be using
power from H_CAP and not loading the bus for power. The
current will be drawn from either BUSIN or BUSOUT or split
between them. The split can be in any proportion as long as
the total is correct.
The 5.0 V regulator supplies internal power for the device
and also provides approximately 6.0 mA through the
REGOUT pin to power an external sensor.
UNDERVOLTAGE DETECTOR
The current source is turned off whenever the bus is at Idle
level.
The undervoltage detector monitors the output voltage of
the 5.0 V regulator. If the REGOUT voltage drops too low for
accurate A/D operation, a signal is sent to the control logic.
The control logic will interpret this signal and, in response to
a command, report a status indicating an undervoltage
condition to have existed. When received, the command will
clear the signal after having read the status. If the voltage is
too low when the A/D conversion was completed, the
returned value will be zero (binary 00000000).
LEVEL DETECTOR
The level detector contains comparators to determine if
the BUSIN or BUSOUT is at idle, logic high, or logic low. The
inputs from BUSIN and BUSOUT are sensed by the device
so that if either side is driven by the signaling waveform while
the other is not, the signaling will be detected. This circuit also
provides a signal to indicate if the signal is being received on
the BUSOUT pin. If a "reverse initialization" command is
received, it can only be acted upon if the device is not already
initialized and if the signal is present on BUSOUT.
IO PINS 0 TO 3
The IO pins can serve as logic inputs, logic outputs, or
analog inputs. At power-up or after a clear, the pins are all
logic inputs and can be used to measure an analog level
value for an analog value request command. The pins can be
individually configured as logic inputs or outputs by the IO
Control command. If the pin is configured as a logic output,
reading the analog value will return the analog level the
output is being driven to.
SERIAL DECODER
The Serial Decoder monitors transitions on the BUSIN or
BUSOUT. When the 33793 is Idle and supplying power to
itself and the external device(s) (via REGOUT), the input to
BUSIN will be in the Idle state. A transition from this level to
Signal Low (through Signal High) will start the process of
decoding a word of data. BUSIN is driven from Signal Low to
Signal High for each bit and back to Signal Low to start the
next bit. The determination of whether the bit was a one or a
zero is made by determining whether it spent more time low
(a zero) or high (a one). The end of the word is signaled by a
transition at the end of the last bit from Signal High to Idle.
The advantage of this method is that it will accept data over
a wide range of rates and is not dependent on an accurate
clock.
ANALOG-TO-DIGITAL CONVERTER
The ADC is an 8-bit successive approximation type using
on-board capacitive division. It uses the Clk signal from the
on-board oscillator for sequencing.
The ADC uses REGOUT as a full-scale reference voltage
and ground AGND for a zero-level reference.
The ADC signals when it has made a valid conversion by
asserting a signal to the controller. If this signal is not
asserted when a value is being captured by the controller, the
controller will signal that an invalid A/D value was obtained.
The controller will typically indicate a logic zero by
spending 2/3 of the bit period at Signal Low and 1/3 at Signal
High. A logic one would be 1/3 of the bit period at Signal Low
and 2/3 at Signal High.
The value of “0" (binary 00000000) is reserved by the
control logic to signal an error. A value of “0” from the ADC
will be reported as “1” (binary 00000001) by the control logic.
CONTROL LOGIC
SERIAL ENCODER
The control logic performs the digital operations carried
out by this device. Its principle functions include:
The Serial Encoder accepts the digitized value from the
ADC and formatting/data from the Control Logic. A logic
transition from Idle to Signal High and then to Signal Low at
BUSIN will cause the first bit to be presented to the current
switch (Response Loading). A transition to Signal High and
back to Signal Low will cause the next bit to be presented to
the current switch. This will continue until a transition back to
Idle turns off the current switch.
• Decoding input instructions.
• Control the general purpose I/O and LOGICOUT in
response to BUSIN or BUSOUT commands.
• Control A/D conversions.
• Form response word.
• Capture and store address.
• Control BUSSW.
• Reset device on power-up.
SLEW
• Control the general purpose I/O logic configuration.
The slew circuit serves to reduce EMI produced as a result
of switching the bus loading current sink element. The slew
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FUNCTIONAL DESCRIPTION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
• Read the general purpose I/O logic values and respond
to request for these values.
• Generating a cycle redundancy check (CRC) for the
received data and transmitted data in conformance with
the DSI Bus Standard.
ADDRESSING
The 33793 IC supports both runtime programmable and
pre-programmed addressing as defined in the DSI
Specification. Runtime programmable addressing uses the
daisy chain bus connection. Pre-programmed devices may
either be connected in daisy chain or in parallel on the bus
wires.
Additionally, the control logic performs error checking on
the received data. If errors are found, no action is taken and
no response is made. Errors include:
Programmable address devices all power up with a device
address of $0 in their address register and their bus switches
open. In the daisy chain, if the first device receives the
initialization command device on BUSIN, it will accept the
address in the command and close its switch at the end of the
command. The next device in the chain will now be able to
receive the initialization command on its BUSIN and will
accept the next address. This proceeds down the chain until
the last device is addressed. The devices can also be
initialized by the reverse initialization command if the signal is
applied to BUSOUT.
• CRC received doesn’t match CRC of received data.
• Number of received bits is not 12 or 20.
CLOCK
The clock is a low-stability type with the capacitor
integrated onto the die. The signaling system and all internal
operations are such that no external precision timing device
is needed in the normal operation of this device.
BUS SWITCH (BUSSW)
Pre-programmed devices power up with their pre-
programmed address in its address register. It will ignore all
Initialization commands unless the address in the command
matches its pre-programmed address. In this event the
device stores the other information contained in the
Initialization command.
The bus switch passes signaling and power to all
subsequent devices on the bus. It can block a voltage of
either polarity up to the highest idle state level between
BUSIN and BUSOUT.
LOGICOUT
LOGICOUT is a logic level output with enhanced high-side
drive capability.
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FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
A device may be permanently programmed one time with
MESSAGES
an address using a two-command sequence. The first step is
satisfied on the reception of an Initialization command with
address set to zero, the PA[3:0] set to the address to be
programmed, and the NV bit set. This will cause the address
contained in the PA[3:0] bits to be stored in the address
register and the bus switch closed. The second step is taken
when a Read/Write NVM command is received with the
PA[3:0] bits matching the A[3:0] bits and also matching the
bits stored in the 33793 address register. This will cause the
33793 to permanently store this address into an internal NVM
area.
The messages follow the format defined in the Distributed
Systems Interface Specification rev 1.0 unless otherwise
noted.
DSI BUS COMMANDS
This device can recognize and respond to both long-word
and short-word commands. A command word summary is
shown in Table 6. SW in the “Size” column of the table
indicates short-word commands and LW indicates long-word
commands. Short-word commands may also be sent in the
long-word format. However, when these commands are sent
in the long-word format, it is recommended that the data byte
be sent as $00 to maintain future compatibility. All commands
marked reserved should not be sent to 33793 slaves.
Table 6. DSI Bus Commands
Command
Data
Size
Description
C3
C2
C1
C0
D7
D6
D5
D4
D3
D2
D1
D0
Initialization
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
LW
SW
SW
LW
SW
SW
SW
SW
SW
LW
NV
–
BS
–
G1
–
G0
–
PA3
PA2
PA1
PA0
Request Status
Request Value 0
I/O Control
0
–
–
–
–
–
–
–
–
0
–
–
–
–
0
L3
–
L2
–
L1
–
L0
–
DR3
–
DR2
–
DR1
–
DR0
–
Request ID Information
Request Value 1
Request Value 2
Clear
0
0
–
–
–
–
–
–
–
–
0
–
–
–
–
–
–
–
–
0
–
–
–
–
–
–
–
–
Request Value 3
Read/Write NVM
Reserved
1
–
–
–
–
–
–
–
–
1
1
1
1
1
PA3
PA2
PA1
PA0
1
Reserved
1
Clear Logic Out
Set Logic Out
Reserved
1
SW
SW
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
1
1
Reverse Initialization
1
LW
NV
BS
G1
G0
PA3
PA2
PA1
PA0
Legend
BS = Controls closing of the Bus Switch (1 = close).
DR[3:0] = Direction of I/O. 1 = Output.
LO = Logic Out level.
PA[3:0] = Bus Address to set the device to.
NV = Allows nonvolatile address programming if set to "1".
G[1:0] = Group assignment (the 33793 does not use these bits).
L[3:0] = Level to output on I/O if configured as outputs.
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FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
LONG- AND SHORT-WORD RESPONSES
The device responds to Long-word commands with long-word responses and short-word commands with short-word
responses. Responses are sent during the next message following the command. A long-word response summary is found in
Table 7 and a short-word response summary is found in Table 8, page 15.
Table 7. Long-Word Response Summary
CMD
hex
Command
Description
Response
Initialization
0
A3
A3
A3
A3
A3
A3
A3
A2
A2
A2
A2
A2
A2
A2
A1
A1
A1
A1
A1
A1
A1
A0
A0
A0
A0
A0
A0
A0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BF
NV
NV
B7
L3
BS
U
G1
LO
B5
L1
G0 PA3 PA2 PA1 PA0
Request Status
Request Value 0
I/O Control
1
0
0
0
0
0
0
BS
B4
L0
0
IO3
B3
IO2
B2
IO1
B1
IO0
B0
2
B6
L2
V1
B6
B6
3
DR3 DR2 DR1 DR0
Request ID
4
V2
B7
B7
V0
B5
B5
0
0
1
1
Request Value 1
Request Value 2
Clear
5
B4
B4
B3
B3
B2
B2
B1
B1
B0
B0
6
7
No Response
Request Value 3
Read/Write NVM
Reserved
8
A3
A3
A2
A2
A1
A1
A0
A0
0
0
0
0
0
0
0
0
B7
1
B6
1
B5
1
B4
1
B3
B2
B1
B0
9
PA3 PA2 PA1 PA0
A
Reserved
B
Clear Logic Out
Set Logic Out
Reserved
C
A3
A3
A2
A2
A1
A1
A0
A0
0
0
0
0
0
0
0
0
NV
NV
U
U
LO
LO
BS
BS
IO3
IO3
IO2
IO2
IO1
IO1
IO0
IO0
D
E
F
Reverse Initialization
A3
A2
A1
A0
0
0
0
BF
NV
BS
G1
G0 PA3 PA2 PA1 PA0
Legend
A[3:0] = Address bits. The slave address.
B[7:0] = 8-bit A/D value.
L[3:0] = Level to output on I/O if configured as outputs.
LO = Logic Out level at the Logic Out pin.
NV = Allows nonvolatile address programming if set to “1”.
PA[3:0] = Bus Address to set the device to.
U = Undervoltage Flag.
BF = Bus Fault
BS = Status of the Bus Switch (1 = close).
DR[3:0] = I/O direction bits (1 = Output).
G[1:0] = Group assignment (the 33793 does not use these bits).
IO[3:0] = Logic level of I/O.
V[2:0] = Version number.
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FUNCTIONAL DEVICE OPERATION
DSI COMMANDS AND RESPONSES
Table 8. Short-Word Response Summary
Command
Command
Response
Description
Initialization
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Not Valid
Request Status
Request Value 0
I/O Control
NV
B7
U
LO
B5
BS
IO3
B3
IO2
B2
IO1
B1
IO0
B0
B6
B4
Not Valid
Request ID Information
Request Value 1
Request Value 2
Clear
V2
B7
B7
V1
B6
B6
V0
B5
B5
0
0
0
1
1
B4
B4
B3
B3
B2
B2
B1
B1
B0
B0
No Response
Request Value 3
Read/Write NVM
Reserved
B7
B6
B5
B4
B3
B2
B1
B0
Not Valid
Reserved
Clear Logic Out
Set Logic Out
Reserved
NV
NV
U
U
LO
LO
BS
BS
IO3
IO3
IO2
IO2
IO1
IO1
IO0
IO0
Reverse Initialization
Not Valid
Legend
B[7:0] = 8-bit A/D value.
NV = Allows nonvolatile address programming if set to “1”.
PA[3:0] = Bus Address to set the device to.
U = Undervoltage Flag.
BS = Status of the Bus Switch (1 = close).
LO = Logic Out level at the Logic Out pin.
IO[3:0] = Logic level of I/O.
V[2:0] = Version number.
DSI COMMANDS AND RESPONSES
Reception of the command will assign the device address
and group number. A Read/Write NVM command then may
be sent to complete the setting of a pre-programmed
address.
INITIALIZATION COMMAND
The Initialization command must be sent to the 33793
before it may commence communications over the bus. The
command may be used three ways. The first is to initialize a
programmable address device. The second is the first step in
assigning a pre-programmed address. The third is to initialize
a pre-programmed device.
A pre-programmed device must be initialized by putting its
address in both PA3:PA0 and A3:A0 fields.
Once a device has received an initialization command, it
will ignore further initialization commands unless it has
received a Clear command or undergone a power-up reset.
For the first case this command is sent to address zero
with the NV bit set to zero. The command will be received by
the next daisy chain device with its bus switch open.
Reception of this command will assign the device address
and group number.
If BS = 1 and no faults are detected, initialization will cause
the bus switch to close.
The command format is found in Table 9.
For the second case the Initialization command is sent the
same as the first except that the NV bit is set to one.
Table 9. Initialization Command Format
Data
Address
A2 A1
Command
CRC
X2 X1
NV
BS
G1
G0
PA3
PA2
PA1
PA0
A3
A0
0
0
0
0
X3
X0
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FUNCTIONAL DEVICE OPERATION
DSI COMMANDS AND RESPONSES
Table 9. Initialization Command Format
Legend
A[3:0] = Address bits. The slave address.
BS = Bus Switch Position (1 = closed).
G[1:0] = Group bits (unused).
NV = Nonvolatile Memory Write. The value of the NV bit in the slave.
PA[3:0] = Bus Address to set the device to.
X[3:0] = Cyclic Redundancy Check (CRC). The CRC as calculated by the
master.
device. The response is shown in Table 10. Because this is a
long-word only command, the short-word response is invalid.
INITIALIZATION RESPONSE
This response message is sent during the next message
following a valid Initialization command to the addressed
Table 10. Initialization Response Format
High Byte
Low Byte
G0 PA3 PA2 PA1 PA0
CRC
X1
A3
A2
A1
A0
0
0
0
BF
NV
BS
G1
X3
X2
X0
Legend
A[3:0] = Address bits. The slave address.
NV = Nonvolatile Memory Write. The value of the NV bit in the slave.
PA[3:0] = Bus Address to set the device to.
BF = Bus Fault. Bus out short to battery detected.
BS = Bus Switch Position (1 = closed).
G[1:0] = Group bits (unused).
X[3:0] = Cyclic Redundancy Check (CRC). The CRC as calculated by
the slave.
I/O and LOGICOUT. The command format is found in
Table 11.
REQUEST STATUS COMMAND
This command will cause the addressed device to return
the status of the NV, U, and BS bits and the logic levels of the
Table 11. Request Status Command Format
Data
Address
A2 A1
Command
CRC
X2 X1
–
–
–
–
–
–
–
–
A3
A0
0
0
0
1
X3
X0
Legend
A[3:0] = Address bits. The address of the selected device. An
address value of "0000" is ignored by all devices.
X[3:0] = Cyclic Redundancy Check (CRC). The CRC as calculated by the
master.
device. The response format is found in Table 12. The high
byte is omitted during the short-word response. No response
is generated if the command address field was $0.
REQUEST STATUS RESPONSE
This response message is sent during the next message
following a valid Request Status command to the addressed
Table 12. Request Status Response Format
High Byte
Low Byte
BS IO3
CRC
X2 X1
A3
A2
A1
A0
0
0
0
0
NV
U
LO
IO2
IO1
IO0
X3
X0
Legend
A[3:0] = Address bits. The slave address.
BS = Bus Switch Position (1 = closed).
LO = Logic out driven level.
NV = Nonvolatile Memory Write. The value of the NV bit in the slave.
U = Undervoltage indicated true by a “1”.
X[3:0] = Cyclic Redundancy Check (CRC). The CRC as calculated by the
slave.
IO[3:0] = Values at logic I/Os.
command. The command format is found in Table 13. The
analog input measured is defined in Table 14.
REQUEST VALUE n COMMAND
This command will cause the analog level at one of the
four I/O lines to be measured and returned on the following
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FUNCTIONAL DEVICE OPERATION
DSI COMMANDS AND RESPONSES
Table 13. Request Value n Command Format
Data
Address
A2 A1
Command
C2 C1
CRC
X2 X1
–
–
–
–
–
–
–
–
A3
A0
C3
C0
X3
X0
Legend
A[3:0] = Address bits. The address of the selected device.
An address value of "0000" is ignored by all devices.
C[3:0] = Command number.
X[3:0] = Cyclic Redundancy Check (CRC). The CRC as calculated by the
master.
REQUEST VALUES RESPONSE
Table 14. Analog Input Selection
This response is an 8-bit value representing the value
measured by the ADC. The selection of “n” is a function of the
command. This is shown in Table 15.
Command
A/D Input
0010
0101
0110
1000
I/O0
I/O1
I/O2
I/O3
The read will be completed during the idle period and will
represent the voltage at the end of the command. If an
undervoltage condition exists at any time during the
command or the measurement has not completed properly, a
value of “00000000” will be returned. This is a reserved value
to indicate a problem with the measurement. The minimum
valid level reported will be “00000001”. No response is
generated if the command address field was $0.
Table 15. Request Values Response Format
High Byte
Low Byte
D4 D3
CRC
X2
A3
A2
A1
A0
0
0
0
0
D7
D6
D5
D2
D1
D0
X3
X1
X0
Legend
A[3:0] = Address bits. The address of the selected device.
An address value of "0000" is ignored by all devices.
D[7:0] = Measured value (MSB = D7).
X[3:0] = Cyclic Redundancy Check (CRC).
settings control the level of the corresponding I/O if it is
I/O CONTROL COMMAND
enabled as an output. The format of this command is shown
in Table 16.
This register controls the I/O ports. When the “DR” bits are
set, the corresponding I/O is enabled as an output. The “L” bit
Table 16. I/O Control Command Format
Data
Address
A2 A1
Command
CRC
X2 X1
L3
L2
L1
L0
DR3
DR2
DR1
DR0
A3
A0
0
0
1
1
X3
X0
Legend
A[3:0] = Address bits.
L[3:0] = Level to output on I/O if configured as output. All bits are set to “0”
by reset/clear
DR[3:0] = I/O direction bits. 1 = Output. All bits are set to “0” by
reset/clear.
X[3:0] = Cyclic Redundancy Check (CRC). The CRC as calculated by the
master.
The values returned will be the values programmed. The
values at the pins will not be the ones that were programmed
if the pin has been forced to the opposite state. The response
format is shown in Table 17. No response is generated if the
command address field was $0.
I/O CONTROL RESPONSE
The response indicates which I/O has been configured as
outputs and their current values.
Table 17. I/O Control Response Format
High Byte
Low Byte
CRC
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FUNCTIONAL DEVICE OPERATION
DSI COMMANDS AND RESPONSES
Table 17. I/O Control Response Format
A3
A2
A1
A0
0
0
0
0
L3
L2
L1
L0
DR3
DR2
DR1
DR0
X3
X2
X1
X0
Legend
A[3:0] = Address bits.
L[3:0] = Programmed values.
DR[3:0] = I/O enabled as outputs (1 = enabled as output).
X[3:0] = Cyclic Redundancy Check (CRC). The CRC as calculated by the
slave.
the response to the next message. The command format is
found in Table 18.
REQUEST ID COMMAND
This command will cause the device ID information to be
read from internal storage and returned to the master during
Table 18. Request ID Command Format
Data
Address
A2 A1
Command
CRC
X2 X1
–
–
–
–
–
–
–
–
A3
A0
0
1
0
0
X3
X0
Legend
A[3:0] = Address bits. The address of the selected device. An
address value of “0000” is ignored by all devices.
X[3:0] = Cyclic Redundancy Check (CRC). The CRC as calculated by the
master.
addressed device. The response format is found in Table 19.
The high byte is omitted during the short-word response. No
response is generated if the command address field was $0.
REQUEST ID RESPONSE
This response message is sent during the next message
following a valid long-word Request ID command to the
Table 19. Request ID Response Format
Address
A2 A1
Status
Data
CRC
X2 X1
A3
A0
0
0
0
0
V2
V1
V0
0
0
0
1
1
X3
X0
Legend
A[3:0] = Address bits. The slave address.
X[3:0] = Cyclic Redundancy Check (CRC). The CRC as calculated by the
slave.
V[2:0] = Device version number. The silicon version number of the
device. For this device the device type is 00011 as indicated by the
lowest bits.
CLEAR COMMAND
This command will open the bus switch and reset all
registers to the reset state. The command format is found in
Table 20. No response is generated for the Clear command.
Table 20. Clear Command Format
Data
Address
A2 A1
Command
CRC
X2 X1
–
–
–
–
–
–
–
–
A3
A0
0
1
1
1
X3
X0
Legend
A[3:0] = Address bits. The address of the selected device. An
address value of “0000” clears all devices.
X[3:0] = Cyclic Redundancy Check (CRC). The CRC as calculated by the
master.
programmed, this nonvolatile address is used to set the
device address register on the next and all subsequent
power-ups. If the device is not blank, this command will return
the programmed value during the next message time.
READ/WRITE NVM COMMAND
If the NV bit has been set by a previous Initialization
command and the NVM has not been programmed
previously, this command will permanently program the
device’s one-time programmable address and return the
programmed value during the next message time. Once
Programming the NVM address to $0 is allowed. This
ensures that the device always acts as a dynamically
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FUNCTIONAL DEVICE OPERATION
DSI COMMANDS AND RESPONSES
addressable device and would be immune to any inadvertent
future NVM programming sequences.
Reads and writes are long-word commands only. The
command format is found in Table 21.
Table 21. Read/Write NVM Command Format
Data
Address
A2 A1
Command
CRC
X2 X1
1
1
1
1
PA3
PA2
PA1
PA0
A3
A0
1
0
0
1
X3
X0
Legend
A[3:0] = Address bits. These bits are the address of the device
PA[3:0] = Program Address bits. These bits are the address that is to be
previously sent with the Initialization command. They must match programmed into the slave.
the address in the PA[3:0] field and the address stored in the
X[3:0] = Cyclic Redundancy Check (CRC). The CRC as calculated by the
master.
device address register.
device. The response format is found in Table 22. The high
READ/WRITE NVM RESPONSE
byte is omitted during the short-word response. No response
is generated if the command address field was $0.
This response message is sent during the next message
following a valid Read/Write NVM command to the addressed
Table 22. Read/Write NVM Response Format
High Byte
Low Byte
CRC
X2 X1
A3
A2
A1
A0
0
0
0
0
1
1
1
1
PA3
PA2
PA1
PA0
X3
X0
Legend
A[3:0] = Address bits. The slave address.
X[3:0] = Cyclic Redundancy Check (CRC). The CRC as calculated by the
slave.
PA[3:0] = Programmed Address bits. The address that was
programmed into the NVM address bits of the slave.
Out. The Logic Out is also cleared at power-up or following a
Clear command. The format of the Clear Logic Out command
is shown in Table 23.
CLEAR LOGIC OUT COMMAND
The Clear Logic Out command sets the Logic Out pin to a
logic low. The compliment to this command is the Set Logic
Table 23. Clear Logic Out Command Format
Data
Address
A2 A1
Command
CRC
X2 X1
–
–
–
–
–
–
–
–-
A3
A0
1
1
0
0
X3
X0
Legend
A[3:0] = Address bits. The address of the selected device.
X[3:0] = Cyclic Redundancy Check (CRC). The CRC as calculated by the
master.
device. The response is shown in Table 24. No response is
generated if the command address field was $0.
CLEAR LOGIC OUT RESPONSE
This response message is sent during the next message
following a valid Clear Logic Out command to the addressed
Table 24. Clear Logic Out Response Format
High Byte
Low Byte
BS IO3
CRC
X2 X1
A3
A2
A1
A0
0
0
0
0
NV
U
LO
IO2
IO1
IO0
X3
X0
Legend
A[3:0] = Address bits. The slave address.
BS = Bus Switch Position (1=closed).
LO = Logic out driven level.
NV = Nonvolatile Memory Write. The value of the NV bit in the slave.
U = Undervoltage indicated true by a “1”.
X[3:0] = Cyclic Redundancy Check (CRC). The CRC as calculated by the
slave.
IO[3:0] = Values at logic I/Os.
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FUNCTIONAL DEVICE OPERATION
DSI COMMANDS AND RESPONSES
Logic Out. The Logic Out is cleared at power-up or following
a Clear command. The format of the Clear Logic Out
command is shown in Table 25.
SET LOGIC OUT COMMAND
The Set Logic Out command sets the Logic Out pin to a
logic high. The compliment to this command is the Clear
Table 25. Set Logic Out Command Format
Data
Address
A2 A1
Command
CRC
X2 X1
-
-
-
-
-
-
-
-
A3
A0
1
1
0
1
X3
X0
Legend
A[3:0] = Address bits. The address of the selected device.
X[3:0] = Cyclic Redundancy Check (CRC). The CRC as calculated by the
master.
device. The response is shown in Table 26. No response is
generated if the command address field was $0.
SET LOGIC OUT RESPONSE
This response message is sent during the next message
following a valid Set Logic Out command to the addressed
Table 26. Set Logic Out Response Format
High Byte
Low Byte
BS IO3
CRC
X2 X1
A3
A2
A1
A0
0
0
0
0
NV
U
LO
IO2 IO1 IO0
X3
X0
Legend
A[3:0] - Address bits. The slave address.
BS = Bus Switch Position (1=closed)
IO[3:0] = Values at logic I/Os.
NV = Nonvolatile Memory Write. The value of the NV bit in the slave.
U = Undervoltage indicated true by a “1”.
X[3:0] = Cyclic Redundancy Check (CRC). The CRC as calculated by the
slave.
LO = Logic out driven level.
For the second case the Initialization command is sent the
same as the first except that the NV bit is set to one.
Reception of the command will assign the device address
and the group number and cause the bus switch to close if BS
= 1 and there are no faults. A Read/Write NVM command
then may be sent to complete the setting of a pre-
programmed address.
REVERSE INITIALIZATION
The Reverse Initialization is similar to the Initialization
command and will only work under the condition that it has
not already been initialized. The command may be used
three ways. The first is to initialize a programmable address
device. The second is the first step in assigning a pre-
programmed address. The third is to initialize a pre-
programmed device.
A pre-programmed device must be initialized by putting its
address in both PA3:PA0 and A3:A0 fields.
For the first case this command is sent to address zero
with the NV bit set to zero. The command will be received by
the next daisy chain device with its bus switch open.
Reception of this command will assign the device address
and the group number. Reception of this command will also
cause the bus switch to close if BS = 1 and no fault is
detected.
Once a device has received a reverse initialization
command, it will ignore further reverse initialization
commands or initialization commands unless it has received
a Clear command or undergone a power-up reset.
The command format is found in Table 27.
Table 27. Reverse Initialization Command Format
Data
Address
A2 A1
Command
CRC
X2 X1
NV
BS
G1
G0
PA3
PA2
PA1
PA0
A3
A0
1
1
1
1
X3
X0
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FUNCTIONAL DEVICE OPERATION
DSI COMMANDS AND RESPONSES
Table 27. Reverse Initialization Command Format
Legend
A[3:0] = Address bits. These bits are the slave address. For
programmable devices these bits are all set to zero. For pre-
programmed devices these bits contain the pre-programmed
address and must match the PA[3:0] bits.
NV = Nonvolatile Memory Write. When set to a one, this bit allows a
subsequent NVM command to store a nonvolatile address. When set to a
zero, NVM programming is disallowed. Once a permanent address has
been stored in the device, setting the NV bit to a one has no effect.
G[1:0] = Group bits. These bits are the group number for the slave. X[3:0] = Cyclic Redundancy Check (CRC). The CRC as calculated by the
These bits are not used by this device and should be set to “0”.
master.
PA[3:0] = Program Address bits. These bits are the address that is
to be stored into the slave’s address register.
this is a long-word only command, the short-word response is
REVERSE INITIALIZATION RESPONSE
invalid. No response is generated if the command address
field was $0.
This response message is sent during the next message
following a valid Reverse Initialization command to the
addressed device. The response is shown in Table 28. Since
Table 28. Reverse Initialization Response Format
High Byte
Low Byte
G0 PA3 PA2 PA1 PA0 X3
CRC
X1
A3
A2
A1
A0
0
0
0
BF
NV
BS
G1
X2
X0
Legend
A[3:0] = Address bits.The slave address.
NV = Nonvolatile Memory Write. The value of the NV bit in the slave.
PA[3:0] = Bus Address to set the device to.
BF = Bus Fault. BUSIN short to battery detected.
BS = Controls closing of the Bus Switch (1=close).
X[3:0] = Cyclic Redundancy Check (CRC). The CRC as calculated by the
slave.
G[1:0] = Group bits. Not used on this part, will be set to “0”. The
group number programmed into the slave.
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TYPICAL APPLICATIONS
TYPICAL APPLICATIONS
H_CAP
1.0 µF
Typical
Rectifiers
BUSIN
Bus Switch
0 – 35 V Bi-Directional
BUSOUT
Reverse Receiver
Forward Receiver
Data
Data
Response
Current
0 –11 mA
7.0 mA/µS
Frame
Frame
BUSRTN
Received
Message
Bandgap
Reference
Bandgap
Reference
Bus Return
from MCU
Oscillator
4.0 MHz
Logic
Command Decode
State Machine
LOGOUT
REGOUT
DataOut <3:0>
Response Generation
Logic Out
HighCurrent
Buffer
I/O Buffers
4
Power
DataOut <0>
Address A<3:0>
4 Bits NVM
Management
5.0 V Regulator
BG Reference
Bias Currents
IO0
DataOut <1>
DataOut <2>
DataOut <3>
4.7 µF
IO1
IO2
GND
SEL
Supply Comparators
POR
I/O0
I/O1
4:1
ADC
8 Bits
IO3
I/O2
I/O3
Undervoltage
Detector
MUX
I/O<3:0>
BG
time to decode the command, retrieve the information and
prepare to send it to the master. A bus traffic example is
shown in Figure 6.
COMMUNICATION FORMAT
DSI messages are composed of individual words
separated by a frame delay. Transfers are full duplex.
The example shows three commands separated by the
minimum frame delay followed by a command after a longer
delay.
Command messages from the master occur at the same time
as responses from the slaves. Slave responses to commands
occur during the next command message. This allows slaves
Master
Slave
Figure 6. Bus Traffic Example
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22
TYPICAL APPLICATIONS
In case there is a bus error (due to induced noise or a bus
fault), both the master and slave devices will read bad data.
The slave reacts to bad data by not sending a response
during the next frame. The master will detect a CRC error
once it receives the corrupted data sent by the slave, and
once again when the slave fails to respond. This is illustrated
in Figure 7. When this error occurs, the system software
needs to acknowledge this condition and resend a command
(any command of same size) so that it can receive the
previous response just prior to the bus fault condition (in this
case, Command N).
Failure to take corrective action will result in unintended
errors as shown in Figure 7. In this case, the master will miss
Responses N+1 and N+2 and will mistake them for N+3 and
N+4. The master should send another N+1 command after
the error is acknowledged to re-synchronize the command-
response sequence.
CRC
Error
CRC
Error
Bus Error
Data misinterpreted by Master
Master
Command N
Command N+1
Response N
Command N+2
No Response
Command N+3
Response N
Command N+4
Response N+3
Slave
Response N-1
CRC
Error
Figure 7. Bus Traffic With Receive Errors (Master Reads Incorrect Data)
just before a device is Reverse Initialized, the BUSIN is
defined as the inactive side.
POWER UP RESET
When power is first applied to the DSI bus, the system
must allow enough time for the internal 5 volt regulator of
each device to come up to a proper level. This implies that
H_CAP must charge up to VRECT + 5 V, or approximately 6
volts. The time this takes is a function of the size of H_CAP,
and the current drive of the Master. The following equation
can be used to estimate the minimum time to wait before
sending an Initialization Command:
The test for a bus fault is only performed once during
Forward or Reverse Initialization (when BS bit is set) by
applying an 11mA pull-down current to the inactive side of the
Bus Switch and monitoring the voltage. The fault test takes
approximately 200uS. If no fault is detected, the bus switch
will be closed, and if a fault is detected, the bus switch will not
close. The fault test applies to both programmed and
unprogrammed devices.
tMIN ≅ (H_CAP x 6V) / ICHARGE
Exception: In the case of a daisy-chain bus topology where
the last device BUSOUT line connects to BUSIN of the first
device (loop-back), then the fault test will NOT be executed
since both BUSIN and BUSOUT are connected to active
busses. It is up to the system software to run the appropriate
diagnostic tests to resolve this special case. (One alternative
is to use a separate DSI Master to handle the loop-back
signal path. This second DSI Master is only activated in the
case of a bus fault so that the last device can be accessed by
means of a reverse initialization.)
where ICHARGE is the charging current provided by the DSI
Master.
The above assumes a daisy-chain type of bus topology,
and enough time must be allowed for all down-stream
devices in the chain to charge up. For example, if device #1
has it’s switch closed after its Initialization Command, then
the system must wait for device #2 to power up before
sending its Initialization Command, and so on down the line.
If the devices are attached in a parallel or point-to-point
bus configuration, then the total capacitor value is the sum of
all H_CAPS.
GLOBAL ADDRESS 0
In addition to the charge up time, enough time must be
allocated for the bus fault test (see next section).
Any time an Initialization or Reverse Initialization
command is sent to the 33793 with an address of 0x0 (global
address), the device behaves as follows:
BUS FAULTS
• Device initializes to address 0.
A bus fault is defined as an external voltage on the
“Inactive Side” of the Bus Switch that is greater than 3V
(typical). Inactive refers to the side of the bus that is not yet
connected to the bus. Just before a device is Forward
Initialized, the inactive side is defined as BUSOUT. Similarly,
• Bus switch remains open. This implies that in a daisy-
chain bus topology, all devices past the first device will
remain off.
• NV and BS bits are not stored and have no effect.
33793
Analog Integrated Circuit Device Data
Freescale Semiconductor
23
TYPICAL APPLICATIONS
• Device will respond to further commands at address 0
(such as setting and clearing the I/O bits and LOGOUT)
but there is no response (Master will read all zeros). If
the devices are connected in a daisy chain, then only
the fist device will respond.
• Subsequent writes to re-initialize the device will not be
possible until the device is cleared.
33793
Analog Integrated Circuit Device Data
Freescale Semiconductor
24
PACKAGING
PACKAGE DIMENSIONS
PACKAGING
PACKAGE DIMENSIONS
For the most current package revision, visit www.freescale.com and perform a keyword search using the “98A” listed below.
EF SUFFIX
(PB-FREE)
16-PIN PLASTIC PACKAGE
98ASB42566B
ISSUE M
33793
Analog Integrated Circuit Device Data
Freescale Semiconductor
25
REVISION HISTORY
REVISION HISTORY
REVISION
DATE
DESCRIPTION OF CHANGES
• Implemented Revision History page
• Converted to Freescale format
8/2006
12.0
• Added PC33793EF
• Added Feature bullets
• Rewrote and enhanced Device Operation - No electrical changes
• Updated to the prevailing Freescale form and style
• Removed PC33793EF and replaced with MCZ33793EF/R2 in the Ordering Information
block
• Added MCZ33793AEF/R2 to the Ordering Information
• Added Device Variations table on page 2
11/2006
13.0
• Removed Peak Package Reflow Temperature During Reflow (solder reflow) parameter
from Maximum Ratings on page 5. Added note with instructions to obtain this information
from www.freescale.com.
33793
Analog Integrated Circuit Device Data
Freescale Semiconductor
26
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MC33793
Rev 13.0
11/2006
相关型号：
MCZ33793EF
SPECIALTY ANALOG CIRCUIT, PDSO16, 1.27 MM PITCH, LEAD FREE, PLASTIC, MS-012AC SOIC-16
ROCHESTER
MCZ33793EF
SPECIALTY ANALOG CIRCUIT, PDSO16, 1.27 MM PITCH, ROHS COMPLIANT, PLASTIC, MS-012AC SOIC-16
NXP
MCZ33810EKR2
6A BUF OR INV BASED PRPHL DRVR, PDSO32, 0.65 MM PITCH, ROHS COMPLIANT, SOIC-32
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