MCZ33800R2_技术文档

Document Number: MC33800

Rev. 5.0, 10/2007

Freescale Semiconductor

Advance Information

Engine Control Integrated

Circuit

33800

The 33800 is a combination output switch and driver Integrated

Circuit (IC) which can be used in numerous powertrain applications.

The IC contains two programmable constant current drivers (CCD),

an octal, low side, serial switch (OSS), and six, external MOSFET

gate pre-drivers (GD). The IC has over-voltage, under-voltage, and

thermal protection. All drivers and switches, including the external

MOSFETs, have over-current protection, off-state open load

detection, on-state shorted load detection, and fault annunciation via

the serial peripheral interface (SPI).

ENGINE CONTROL

Additional features include: Low power Sleep Mode, Heated

Exhaust Gas Oxygen (HEGO) sensor diagnostics, output control via

serial and/or parallel inputs, PWM capability, and programmable

current output with dithering. These features, along with cost effective

packaging, make the 33800 ideal for Powertrain Engine Control

applications.

EK SUFFIX (Pb-FREE)

98ASA99334D

54-PIN SOICW-EP

ORDERING INFORMATION

Features

Temperature

Package

• Wide operating voltage range, 5 < VPWR < 36V

• Interfaces to 3.3V and 5V microprocessors via SPI protocol

• Low, Sleep Mode, standby current, typically 10uA.

• Internal or external voltage reference

Device

Range (T )

A

MCZ33800EK/R2

-40°C to 125°C

54 SOICW EP

• Internal oscillator with calibrate capability

• Measures resistance to monitor HEGO sensors

• CCDs have programmable current, dither frequency and amplitude

• OSSs can be paralleled to increase current capability

• GDs have programmable frequency and duty cycle PWM

• All outputs controllable via serial and/or parallel inputs

• Pb-free packaging designated by suffix code EK

33800

V_PWR

V_BAT

VPWR

CCD1_REC

CCD1_OUT

V

DD

MCU

VDD

V_PWR

2.5V

VCAL

CCD2_REC

CCD2_OUT

RI_REF

REXT

V_BAT

MOSI

SCLK

CS

SI

V_BAT

OUT1

OUT8

SCLK

CS

SO

MISO

VDSNS1

DEFAULT

EN

{

GD1

VSSNS123

LRFDBK

AN0

P1,P3,P5,P7

PWM1

VDSNS6

{

GD6

PWM6

GND

VSSNS456

Figure 1. MC33800 Simplified Application Diagram

* This document contains certain information on a new product.

Specifications and information herein are subject to change without notice.

INTERNAL BLOCK DIAGRAM

VPWR, VDD

VPWR

VDD

GND

POR

80µA

Sleep PWR

Oscillator

Bandgap

VCAL

V

CCD2_OUT

CCD1_OUT

DD

15µA

CCD2 Outputs

CCD1 Outputs

15µA

CCD2_REC

CCD1_REC

DEFAULT

EN

53V

100K

Gate Control

Open/Short

40µA

P1

P3

P5

P7

SI

+

–

R

15µA

S

CCGND

lLimit

Outputs 1 to 8

OUT 1

75µA

53V

to

Gate Control

Open/Short

OUT 8

Logic Control &

SPI Interface

+

–

R

S

PGND

V

lLimit

DD

15µA

Predriver1,2,3

CS

SCLK

SO

VDSNS1

V

PWR

PWM1

Gate Drive

Control &

Diagnostics

GD1

15µA

PWM2

PWM3

PWM4

PWM5

PWM6

VSSNS123

15µA

Predriver4,5,6

VDSNS4

V

PWR

Gate Drive

Control &

Diagnostics

GD4

VSSNS456

Differential

Amplifier

+

−

+

−

LRFDBK

REXT

+

−

VCAL

+

−

VCAL

RI_REF

Exposed

Pad

Figure 2. 33800 Simplified Internal Block Diagram

33800

Analog Integrated Circuit Device Data

Freescale Semiconductor

2

PIN CONNECTIONS

1

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

VDSNS4

GD4

VDSNS5

GD5

VDSNS6

GD6

VSSNS456

LRFDBK

SI

VDSNS3

GD3

VDSNS2

GD2

VDSNS1

GD1

VSSNS123

REXT

PGND1

OUT1

PGND2

OUT2

OUT3

OUT4

OUT5

PGND

OUT6

OUT7

OUT8

DEFAULT

SO

VDD

VCAL

GND

2

3

4

5

6

7

8

9

SCLK

CS

P1

P3

P5

P7

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

PWM1

PWM2

PWM3

PWM4

PWM5

PWM6

CCD2_GND

CCD2_OUT

CCD2_REC

EN

VPWR

CCD1_GND

CCD1_REC

RI_REF

CCD1_OUT

Figure 3. 33800 Pin Connections

Table 1. 33800 Pin Definitions

A functional description of each pin can be found in the Functional Pin Description section beginning on page 16.

Pin Number Pin Name Pin Function

Formal Name

Definition

The VDSNS pin is used to monitor the drain voltage of the external

MOSFET.

1, 3, 5, 50,

52, 54

VDSNS1-

VDSNS6

Input

Drain Voltage Sense

The GD pin provides gate drive for an external MOSFET

2, 4, 6, 49,

51, 53

GD1-GD6

Output

Input

Gate Driver Output

The VSSNS pins are used to monitor the source voltage of the external

MOSFETS.

7

VSSNS456

VSSNS123

Source Voltage Sense

48

The LRFDBK pin is an operational amplifier output.

8

LRFDBK

Output

Input

Load Resistance

Feedback

The SI input pin is used to receive serial data from the MCU. The serial

input data is latched on the rising edge of SCLK, and the input data

transitions on the falling edge of SCLK.

9

SI

Serial Input Data

The SCLK input pin is used to clock in and out the serial data on the SI

and SO Pins while being addressed by the CS.

10

11

SCLK

CS

Input

Serial Clock Input

Chip Select

The Chip Select input pin is an active low signal sent by the MCU to

indicate that the device is being addressed. This input requires CMOS

logic levels and has an internal active pull up current source.

Input control of OSS output 1. When configured via the SPI, P1 input may

be used to control OSS output 1 and output 2 in parallel.

12

13

14

P1

P3

P5

Input

Input One

Input Three

Input Five

Input control of OSS output 3. When configured via the SPI, P3 input may

be used to control OSS output 3 and output 4 in parallel.

Input control of OSS output 5. When configured via the SPI, P5 input may

be used to control OSS output 5 and output 6 in parallel.

33800

Analog Integrated Circuit Device Data

Freescale Semiconductor

3

PIN CONNECTIONS

Table 1. 33800 Pin Definitions(continued)

A functional description of each pin can be found in the Functional Pin Description section beginning on page 16.

Pin Number Pin Name Pin Function

Formal Name

Definition

Input control of OSS output 7. When configured via the SPI, P7 input may

be used to control OSS output 7 and output 8 in parallel.

15

P7

Input

Input Seven

The PWMX input pin is used for direct parallel control of the GDX (Gate

Drive Output X) predriver or as on/off control of the internal PWM

controller. Control strategy is programmed via the SPI.

16,17, 18, 19,

20, 21

PWMX

Pulse Width

Modulated Input

The CCD2_GND pin provides a dedicated ground for the CCD2 constant

current controller

22

23

CCD2_GND

CCD2_OUT

Ground

Output

CCD2 Ground

The CCD2_OUT pin is connected to a series internal sense resistor and

power MOSFET driver. The CCD2_OUT has a pull up and pull down

current source and is used for fault threshold monitoring.

Current Controlled

Driver 2 Output

The CCD2_REC pin provides a recirculation path for the load current.

The CCD2_REC pin is connected to the node between the internal sense

resistor and power MOSFET driver. The device uses the differential

voltage between CCD2_REC and CCD2_OUT to determine the load

solenoid current.

24

CCD2_REC

Input

Current Controlled

Driver 2 Recirculation

Input

The EN pin is an active high input.

25

26

EN

Input

ENABLE

The RI_REF pin is used to generate a reference current. The reference

is used in the regulation of the constant current controller. The constant

current controller regulation current is inversely proportional to the

reference current through the external resistor. A 39.2kΩ 1% resistor to

ground will set the 1FF programmed current value of the CCD1 to

1075mA and the CCD2 to be 232mA.

RI_REF

Output

Resistor for Current

Reference

The CCD1_OUT pin is connected to a series internal sense resistor and

power MOSFET driver. The CCD1_OUT has a pull up and pull down

current source and is used for fault threshold monitoring.

27

28

CCD1_OUT

CCD1_REC

Output

Input

Current Controlled

Driver 1 Output

The CCD1_REC pin provides a recirculation path for the load current.

The CCD1_REC pin is connected to the node between the internal sense

resistor and power MOSFET driver. The device uses the differential

voltage between CCD1_REC and CCD1_OUT to determine the load

solenoid current.

Current Controlled

Driver 1 Recirculation

Input

The CCD1_GND pin provides a dedicated ground for the CCD1 constant

current controller

29

30

31

32

CCD1_GND

VPWR

Ground

CCD1 Ground

The VPWR pin provides power to all pre-driver, driver and output circuits

and other internal functions such as the oscillator and SPI circuits.

Power Input Analog Voltage Supply

Analog ground for the internal control circuits of the IC. This ground

should be used for decoupling of VDD and VPWR supply.

GND

Ground

Input

Ground

VCAL input is a precision (2.5V, +8.0mV, -20mV over temperature)

reference input, used in several internal circuits. A 1.0nF to 10nF

decoupling capacitor is required on the VCAL input pin to ground.

VCAL

Voltage Calibrated

Input

The VDD pin supplies power to the Serial Output (SO) buffer along with

the pull up current sources for the chip select (CS) and DEFAULT inputs.

33

34

VDD

SO

Power Input Digital Voltage Supply

The SO output pin is used to transmit serial data from the device to the

MCU. The SO pin remains tri-stated until selected by the active low CS.

The serial output data is available to be latched by the MCU on the rising

edge of SCLK. The SO data transitions on falling edge of the SCLK.

Output

Serial Output Data

The DEFAULT pin is an active high input.

35

DEFAULT

Input

Default Mode Enable

OSS Output 1-8

Octal Serial Switch (OSS) low side driver output 1-8.

36-38, 40, OUT1-OUT8

41-43, 45

Output

33800

Analog Integrated Circuit Device Data

Freescale Semiconductor

4

PIN CONNECTIONS

Table 1. 33800 Pin Definitions(continued)

A functional description of each pin can be found in the Functional Pin Description section beginning on page 16.

Pin Number Pin Name Pin Function

Formal Name

Definition

This PGND pins provide a dedicated ground for the Octal Serial Switch

(OSS) low side driver outputs 3 - 8.

39

44

46

47

_

PGND3

PGND2

PGND1

REXT

_

Ground

Output

Ground

OSS 3-8 Ground

This PGND pin provides a dedicated ground for the Octal Serial Switch

(OSS) low side driver output 2.

OSS 2 Ground

OSS 1 Ground

This PGND pin provides a dedicated ground for the Octal Serial Switch

(OSS) low side driver output 1.

The REXT pin is used to generate a reference current.

Resistor External

Reference

The package exposed pad provides thermal conductivity for the die and

should be grounded to system ground.

Exposed Pad Ground

33800

Analog Integrated Circuit Device Data

Freescale Semiconductor

5

ELECTRICAL CHARACTERISTICS

MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

MAXIMUM RATINGS

Table 2. Maximum Ratings

All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or

permanent damage to the device.

Ratings

Symbol

Value

Unit

ELECTRICAL RATINGS

Supply Voltage

V_PWR

V_DC

V_PWR

V_DD

-1.5 to 45

-0.3 to 7.0

V_DD

CS, SI, SO, SCLK, EN, DEFAULT, PWMx, P1, P3, P5, P7

Predriver Drain Voltage (VDSNS1 to VDSNS6)

–

-0.3 to V_DD

-0.3 to 60

30

V_DC

mJ

V_DSNS

OSS Output Clamp Energy (OUT3 to OUT8)(Single Pulse)

T_Junction= 150°C, I_OUT= 0.45A

E

CLAMP

OSS Output Clamp Energy (OUT1 & OUT2)(Single Pulse)

T_Junction= 150°C, I_OUT= 0.45A

45

75

mJ

mA

mJ

CCD1 Output Clamp Energy (Single Pulse)

T_Junction= 150°C, I_OUT= 0.45A

CCD2 Output Clamp Energy (Single Pulse)

T_Junction= 150°C, I_OUT= 0.45A

25

OSS Output Continuous Current (OUT1 to OUT8 Steady State)

T_Junction= 150°C

I_{OSS_SS}

350

75

CCD1 Output Clamp Energy (CCD1_REC OUTPUT)

T_Junction= 150°C, I_OUT= 1.0 A

E

CLAMP

–

Frequency of SPI Operation (V_DD= 5.0V)⁽³⁾

4.0

MHz

V

ESD Voltage⁽¹⁾

V_ESD1

V_ESD2

±2000

±200

Human Body Model

Machine Model

THERMAL RATINGS

Storage Temperature

T

-55 to 150

-40 to 125

-40 to 150

1.7

°C

W

STG

Operating Case Temperature

Operating Junction Temperature

Power Dissipation (T_A= 25°C)⁽²⁾

THERMAL RESISTANCE

T_C

T_J

P_D

Thermal Resistance

R

71

Junction to Ambient

θJA

°C/W

R

1.2

Between the Die and the Exposed Die Pad

θJC

Notes

1. ESD data available upon request. All pins tested individually. ESD1 testing is performed in accordance with the Human Body Model

(AEC-Q100-002). and the Machine Model (AEC-Q100-003).

2. Maximum power dissipation at T_J=150°C junction temperature with no heat sink used.

3. This parameter is guaranteed by design but is not production tested.

33800

Analog Integrated Circuit Device Data

Freescale Semiconductor

6

ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

Table 3. Static Electrical Characteristics

Characteristics noted under conditions 3.0V ≤ V_DD≤ 5.5V, 9.0V ≤ V_PWR≤ 18V, -40°C ≤ T_A≤ 125°C, GND = 0V, unless

otherwise noted. Typical values noted reflect the approximate parameter means at T_A= 25°C under nominal conditions, unless

otherwise noted.

Characteristic

POWER INPUT (VPWR, VDD)

Symbol

Min

Typ

Max

Unit

Supply Voltage

V

Fully Operational

V

5.0

–

36

PWR(FO)

Supply Current

I

mA

µA

(ON)

PWR

All Outputs Disabled (Normal & Default Mode)

10.0

14.0

Sleep State Supply Current

V

≤ 0.8 V, V_PWR= 18V

I

–

10

30

DD

SS

PWR(

)

EN ≤ 0.8 V, V_DD= 5.5V

I

2.0

5.0

VDD(SS)

V

Over-voltage Shutdown Threshold Voltage⁽⁴⁾

V_PWR(OV)

V_PWR(OVHYS)

V_PWR(UV)

36.5

0.5

39

1.5

4.0

200

–

44

3.0

4.4

650

5.5

V

PWR

Over-voltage Shutdown Hysteresis Voltage

Under-voltage Shutdown Threshold Voltage⁽⁵⁾

Under-voltage Shutdown Hysteresis Voltage

PWR

3.0

V

V_PWR(UVHYS)

100

3.0

mV

V

Logic Supply Voltage

V

DD

Logic Supply Current

Static Condition

I

µA

180

0.8

100

2.2

300

2.5

–

525

2.8

650

2.8

Logic Supply Under-voltage Shutdown Threshold Voltage ⁽⁵⁾

Logic Supply Under-voltage Hysteresis

V

mV

V

DD(UV)

V

DD(UVHYS)

V_BIAS

(6)

Internally Generated V_CAL

2.5

CONSTANT CURRENT SOLENOID DRIVER OUTPUT (CCD1_OUT)

Drain-to-Source ON Resistance

Ω

RDS(ON)

T = 125°C, V

= 13V

PWR

–

0.25

–

0.60

–

J

T = 25°C, V

= 13V

PWR

J

PWR

T = -40°C, V

J

Internal Current Sense Resistor

R

Ω

SENSE

DAC Value = 000, V_CCD1REC= 0.0V, I_CCD1OUT= 100mA

R_SENSE= V_CCD1OUT/ I_CCD1OUT

0.7

1.2

Current Regulation

I

mA

CCD1

DAC Value = 17C HEX +/- (3%)

DAC Value = 05F HEX +/- (15%)

Load Resistance = 5Ω, Load Inductance = 10mH, Dither Off

775

157

800

200

823

235

Programmable Dither Frequency

f_DITHER

%

Programmable from 50Hz to 500Hz in 50Hz Increments after

Calibration

-10

10

Notes

4. Over-voltage thresholds minimum and maximum include hysteresis.

5. Under-voltage thresholds minimum and maximum include hysteresis.

6. Using the internally generated V_CALincreases all applicable parametric tables by +- 10%

33800

Analog Integrated Circuit Device Data

Freescale Semiconductor

7

ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

Table 3. Static Electrical Characteristics

Characteristics noted under conditions 3.0V ≤ V_DD≤ 5.5V, 9.0V ≤ V_PWR≤ 18V, -40°C ≤ T_A≤ 125°C, GND = 0V, unless

otherwise noted. Typical values noted reflect the approximate parameter means at T_A= 25°C under nominal conditions, unless

otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

CONSTANT CURRENT SOLENOID DRIVER OUTPUT (CDD1_OUT) (CONTINUED)

Programmable Dither Amplitude Peak to Peak

I

%

V

DITHER

Programmable from 0.0mA to 350mA in 50mA increments

-10

2.0

10

CCD1 Fault Detection Voltage Threshold

Outputs Programmed OFF

V

OUT(FLTTH)

2.5

3.0

CCD1 Output Clamp Voltage

Outputs Programmed OFF

V

OC

50

55

–

60

CCD1 Output Self Limiting Current

CCD1 Output Leakage Current

I

1.5

2.8

A

OUT(LIM)

I

µA

CCD1(LKG)

Pull-up enabled, Dither Off, CCD1OUT = V_OC- 1.0V

Pull-up enabled, Dither Off, CCD1OUT = V_PWR= 24V

–

8000

20

–

CCD1 Pull Up Current

I

-60

-40

-20

µA

CCD1(PULLUP)

Pull-up enabled, DAC = 000, CCD1OUT = CCD1REC = 2.0V

CCD1 Pull Down Current

I

20

40

60

CCD1(PULLDOWN)

Pull-up disabled, DAC = 000, CCD1OUT = CCD1REC = 2.0V

CONSTANT CURRENT SOLENOID DRIVER OUTPUT (CCD2_OUT)

Drain-to-Source ON Resistance

Ω

RDSON

T = 125°C, V

= 13V

PWR

–

1.0

–

2.0

–

J

T = 25°C, V

= 13V

PWR

J

PWR

T = -40°C, V

J

Internal Current Sense Resistor

R_SENSE

Ω

DAC Value = 000, V_CCD2REC= 0V, I_CCD2OUT= 100mA

R_SENSE= V_CCD2OUT/ I_CCD2OUT

3.5

5.0

Current Regulation

I

mA

CCD2

DAC Value = 17C HEX +/- (4%)

DAC Value = 05F HEX +/- (10%)

Load Resistance = 32Ω, Load Inductance = 130mH, Dither Off

166

38.9

173

43.2

180

47.5

Programmable Dither Frequency

f_DITHER

%

Programmable from 50Hz to 500Hz in 50Hz Increments after

Calibration

-10

10

Programmable Dither Amplitude Peak to Peak

I_DITHER

%

V

Programmable from 0.0mA to 90mA in 10.9mA increments

-10

2.0

50

10

3.0

60

CCD2 Fault Detection Voltage Threshold

Outputs Programmed OFF

V

OUT(FLTTH)

2.5

55

CCD2 Output Clamp Voltage

Outputs Programmed OFF

V

OC

CCD2 Output Leakage Current

I

µA

CCD2(LKG)

Pull-up enabled, Dither Off, CCD2OUT = V_OC- 1.0V

Pull-up enabled, Dither Off, CCD2OUT = V_PWR= 24V

–

8000

20

–

CCD2 Output Self Limiting Current

I

0.5

1.0

A

OUT(LIM)

33800

Analog Integrated Circuit Device Data

Freescale Semiconductor

8

ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

Table 3. Static Electrical Characteristics

Characteristics noted under conditions 3.0V ≤ V_DD≤ 5.5V, 9.0V ≤ V_PWR≤ 18V, -40°C ≤ T_A≤ 125°C, GND = 0V, unless

otherwise noted. Typical values noted reflect the approximate parameter means at T_A= 25°C under nominal conditions, unless

otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

CONSTANT CURRENT SOLENOID DRIVER OUTPUT (CCD2_OUT) (CONTINUED)

CCD2 Pull Up Current

I

-60

20

-40

40

-20

60

µA

CCD2(PULLUP)

Pull-up enabled, DAC = 000, CCD1OUT = CCD1REC = 2.0V

CCD2 Pull Down Current

I

CCD2(PULLDOWN)

Pull-up disabled, DAC = 000, CCD2OUT = CCD2REC = 2.0V

OCTAL SERIAL DRIVERS (OUT1 - 8)

Drain-to-Source ON Resistance (OUT1 - 2)

R

Ω

A

DS (ON)

–

0.7

–

1.4

–

I

= 0.350A, T = 125°C, V

= 13V

PWR

OUT

J

= 0.350A, T = 25°C, V

= 13V

PWR

J

PWR

= 0.350A, T = -40°C, V

–

J

Drain-to-Source ON Resistance (OUT3 - 8)

–

1.0

–

1.7

–

I

= 0.350A, T = 125°C, V

= 13V

PWR

OUT

J

= 0.350A, T = 25°C, V

= 13V

PWR

J

PWR

= 0.350A, T = -40°C, V

–

J

Output Self Limiting Current

Output 3 to Output 8

Output 1, Output 2

I

OUT(LIM)

1.0

4.0

–

2.0

6.0

Output Fault Detection Voltage Threshold.⁽⁷⁾

Outputs Programmed OFF

V

OUT(FLTTH)

2.0

40

2.5

75

3.0

Output OFF Open Load Detection Current

I

µA

OCO

V

= 18V, Outputs Programmed OFF

100

Drain

Output Clamp Voltage Low Side Drive

= 20mA

V

OC

I

50

55

60

D

Output Leakage Current

I

µA

OUT(LKG)

V

= 5.0V, V

= 24V, Open Load Detection Current Disabled

= V_OC- 1.0V, Open Load Detection Current

–

20

3000

10

DD

Drain

Disabled

= 0V, V

V

= 24V, Device Disabled

Drain

DD

Over-temperature Shutdown⁽⁸⁾

TLim

TLim_(HYS)

155

5.0

–

185

15

°C

Over-temperature Shutdown Hysteresis⁽⁸⁾

SPI DIGITAL INTERFACE (SO, SI, CS, SCLK)

Input Logic High-voltage Thresholds⁽⁸⁾

Input Logic Low-voltage Thresholds⁽⁸⁾

Input Logic Voltage Hysteresis⁽⁸⁾

10

V

0.7 x V_DD

GND - 0.3

100

–

V_DD+ 0.3

0.2 x V_DD

300

V

IH

V

IL

V

mV

pF

µA

HYS

Input Logic Capacitance⁽⁸⁾

C

–

20

IN

Sleep Mode Input Logic Current⁽⁸⁾

I

LOGICSS

V

= 0.0V

-10

–

10

DD

Notes

7. Output fault detection thresholds with outputs programmed OFF. Output fault detect thresholds are the same for output open and shorts.

8. This parameter is guaranteed by design, however is not production tested.

33800

Analog Integrated Circuit Device Data

Freescale Semiconductor

9

ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

Table 3. Static Electrical Characteristics

Characteristics noted under conditions 3.0V ≤ V_DD≤ 5.5V, 9.0V ≤ V_PWR≤ 18V, -40°C ≤ T_A≤ 125°C, GND = 0V, unless

otherwise noted. Typical values noted reflect the approximate parameter means at T_A= 25°C under nominal conditions, unless

otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

SPI DIGITAL INTERFACE (SO, SI, CS, SCLK) (CONTINUED)

Sleep Mode EN and DEFAULT Input Current

I

µA

LOGICSS

LOGICPD

V

= 0.0V, V = 5.0V, V

= 5.0V

D E FA U LT

-10

–

10

D D

EN

Normal Mode Input Logic Pull-down Current⁽⁹⁾

0.8V to 5.0V

I

5.0

15

–

25

Normal Mode DEFAULT Pull-up Current

I_DEFAULTPU

-5.0

-25

µA

SCLK, Tri-state SO Output

0.0V to 5.0V

I_SCLK,I_TRISO

-10

–

10

CS Input Current

CS = V_DD

I

µA

CS

CS Pull-up Current

CS = 0.0V

I

µA

CSPU

-5.0

–

-30

10

CS Leakage Current to V_DD

I

CS(LKG)

CS = 5.0V, V

= 0.0V

DD

SO High-state Output Voltage

= -1.0mA

V

SOHIGH

I

V

- 0.4

–

SOHIGH

DD

SO Low-state Output Voltage

= 1.0mA

V

SOLOW

I

–

0.4

SOLOW

^IENPD

10

50

100

µA

EN Input Pull-down Current

EN = V_DD

PREDRIVER OUTPUT FUNCTION (GD1 - GD6)

Gate Drive Output Voltage

I_GATEDRIVE= 100µA

I_GATEDRIVE= - 100µA

V_GS(ON)

V_GS(OFF)

5.0

–

7.0

0.2

9.0

0.5

V

Gate Drive Sink and Source Current

Sleep Mode Gate to Source Resistor

Short Fault Detection Voltage Threshold

I_GATEDRIVE

R_GS(PULLDOWN)

V_DS(FLTTH)

–

2.0

5.0

mA

KΩ

V

65

200

300

V

= High, Outputs Programmed ON

-20%

+20%

3.0

DD

Programmable from 0.5V to 3.0V in 0.5V increments.

Open Fault Detection Voltage Threshold

V_DS(FLTTH)

V

= High, Outputs Programmed OFF

2.0

2.5

DD

Notes

9. Parameter applies to P1, P3, P5, P7, PWM1 to PWM6, SI and VCAL, and are guaranteed by design.

33800

Analog Integrated Circuit Device Data

Freescale Semiconductor

10

ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

Table 3. Static Electrical Characteristics

Characteristics noted under conditions 3.0V ≤ V_DD≤ 5.5V, 9.0V ≤ V_PWR≤ 18V, -40°C ≤ T_A≤ 125°C, GND = 0V, unless

otherwise noted. Typical values noted reflect the approximate parameter means at T_A= 25°C under nominal conditions, unless

otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

PREDRIVER OUTPUT FUNCTION (GD1 - GD6) (CONTINUED)

Drain Sense Fault Detection Current

Gate Drive Off, VDS = 18V

I

µA

DSNS(flt-sns)

40

50

180

55

400

60

Output Clamp Voltage

V

OC

Driver Command Off, V_GATE= 2.0V

Sleep Mode Drain Sense Leakage Current

I_DSNS(LKG)

µA

V

= 0.0V, V

= 24V,

DSNS

–

25

DD

Load Resistance Feedback Accuracy Sample and Hold After 150ms

R_EXT= 24ohm, R_LOAD= 10ohm, LR_FDBK= VCAL*2.5*(R_LOAD/R_EXT

LR_FBCKACC

-10%

2.6

+10%

)

Load Resistance Feedback Output Voltage

LR_FBCKMax

6.0

V

(V_DSNS1- V_DSNS2) ≥ 10V, PWM Diagnostics Select = 0001

33800

Analog Integrated Circuit Device Data

Freescale Semiconductor

11

ELECTRICAL CHARACTERISTICS

DYNAMIC ELECTRICAL CHARACTERISTICS

Table 4. Dynamic Electrical Characteristics

Characteristics noted under conditions 3.0V ≤ V_DD≤ 5.5V, 9.0V ≤ V_PWR≤ 18V, -40°C ≤ T_A≤ 125°C, GND = 0V, unless

otherwise noted. Typical values noted reflect the approximate parameter means at T_A= 25°C under nominal conditions, unless

otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

CONSTANT CURRENT SOLENOID DRIVER OUTPUT (CCD1_OUT)

On State Open Load Detect Timer⁽¹⁰⁾

ms

Fault is detected with driver on, timer expired

t_ONOPENTIMER

6.0

30

12

60

24

90

Off State Open Load Detect Timer⁽¹⁰⁾

µs

Fault detected with driver off & voltage threshold not achieved

(Driver off timer)

t_OFFOPENTIMER

On State Shorted Load Detect Timer⁽¹⁰⁾

t_ONSHORTTIMER

µs

Fault is detected with driver switching and drain voltage remains greater

than threshold for specified time.

30

10

60

14

90

24

Short Retry Time⁽¹⁰⁾

t_RETRY

ms

Output Slew Rate

V_BAT= 14V, Measured from 4.0V to 10.0V

V_BAT= 14V, Measured from 10.0V to 4.0V

t_SR(RISE)

t_SR(FALL)

2.0

3.0

4.0

V/µs

-2.0

-3.0

-4.0

Driver On Time Blanking Period⁽¹⁰⁾

t_BP(OFF)

t_BP(ON)

7.0

10

µs

Driver Off Time Blanking Period⁽¹⁰⁾

CONSTANT CURRENT SOLENOID DRIVER OUTPUT (CCD2_OUT)

On State Open Load Detect Timer⁽¹⁰⁾

ms

Fault is detected with driver on, timer expires (Driver on timer)

t_ONOPENTIMER

t_OFFOPENTIMER

6.0

30

12

60

24

90

Off State Open Load Detect Timer⁽¹⁰⁾

µs

Fault is detected with driver off and voltage threshold is not achieved.

(Driver off timer)

On State Shorted Load Detect Timer⁽¹⁰⁾

t_ONSHORTTIMER

µs

Fault is detected with driver switching and drain voltage remains greater

than threshold for specified time.

30

10

60

14

90

24

Short Retry Time⁽¹⁰⁾

t_RETRY

ms

Output Slew Rate

V/µs

V_BAT= 14V, Measured from 4.0V to 10.0V

V_BAT= 14V, Measured from 10.0V to 4.0V

t_SR(RISE)

t_SR(FALL)

1.5

–

4.0

-1.5

-4.0

CCD2 DAC Update Rate⁽¹⁰⁾

ms

Response time from present current level to new programmed level

t_RESPONSE

t_BP(ON)

1.0

Driver On Time Blanking Period⁽¹⁰⁾

Driver Off Time Blanking Period⁽¹⁰⁾

OCTAL SERIAL DRIVERS (OUT1 - OUT8)

Output On Current Limit Fault Filter Timer⁽¹⁰⁾

Output Refresh Timer⁽¹⁰⁾

3.0

12

4.3

µs

t_BP(OFF)

17.2

t

30

5.0

400

50

10

90

15

µs

ms

µs

CL

t

REF

Output On Short Circuit Fault Filter Timer⁽¹⁰⁾

t

500

650

SC

Notes

10. Assumes oscillator has been calibrated using SPI Calibrate Command.

33800

Analog Integrated Circuit Device Data

Freescale Semiconductor

12

ELECTRICAL CHARACTERISTICS

DYNAMIC ELECTRICAL CHARACTERISTICS

Table 4. Dynamic Electrical Characteristics

Characteristics noted under conditions 3.0V ≤ V_DD≤ 5.5V, 9.0V ≤ V_PWR≤ 18V, -40°C ≤ T_A≤ 125°C, GND = 0V, unless

otherwise noted. Typical values noted reflect the approximate parameter means at T_A= 25°C under nominal conditions, unless

otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

OCTAL SERIAL DRIVERS (OUT1 - OUT8) (CONTINUED)

Output Off Open Circuit Fault Filter Timer⁽¹¹⁾

Output Slew Rate

t_OC

400

500

650

µs

V/µs

R

= 51Ω

t_SR(RISE)

t_SR(FALL)

1.0

5.0

10

LOAD

R

P1 Input Propagation Delay

µs

Input @ 50% V_DDto Output voltage 10% of final value

Input @ 50% V_DDto Output voltage 90% of initial value

t_(RISEDELAY)

t_(FALLDELAY)

6.0

P3, P5, P7 Input Propagation Delay

Input @ 50% V_DDto Output voltage 10% of final value

Input @ 50% V_DDto Output voltage 90% of initial value

t_(RISEDELAY)

t_(FALLDELAY)

5.0

OSCILLATOR AND TIMER ACCURACY

Calibrated Timer Accuracy⁽¹¹⁾

t_TIMER

–

±10

±80

%

Un-calibrated Timer Accuracy

SPI DIGITAL INTERFACE TIMING (SO, SI, CS, SCLK)⁽¹²⁾

Required Low State Duration on V_PWRfor Reset⁽¹³⁾

t

µs

RESET

t_LEAD

t_LAG

V_PWR≤ 0.2V

1.0

–

Falling Edge of CS to Rising Edge of SCLK

Required Setup Time

ns

100

50

–

Falling Edge of SCLK to Rising Edge of CS

Required Setup Time

SI to Rising Edge of SCLK

Required Setup Time

t_SI(SU)

16

Rising Edge of SCLK to SI

Required Hold Time

t_SI(HOLD)

20

–

5.0

–

SI, CS, SCLK Signal Rise Time⁽¹⁴⁾

t_R(SI)

t_F(SI)

–

ns

µs

SI, CS, SCLK Signal Fall Time⁽¹⁴⁾

–

Time from Falling Edge of CS to SO Low-impedance⁽¹⁵⁾

Time from Rising Edge of CS to SO High-impedance⁽¹⁶⁾

Time from Falling Edge of SCLK to SO Data Valid⁽¹⁷⁾

t_SO(EN)

t_SO(DIS)

t_VALID

t_STR

–

150

1.0

–

25

Sequential Transfer Rate

Time required between data transfers

Notes

11. Assumes oscillator has been calibrated using SPI Calibrate Command

12. These parameters are guaranteed by design. Production test equipment uses 1MHz, 5.0V SPI interface.

13. This parameter is guaranteed by design, however it is not production tested.

14. Rise and Fall time of incoming SI, CS, and SCLK signals for design consideration to prevent the occurrence of double pulsing.

15. Time required for valid output status data to be available on SO pin.

16. Time required for output states data to be terminated at SO pin.

17. Time required to obtain valid data out from SO following the fall of SCLK with 200pF load.

33800

Analog Integrated Circuit Device Data

Freescale Semiconductor

13

ELECTRICAL CHARACTERISTICS

DYNAMIC ELECTRICAL CHARACTERISTICS

Table 4. Dynamic Electrical Characteristics

Characteristics noted under conditions 3.0V ≤ V_DD≤ 5.5V, 9.0V ≤ V_PWR≤ 18V, -40°C ≤ T_A≤ 125°C, GND = 0V, unless

otherwise noted. Typical values noted reflect the approximate parameter means at T_A= 25°C under nominal conditions, unless

otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

PREDRIVER OUTPUT FUNCTION (GD1 - GD6)

Open Fault Detection Filter Timer⁽¹⁸⁾

V_DS(FLTTH)

µs

V

= High, Outputs Programmed OFF

100

128

400

DD

Short Fault Detection Filter Timer⁽¹⁸⁾

= High, Outputs Programmed ON

t_DS(FLTTMR)

V

-10%

+10%

DD

Programmable from 30µs to 960µs in replicating increments.

Gate Drive Rise Slew Rate

t_GDSR(RISE)

t_GDSR(FALL)

t_PWMDELAY

t_LRSR(RISE)

V/µs

ns

Cload = 1.0nF, VGS from 0.5 to 5.0V

–

1.7

–

Gate Drive Fall Slew Rate

Cload = 1.0nF, VGS from 5.0 to 0.5V

–

PWM1 to PWM6 Input Propagation Delay

20

300

Measured from PWM input at 4.5V and GDx output at 0.5V.

Load Resistance Feedback Output Rise Slew Rate

C_LOAD= 40pF

0.5

–

2.0

V/µs

Load Resistance Feedback Output Fall Slew Rate

C_LOAD= 40pF

t_LRSR(FALL)

V/µs

Load Resistance Sample Duration⁽¹⁸⁾

t_LOADSAMPLE

t_FDBKVALID

200

400

µs

Load Resistance Feedback Valid ⁽¹⁸⁾

us

Time from rising edge of CS to Load Resistance measurement valid

Notes

18. Assumes oscillator has been calibrated using SPI Calibrate Command.

33800

Analog Integrated Circuit Device Data

Freescale Semiconductor

14

ELECTRICAL CHARACTERISTICS

TIMING DIAGRAMS

CS

0.2 V

DD

t

LAG

LEAD

0.7 V

0.2 V

DD

SCLK

SI

t

SI(SU)

SI(HOLD)

0.7 V

0.2 V

DD

MSB IN

t

SO(EN)

t

VALID

SO(DIS)

0.7 V

DD

LSB OUT

SO

MSB OUT

0.2 V

Figure 4. SPI Timing Characteristics

33800

Analog Integrated Circuit Device Data

Freescale Semiconductor

15

FUNCTIONAL DESCRIPTION

FUNCTIONAL PIN DESCRIPTION

FUNCTIONAL DESCRIPTION

FUNCTIONAL PIN DESCRIPTION

ANALOG VOLTAGE SUPPLY (VPWR)

SERIAL CLOCK INPUT (SCLK)

The system clock (SCLK) pin clocks the internal shift

register of the 33800. The SI data is latched into the input

shift register on the rising edge of SCLK signal. The SO pin

shifts status bits out on the falling edge of SCLK. The SO data

is available for the MCU to read on the rising edge of SCLK.

With CS in a logic high state, signals on the SCLK and SI pins

will be ignored and the SO pin is tri-state.

The VPWR pin is battery input to the 33800 IC. The VPWR

pin requires external reverse battery and transient protection.

Maximum input voltage on VPWR is 45V. All IC analog

current and internal logic current is provided from the VPWR

pin. With V_DDand EN applied to the IC, the application of

V_PWRwill perform a Power-ON Reset (POR).

CHIP SELECT (CS)

DIGITAL VOLTAGE SUPPLY (VDD)

The system MCU selects the 33800 to receive

communication using the chip select (CS) pin. With the CS in

a logic low state, command words may be sent to the 33800

via the serial input (SI) pin, and status information is received

by the MCU via the serial output (SO) pin. The falling edge of

CS enables the SO output and transfers status information

into the SO buffer.

The VDD input pin is used to determine communication

logic levels between the microprocessor and the 33800

device. Current from V_DDis used to drive SO output and pull-

up current for CS. V_DDmust be applied for Normal Mode

operation. Removing V_DDfrom the IC will place the device in

Sleep Mode. Power-ON Reset will be performed with the

application of V_DDsupply_.

Rising edge of the CS initiates the following operation:

1. Disables the SO driver (high-impedance)

GROUND (GND)

The GND pin provides a low current analog ground for the

IC. The VPWR and VDD supplies are both referenced to the

GND pin. GND pin should be used for decoupling both

supplies.

2. Activates the received command word, allowing the

33800 to activate/deactivate output drivers.

To avoid any spurious data, it is essential the high-to-low

and low-to-high transitions of the CS signal occur only when

SCLK is in a logic low state. Internal to the 33800 device is an

active pull-up to VDD on CS. In cases were voltage exists on

CS without the application of V_DD, no current will flow from

CS to the VDD pin.

CONSTANT CURRENT DRIVER GROUND

(CCDX_GND)

The Constant Current Driver Ground (CCDX_GND) pins

provide dedicated grounds for the Constant Current output

drivers. Both CCDX_GND1 and CCDX_GND2 grounds are

isolated from the other grounds of the IC.

SERIAL INPUT DATA (SI)

The SI pin is used for serial instruction data input. SI

information is latched into the input register on the rising edge

of SCLK. A logic high state present on SI will program a one

in the command word on the rising edge of the CS signal. To

program a complete word, 16-bits of information must be

entered into the device.

GROUND (PGND1 - 3, CCD1_GND, CCD2_GND)

There are three PGND pins associated with the OSS

drivers. OUT1 driver and OUT2 driver have dedicated

PGND1 & PGND2 pins. Drivers OUT3 through Driver OUT8

share one PGND3 pin. In general all ground pins must be

connected together and terminated to ground on the circuit

board.

SERIAL OUTPUT DATA (SO)

The SO pin is the output from the shift register. The SO pin

remains tri-stated until the CS pin transitions to a logic low

state. All normal operating drivers are reported as zero, all

faulted drivers are reported as one. The negative transition of

CS enables the SO driver.

SOURCE VOLTAGE SENSE (VSSNS123

VSSNS456)

,

The Source Sense Ground pins (VSSNS123, VSSNS456)

provide dedicated grounds for the hex MOSFET pre-drivers.

The pins are used by the IC to monitor the drain to source

voltage of the external MOSFET. This pin must be connected

to the source of the external MOSFET and system ground.

VSSNS123 and VSSNS456 ground pins are isolated from

other internal IC grounds.

The SI/SO shifting of the data follows a first-in-first-out

protocol, with both input and output words transferring the

most significant bit (MSB) first.

ENABLE (EN)

The ENABLE pin is an active high digital input pin used to

enable the device. With the EN pin low the device is in Sleep

Mode. With the EN pin high, the device is in Normal Mode

(V_DDand V_PWRapplied). Exit from Sleep Mode initiates a

33800

Analog Integrated Circuit Device Data

Freescale Semiconductor

16

FUNCTIONAL DESCRIPTION

FUNCTIONAL PIN DESCRIPTION

Power On Reset (POR). All internal registers will be placed in

the reset state. The device has an Internal 100 kΩ resistor

pull down on the ENABLE pin.

operate. For applications where measurements are not

critical, the VCAL pin may grounded and an internally

generated reference will be used. Using the internally

^{generated reference will add}±10% to all tolerances in the

parametric table.

PULSE WIDTH MODULATION (PWM)

The PWM pins are control input pins for the MOSFET pre-

drivers. The PWM pins provide parallel control and can be

programmed for an OR function with the SPI bit or an AND

function with the SPI bit (See Table 12, on page 25 for SPI

message detail). Each PWM input pin has an internal 15µA

pull down current source. The current sources are active

when the device is in Normal Mode.

LOAD RESISTANCE FEEDBACK (LRFDBK)

The LRFDBK pin is an operational amplifier output. The

amplifier output voltage is proportional to the load resistance

for the selected channel. The channel is selected via the SPI.

DEFAULT

The DEFAULT input controls the operation of each driver

to a Default Mode. The DEFAULT input must be logic 0 for full

function of all output drivers. For more information on the

DEFAULT operation (See Functional Device Operation on

page 19).

DRAIN VOLTAGE SENSE (VDSNSX)

The VDSNSx pin has multiple functions for control and

diagnostics of the external MOSFET:

1. By monitoring the drain voltage of the external device,

short circuits and open circuits are detected. The filter

timer and threshold voltage are easily programmed

through SPI (see Table 10, on page 23 and Table 11,

on page 24 for SPI messages).

With the DEFAULT pin HIGH, the device is placed in

Default Mode. The DEFAULT pin is pulled up to the VDD

supply through an active pull up current source. In Default

Mode the device operates in the following manner:

1. OSS outputs are disabled.

2. The VDSNSx pins are use to determine the external

load resistance. Further information is provided in the

Device Operation section of this specification.

2. CCD1 and CCD2 outputs are disabled.

3. SPI ON/OFF control of GATE DRIVE (GD1 to GD6)

outputs and on board PWM controllers are disabled. PWMx

input control is enabled.

3. The VDSNSx pins provide a drain to gate clamp for

fast turn off of inductive loads and MOSFET protection.

In the Default Mode the device retains all register

GATE DRIVER OUTPUTS (GDX)

information and output status information. Normal operation

will resume when the DEFAULT pin transitions low again and

the device will operate as programmed prior to Default Mode.

The GDX pins are the gate drive outputs for an external

MOSFETS. Internal to the device is a Gate to Source resistor

designed to hold the external MOSFET in the OFF state while

the device is in POR.

RESISTOR EXTERNAL REFERENCE (REXT)

The reference current is used in the equation to calculate

the load resistance of the PWM outputs. The load resistance

measurement current is inversely proportional to REXT

current. The resistor value may be changed to adjust the load

measurement current. A 24Ω resistor to ground sets the

LRFDBK output to 260mV/Ω.

INPUTS (P1, P3, P5, P7)

The input pins for octal serial switch outputs 1,3,5,7. Each

input control pin has an internal pull down current source.

Two outputs may be controlled in parallel using the PX pins

(See Functional Device Operation on page 25).

EXPOSED PAD

VOLTAGE CALIBRATED INPUT (VCAL)

The silicon die is epoxy attached to the top side of the pad.

Although the device does not use the pad for electrical

conduction, the bottom side exposed pad of the package

should be grounded.

The Voltage calibrated input (VCAL) provides the IC with

a reference voltage for analog circuits. VCAL (EXT or INT)

must be applied for the CCD1 and CCD2 constant current

controllers and Load Resistance measurement function to

33800

Analog Integrated Circuit Device Data

Freescale Semiconductor

17

FUNCTIONAL DESCRIPTION

FUNCTIONAL INTERNAL BLOCK DESCRIPTION

Figure 5. Functional Block Diagram

current limits to accommodate lamp inrush current. The

ANALOG CONTROL CIRCUITRY

device allows for parallel control of the outputs or SPI control

through the use of several input command words.

The 33800 is designed to operate from 5.0 to 36V on the

VPWR pin. The VPWR pin supplies power to all internal

regulators, analog and logic circuit blocks. The VDD supply is

used for setting communication threshold levels and

supplying power to the SO driver. This IC architecture

provides low quiescent current Sleep Modes. Applying

VPWR to the device will cause a Power On Reset (POR). The

on-chip oscillator supports the selectable PWM frequency

and duty cycle. The on-chip voltage regulator and bandgap

supply the required voltages to the internal circuitry.

CONSTANT CURRENT LOW SIDE DRIVERS: CCD1

AND CCD2

The CCD1/CCD2 constant current controllers are

switching hysteretic current controllers with a superimposed

dither. The controllers are designed to provide a

programmable constant current through a solenoid valve.

Fluid flow is controlled by the amount of current run through

the driven solenoid valve.

MCU INTERFACE AND OUTPUT CONTROL

GATE PRE-DRIVERS: GD1 – GD6

The device is designed with six flexible PWM gate driver

outputs. Each driver may be controlled directly from the MCU

and may be programmed through the SPI for a specific

frequency and duty cycle.

The GD1 – GD6 pins are the gate drive outputs for external

MOSFETS. They can be PWM’ed with speed and duty cycle

choices per the SPI command registers. Internal to the device

is a Gate to Source resistor designed to hold the external

MOSFET in the OFF state while the device is in POR.

LOW–SIDE DRIVERS: OUT1 – OUT8

The 33800 provides flexible control of 8 low side driver

outputs. Outputs 1 and 2 are specifically designed with higher

33800

Analog Integrated Circuit Device Data

Freescale Semiconductor

18

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

POWER SUPPLY

NORMAL MODE

The 33800 is designed to operate from 5.0 to 36V on the

VPWR pin. The VPWR pin supplies power to all internal

regulators, analog and logic circuit blocks. The V_DDsupply is

used for setting communication threshold levels and

supplying power to the SO driver. This IC architecture

provides flexible microprocessor interfacing with low

quiescent current Sleep Modes.

Normal Mode allows full functional control of the device.

Transferring from Sleep Mode to Normal Mode performs a

POR and resets all internal registers to the POR state. When

entering Normal Mode from Default Mode, no POR is

performed and register states are maintained.

Features programmed in Normal Mode are listed below.

Further explanation of each feature is provided in subsequent

paragraphs.

POWER-ON RESET (POR)

• Programmable PWM Frequency & Duty Cycle

• Programmable PWM Drain Fault Threshold

• CCD2 Constant Current Dither Frequency and Amplitude

• CCD2 DAC Programming

Applying V_PWR, V_DDand EN to the device will cause a

Power On Reset (POR) and place the device in Normal or

Default Mode.

• CCD1 Constant Current Dither Frequency and Amplitude

• CCD1 DAC Programming

Table 5. Modes of Operation

• On/Off OSS Open Load Detect Current

• Calibration of Timers (Calibration Command)

• Reset (Reset Command)

V_PWR

V_DD

ENable

DEFAULT

MODE

L

X

Power

Off

• No Operation (NO_OP Command)

H

L

H

X

L

X

L

SLEEP

DEFAULT MODE

The Default Mode allows the user to disable all outputs

except the PWM pre-driver. In Default Mode the PWM pre-

driver outputs may only be controlled via the PWM input pins.

All register control bits and fault bits are maintained in Default

Mode, however control for the pre-driver is accomplished

through the PWM pins only.

H

NORMAL

DEFAULT

H

Command register settings from Power-ON Reset (POR)

via V_PWRor V_DDare as follows:

With the DEFAULT pin HIGH, the device is placed in

Default Mode. When exiting Default Mode, output control

reverts to the internal register settings.

• All Outputs Off

• Inputs Enabled and OR’d with SPI Bit.

• PWM Frequency and Duty Cycle Control Disabled.

• OSS Open Load Detect Current Enabled.

• OSS Outputs with Individual Control.

• Control Inputs P1,P3,P5,P7 Enabled and OR’d with the

SPI Bit.

In Default Mode the device operates with the following

parameters.

1. OSS outputs are disabled.

2. CCD1 and CCD2 outputs are disabled.

• CCD1 Output Off, Diagnostic Pull-up Enabled, DAC = 0.

• CCD2 Output Off, Diagnostic Pull-up Enabled, DAC = 0.

3. SPI ON/OFF control of GATE DRIVE (GD1 to GD6)

outputs is disabled. PWMx input control is enabled. The

device will operate as programmed prior to Default Mode.

Power On Reset circuit incorporates a 0.5µs timer to

prevent high frequency transients from causing a POR.

During the low-voltage condition, internal logic states are

maintained. To guarantee a POR from V_PWR, the VPWR pin

must be less than 0.2V for greater than 1.0µs.

In Default Mode the device retains all register information

and output status information. Normal operation will resume

when the DEFAULT pin transitions low again.

SLEEP MODE

MODES OF OPERATION

Sleep Mode is entered by placing a logic [0] on the

ENABLE or VDD pins. All outputs are commanded off and the

device enters a low quiescent current state.

The 33800 has three operating modes, Normal, Sleep and

Default Mode. A discussion on Normal Mode follows.

33800

Analog Integrated Circuit Device Data

Freescale Semiconductor

19

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

the serial configuration, 32-clock cycles are required to

transfer data in/out of the ICs.

SPI AND MCU INTERFACE DESCRIPTION

The 33800 device directly interfaces to a 3.3 or 5.0V

microcontroller unit (MCU) using 16 bit Serial Peripheral

Interface (SPI) protocol. SPI serial clock frequencies up to

4.0MHz may be used when programming and reading output

status information (production tested at 1MHz). Figure 6

illustrates the serial peripheral interface (SPI) configuration

between an MCU and one 33800.

Microcontroller

33800

MOSI

SI

Shift Register

MISO

SO

SCLK

Command data is sent to the 33800 device through the SI

input pin. As data is being clocked into the SI pin, status

information is being clocked out of the device by the SO

output pin. The response data received by the MCU during

SPI communication depends on the previous SPI message

sent to the device. The next SO response data is listed at the

bottom of each command table ( Table 7, on page 22, Table

12, on page 25, Table 22, on page 30 Table 23, on page 31,

Table 26, on page 34.

SCLK

CS

Parallel

Ports

33800

SI

SO

SCLK

CS

SPI Integrity Check

Checking the integrity of the SPI communication with the

initial power-up of the VDD and EN pins is recommended.

After initial system start-up or reset, the MCU will write one

32-bit pattern to the 33800. The first 16-bits read by the MCU

will be the fault status (SO message 1) of the outputs. The

second 16-bits will be the same bit pattern sent by the MCU.

By the MCU receiving the same bit pattern it sent, bus

integrity is confirmed. The second 16-bit pattern the MCU

sends to the device is the a command word and will be

operated on by the device accordingly on rising edge of CS.

Figure 7. SPI Parallel Interface with Microprocessor

Microcontroller

33800

MOSI

SI

Important A SCLK pulse count strategy has been

implemented to ensure integrity of SPI communications. SPI

messages consisting of 16 SCLK pulses and multiples of 8

clock pulses thereafter will be acknowledged. SPI messages

consisting of other than 16 + multiples of 8 SCLK pulses will

be ignored by the device.

Shift Register

MISO

SO

SCLK

Parallel

Ports

CS

33800

Microcontroller

MOSI

MISO

SI

Shift Register

16-Bit Shift Register

SO

SCLK

CS

SCLK

Receive

Buffer

To Logic

CS

Parallel

Ports

Figure 8. SPI Serial Interface with Microprocessor

PROGRAMMABLE PWM GATE DRIVER OUTPUTS

The 33800 device is designed with six flexible PWM gate

driver outputs. Each driver may be controlled directly from the

MCU or may be programmed through the SPI for a specific

frequency and duty cycle.

Figure 6. SPI Interface with Microprocessor

Two or more 33800 devices may be used in a module

system. Multiple ICs may be SPI-configured in parallel or

serial. Figures 7 and 8 show the configurations. When using

The pre-drivers are designed with four diagnostic features:

33800

Analog Integrated Circuit Device Data

Freescale Semiconductor

20

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

• Off State Open Load Detect

• On State Short Circuit Detect

• Programmable Drain Threshold and Timer for Short Fault

Detection

Table 6. Load Resistance Measurement Select

Bits 9876

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

MUX Select

Normal Operation

• Load Resistance Measurement

Each pre-driver is capable of detecting an open load in the

off state and shorted load in the on state. All faults are

reported through SPI communication. For open load

detection, a resistor is placed between the drain sense pin

and source sense pin of the IC. An open load fault is reported

when the drain voltage is less than the 2.5V threshold. A

shorted load fault is reported when the drain voltage is

greater than the programmed threshold voltage.

V_DSNS1to R_EXT, V_DSNS2to Diff-Amp +

V_DSNS2to R_EXT, V_DSNS1to Diff-Amp +

V_DSNS3to R_EXT, V_DSNS4to Diff-Amp +

V_DSNS4to R_EXT, V_DSNS3to Diff-Amp +

V_DSNS5to R_EXT, V_DSNS6to Diff-Amp +

V_DSNS6to R_EXT, V_DSNS5to Diff-Amp +

Normal Operation

Programming of the drain short fault threshold voltage is

done through SPI commands provided in Table 7.

Bits 6 through 9 are used to perform the load resistance

measurement function as described in the Gate Drive On/Off

Command section below.

Normal Operation

GATE DRIVE ON/OFF COMMAND

V_DSNS2to R_EXT, V_DSNS1to Diff-Amp +

V_DSNS3to R_EXT, V_DSNS1to Diff-Amp +

V_DSNS4to R_EXT, V_DSNS1to Diff-Amp +

V_DSNS5to R_EXT, V_DSNS1to Diff-Amp +

V_DSNS6to R_EXT, V_DSNS1to Diff-Amp +

Normal Operation

The GD ON/OFF Command provides control bits for two

functions:

• On/Off control of the GDx outputs.

• Load Resistance measurement function.

On/Off control bit 0 through bit 5 control gate drive outputs

GD1 through GD6 respectively. Setting the bit to logic1 will

enable the gate drive to the external MOSFET. Setting the bit

to logic 0 will actively pull the gate to ground.

GD ON/OFF Command bits 6 through 9 control the load

measurement feature. The gate drive pre-drivers are

selected in matched pairs. Selecting a load resistance

measurement disables a specified output pair and performs

the resistance measurement using the defined pair. All other

outputs will operate as programmed. Resistance is measured

by passing a known current through the load and by

measuring the voltage across it. The resistor placed on the

REXT pin determines the current through the load during

measurement. The voltage output on the LRFDBK pin is the

differential load voltage with the defined current through it.

From the two parameters, the load resistance may be

calculated. Table 6 illustrates the load diagnostic multiplex

function.

PWM PIN ENABLE COMMAND

The PWM Pin Enable Command provides control bits for

two functions:

• Enable or Disable of PWM input pins.

• Enable or Disable of the internal PWM controller for GD1

through GD6.

PWM pin Enable bit 0 through bit 5 enable or disable the

PWM1 through PWM6 input pins respectively. A logic 0 in the

SPI word will enable the PWM input pin, while logic 1 in the

SPI word will disable the PWM input pin. Default state is with

the PWM input pin enabled. With the PWM input pin disabled,

the AND/OR function is also disabled and control is achieved

through the Gate Drive ON/OFF command or the internal

PWM controller.

AND/OR COMMAND

The AND/OR Command provides control bits for two

functions:

• Determines AND/OR relation between ON/OFF SPI bit

and PWM input pin.

• Enable or Disable of the internal PWM controller for G1

through GD6.

The AND/OR command describes the condition by which

the PWM input pin controls the output driver. A logic[0] in the

AND/OR register will OR the PWM input pin with the

respective bit in the ON/OFF register. Likewise, a logic[1] in

33800

Analog Integrated Circuit Device Data

Freescale Semiconductor

21

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

the AND/OR register will AND the PWM input pin with the

respective bit in the ON/OFF register. The AND/OR function

is disabled when the PWM input pin is disabled.

Table 7. PWM Command

PWM Commands

Control Address

Command Bits

15

0

14

13

12

11

1

10

X

9

8

7

6

5

4

3

2

1

0

R_ldLoad Resistance

Measurement Select

Gate Drive ON/OFF Bit

GDX ON/OFF Command

0 = Off, 1 = On

1

0

PWM Controller

Enable Bit

PWM Pin Enable Bit

PWM Pin Enable Command

0 = PWMX Pin Enabled

1 = PWMX Pin Disabled

0

1

0

1

0

1

X

0

PWM3 PWM2 PWM1

AND/OR Command

0

0 = PWMX Pin OR with SPI

1 = PWMX Pin AND with SPI

PWM6 PWM5 PWM4

Command

PWM1 Freq & DC

PWM2 Freq & DC

PWM3 Freq & DC

PWM4 Freq & DC

PWM5 Freq & DC

PWM6 Freq & DC

Control Address

Frequency Select

Duty Cycle Select

0

1

0

1

0

1

0

1

0

1

0

1

X

0

Control Address

V _DSNS3

V_DSNS2

V_DSNS1

VDSNS123 Short Threshold

VDSNS123 Short Timer

1

0

1

0

1

X

0

1

0

1

0

1

Control Address

V_DSNS6

V_DSNS5

V_DSNS4

VDSNS456 Short Threshold

VDSNS456 Short Timer

1

0

1

0

1

X

0

1

0

1

0

1

Next SO Response (Message 1)

0 = No Fault, 1 = Fault

OvrVlt Reset Fault Fault Fault Fault Fault Fault Fault Fault Fault Fault Fault Fault Fault Fault

,TLim

or

Statu Statu Statu Statu Statu Statu Statu Statu Statu Statu Statu Statu Statu Statu

sPW sPW sPW sPW sPW sPW sOUT sOUT sOUT sOUT sOUT sOUT sOUT sOUT

CAL

Flt

M6

M5

M4

M3

M2

M1

8

7

6

5

4

3

2

1

33800

Analog Integrated Circuit Device Data

Freescale Semiconductor

22

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

Table 8. And/Or/SPI/Parallel Control

Table 9 defines the output frequency with the selected

input bits.

Table 9. Frequency Select

PWM Pin AND/OR

PWM

Freq/

DC EN

Bit

ON/

OFF

Bit

R_load

EN

Bit

PWM

Output

0 = en 0 = OR

1 = dis 1 = AND

Measure

Frequency Select

Bits

987

Frequency Hz

≠ 0

X

Rload

Measure

000

001

010

011

100

101

110

111

10 Hz

20 Hz

0

1

0

X

0

1

0

X

1

0

1

X

0

OFF

Freq/DC

ON

40 Hz

X

0

80 Hz

OFF

160 Hz

320 Hz

640 Hz

1.28 kHz

1

0

Freq/DC

ON

X

1

X

ON

Notes: Tolerance on selected frequency is +-10% with part

calibrated. On state short faults may not be detected if t_on_short >

1/f_pwm * duty_cycle * 0.98.Off state open faults may not be

detected if t_off_open > 1/fpwm * (1-duty_cycle) * 0.75.

0

1

0

X

0

X

1

0

1

X

0

X

0

1

OFF

Freq/DC

ON

VDSNSX SHORT THRESHOLD COMMAND

The short fault threshold voltage of the external MOSFET

may be programmed via SPI. Table 10 illustrates the bit

pattern required for a particular short fault threshold. Open

load fault detect threshold is set internally to 2.5V and may

not be programmed.

PWM FREQUENCY/DUTY CYCLE COMMAND

Table 10. VDSNSx Fault Threshold Select

The PWM Frequency/Duty Cycle Command allows the

user to individually program a PWM output with a frequency

and duty cycle. Once the PWM Freq/DC registers are

programmed, the PWM output GD1, GD2, GD3 are

controlled via the AND/OR command and GD4, GD5, GD6

are controlled via the PWM pin Enable Command. Pre-driver

output control bits supersede the internal PWM controller.

GDx outputs must be commanded OFF for the controller to

function. (SeeTable 8)

PWM V_DSFLT

Bits

VDSNSx Fault Threshold Select

210

543

876

000

001

010

011

100

101

110

111

0.5V

1.0V

The duty cycle of the PWM outputs is controlled by bits 0

through 6, inclusive. The duty cycle value is 1% per binary

count from 1 to 100 with counts of 101 through 127 defaulting

to 100%. For example:

1.5V

2.0

2.5V

Sending SPI WORD; 01100x1110001100

This would set PWM1 output to 1.28Khz frequency with a

12% duty cycle.

3.0V

No Change

VDSNSX SHORT FAULT TIMER COMMAND

The Short Fault Timer can be programmed via the SPI to

the values listed in Table 11, on page 24. When the 33800

detects an over-current condition, as defined by V_DS

exceeding the programmed short fault voltage threshold, the

33800

Analog Integrated Circuit Device Data

Freescale Semiconductor

23

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

33800 will wait for the Short Fault Time period and then shut

down the output drive, setting the fault status bit to a 1 in the

Serial Output Response Register.

Table 11. PWM Short Fault Timer

Predriver 1

VDSNS1

PWM FLT Timer

Bits

V

PWR

210

543

876

Fault Timer Select

Gate Drive

Control &

Diagnostics

GD1

000

001

010

011

100

101

110

111

30µs

60µs

VSSNS123

Predriver 2

120µs

VDSNS2

V

PWR

240µs

Gate Drive

Control &

Diagnostics

GD2

480µs

960µs

VSSNS123

No Change

Differential

Amplifier

+

−

+

−

Notes: Tolerance on fault timer setting is ±10% with calibrated part.

LRFDBK

Example: Load Measurement Operation

To perform an accurate load resistance measurement the

33800 device uses an alternate channel to determine a

differential load voltage and forces a known load current.

With the differential load voltage and the forced current the

load resistance is calculated. As shown in Table 6, channel 2

is used as the battery reference for the load measurement of

channel 1. The current through the channel 1 load is set by

the external resistor. Setting the resistance to 25Ω forces a

current of 100mA. The measurement is sampled within

200µs and is held for 150ms on the Load Resistance

Feedback (L_RFDBK) output. The differential amplifier has a

fixed gain of 2.5V. Hence for this example, a 10Ω load will

produce a 2.5V output. When a second pair is selected for

measurement, the sample and hold is reset and the

measurement is immediately directed to the new load

measurement. The previous pair immediately revert back to

normal operation.

+

−

VCAL

REXT

Figure 9. Example of Channel 1 Measurement

OCTAL OUTPUT DRIVER (OCTAL SERIAL

SWITCH; OSS)

The 33800 provides flexible control of 8 low side driver

outputs. Outputs 1 and 2 are specifically designed with higher

current limit to accommodate lamp inrush current. The device

allows for parallel control and/or SPI control through the use

of several input command words. This section describes the

logic operation and commands for the octal driver.

The 33800 Octal Output Driver message set consists of

eight commands, and one response as shown in Table 12.

Bits 11 through 15 determine the specific command and bits

0 through 10 determine how a specific output will operate.

The 33800 operates on the command word on the rising edge

of CS. The Most Significant Bit (MSB) is sent and received

first.

Note Upon Power-ON Reset all OSS bits are defined as

shown in Table 12.

33800

Analog Integrated Circuit Device Data

Freescale Semiconductor

24

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

Table 12. OSS SPI Control Commands and Response

Command

Control Address

Command Bits

15

0

14

0

13

0

12

0

11

1

10

X

9

8

7

0

6

0

5

0

4

0

3

0

2

0

1

0

OSS ON/OFF Command

0 = off, 1 = on

X

Open Load Current Enable

0 = disable, 1 = enable

0

1

0

1

X

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Shutdown/Retry from V_PWROver

Voltage

0 = shutdown, 1 = retry

Shutdown/Retry from Short

Circuit

0

1

0

X

1

0 = shutdown, 1 = retry

TLim Command

0 = disable, 1 = enable

0

1

0

1

0

X

1

Fault Timer Command

0 = Fault Timer Disabled

1 = Fault Timer Enabled

Parallel

0

1

0

1

0

1

0

X

0

Outputs(7&8,5&6,3&4,1&2)

Parallel Input Pin Enable

0 = Individual Control, PX enabled

1 = Parallel Control, PX disabled

Output Output Output Output P7 en P5 en P3 en P1 en

7&8

5&6

3&4

1&2

AND/OR Control

0

0 = PX Pin OR with SPI

1 = PX Pin AND with SPI

Next SO Response (Message 1)

0 = No Fault, 1 = Fault

OvrVlt Reset Fault Fault Fault Fault Fault Fault Fault Fault Fault Fault Fault Fault Fault Fault

,TLim

or

Statu Statu Statu Statu Statu Statu Statu Statu Statu Statu Statu Statu Statu Statu

sPW sPW sPW sPW sPW sPW sOUT sOUT sOUT sOUT sOUT sOUT sOUT sOUT

CAL

Flt

M6

M5

M4

M3

M2

M1

8

7

6

5

4

3

2

1

faults may not be reported with the pull-down current source

disabled.

ON/OFF CONTROL COMMAND

To program the 8 outputs of the 33800 ON or OFF, a 16-

bit serial stream of data is entered into the SI pin. The first 8-

bits of the control word are used to identify the on/off

command and the remaining 8-bits are used to turn ON or

OFF the specific output driver. When commanding an output

ON or OFF, the Most Significant Bit (MSB) is sent and

received first. Bit 7 corresponds to output 8 down to bit 0

which corresponds to output 1.

OVER-VOLTAGE SHUTDOWN/RETRY COMMAND

The Over Voltage Shutdown/Retry Command allows the

user to select the fault strategy for the outputs. The over-

voltage control bit sets the operation of the outputs when

returning from over-voltage. Setting the over-voltage bit to

logic[0] will force all outputs to remain OFF when V_PWR

returns to normal level. Setting the over-voltage bit to logic[1]

will command outputs to resume their previous state when

V_PWRreturns to normal level.

OPEN LOAD CURRENT ENABLE COMMAND

The Open Load Enable Command is provided to enable or

disable the open load detect pull-down current. This feature

allows the device to be used in LED applications. On power

up reset (POR) or the RESET command the pull-down

current sources are disabled. To enable the open load

current source, the user must program the Open Load

Current Disable Control register with logic[1]. Open load

TLIM COMMAND, TIMER COMMAND

The TLim and Timer commands are used to enhance the

short circuit protection strategy of the Octal Serial Switch

output drivers.

The Timer protection scheme uses a low duty cycle in the

event of a short circuit. The TLim protection circuit uses the

33800

Analog Integrated Circuit Device Data

Freescale Semiconductor

25

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

temperature of the output driver to determine the fault. Both

methods may be selected or used individually. The following

table provides an explanation of operation during fault

condition.

PARALLEL OUTPUT, PX PIN ENABLE COMMAND

The Parallel Output command allows the user to parallel

output for increased current capability and enables control of

the PX input pin.

The low duty cycle used for the timer protection scheme is

set by the fault timer used to detect the short circuit. For short

circuits detected based on the output voltage exceeding the

fault detection voltage threshold, the outputs will be turned off

for the duration of the refresh timer (typically 10ms) and

turned on for the duration of the on-state short circuit fault

timer (typically 500µs). For short circuits detected based on

the output current exceeding the output current limit, the

outputs will be turned off for the duration of the refresh timer

(typically 10 ms) and turned on for the duration of the current

limit fault timer (typically 50µs).

A logic 0 in the Parallel Output Command provides

individual control. Logic 1 commands outputs to operate in

parallel. For example, with bit 4 in the Parallel Output

command a logic 1, outputs 1 & 2 are controlled together

With the outputs paralleled, and the P1 pin enabled, a logic

1 on SPI bit 0 or SPI bit 1 will command both outputs on.

Similarly a logic 1 on the P1 pin will command both outputs

on.

PX pin Enable bit 0 through bit 3 enables or disables the

P1, P3, P5, P7 pins respectively. A logic 0 in the SPI word will

enable the PX input pin, while logic 1 in the SPI word will

disable the PX input pin. Default state is with the PX input

pins enabled.

For off-state open load faults with retry timer enabled, the

off-open fault is released and re-detected every 1-2 retry

timer periods. Retry timer for 1-2, 3-4, 5-6, and 7-8 are out of

phase and may report a load present, if the OSS read

command CS is issued after the release, and before the re-

detection (~500µs) of the off-state open load fault.

When paralleling output 1 & 2 the current limit is

maintained at 4.0 to 6.0A. Parallel current limit for drivers

3&4, 5&6, 7&8 is increased to a range of 2.0 to 4.0A.

Using a MOSFET as output switches allows the

connection of paired outputs. The R_DS(ON)of MOSFET

devices have inherent positive temperature coefficient

providing balanced current sharing between outputs without

destructive operation. This mode of operation may be

desirable in the event the application requires lower power

dissipation or the added capability of switching higher

currents. Performance of parallel operation results in a

corresponding decrease in R_DS(ON), while the Output Current

Limit increases correspondingly. Output OFF Open Load

Detect current may increase based on how the Output OFF

Open Load Detect is programmed.

Table 13. TLim/Timer Control

Fault

Timer

Bit

Shutdn

Retry Bit

TLIM

Bit

Operation During Short Fault

Timer only, Outputs will retry on

period

1

0

X

OUT1-8 = ~500us for short

circuit faults, and 50us for current

limit faults ON, ~10ms OFF.

TLim only, Outputs will retry on

TLim hysteresis.

1

0

1

Table 14. And/Or/SPI/Parallel Control

Timer and TLim, Outputs will

retry on period and driver

temperature below threshold.

Parallel PX Pin

AND/

OR Bit Bit 1

SPI

Bit 0

Output

1&2

PX Pin

En Bit

OUT1-8 = ~500us ON, ~10ms

OFF

1

0

1

X

0

X

1

X

0

1

0

1

X

0

1

0

1

0

1

0

1

0

1

X

0

1

0

1

OFF

ON

X

Timer only, Outputs will not retry

on period

0

X

ON

OUT1-8 = ~500us ON, OFF

X

ON

TLim only, Outputs will not retry

on TLim hysteresis.

0

1

0

1

1(or)

0(and)

OFF

ON

Timer and TLim, Outputs will not

retry on period or TLim.

ON

OUT1-8 = ~500us ON, OFF

ON

All OSS outputs have a current limit control loop. Current

limit is always active in Normal Mode. Current limit for OUT1

and OUT2 is 4.0 to 6.0A. Current limit for OUT3 through

OUT8 is 1.0 to 2.0A.

OFF

ON

33800

Analog Integrated Circuit Device Data

Freescale Semiconductor

26

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

produce a threshold level. The comparator drives a switch

control circuit which generates a frequency modulated signal

for the output drive. The differential voltage across the sense

resistor provides the feedback necessary to maintain the

desired output current. The output current is continuously

monitored as a differential voltage across the internal sense

resistor. When the current is in recirculation and the driver is

in the off state, the current will decay to the lower limit switch

point. When the current reaches the lower limit, the driver will

turn on to increase the current until the upper limit switch

point is reached. The output current will continue to switch

between the switch points, resulting in the desired average

current. The switch points are set to a fixed ±5% of the

commanded current. The switching frequency and accuracy

are dependent upon the load inductance and resistance,

battery voltage, dither amplitude and frequency, switch points

and the commanded current.

AND/OR COMMAND

The AND/OR Command provides control bits for the

following function:

• Determines AND/OR relation between ON/OFF SPI bit

and PX input pin.

The AND/OR command describes the condition by which

the PX input pin controls the output driver. A logic[0] in the

AND/OR register will OR the PX input pin with the respective

bit in the ON/OFF register. Likewise, a logic[1] in the AND/

OR register will AND the PX input pin with the respective bit

in the ON/OFF register. The AND/OR function is disabled

when the PX input pin is disabled.

SERIAL OUTPUT (SO) RESPONSE REGISTER

Fault reporting is accomplished through the SPI interface.

All logic[1]s received by the MCU via the SO pin indicate fault.

All logic[0]s received by the MCU via the SO pin indicate no

fault. All fault bits are cleared on the positive edge of CS. SO

bits 15 to 0 represent the fault status of outputs 15 to 0. The

timing between two write words must be greater than 450µs

to allow adequate time to sense and report the proper fault

status.

Current dither is a method by which the average current is

increased and decreased through the solenoid valve. The

33800 allows the user to program the frequency and

amplitude of the dither control. Dither amplitude is

implemented by increasing and decreasing the DAC by the

programmed dither value. The rate at which the value

changes is set by the programmed dither frequency. When

reprogramming the dither amplitude or dither frequency, the

update will occur on the start of a positive cycle.

CCD1 CONSTANT CURRENT CONTROLLER

The CCD1 constant current controller is a switching

hysteretic current controller with a superimposed dither. The

controller is designed to provide a programmable constant

current through a solenoid valve. Fluid flow is controlled by

the amount of current run through the solenoid valve.

The maximum value of the output (DAC + Dither) must be

less than 1075mA. When a greater value is programmed the

device will disable the dither on the output. Similarly, the

minimum value of the output (DAC - Dither) must be greater

than 0.0mA. Requesting a lower value will disable the dither

on the output.

The master SPI device sends 16 bit command words to

the 33800 device (see Table 15). The master device sets up

the output current based on the CCD1 Control command.

The IC is capable of sinking an average output current from

0mA to 1075mA (without dither). If operating the device with

dither, the DAC + Dither value must be less than 1075mA or

greater than 0.0mA. Commands outside of this command

range will automatically lock out dither.

ON/OFF CONTROL BIT

The CCD1 output may be used as a standard 1.0A low

side driver. For on/off control, the CCD1_DIS bit int the

CCD1Frequency & Amplitude command must be set to logic

1. This disables the constant current driver and enables the

on/off control. To turn the driver ON a logic 1 is placed in the

ON/OFF control bit. A logic 0 placed in the ON/OFF control

bit will turn the driver OFF.

Programming the solenoid current begins by sending the

CCD1 Control command. The command consists of an

control address, Diagnostic Pull Up Enable bit

(Diag_pu_EN), Dither Disable bit (DTHR_DIS), and a 9-bits

of data for digital to analog conversion (DAC). The data is

received and the DAC provides bias for a comparator to

The protection scheme in low side driver mode operates

the same as constant current mode.

33800

Analog Integrated Circuit Device Data

Freescale Semiconductor

27

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

Table 15. CCD1 Constant Current Controller Commands

Command

Control Address

Command Bits

15

1

14

13

12

11

0

10

9

8

0

7

0

6

5

4

3

2

0

1

0

CCD1 Command Address

Diag DTHR

Pull Up DIS

9 BIT DAC Command Data

CCD1 Control

0 = Pull Down

Current Source

1 = Pull Up Current

Source

0

1

0

CCD1 Command Address

CCD1 ON/ CCD1 TLim

Dither Amplitude

Dither Frequency

Retry OFF

DIS

EN

CCD1 Frequency

& Amplitude

1

0

1

0

1

0

1

0

1

0

NextSOResponse

(Message 2)

0 = No Fault, 1 =

Fault

OvrVlt Reset Trim VCAL Open Short Open Short Fault Fault Fault Fault Fault Fault Fault Fault

TLimor

CAL Flt

Set⁽¹⁹⁾Status Fault Fault Fault Fault Status Status Status Status Status Status Status Status

int=0 CCD2 CCD2 CCD1 CCD1 OUT8 OUT7 OUT6 OUT5 OUT4 OUT3 OUT2 OUT1

ext=1

Notes

19. Trim Set bit indicates (0=untrimmed, 1= trimmed)

20. VCAL Status bit indicates when internal or external supply is used. VCAL Bit = 0 indicates external, VCAL Bit = 1indicates internal.

21. Reset Bit indicates the device has performed a POR.

22. CCD1 DISable bit allows the CCD1 driver to operate as a standard 1.0A low side driver. With CCD1_DIS bit = 1 the CCD1 function is

disabled.

Table 16. CCD1 Dither Frequency Select

Table 17. CCD1 Dither Amplitude Select

Bits 3210

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

Dither Frequency

Dither Off

50Hz

Bits 654

000

Dither Amplitude

Dither Off

50.4mA

001

100Hz

010

100.8mA

150Hz

011

151.2mA

200Hz

100

201.6mA

250Hz

101

252.0mA

300Hz

110

302.4mA

350Hz

111

352.8mA

400Hz

CCD2 CONSTANT CURRENT CONTROLLER

450Hz

The CCD2 constant current controller is a switching

hysteretic current controller with a superimposed dither. The

controller is designed to provide a programmable constant

current through a solenoid valve. By controlling current

through the solenoid valve, fluid flow control is achieved.

500 Hz

133Hz

166Hz

The master SPI device sends 16-bit command words to

the 33800 device (see Table 18). The master device sets up

the output current based on the CCD2 Control command.

The IC is capable of sinking an average output current from

0.0mA to 232mA (without dither). If operating the device with

dither, the DAC + Dither value must be less than 232mA or

233Hz

266Hz

No change

Notes: Frequencies above 250Hz are +- 20%

33800

Analog Integrated Circuit Device Data

Freescale Semiconductor

28

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

greater than 0.0mA. Commands outside of this command

range will automatically lock out dither.

current. The switching frequency and accuracy are

dependent upon the load inductance and resistance, battery

voltage, dither amplitude and frequency, switch points, and

the commanded current.

Programming the solenoid current begins by sending the

CCD2 Control command. The command consists of an

control address, Diagnostic Pull-up Enable bit (Diag_pu_EN),

Dither Disable bit (DTHR_DIS), and a 9-bits of data for digital

to analog conversion (DAC). The data is received and the

DAC provides bias for a comparator to produce a threshold

level. The comparator drives a switch control circuit which

generates a frequency modulated signal for the output drive.

The differential voltage across the sense resistor provides

the feedback necessary to maintain the desired output

current. The output current is continuously monitored as a

differential voltage across the internal sense resistor. When

the current is recirculation and the driver is in the off state, the

current will decay to the lower limit switch point. When the

current reaches the lower limit, the driver will turn on to

increase the current until the upper limit switch point is

reached. The output current will continue to switch between

the switch points, resulting in the desired average current.

The switch points are set to a fixed +/-5% of the commanded

Current dither is a method by which the average current is

increased and decreased through the solenoid valve. The

33800 allows the user to program the frequency and

amplitude of the dither control. Dither amplitude is

implemented by increasing and decreasing the DAC by the

programmed dither value. The rate at which the value is

changed is set by the programmed dither frequency. When

reprogramming the dither amplitude or dither frequency, the

update will occur on the start of a positive cycle.

The maximum value of the output (DAC + Dither) must be

less than 232mA. When a greater value is programmed, the

device will disable dither on the output. Similarly, the

minimum value of the output (DAC - Dither) must be greater

than 0.0mA. Requesting a lower value will disable dither on

the output.

Table 18. CCD2 Constant Current Controller Commands

Command

Control Address

14 13 12

CCD2 Command Address

Command Bits

15

11

10

9

8

0

7

0

6

5

4

3

2

1

0

Diag DTHR

Pull- DIS

up

9 BIT DAC Command Data

CCD2 Control

1

0

0 = Pull-down Current Source

1 = Pull-up Current Source

CCD2 Command Address

CCD2

Retry

Dither Amplitude

Dither Frequency

CCD2 Frequency & Amplitude

1

0

1

X

0

1

0

1

0

VCAL

Next SO Response (Message 2)

0 = No Fault, 1 = Fault

OvrVlt Reset Trim

,TLim

or

CAL

Flt

Open Short Open Short Fault Fault Fault Fault Fault Fault Fault Fault

Set ^(23)StatusFault Fault Fault Fault StatusStatusStatusStatusStatusStatusStatusStatus

int=0

CCD2 CCD2 CCD1 CCD1 OUT8 OUT7 OUT6 OUT5 OUT4 OUT3 OUT2 OUT1

ext=1

Notes

23. Trim Set bit indicates (0 = untrimmed, 1 = trimmed)

24. VCAL Status bit indicates when internal or external supply is used. VCAL Bit = 0 indicates external, VCAL Bit = 1indicates internal.

25. Reset Bit indicates the device has performed a POR.

33800

Analog Integrated Circuit Device Data

Freescale Semiconductor

29

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

Table 19. CCD2 Dither Frequency Select

Table 20. CCD2 Dither Amplitude Select

Bits 3210

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

Dither Frequency

Dither Off

50Hz

Bits 456

000

Dither Amplitude

Dither Off

21.8mA

001

100Hz

010

32.7mA

150Hz

011

43.6mA

200Hz

100

54.5mA

250Hz

101

65.4mA

300Hz

110

75.3mA

350Hz

111

87.2mA

400Hz

Calibration Command

450Hz

In cases where an accurate time base is required, the user

may calibrate the internal timers using the calibration

command (refer to Table 5). After the 33800 device receives

the calibration command, the device expects a 32µs logic[0]

calibration pulse on the CS pin. The pulse is used to calibrate

the internal clock. SPI communication is allowed during

calibration. Because the oscillator frequency changes with

temperature, calibration is required for an accurate time

base. The calibration command may be used to update the

device on a periodic basis.

500Hz

133Hz

166Hz

233Hz

266Hz

No change

Notes: Frequencies above 250Hz are +- 20% -

assumes part is calibrated

Table 21. Calibration Command

Command

Control Address

Command Bits

15

14

1

13

0

12

1

11

0

10

X

9

8

7

6

5

4

3

2

1

0

Calibration Command

1

X

Reset Command

states or the paragraph entitled Power-ON Reset (POR) on

page 19 of this datasheet.

The reset command resets all registers to Power-ON

Reset (POR) state. Refer to Table 22, on page 30, for POR

.

Table 22. Reset Command

Command

Control Address

Command Bits

15

1

14

1

13

0

12

1

11

1

10

X

9

8

7

6

5

4

3

2

1

0

Reset

X

Next SO Response

(Message 1)

0 = No Fault, 1 =

Fault

OvrVlt Reset Fault Fault Fault Fault Fault Fault Fault Fault Fault Fault Fault Fault Fault Fault

,TLim

or

Status Status Status Status Status Status Status Status Status Status Status Status Status Status

PWM PWM PWM PWM PWM PWM OUT8 OUT7 OUT6 OUT5 OUT4 OUT3 OUT2 OUT1

CAL

Flt

6

5

4

3

2

1

33800

Analog Integrated Circuit Device Data

Freescale Semiconductor

30

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

No Operation Command

Sending these two commands perform no operation. The device outputs will remain in previous state.

.

Table 23. No Operation Command

Command

Control Address

Command Bits

15

1

14

1

13

1

12

1

11

1

10

X

9

X

8

X

7

X

6

5

X

4

3

X

2

X

1

X

0

X

NO Operation

X

NO Operation

0

X

Next SO Response

(Message 1)

0 = No Fault, 1 = Fault

OvrVl Reset Fault Fault Fault Fault Fault Fault Fault Fault Fault Fault Fault Fault Fault Fault

t,TLi

m or

CAL

Flt

Statu Statu Statu Statu Statu Statu Statu Statu Statu Statu Statu Statu Statu Statu

sPW sPW sPW sPW sPW sPW sOUT sOUT sOUT sOUT sOUT sOUT sOUT sOUT

M6

M5

M4

M3

M2

M1

8

7

6

5

4

3

2

1

Command Register Definition:

FAULT OPERATION

0 = Output Command Off

1 = Output Command On

On each SPI communication, a 16-bit command word is

sent to the 33800 and a 16-bit status word is received from

the 33800.

SO Definition:

0 = No fault

1 = Fault

The Most Significant Bit (MSB) is sent and received first.

Table 24. Fault Operation

Serial Output (SO) Pin Reports

Over-current

SO Pin reports short-to-battery/supply or over-current condition.

Output ON Open Load Fault

Output OFF Open Load Fault

Not reported on GDX and OUTX outputs. Reported on CCD1 and CCD2 outputs

SO Pin reports output “OFF” open load condition.

Device Shutdowns

Over-voltage

Total device shutdown at V

= 36.5 to 44V. Resumes normal operation with proper voltage. Upon

PWR

recovery all outputs assume previous state or OFF based on the over-voltage bit in the Shutdown/Retry

Control register.

Over-current

OUTX & CCDX outputs will remain in current limit until t_SClimit is reached. With TLim enabled, OUTX &

CCDX outputs will remain in current limit until TLim is reached.

SPI Command Summary

Table 25 below provides a comprehensive list of SPI

commands recognized by device 33800 and the reset state

of each register.

Table 25. SPI Commands

Command Name

Control Address

Command Bits

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MISCELLANEOUS

Common Commands

Calibration Command

1

0

1

0

X

33800

Analog Integrated Circuit Device Data

Freescale Semiconductor

31

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

Table 25. SPI Commands

Command Name

Control Address

Command Bits

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Reset

1

0

1

0

1

0

1

0

1

0

X

NO Operation

OSS COMMANDS

OSS Commands

X

OUT OUT OUT OUT OUT OUT

OUT

2

OUT

1

8

7

6

5

4

3

OSS ON/OFF

1 = on, 0 = off

0

1

0

1

X

0

1

0

1

Open Load Current Enable

0 = enable, 1 = disable

0

1

0

1

0

1

0

1

0

1

0

1

Shutdown/Retry from V

PWR

Over-voltage

0 = shutdown, 1 = retry

Shutdown/Retry from Short

Circuit

0

1

0

X

1

0 = shutdown, 1 = retry

TLim Enable

1 = enable, 0 = disable

0

1

0

1

0

1

X

1

Fault Timer Enable

1 = enable, 0 = disable

Parallel Outputs Enable

(7&8,5&6,3&4,1&2)

0 = Individual Control

1 = Parallel Control

1

Out

OUT OUT OUT

7 & 8 5 & 6 4 & 3 2 & 1

PX Pin Enable

0 = enable PX

0

P7

EN

P5

EN

P3

EN

P1

EN

1 = disable PX (SPI only)

AND/OR Control

1 = PX Pin AND with SPI

0

1

0

X

0

0 = PX Pin OR with SPI

33800

Analog Integrated Circuit Device Data

Freescale Semiconductor

32

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

Table 25. SPI Commands

Command Name

Control Address

Command Bits

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

GDX COMMANDS

R

Load Resistance

Gate Drive ON/OFF Bit

LD

Measurement Select

GDX ON/OFF Command

0 = Off, 1 = On

0

1

0

1

X

0

PWM Controller

Enable Bit

PWM Pin Enable Bit

PWM Pin Enable Command

0 = PWMX Pin Enabled

1 = PWMX Pin Disabled

0

1

0

1

0

1

X

0

PWM3 PWM2 PWM1

AND/OR Command

0 = PWMX Pin OR with SPI

1 = PWMX Pin AND with SPI

0

PWM6 PWM5 PWM4

Frequency Select

Duty Cycle Select

PWM1 Freq & Duty Cycle

PWM2 Freq & Duty Cycle

PWM3 Freq & Duty Cycle

PWM4 Freq & Duty Cycle

PWM5 Freq & Duty Cycle

PWM6 Freq & Duty Cycle

0

1

0

1

0

1

0

1

0

1

0

1

X

0

V

DSNS3

DSNS2

1

DSNS1

V

Short Threshold

Short Timer

1

0

1

0

1

X

0

1

0

1

0

1

DSNS123

1

DSNS123

DSNS6

1

DSNS5

1

DSNS4

1

V

Short Threshold

Short Timer

1

0

1

0

1

X

0

1

0

1

0

1

DSNS456

1

0

DSNS456

CCD COMMANDS

Diag DTHR

EN

9 BIT DAC Command Data

DIS

CCD1 Control

1

0

1

0

1

0

CCD1 LSD CCD1 TLim

Dither Amplitude

Dither Frequency

Retry ON/

OFF

DIS

EN

CCD1 Frequency & Amplitude

1

0

1

0

Diag DTHR

EN DIS

9 BIT DAC Command Data

33800

Analog Integrated Circuit Device Data

Freescale Semiconductor

33

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

Table 25. SPI Commands

Command Name

Control Address

Command Bits

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

CCD2 Control

1

0

1

0

CCD2

Retry

X

Dither Amplitude

Dither Frequency

CCD2 Frequency & Amplitude

TLIM Query Command

1

0

1

0

1

0

1

0

1

X

0

X

0

X

0

X

0

X

0

X

0

X

0

X

0

X

0

X

0

X

0

(27)

TLim Query Response

1=TLIM Fault on:

CCD1 OSS7 OSS6 OSS5 OSS4 OSS3 OSS2 OSS1 OSS0

Calibration Error, Freq. high:

Calibration Error, Freq. low:

VPWR Over-voltage

1

UNUSED COMMANDS

Invalid Command

1

0

1

0

X

Invalid Command

Notes

26. 1 = VPWR Over-Voltage and 0 = Ok

27. 1 = 0 = Ok

Table 26. Serial Output (SO) Response Register

Next SO Response (Message 1)

0 = No Fault, 1 = Fault

OvrVlt, Reset Fault Fault Fault Fault Fault Fault Fault Fault Fault Fault Fault Fault Fault Fault

or

Status Status Status Status Status Status Status Status Status Status Status Status Status Status

PWM6 PWM5 PWM4 PWM3 PWM2 PWM1 OUT8 OUT7 OUT6 OUT5 OUT4 OUT3 OUT2 OUT1

TLim

Fault

VCAL

Status

Next SO Response (Message 2)

0 = No Fault, 1 = Fault

OvrVlt, Reset Trim

Open Short Open Short Fault Fault Fault Fault Fault Fault Fault Fault

Fault Fault Fault Fault Status Status Status Status Status Status Status Status

CCD2 CCD2 CCD1 CCD1 OUT8 OUT7 OUT6 OUT5 OUT4 OUT3 OUT2 OUT1

(28)

or

Set

TLim

Fault

int=0

ext=1

Notes

28. Trim Set bit indicates (0 = untrimmed, 1 = trimmed)

33800

Analog Integrated Circuit Device Data

Freescale Semiconductor

34

TYPICAL APPLICATIONS

INTRODUCTION

TYPICAL APPLICATIONS

INTRODUCTION

Output OFF Open Load Fault

Output Voltage Shutdown

An Output OFF Open Load Fault is the detection and

reporting of an open load when the corresponding output is

disabled (input bit programmed to a logic low state). The

Output OFF Open Load Fault is detected by comparing the

drain-to-source voltage of the specific MOSFET output to an

internally generated reference. Each output has one

dedicated comparator for this purpose.

An over voltage condition on VDD (> 7.0) may result in

permanent damage to the 33800. Over-voltage on the VPWR

pin will cause the 33800 to shut down until the voltage returns

to a normal value. Over voltage exceeding the maximum

recommended voltage (45V) may cause permanent damage

to the 33800.

Each output has an internal pull-down current source or

resistor. The pull-down current sources are enabled on

power-up and must be enabled for Open Load Detect to

function. In cases were the Open Load Detect current is

disabled, the status bit will always respond with logic 0. The

device will only shut down the pull-down current in Sleep

Mode or when disabled via the SPI.

Output Voltage Clamp

Each output of the 33800 incorporates an internal voltage

clamp to provide fast turn-OFF and transient protection of

each output. Each clamp independently limits the drain-to-

source voltage to 50V. The total energy clamped (E_J) can be

calculated by multiplying the current area under the current

curve (I_A) times the clamp voltage (V_CL) (see Figure 10).

During output switching, especially with capacitive loads,

a false Output OFF Open Load Fault may be triggered. To

prevent this false fault from being reported, an internal fault

filter of 100µs to 450µs is incorporated. The duration for

which a false fault may be reported is a function of the load

impedance, R_DS(ON), C_OUTof the MOSFET, as well as the

supply voltage, V_PWR. The rising edge of CS triggers the built-

in fault delay timer. The timer must time out before the fault

comparator is enabled to detect a faulted threshold. Once the

condition causing the Open Load Fault is removed, the

device resumes normal operation. The Open Load Fault,

however, will be latched in the output SO Response register

for the MCU to read.

Characterization of the output clamps, using a single pulse

non-repetitive method at 0.3A, indicates the maximum

energy to be 50mJ at 150°C junction temperature per output.

.

Drain-to-SourceClamp

Drain-to-Source Clamp

Voltage (V = 45 V)

50V)

Drain Voltage

CL

Voltage (V_CL= 50V)

Clamp Energy

Drain Current

(I = 0.3 A)

(I_DD= 0.3A)

(E_J= I_Ax V

)

(E_J= I_Ax^CV^L_CL

)

Drain-to-SourceON

Drain-to-Source ON

Voltage (V^{DS(O N)})

Voltage (V_DS(ON)

)

Current

Area (I )

Under-voltage Shutdown

A

Time

GND

An under-voltage condition on V_DDresults in the global

shutdown of all outputs and reset of all control registers. The

under-voltage threshold is between 0.8 and 2.8V.

Figure 10. Output Voltage Clamping

An under-voltage condition on V_PWRalso results in the

global shutdown of all outputs and reset of all control

registers. The under-voltage threshold is between 3.0 and

4.4V

Reverse Battery Protection

The 33800 device requires external reverse battery

protection on the VPWR pin.

All outputs consist of a power MOSFET with an integral

substrate diode. During reverse battery condition, current will

flow through the load via the substrate diode. Under this

circumstance relays may energize and lamps will turn on. If

load reverse battery protection is desired, a diode must be

placed in series with the load.

Low-voltage condition (4.4V< V_PWR<9.0V) will operate

per the command word, however status reported on SO pin

is not guaranteed and performance may be out of

specification limits.

33800

Analog Integrated Circuit Device Data

Freescale Semiconductor

35

PACKAGING

PACKAGE DIMENSIONS

PACKAGING

PACKAGE DIMENSIONS

For the most current package revision, visit www.freescale.com and perform a keyword search using the “98A” listed below.

EK (Pb-FREE) SUFFIX

54-PIN SOICW EXPOSED PAD

98ASA99334D

ISSUE C

33800

Analog Integrated Circuit Device Data

Freescale Semiconductor

36

PACKAGING

PACKAGE DIMENSIONS

EK (Pb-FREE) SUFFIX

54-PIN SOIC EXPOSED PAD

98ASA99334D

ISSUE C

33800

Analog Integrated Circuit Device Data

Freescale Semiconductor

37

REVISION HISTORY

REVISION

DATE

7/2006

8/2006

7/2007

DESCRIPTION OF CHANGES

• Initial Release

1.0

2.0

3.0

• Updated format and style

• Changed Part Number PC33800EK/R2 to MCZ33800EK/R2 in Ordering Information.

• Changed Category from Product Preview to Advance Information.

• Changed Octal Serial Driver, Output Refresh Timer, minimum value from “-” to 2.0ms on

page 12

8/2007

4.0

5.0

• Added paragraph for PWM Frequency/Duty Cycle Command on page 23

• Revised Table 12, OSS SPI Commands and Response on page 25

• Revised Table 26, SPI Commands on page 31

10/2007

33800

Analog Integrated Circuit Device Data

Freescale Semiconductor

38

How to Reach Us:

Home Page:

www.freescale.com

Web Support:

http://www.freescale.com/support

USA/Europe or Locations Not Listed:

Freescale Semiconductor, Inc.

Technical Information Center, EL516

2100 East Elliot Road

Tempe, Arizona 85284

+1-800-521-6274 or +1-480-768-2130

www.freescale.com/support

Europe, Middle East, and Africa:

Freescale Halbleiter Deutschland GmbH

Technical Information Center

Schatzbogen 7

81829 Muenchen, Germany

+44 1296 380 456 (English)

+46 8 52200080 (English)

+49 89 92103 559 (German)

+33 1 69 35 48 48 (French)

www.freescale.com/support

Information in this document is provided solely to enable system and software

implementers to use Freescale Semiconductor products. There are no express or

implied copyright licenses granted hereunder to design or fabricate any integrated

circuits or integrated circuits based on the information in this document.

Freescale Semiconductor reserves the right to make changes without further notice to

any products herein. Freescale Semiconductor makes no warranty, representation or

guarantee regarding the suitability of its products for any particular purpose, nor does

Freescale Semiconductor assume any liability arising out of the application or use of any

product or circuit, and specifically disclaims any and all liability, including without

limitation consequential or incidental damages. “Typical” parameters that may be

provided in Freescale Semiconductor data sheets and/or specifications can and do vary

in different applications and actual performance may vary over time. All operating

parameters, including “Typicals”, must be validated for each customer application by

customer’s technical experts. Freescale Semiconductor does not convey any license

under its patent rights nor the rights of others. Freescale Semiconductor products are

not designed, intended, or authorized for use as components in systems intended for

surgical implant into the body, or other applications intended to support or sustain life,

or for any other application in which the failure of the Freescale Semiconductor product

could create a situation where personal injury or death may occur. Should Buyer

purchase or use Freescale Semiconductor products for any such unintended or

unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and

its officers, employees, subsidiaries, affiliates, and distributors harmless against all

claims, costs, damages, and expenses, and reasonable attorney fees arising out of,

directly or indirectly, any claim of personal injury or death associated with such

unintended or unauthorized use, even if such claim alleges that Freescale

Japan:

Freescale Semiconductor Japan Ltd.

Headquarters

ARCO Tower 15F

1-8-1, Shimo-Meguro, Meguro-ku,

Tokyo 153-0064

Japan

0120 191014 or +81 3 5437 9125

support.japan@freescale.com

Asia/Pacific:

Freescale Semiconductor Hong Kong Ltd.

Technical Information Center

2 Dai King Street

Tai Po Industrial Estate

Tai Po, N.T., Hong Kong

+800 2666 8080

support.asia@freescale.com

For Literature Requests Only:

Freescale Semiconductor Literature Distribution Center

P.O. Box 5405

Semiconductor was negligent regarding the design or manufacture of the part.

Denver, Colorado 80217

Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc.

All other product or service names are the property of their respective owners.

1-800-441-2447 or 303-675-2140

Fax: 303-675-2150

LDCForFreescaleSemiconductor@hibbertgroup.com

MC33800

Rev. 5.0

10/2007


型号：	MCZ33800R2
厂家：	Freescale
描述：	Engine Control Integrated Circuit 发动机控制集成电路
文件：	总39页 (文件大小：1879K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MCZ33800R2 [FREESCALE]

相关型号：

MCZ33810EK

MCZ33810EK

MCZ33810EK/R2

MCZ33810EKR2

MCZ33810EKR2

MCZ33810R2

MCZ33811EG

MCZ33811EGR2

MCZ33812AEK/R2

MCZ33812EK/R2

MCZ33879AEK

MCZ33879AEK