MPC8306EC [FREESCALE]
PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications; 的PowerQUICC II Pro的集成通信处理器系列硬件规格
| 型号： | MPC8306EC |
| 厂家： | 
Freescale |
| 描述： | PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications |
| 文件： | 总76页 (文件大小：463K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Document Number: MPC8306EC
Rev. 0, 03/2011
Freescale Semiconductor
Technical Data
MPC8306
PowerQUICC II Pro Integrated
Communications Processor
Family Hardware Specifications
Contents
This document provides an overview of the MPC8306
1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
PowerQUICC II Pro processor features. The MPC8306 is a
cost-effective, highly integrated communications processor
that addresses the requirements of several networking
applications, including residential gateways,
modem/routers, industrial control, and test and measurement
applications. The MPC8306 extends current PowerQUICC
offerings, adding higher CPU performance, additional
functionality, and faster interfaces, while addressing the
requirements related to time-to-market, price, power
consumption, and board real estate. This document describes
the electrical characteristics of MPC8306.
2. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 7
3. Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 10
4. Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5. RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 13
6. DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
7. Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
8. Ethernet and MII Management . . . . . . . . . . . . . . . . . 22
9. TDM/SI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
10. HDLC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
11. USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
12. DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
13. eSDHC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
14. FlexCAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
15. I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
16. Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
17. GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
18. IPIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
19. SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
20. JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
21. Package and Pin Listings . . . . . . . . . . . . . . . . . . . . . 50
22. Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
23. Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
24. System Design Information . . . . . . . . . . . . . . . . . . . 70
25. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 73
26. Document Revision History . . . . . . . . . . . . . . . . . . . 75
To locate published errata or updates for this document, refer
to the MPC8306 product summary page on our website
listed on the back cover of this document or contact your
local Freescale sales office.
© 2011 Freescale Semiconductor, Inc. All rights reserved.
Overview
1 Overview
The MPC8306 incorporates the e300c3 (MPC603e-based) core built on Power Architecture® technology,
which includes 16 Kbytes of each L1 instruction and data caches, dual integer units, and on-chip memory
management units (MMUs). The MPC8306 also includes two DMA engines and a 16-bit DDR2 memory
controller.
A new communications complex based on QUICC Engine technology forms the heart of the networking
capability of the MPC8306. The QUICC Engine block contains several peripheral controllers and a 32-bit
RISC controller. Protocol support is provided by the main workhorses of the device — the unified
communication controllers (UCCs). A block diagram of the MPC8306 is shown in Figure 1.
2x DUART
e300c3 Core with Power
Management
I2C
Timers
16-KB
I-Cache
16-KB
D-Cache
GPIO
SPI
RTC
ULPI
Enhanced Local
Bus Controller
Interrupt
DDR2
USB 2.0 HS
Host/Device/OTG
FPU
Controller
Controller
eSDHC
DMA
Engine
4 FlexCAN
QUICC Engine™ Block
16 KB Multi-User RAM
48 KB Instruction RAM
Accelerators
Baud Rate
Generators
Serial DMA
Single 32-bit RISC CP
Time Slot Assigner
Serial Interface
1 RMII/MII
2x TDM Ports
2x HDLC
2 RMII/MII
2x IEEE 1588
Figure 1. MPC8306 Block Diagram
Each of the five UCCs can support a variety of communication protocols such as 10/100 Mbps
EthernetIEEE-1588, and HDLC.
MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0
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Overview
In summary, the MPC8306 provides users with a highly integrated, fully programmable communications
processor. This helps to ensure that a low-cost system solution can be quickly developed and offers
flexibility to accommodate new standards and evolving system requirements.
1.1
Features
The major features of the device are as follows:
•
e300c3 Power Architecture processor core
— Enhanced version of the MPC603e core
— High-performance, superscalar processor core with a four-stage pipeline and low interrupt
latency times
— Floating-point, dual integer units, load/store, system register, and branch processing units
— 16-Kbyte instruction cache and 16-Kbyte data cache with lockable capabilities
— Dynamic power management
— Enhanced hardware program debug features
— Software-compatible with Freescale processor families implementing Power Architecture
technology
— Separate PLL that is clocked by the system bus clock
— Performance monitor
•
QUICC Engine block
— 32-bit RISC controller for flexible support of the communications peripherals with the
following features:
– One clock per instruction
– Separate PLL for operating frequency that is independent of system’s bus and e300 core
frequency for power and performance optimization
– 32-bit instruction object code
– Executes code from internal IRAM
– 32-bit arithmetic logic unit (ALU) data path
– Modular architecture allowing for easy functional enhancements
– Slave bus for CPU access of registers and multiuser RAM space
– 48 Kbytes of instruction RAM
– 16 Kbytes of multiuser data RAM
– Serial DMA channel for receive and transmit on all serial channels
— Five unified communication controllers (UCCs) supporting the following protocols and
interfaces:
– 10/100 Mbps Ethernet/IEEE® Std. 802.3® through MII and RMII interfaces.
– IEEE Std. 1588™ support
– HDLC/Transparent (bit rate up to QUICC Engine operating frequency / 8)
– HDLC Bus (bit rate up to 10 Mbps)
MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0
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Overview
– Asynchronous HDLC (bit rate up to 2 Mbps)
– Two TDM interfaces supporting up to 128 QUICC multichannel controller channels, each
running at 64 kbps
For more information on QUICC Engine sub-modules, see QUICC Engine Block Reference
Manual with Protocol Interworking.
•
DDR SDRAM memory controller
— Programmable timing supporting DDR2 SDRAM
— Integrated SDRAM clock generation
— 16-bit data interface, up to 266-MHz data rate
— 14 address lines
— The following SDRAM configurations are supported:
– Up to two physical banks (chip selects), 256-Mbyte per chip select for 16 bit data interface
512-Mbyte addressable space for 32 bit data interface
– 64-Mbit to 2-Gbit devices with x8/x16 data ports (no direct x4 support)
– One 16-bit device or two 8-bit devices on a 16-bit bus,
— Support for up to 16 simultaneous open pages for DDR2
— One clock pair to support up to 4 DRAM devices
— Supports auto refresh
— On-the-fly power management using CKE
•
Enhanced local bus controller (eLBC)
— Multiplexed 26-bit address and 8-/16-bit data operating at up to 66 MHz
— Eight chip selects supporting eight external slaves
– Four chip selects dedicated
– Four chip selects offered as multiplexed option
— Supports boot from parallel NOR Flash and parallel NAND Flash
— Supports programmable clock ratio dividers
— Up to eight-beat burst transfers
— 16- and 8-bit ports, seperate LWE for each 8 bit
— Three protocol engines available on a per chip select basis:
– General-purpose chip select machine (GPCM)
– Three user programmable machines (UPMs)
– NAND Flash control machine (FCM)
— Variable memory block sizes for FCM, GPCM, and UPM mode
— Default boot ROM chip select with configurable bus width (8 or 16)
— Provides two Write Enable signals to allow single byte write access to external 16-bit eLBC
slave devices
•
Integrated programmable interrupt controller (IPIC)
— Functional and programming compatibility with the MPC8260 interrupt controller
MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0
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Freescale Semiconductor
Overview
— Support for external and internal discrete interrupt sources
— Programmable highest priority request
— Six groups of interrupts with programmable priority
— External and internal interrupts directed to host processor
— Unique vector number for each interrupt source
Enhanced secure digital host controller (eSDHC)
•
— Compatible with the SD Host Controller Standard Specification Version 2.0 with test event
register support
— Compatible with the MMC System Specification Version 4.2
— Compatible with the SD Memory Card Specification Version 2.0 and supports the high capacity
SD memory card
— Compatible with the SD Input/Output (SDIO) Card Specification, Version 2.0
— Designed to work with SD Memory, miniSD Memory, SDIO, miniSDIO, SD Combo, MMC,
MMCplus, and RS-MMC cards
— Card bus clock frequency up to 33.25 MHz.
— Supports 1-/4-bit SD and SDIO modes, 1-/4-bit modes
– Up to 133 Mbps data transfer for SD/SDIO/MMC cards using 4 parallel data lines
— Supports block sizes of 1 ~ 4096 bytes
•
•
Universal serial bus (USB) dual-role controller
— Designed to comply with Universal Serial Bus Revision 2.0 Specification
— Supports operation as a stand-alone USB host controller
— Supports operation as a stand-alone USB device
— Supports high-speed (480-Mbps), full-speed (12-Mbps), and low-speed (1.5-Mbps) operations.
Low speed is only supported in host mode.
FlexCAN module
— Full implementation of the CAN protocol specification version 2.0B
— Up to 64 flexible message buffers of zero to eight bytes data length
— Powerful Rx FIFO ID filtering, capable of matching incoming IDs
— Selectable backwards compatibility with previous FlexCAN module version
— Programmable loop-back mode supporting self-test operation
— Global network time, synchronized by a specific message
— Independent of the transmission medium (an external transceiver is required)
— Short latency time due to an arbitration scheme for high-priority messages
2
•
Dual I C interfaces
— Two-wire interface
— Multiple-master support
2
— Master or slave I C mode support
— On-chip digital filtering rejects spikes on the bus
MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0
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Overview
2
— I C1 can be used as the boot sequencer
•
DMA Engine
— Support for the DMA engine with the following features:
– Sixteen DMA channels
– All data movement via dual-address transfers: read from source, write to destination
– Transfer control descriptor (TCD) organized to support two-deep, nested transfer operations
– Channel activation via one of two methods (for both the methods, one activation per
execution of the minor loop is required):
– Explicit software initiation
– Initiation via a channel-to-channel linking mechanism for continuous transfers
(independent channel linking at end of minor loop and/or major loop)
– Support for fixed-priority and round-robin channel arbitration
– Channel completion reported via optional interrupt requests
— Support for scatter/gather DMA processing
•
DUART
— Two 2-wire interfaces (RxD, TxD)
– The same can be configured as one 4-wire interface (RxD, TxD, RTS, CTS)
— Programming model compatible with the original 16450 UART and the PC16550D
Serial peripheral interface (SPI)
•
•
— Master or slave support
Power management controller (PMC)
— Supports core doze/nap/sleep/ power management
— Exits low power state and returns to full-on mode when
– The core internal time base unit invokes a request to exit low power state
– The power management controller detects that the system is not idle and there are
outstanding transactions on the internal bus or an external interrupt.
•
•
•
Parallel I/O
— General-purpose I/O (GPIO)
– 56 parallel I/O pins multiplexed on various chip interfaces
– Interrupt capability
System timers
— Periodic interrupt timer
— Software watchdog timer
— Eight general-purpose timers
Real time clock (RTC) module
— Maintains a one-second count, unique over a period of thousand of years
— Two possible clock sources:
– External RTC clock (RTC_PIT_CLK)
MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0
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Electrical Characteristics
– CSB bus clock
•
IEEE Std. 1149.1™ compliant JTAG boundary scan
2 Electrical Characteristics
This section provides the AC and DC electrical specifications and thermal characteristics for the
MPC8306. The MPC8306 is currently targeted to these specifications. Some of these specifications are
independent of the I/O cell, but are included for a more complete reference. These are not purely I/O buffer
design specifications.
2.1
Overall DC Electrical Characteristics
This section covers the ratings, conditions, and other characteristics.
2.1.1
Absolute Maximum Ratings
Table 1 provides the absolute maximum ratings.
1
Table 1. Absolute Maximum Ratings
Characteristic
Symbol
Max Value
Unit
Notes
Core supply voltage
PLL supply voltage
VDD
–0.3 to 1.26
–0.3 to 1.26
V
V
—
—
AVDD1
AVDD2
AVDD3
DDR2 DRAM I/O voltage
GVDD
OVDD
–0.3 to 1.98
–0.3 to 3.6
V
V
—
4
Local bus, DUART, system control and power management, I2C,
SPI, MII, RMII, MII management, eSDHC, FlexCAN, USB and JTAG
I/O voltage
Input voltage
DDR2 DRAM signals
MVIN
MVREF
OVIN
–0.3 to (GVDD + 0.3)
–0.3 to (GVDD + 0.3)
–0.3 to (OVDD + 0.3)
V
V
V
2
2
3
DDR2 DRAM reference
Local bus, DUART, SYS_CLK_IN,
system control and power
management, I2C, SPI, and JTAG
signals
Storage temperature range
TSTG
–55 to 150
C
—
Notes:
1. Functional and tested operating conditions are given in Table 2. Absolute maximum ratings are stress ratings only, and
functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause
permanent damage to the device.
2. Caution: MVIN must not exceed GVDD by more than 0.3 V. This limit may be exceeded for a maximum of 100 ms during
power-on reset and power-down sequences.
3. Caution: OVIN must not exceed OVDD by more than 0.3 V. This limit may be exceeded for a maximum of 100 ms during
power-on reset and power-down sequences.
4. OVDD here refers to NVDDA, NVDDB,NVDDC, NVDDF, NVDDG, and NVDDH from the ball map.
MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0
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Electrical Characteristics
2.1.2
Power Supply Voltage Specification
Table 2 provides the recommended operating conditions for the MPC8306. Note that these values are the
recommended and tested operating conditions. Proper device operation outside of these conditions is not
guaranteed.
Table 2. Recommended Operating Conditions
Recommended
Characteristic
Symbol
Unit
Notes
Value
Core supply voltage
PLL supply voltage
VDD
1.0 V ± 50 mV
1.0 V ± 50 mV
V
V
1
1
AVDD1
AVDD2
AVDD3
DDR2 DRAM I/O voltage
GVDD
OVDD
1.8 V ± 100 mV
3.3 V ± 300 mV
V
V
1
Local bus, DUART, system control and power management, I2C,
SPI, MII, RMII, MII management, eSDHC, FlexCAN, USB and
JTAG I/O voltage
1, 3
Junction temperature
TA/TJ
0 to 105
C
2
Note:
1. GVDD, OVDD, AVDD, and VDD must track each other and must vary in the same direction—either in the positive or negative
direction.
2. Minimum temperature is specified with TA(Ambient Temperature); maximum temperature is specified with TJ(Junction
Temperature).
3. OVDD here refers to NVDDA, NVDDB,NVDDC, NVDDF, NVDDG, and NVDDH from the ball map.
Figure 2 shows the undershoot and overshoot voltages at the interfaces of the MPC8306
G/OVDD + 20%
G/OVDD + 5%
G/OVDD
VIH
GND
GND – 0.3 V
VIL
GND – 0.7 V
Not to Exceed 10%
1
of tinterface
Note:
1. tinterface refers to the clock period associated with the bus clock interface.
Figure 2. Overshoot/Undershoot Voltage for GV /OV
DD
DD
MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0
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Electrical Characteristics
2.1.3
Output Driver Characteristics
Table 3 provides information on the characteristics of the output driver strengths.
Table 3. Output Drive Capability
Output Impedance
Driver Type
Supply Voltage (V)
()
Local bus interface utilities signals
DDR2 signal
42
18
42
42
OVDD = 3.3
GVDD = 1.8
OVDD = 3.3
OVDD = 3.3
DUART, system control, I2C, SPI, JTAG
GPIO signals
2.1.4
Input Capacitance Specification
Table 4 describes the input capacitance for the SYS_CLK_IN pin in the MPC8306.
Table 4. Input Capacitance Specification
Parameter/Condition
Symbol
Min
Max
Unit
Notes
Input capacitance for all pins except SYS_CLK_IN and
QE_CLK_IN
CI
6
8
pF
—
Input capacitance for SYS_CLK_IN and QE_CLK_IN
CICLK_IN
10
—
pF
1
Note:
1. The external clock generator should be able to drive 10 pF.
2.2
Power Sequencing
The device does not require the core supply voltage (V ) and IO supply voltages (GV and OV ) to
DD
DD
DD
be applied in any particular order. Note that during power ramp-up, before the power supplies are stable
and if the I/O voltages are supplied before the core voltage, there might be a period of time that all input
and output pins are actively driven and cause contention and excessive current. In order to avoid actively
driving the I/O pins and to eliminate excessive current draw, apply the core voltage (V ) before the I/O
DD
voltage (GV and OV ) and assert PORESET before the power supplies fully ramp up. In the case
DD
DD
where the core voltage is applied first, the core voltage supply must rise to 90% of its nominal value before
the I/O supplies reach 0.7 V; see Figure 3. Once both the power supplies (I/O voltage and core voltage) are
stable, wait for a minimum of 32 clock cycles before negating PORESET.
NOTE
There is no specific power down sequence requirement for the device. I/O voltage supplies (GV and
DD
OV ) do not have any ordering requirements with respect to one another.
DD
MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0
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Power Characteristics
I/O Voltage (GVDD and OVDD
)
V
Core Voltage (VDD
)
0.7 V
90%
t
0
PORESET
>= 32 tSYS_CLK_IN
Figure 3. MPC8306Power-Up Sequencing Example
3 Power Characteristics
The typical power dissipation for this family of MPC8306 devices is shown in Table 5.
Table 5. MPC8306 Power Dissipation
Core
Frequency (MHz)
QUICC Engine
Frequency (MHz)
CSB
Frequency (MHz)
Typical
Maximum
Unit
Notes
133
200
266
133
200
200
133
133
133
0.272
0.291
0.451
0.618
0.631
0.925
W
W
W
1, 2,3
1, 2, 3
1, 2, 3
Notes:
1. The values do not include I/O supply power (OVDD and GVDD), but it does include VDD and AVDD power . For I/O power
values, see Table 6.
2. Typical power is based on a nominal voltage of VDD = 1.0 V, ambient temperature, and the core running a Dhrystone
benchmark application. The measurements were taken on the evaluation board using WC process silicon.
3. Maximum power is based on a voltage of VDD = 1.05 V, WC process, a junction TJ = 105C, and an artificial smoke test.
MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0
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Power Characteristics
Table 6 shows the estimated typical I/O power dissipation for the device.
Table 6. Typical I/O Power Dissipation
GVDD
(1.8 V)
OVDD
(3.3 V)
Interface
Parameter
Unit
W
Comments
DDR I/O
65% utilization
1.8 V
Rs = 20
Rt = 50
1 pair of clocks
266 MHz, 1 16 bits
0.141
—
—
Local bus I/O load = 25 pF
1 pair of clocks
66 MHz, 26 bits
QUICC Engine block and other I/Os
TDM serial, HDLC/TRAN
serial, DUART, MII, RMII,
Ethernet management,
USB, SPI ,
—
0.150
W
1
Timer output
FlexCAN
eSDHC
Note:
1. Typical IO power is based on a nominal voltage of VDD = 3.3V, ambient temperature, and the core running a Dhrystone
benchmark application. The measurements were taken on the evaluation board using WC process silicon.
MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0
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Clock Input Timing
4 Clock Input Timing
This section provides the clock input DC and AC electrical characteristics for the MPC8306.
NOTE
The rise/fall time on QUICC Engine input pins should not exceed 5 ns. This
should be enforced especially on clock signals. Rise time refers to signal
transitions from 10% to 90% of OV ; fall time refers to transitions from
DD
90% to 10% of OV
.
DD
4.1
DC Electrical Characteristics
Table 7 provides the clock input (SYS_CLK_IN) DC specifications for the MPC8306. These
specifications are also applicable for QE_CLK_IN.
Table 7. SYS_CLK_IN DC Electrical Characteristics
Parameter
Input high voltage
Condition
Symbol
Min
Max
Unit
—
—
VIH
VIL
IIN
2.4
–0.3
—
OVDD + 0.3
V
V
Input low voltage
0.4
±5
±5
SYS_CLK_IN input current
SYS_CLK_IN input current
0 V VIN OVDD
A
A
0 V VIN 0.5 V or
IIN
—
OVDD – 0.5 V VIN OVDD
SYS_CLK_IN input current
0.5 V VIN OVDD – 0.5 V
IIN
—
±50
A
4.2
AC Electrical Characteristics
The primary clock source for the MPC8306 is SYS_CLK_IN. Table 8 provides the clock input
(SYS_CLK_IN) AC timing specifications for the MPC8306. These specifications are also applicable for
QE_CLK_IN.
Table 8. SYS_CLK_IN AC Timing Specifications
Parameter/Condition
SYS_CLK_IN frequency
Symbol
Min
Typical
Max
Unit
Notes
fSYS_CLK_IN
tSYS_CLK_IN
tKH, tKL
24
15
—
—
—
66.67
41.6
2.8
MHz
ns
1
—
2
SYS_CLK_IN cycle time
SYS_CLK_IN rise and fall time
1.1
ns
MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0
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RESET Initialization
Table 8. SYS_CLK_IN AC Timing Specifications
SYS_CLK_IN duty cycle
tKHK SYS_CLK_
/t
40
—
60
%
3
IN
SYS_CLK_IN jitter
—
—
—
±150
ps
4, 5
Notes:
1. Caution: The system, core and QUICC Engine block must not exceed their respective maximum or minimum operating
frequencies.
2. Rise and fall times for SYS_CLK_IN are measured at 0.33 and 2.97 V.
3. Timing is guaranteed by design and characterization.
4. This represents the total input jitter—short term and long term—and is guaranteed by design.
5. The SYS_CLK_IN driver’s closed loop jitter bandwidth should be < 500 kHz at –20 dB. The bandwidth must be set low to
allow cascade-connected PLL-based devices to track SYS_CLK_IN drivers with the specified jitter.
6. Spread spectrum is allowed upto 1% down-spread @ 33kHz (max rate).
5 RESET Initialization
This section describes the AC electrical specifications for the reset initialization timing requirements of
the MPC8306. Table 9 provides the reset initialization AC timing specifications for the reset
component(s).
Table 9. RESET Initialization Timing Specifications
Parameter/Condition
Min
Max
Unit
Notes
Required assertion time of HRESET to activate reset flow
32
32
—
—
tSYS_CLK_IN
tSYS_CLK_IN
1
1
Required assertion time of PORESET with stable clock applied to
SYS_CLK_IN
HRESET assertion (output)
512
4
—
—
tSYS_CLK_IN
tSYS_CLK_IN
1
Input setup time for POR configuration signals
1, 2
(CFG_RESET_SOURCE[0:3]) with respect to negation of PORESET
Input hold time for POR config signals with respect to negation of
HRESET
0
—
ns
1, 2
Notes:
1. tSYS_CLK_IN is the clock period of the input clock applied to SYS_CLK_IN. For more details, see the MPC8306
PowerQUICC II Pro Integrated Communications Processor Reference Manual.
2. POR configuration signals consists of CFG_RESET_SOURCE[0:3].
Table 10 provides the PLL lock times.
Table 10. PLL Lock Times
Parameter/Condition
Min
Max
Unit
Notes
PLL lock times
—
100
s
—
5.1
Reset Signals DC Electrical Characteristics
Table 11 provides the DC electrical characteristics for the MPC8306 reset signals mentioned in Table 9.
MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0
Freescale Semiconductor
13
DDR2 SDRAM
Table 11. Reset Signals DC Electrical Characteristics
Characteristic
Symbol
Condition
Min
Max
Unit
Notes
Output high voltage
Output low voltage
Output low voltage
Input high voltage
Input low voltage
Input current
VOH
VOL
IOH = –6.0 mA
IOL = 6.0 mA
2.4
—
—
0.5
V
V
1
1
V
I
= 3.2 mA
—
0.4
V
1
OL
OL
VIH
VIL
IIN
—
—
2.0
–0.3
—
OVDD + 0.3
0.8
V
1
V
—
—
0 V VIN OVDD
±5
A
Note:
1. This specification applies when operating from 3.3 V supply.
6 DDR2 SDRAM
This section describes the DC and AC electrical specifications for the DDR2 SDRAM interface of the
MPC8306. Note that DDR2 SDRAM is GV (typ) = 1.8 V.
DD
6.1
DDR2 SDRAM DC Electrical Characteristics
Table 12 provides the recommended operating conditions for the DDR2 SDRAM component(s) of the
MPC8306 when GV (typ) = 1.8 V.
DD
Table 12. DDR2 SDRAM DC Electrical Characteristics for GV (typ) = 1.8 V
DD
Parameter/Condition
I/O supply voltage
Symbol
Min
Max
Unit
Notes
GVDD
MVREF
VTT
1.7
0.49 GVDD
MVREF – 0.04
MVREF+ 0.125
–0.3
1.9
0.51 GVDD
MVREF + 0.04
GVDD + 0.3
MVREF – 0.125
9.9
V
V
1
2
I/O reference voltage
I/O termination voltage
Input high voltage
V
3
VIH
V
—
—
4
Input low voltage
VIL
V
Output leakage current
Output high current (VOUT = 1.35 V)
Output low current (VOUT = 0.280 V)
Notes:
IOZ
–9.9
A
mA
mA
IOH
–13.4
—
—
—
IOL
13.4
—
1. GVDD is expected to be within 50 mV of the DRAM GVDD at all times.
2. MVREF is expected to be equal to 0.5 GVDD, and to track GVDD DC variations as measured at the receiver. Peak-to-peak
noise on MVREF may not exceed ±2% of the DC value.
3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be
equal to MVREF. This rail should track variations in the DC level of MVREF.
4. Output leakage is measured with all outputs disabled, 0 V VOUT GVDD
.
Table 13 provides the DDR2 capacitance when GV (typ) = 1.8 V.
DD
MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0
14
Freescale Semiconductor
DDR2 SDRAM
Notes
Table 13. DDR2 SDRAM Capacitance for GV (typ) = 1.8 V
DD
Parameter/Condition
Symbol
Min
Max
Unit
Input/output capacitance: DQ, DQS
Delta input/output capacitance: DQ, DQS
Note:
CIO
6
8
pF
pF
1
1
CDIO
—
0.5
1. This parameter is sampled. GVDD = 1.8 V ± 0.100 V, f = 1 MHz, TA = 25 °C, VOUT = GVDD 2,
OUT (peak-to-peak) = 0.2 V.
V
6.2
DDR2 SDRAM AC Electrical Characteristics
This section provides the AC electrical characteristics for the DDR2 SDRAM interface.
6.2.1
DDR2 SDRAM Input AC Timing Specifications
Table 14 provides the input AC timing specifications for the DDR2 SDRAM (GV (typ) = 1.8 V).
DD
Table 14. DDR2 SDRAM Input AC Timing Specifications for 1.8-V Interface
At recommended operating conditions with GVDD of 1.8 V± 100mV.
Parameter
AC input low voltage
AC input high voltage
Symbol
Min
Max
Unit
Notes
VIL
—
MVREF – 0.25
—
V
V
—
—
VIH
MVREF + 0.25
Table 15 provides the input AC timing specifications for the DDR2 SDRAM interface.
Table 15. DDR2 SDRAM Input AC Timing Specifications
At recommended operating conditions with GVDD of 1.8V ± 100mV.
Parameter
Symbol
Min
Max
Unit
Notes
Controller skew for MDQS—MDQ/MDM
tCISKEW
ps
1, 2
266 MHz
–750
750
Notes:
1. tCISKEW represents the total amount of skew consumed by the controller between MDQS[n] and any corresponding bit that
is captured with MDQS[n]. This should be subtracted from the total timing budget.
2. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called tDISKEW. This can be
determined by the equation: tDISKEW = ±(T/4 – abs(tCISKEW)) where T is the clock period and abs(tCISKEW) is the absolute
value of tCISKEW
.
MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0
Freescale Semiconductor
15
DDR2 SDRAM
Figure 4 shows the input timing diagram for the DDR controller.
MCK[n]
MCK[n]
tMCK
MDQS[n]
MDQ[x]
D0
D1
tDISKEW
tDISKEW
Figure 4. DDR Input Timing Diagram
6.2.2
DDR2 SDRAM Output AC Timing Specifications
Table 16 provides the output AC timing specifications for the DDR2 SDRAM interfaces.
Table 16. DDR2 SDRAM Output AC Timing Specifications
At recommended operating conditions with GVDD of 1.8V ± 100mV.
Parameter
Symbol1
Min
Max
Unit
Notes
MCK cycle time, (MCK/MCK crossing)
tMCK
6
8
ns
ns
2
3
ADDR/CMD output setup with respect to MCK
tDDKHAS
266 MHz
ADDR/CMD output hold with respect to MCK
266 MHz
2.5
2.5
2.5
—
—
—
tDDKHAX
tDDKHCS
tDDKHCX
tDDKHMH
ns
ns
ns
3
3
3
MCS output setup with respect to MCK
MCS output hold with respect to MCK
MCK to MDQS Skew
266 MHz
266 MHz
2.5
—
–0.6
0.6
ns
ns
4
5
MDQ/MDM output setup with respect to MDQS
tDDKHDS,
tDDKLDS
266 MHz
0.9
—
—
MDQ/MDM output hold with respect to MDQS
tDDKHDX,
tDDKLDX
ps
5
266 MHz
1100
MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0
16
Freescale Semiconductor
DDR2 SDRAM
Notes
Table 16. DDR2 SDRAM Output AC Timing Specifications (continued)
At recommended operating conditions with GVDD of 1.8V ± 100mV.
Parameter
Symbol1
tDDKHMP
tDDKHME
Min
Max
Unit
MDQS preamble start
MDQS epilogue end
Notes:
0.75 x tMCK
0.4 x tMCK
—
ns
ns
6
6
0.6 x tMCK
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. Output hold time can be read as DDR timing
(DD) from the rising or falling edge of the reference clock (KH or KL) until the output went invalid (AX or DX). For example,
tDDKHAS symbolizes DDR timing (DD) for the time tMCK memory clock reference (K) goes from the high (H) state until outputs
(A) are setup (S) or output valid time. Also, tDDKLDX symbolizes DDR timing (DD) for the time tMCK memory clock reference
(K) goes low (L) until data outputs (D) are invalid (X) or data output hold time.
2. All MCK/MCK referenced measurements are made from the crossing of the two signals ±0.1 V.
3. ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MCS, and MDQ/MDM/MDQS. For the ADDR/CMD
setup and hold specifications, it is assumed that the Clock Control register is set to adjust the memory clocks by 1/2 applied
cycle.
4. Note that tDDKHMH follows the symbol conventions described in note 1. For example, tDDKHMH describes the DDR timing (DD)
from the rising edge of the MCK(n) clock (KH) until the MDQS signal is valid (MH). tDDKHMH can be modified through control
of the DQSS override bits in the TIMING_CFG_2 register. This is typically set to the same delay as the clock adjust in the
CLK_CNTL register. The timing parameters listed in the table assume that these 2 parameters have been set to the same
adjustment value. See the MPC8306 PowerQUICC II Pro Integrated Communications Processor Reference Manual for a
description and understanding of the timing modifications enabled by use of these bits.
5. Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ), or data
mask (MDM). The data strobe should be centered inside of the data eye at the pins of the microprocessor.
6. tDDKHMP follows the symbol conventions described in note 1.
Figure 5 shows the DDR SDRAM output timing for the MCK to MDQS skew measurement (t
).
DDKHMH
MCK
MCK
tMCK
tDDKHMH(max) = 0.6 ns
MDQS
tDDKHMH(min) = –0.6 ns
MDQS
Figure 5. Timing Diagram for t
DDKHMH
MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0
Freescale Semiconductor
17
DDR2 SDRAM
Figure 6 shows the DDR2 SDRAM output timing diagram.
MCK[n]
MCK[n]
tMCK
tDDKHAS ,tDDKHCS
tDDKHAX ,tDDKHCX
ADDR/CMD
MDQS[n]
Write A0
tDDKHMP
NOOP
tDDKHMH
tDDKHME
tDDKHDS
tDDKLDS
MDQ[x]/
MECC[x]
D0
D1
tDDKLDX
tDDKHDX
Figure 6. DDR2 SDRAM Output Timing Diagram
MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0
18
Freescale Semiconductor
Local Bus
7 Local Bus
This section describes the DC and AC electrical specifications for the local bus interface of the MPC8306.
7.1
Local Bus DC Electrical Characteristics
Table 17 provides the DC electrical characteristics for the local bus interface.
Table 17. Local Bus DC Electrical Characteristics
Parameter
High-level input voltage
Symbol
Min
Max
Unit
VIH
VIL
2
–0.3
OVDD + 0.3
V
V
Low-level input voltage
0.8
—
High-level output voltage, IOH = –100 A
Low-level output voltage, IOL = 100 A
Input current
VOH
VOL
IIN
OVDD – 0.2
—
V
0.2
±5
V
—
A
7.2
Local Bus AC Electrical Specifications
Table 18 describes the general timing parameters of the local bus interface of the MPC8306.
Table 18. Local Bus General Timing Parameters
Parameter
Symbol1
Min
Max
Unit
Notes
Local bus cycle time
tLBK
15
7
—
—
—
3
ns
ns
ns
ns
ns
2
3, 4
3, 4
3
Input setup to local bus clock (LCLKn)
Input hold from local bus clock (LCLKn)
Local bus clock (LCLKn) to output valid
Local bus clock (LCLKn) to output high impedance for LAD/LDP
Notes:
tLBIVKH
tLBIXKH
tLBKHOV
tLBKHOZ
1.0
—
—
4
5
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tLBIXKH1 symbolizes local bus
timing (LB) for the input (I) to go invalid (X) with respect to the time the tLBK clock reference (K) goes high (H), in this case
for clock one(1).
2. All timings are in reference to falling edge of LCLK0 (for all outputs and for LGTA and LUPWAIT inputs) or rising edge of
LCLK0 (for all other inputs).
3. All signals are measured from OVDD/2 of the rising/falling edge of LCLK0 to 0.4 OVDD of the signal in question for 3.3-V
signaling levels.
4. Input timings are measured at the pin.
5. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered
through the component pin is less than or equal to the leakage current specification.
MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0
Freescale Semiconductor
19
Local Bus
Figure 7 provides the AC test load for the local bus.
OVDD/2
Output
Z0 = 50
RL = 50
Figure 7. Local Bus AC Test Load
Figure 8 through Figure 10 show the local bus signals. These figures has been given indicate timing
parameters only and do not reflect actual functional operation of interface.
LCLK[n]
tLBIXKH
tLBIVKH
Input Signals:
LAD[0:15]
tLBIXKH
tLBIVKH
Input Signal:
LGTA
tLBIXKH
tLBKHOV
Output Signals:
LBCTL/LBCKE/LOE
tLBKHOZ
tLBKHOV
Output Signals:
LAD[0:15]
tLBOTOT
LALE
Figure 8. Local Bus Signals
MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0
20
Freescale Semiconductor
Local Bus
LCLK
T1
T3
tLBKHOZ
tLBKHOV
GPCM Mode Output Signals:
LCS[0:3]/LWE
tLBIXKH
tLBIVKH
UPM Mode Input Signal:
LUPWAIT
tLBIXKH
tLBIVKH
Input Signals:
LAD[0:15]/LDP[0:3]
tLBKHOZ
tLBKHOV
UPM Mode Output Signals:
LCS[0:3]/LBS[0:1]/LGPL[0:5]
Figure 9. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 2
MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0
Freescale Semiconductor
21
Ethernet and MII Management
LCLK
T1
T2
T3
T4
tLBKHOZ
tLBKHOV
GPCM Mode Output Signals:
LCS[0:3]/LWE
tLBIXKH
tLBIVKH
UPM Mode Input Signal:
LUPWAIT
tLBIXKH
tLBIVKH
Input Signals:
LAD[0:15]
tLBKHOZ
tLBKHOV
UPM Mode Output Signals:
LCS[0:3]/LBS[0:1]/LGPL[0:5]
Figure 10. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 4
8 Ethernet and MII Management
This section provides the AC and DC electrical characteristics for Ethernet interfaces.
8.1
Ethernet Controller (10/100 Mbps)—MII/RMII Electrical
Characteristics
The electrical characteristics specified here apply to all MII (media independent interface) and RMII
(reduced media independent interface), except MDIO (management data input/output) and MDC
(management data clock). The MII and RMII are defined for 3.3 V. The electrical characteristics for MDIO
and MDC are specified in Section 8.3, “Ethernet Management Interface Electrical Characteristics.”
8.1.1
DC Electrical Characteristics
All MII and RMII drivers and receivers comply with the DC parametric attributes specified in Table 19.
MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0
22
Freescale Semiconductor
Ethernet and MII Management
Table 19. MII and RMII DC Electrical Characteristics
Parameter
Symbol
Conditions
Min
Max
Unit
Supply voltage 3.3 V
Output high voltage
Output low voltage
Input high voltage
Input low voltage
Input current
OVDD
VOH
VOL
VIH
—
3
3.6
OVDD + 0.3
0.50
V
V
IOH = –4.0 mA OVDD = Min
2.40
GND
2.0
IOL = 4.0 mA
OVDD = Min
V
—
—
—
—
OVDD + 0.3
0.90
V
VIL
–0.3
—
V
IIN
0 V VIN OVDD
±5
A
8.2
MII and RMII AC Timing Specifications
The AC timing specifications for MII and RMII are presented in this section.
8.2.1
MII AC Timing Specifications
This section describes the MII transmit and receive AC timing specifications.
8.2.1.1
MII Transmit AC Timing Specifications
Table 20 provides the MII transmit AC timing specifications.
Table 20. MII Transmit AC Timing Specifications
At recommended operating conditions with OVDD of 3.3 V ± 300mV.
Parameter/Condition
Symbol1
Min
Typical
Max
Unit
TX_CLK clock period 10 Mbps
TX_CLK clock period 100 Mbps
TX_CLK duty cycle
tMTX
tMTX
tMTXH/tMTX
tMTKHDX
tMTXR
—
—
400
40
—
5
—
—
ns
ns
%
35
1
65
15
4.0
4.0
TX_CLK to MII data TXD[3:0], TX_ER, TX_EN delay
TX_CLK data clock rise VIL(min) to VIH(max)
TX_CLK data clock fall VIH(max) to VIL(min)
Note:
ns
ns
ns
1.0
1.0
—
—
tMTXF
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMTKHDX symbolizes MII transmit
timing (MT) for the time tMTX clock reference (K) going high (H) until data outputs (D) are invalid (X). Note that, in general,
the clock reference symbol representation is based on two to three letters representing the clock of a particular functional.
For example, the subscript of tMTX represents the MII(M) transmit (TX) clock. For rise and fall times, the latter convention is
used with the appropriate letter: R (rise) or F (fall).
MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0
Freescale Semiconductor
23
Ethernet and MII Management
Figure 14 provides the AC test load.
OVDD/2
Output
Z0 = 50
RL = 50
Figure 11. AC Test Load
Figure 12 shows the MII transmit AC timing diagram.
tMTXR
tMTX
TX_CLK
tMTXF
tMTXH
TXD[3:0]
TX_EN
TX_ER
tMTKHDX
Figure 12. MII Transmit AC Timing Diagram
8.2.1.2
MII Receive AC Timing Specifications
Table 21 provides the MII receive AC timing specifications.
Table 21. MII Receive AC Timing Specifications
At recommended operating conditions with OVDD of 3.3 V ± 300mV.
Parameter/Condition
Symbol1
Min
Typical
Max
Unit
RX_CLK clock period 10 Mbps
RX_CLK clock period 100 Mbps
RX_CLK duty cycle
tMRX
tMRX
tMRXH/tMRX
—
—
400
40
—
—
—
ns
ns
%
35
65
—
RXD[3:0], RX_DV, RX_ER setup time to RX_CLK
RXD[3:0], RX_DV, RX_ER hold time to RX_CLK
RX_CLK clock rise VIL(min) to VIH(max)
RX_CLK clock fall time VIH(max) to VIL(min)
Note:
tMRDVKH
tMRDXKH
tMRXR
10.0
10.0
1.0
1.0
—
ns
ns
ns
ns
—
—
—
4.0
4.0
tMRXF
—
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMRDVKH symbolizes MII receive
timing (MR) with respect to the time data input signals (D) reach the valid state (V) relative to the tMRX clock reference (K)
going to the high (H) state or setup time. Also, tMRDXKL symbolizes MII receive timing (GR) with respect to the time data input
signals (D) went invalid (X) relative to the tMRX clock reference (K) going to the low (L) state or hold time. Note that, in general,
the clock reference symbol representation is based on three letters representing the clock of a particular functional. For
example, the subscript of tMRX represents the MII (M) receive (RX) clock. For rise and fall times, the latter convention is used
with the appropriate letter: R (rise) or F (fall).
MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0
24
Freescale Semiconductor
Ethernet and MII Management
Figure 13 shows the MII receive AC timing diagram.
tMRXR
tMRX
RX_CLK
tMRXF
Valid Data
tMRXH
RXD[3:0]
RX_DV
RX_ER
tMRDVKH
tMRDXKH
Figure 13. MII Receive AC Timing Diagram
8.2.2
RMII AC Timing Specifications
This section describes the RMII transmit and receive AC timing specifications.
8.2.2.1
RMII Transmit AC Timing Specifications
Table 20 provides the RMII transmit AC timing specifications.
Table 22. RMII Transmit AC Timing Specifications
At recommended operating conditions with OVDD of 3.3 V ± 300mV.
Parameter/Condition
Symbol1
Min
Typical
Max
Unit
REF_CLK clock
tRMX
—
35
2
20
—
—
—
—
—
65
ns
%
REF_CLK duty cycle
tRMXH RMX
tRMTKHDX
tRMXR
/t
REF_CLK to RMII data TXD[1:0], TX_EN delay
REF_CLK data clock rise VIL(min) to VIH(max)
REF_CLK data clock fall VIH(max) to VIL(min)
Note:
13
ns
ns
ns
1.0
1.0
4.0
4.0
tRMXF
1. The symbols used for timing specifications follow the pattern of t(first three letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tRMTKHDX symbolizes RMII
transmit timing (RMT) for the time tRMX clock reference (K) going high (H) until data outputs (D) are invalid (X). Note that, in
general, the clock reference symbol representation is based on two to three letters representing the clock of a particular
functional. For example, the subscript of tRMX represents the RMII(RM) reference (X) clock. For rise and fall times, the latter
convention is used with the appropriate letter: R (rise) or F (fall).
Figure 14 provides the AC test load.
OVDD/2
Output
Z0 = 50
RL = 50
Figure 14. AC Test Load
MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0
Freescale Semiconductor
25
Ethernet and MII Management
Figure 15 shows the RMII transmit AC timing diagram.
tRMXR
tRMX
REF_CLK
tRMXF
tRMXH
TXD[1:0]
TX_EN
tRMTKHDX
Figure 15. RMII Transmit AC Timing Diagram
8.2.2.2
RMII Receive AC Timing Specifications
Table 21 provides the RMII receive AC timing specifications.
Table 23. RMII Receive AC Timing Specifications
At recommended operating conditions with OVDD of 3.3 V ± 300mV.
Parameter/Condition
Symbol1
Min
Typical
Max
Unit
REF_CLK clock period
tRMX
—
35
20
—
—
—
—
—
—
65
—
ns
%
REF_CLK duty cycle
t
RMXH/tRMX
tRMRDVKH
tRMRDXKH
tRMXR
RXD[1:0], CRS_DV, RX_ER setup time to REF_CLK
RXD[1:0], CRS_DV, RX_ER hold time to REF_CLK
REF_CLK clock rise VIL(min) to VIH(max)
REF_CLK clock fall time VIH(max) to VIL(min)
Note:
4.0
2.0
1.0
1.0
ns
ns
ns
ns
—
4.0
4.0
tRMXF
1. The symbols used for timing specifications follow the pattern of t(first three letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tRMRDVKH symbolizes RMII
receive timing (RMR) with respect to the time data input signals (D) reach the valid state (V) relative to the tRMX clock
reference (K) going to the high (H) state or setup time. Also, tRMRDXKL symbolizes RMII receive timing (RMR) with respect
to the time data input signals (D) went invalid (X) relative to the tRMX clock reference (K) going to the low (L) state or hold
time. Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a
particular functional. For example, the subscript of tRMX represents the RMII (RM) reference (X) clock. For rise and fall times,
the latter convention is used with the appropriate letter: R (rise) or F (fall).
MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0
26
Freescale Semiconductor
Ethernet and MII Management
Figure 16 shows the RMII receive AC timing diagram.
tRMXR
tRMX
REF_CLK
tRMXF
Valid Data
tRMXH
RXD[1:0]
CRS_DV
RX_ER
tRMRDVKH
tRMRDXKH
Figure 16. RMII Receive AC Timing Diagram
8.3
Ethernet Management Interface Electrical Characteristics
The electrical characteristics specified here apply to MII management interface signals MDIO
(management data input/output) and MDC (management data clock). The electrical characteristics for
MII, and RMII are specified in Section 8.1, “Ethernet Controller (10/100 Mbps)—MII/RMII Electrical
Characteristics.”
8.3.1
MII Management DC Electrical Characteristics
MDC and MDIO are defined to operate at a supply voltage of 3.3 V. The DC electrical characteristics for
MDIO and MDC are provided in Table 24.
Table 24. MII Management DC Electrical Characteristics When Powered at 3.3 V
Parameter
Symbol
Conditions
Min
Max
Unit
Supply voltage (3.3 V)
Output high voltage
Output low voltage
Input high voltage
Input low voltage
Input current
OVDD
VOH
VOL
VIH
—
3
3.6
OVDD + 0.3
0.50
V
V
IOH = –1.0 mA OVDD = Min
2.40
GND
2.00
—
IOL = 1.0 mA
OVDD = Min
V
—
—
—
V
VIL
0.80
V
IIN
0 V VIN OVDD
—
±5
A
8.3.2
MII Management AC Electrical Specifications
Table 25 provides the MII management AC timing specifications.
Table 25. MII Management AC Timing Specifications
At recommended operating conditions with OVDD is 3.3 V ± 300mV.
Parameter/Condition
MDC frequency
Symbol1
Min
Typical
Max
Unit
Notes
fMDC
tMDC
—
—
32
2.5
400
—
—
—
—
MHz
ns
—
—
—
MDC period
MDC clock pulse width high
tMDCH
ns
MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0
Freescale Semiconductor
27
Ethernet and MII Management
Table 25. MII Management AC Timing Specifications (continued)
At recommended operating conditions with OVDD is 3.3 V ± 300mV.
Parameter/Condition
MDC to MDIO delay
Symbol1
Min
Typical
Max
Unit
Notes
tMDKHDX
tMDDVKH
10
—
—
70
—
ns
ns
—
—
MDIO to MDC setup time
8.5
MDIO to MDC hold time
MDC rise time
MDC fall time
Note:
tMDDXKH
tMDCR
0
—
—
—
—
10
10
ns
ns
ns
—
—
—
—
—
tMDHF
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMDKHDX symbolizes
management data timing (MD) for the time tMDC from clock reference (K) high (H) until data outputs (D) are invalid (X) or data
hold time. Also, tMDDVKH symbolizes management data timing (MD) with respect to the time data input signals (D) reach the
valid state (V) relative to the tMDC clock reference (K) going to the high (H) state or setup time. For rise and fall times, the
latter convention is used with the appropriate letter: R (rise) or F (fall).
Figure 17 shows the MII management AC timing diagram.
tMDC
tMDCR
MDC
tMDCH
tMDCF
MDIO
(Input)
tMDDVKH
tMDDXKH
MDIO
(Output)
tMDKHDX
Figure 17. MII Management Interface Timing Diagram
8.4
IEEE 1588
8.4.1
IEEE 1588 DC Specifications
The IEEE 1588 DC timing specifications are given in Table 27.
8.4.2
IEEE 1588 AC Specifications
The IEEE 1588 AC timing specifications are given in Table 27.
MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0
28
Freescale Semiconductor
Ethernet and MII Management
Table 26. IEEE 1588 DC Electrical Characteristics
Characteristic
Output high voltage
Symbol
Condition
Min
Max
unit
VOH
VOL
IOH = -8.0 mA
IOL = 8.0 mA
IOL = 3.2mA
2.4
—
—
V
V
Output low voltage
Output low voltage
0.5
VOL
—
0.4
V
Input high voltage
Input low voltage
Input current
VIH
VIL
IIN
—
—
2.0
- 0.3
—
OVDD + 0.3
V
V
0.8
± 5
0V ≤ VIN ≤ OVDD
μA
Table 27. IEEE 1588 AC Timing Specifications
At recommended operating conditions with OVDD of 3.3 V ± 300mV.
Parameter/Condition
Symbol
Min
Typ
Max
Unit
Notes
QE_1588_CLK clock period
QE_1588_CLK duty cycle
tT1588CLK
2.5
40
—
50
—
—
TRX_CLK 9
ns
%
1, 3
—
tT1588CLKH T1588CLK
tT1588CLKINJ
tT1588CLKINR
/t
60
250
2.0
QE_1588_CLK peak-to-peak jitter
—
ps
ns
—
Rise time QE_1588_CLK
(20%–80%)
1.0
—
Fall time QE_1588_CLK
(80%–20%)
tT1588CLKINF
1.0
—
2.0
ns
—
QE_1588_CLK_OUT clock period
QE_1588_CLK_OUT duty cycle
tT1588CLKOUT
tT1588CLKOTH
2 tT1588CLK
—
—
ns
%
—
—
30
50
70
/tT1588CLKOUT
QE_1588_PULSE_OUT
QE_1588_TRIG_IN pulse width
Notes:
tT1588OV
0.5
—
—
3.0
—
ns
ns
—
2
tT1588TRIGH
2 tT1588CLK_MAX
1.TRX_CLK is the max clock period of QUICC engine receiving clock selected by TMR_CTRL[CKSEL]. See the MPC8306
PowerQUICC II Pro Integrated Processor Family Reference Manual, for a description of TMR_CTRL registers.
2. It need to be at least two times of clock period of clock selected by TMR_CTRL[CKSEL]. See the MPC8306 PowerQUICC II
Pro Integrated Processor Family Reference Manual, for a description of TMR_CTRL registers.
3. The maximum value of tT1588CLK is not only defined by the value of TRX_CLK, but also defined by the recovered clock. For
example, for 10/100 Mbps modes, the maximum value of tT1588CLK is 3600 and 280ns, respectively.
MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0
Freescale Semiconductor
29
TDM/SI
Figure 18 provides the data and command output timing diagram.
tT1588CLKOUT
tT1588CLKOUTH
TSEC_1588_CLK_OUT
tT1588OV
TSEC_1588_PULSE_OUT
TSEC_1588_TRIG_OUT
Note: The output delay is count starting rising edge if tT1588CLKOUT is non-inverting. Otherwise, it is
count starting falling edge.
Figure 18. IEEE 1588 Output AC Timing
Figure 19 provides the data and command input timing diagram.
tT1588CLK
tT1588CLKH
TSEC_1588_CLK
TSEC_1588_TRIG_IN
tT1588TRIGH
Figure 19. IEEE 1588 Input AC Timing
9 TDM/SI
This section describes the DC and AC electrical specifications for the time-division-multiplexed and serial
interface of the MPC8306.
9.1
TDM/SI DC Electrical Characteristics
Table 28 provides the DC electrical characteristics for the MPC8306 TDM/SI.
Table 28. TDM/SI DC Electrical Characteristics
Characteristic
Output high voltage
Symbol
Condition
Min
Max
Unit
VOH
VOL
VIH
VIL
IOH = –2.0 mA
2.4
—
—
0.5
V
V
Output low voltage
Input high voltage
Input low voltage
Input current
IOL = 3.2 mA
—
—
2.0
–0.3
—
OVDD + 0.3
0.8
V
V
IIN
0 V VIN OVDD
±5
A
MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0
30
Freescale Semiconductor
TDM/SI
9.2
TDM/SI AC Timing Specifications
Table 29 provides the TDM/SI input and output AC timing specifications.
1
Table 29. TDM/SI AC Timing Specifications
Characteristic
Symbol2
Min
Max
Unit
TDM/SI outputs—External clock delay
tSEKHOV
2
14
ns
TDM/SI outputs—External clock High Impedance
TDM/SI inputs—External clock input setup time
TDM/SI inputs—External clock input hold time
Notes:
tSEKHOX
tSEIVKH
tSEIXKH
2
5
2
10
—
—
ns
ns
ns
1. Output specifications are measured from the 50% level of the rising edge of QE_CLK_IN to the 50% level of the signal.
Timings are measured at the pin.
2. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tSEKHOX symbolizes the TDM/SI
outputs external timing (SE) for the time tTDM/SI memory clock reference (K) goes from the high state (H) until outputs (O)
are invalid (X).
Figure 20 provides the AC test load for the TDM/SI.
OVDD/2
Output
Z0 = 50
RL = 50
Figure 20. TDM/SI AC Test Load
MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0
Freescale Semiconductor
31
HDLC
Figure 21 represents the AC timing from Table 29. Note that although the specifications generally
reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge is the
active edge.
TDM/SICLK (Input)
tSEIXKH
tSEIVKH
Input Signals:
TDM/SI
(See Note)
tSEKHOV
Output Signals:
TDM/SI
(See Note)
tSEKHOX
Note: The clock edge is selectable on TDM/SI.
Figure 21. TDM/SI AC Timing (External Clock) Diagram
10 HDLC
This section describes the DC and AC electrical specifications for the high level data link control (HDLC),
of the MPC8306.
10.1 HDLC DC Electrical Characteristics
Table 30 provides the DC electrical characteristics for the MPC8306 HDLC protocol.
Table 30. HDLC DC Electrical Characteristics
Characteristic
Output high voltage
Symbol
Condition
Min
Max
Unit
VOH
VOL
VIH
VIL
IOH = –2.0 mA
2.4
—
—
0.5
V
V
Output low voltage
Input high voltage
Input low voltage
Input current
IOL = 3.2 mA
—
—
2.0
–0.3
—
OVDD + 0.3
0.8
V
V
IIN
0 V VIN OVDD
±5
A
10.2 HDLC AC Timing Specifications
Table 31 provides the input and output AC timing specifications for HDLC protocol.
1
Table 31. HDLC AC Timing Specifications
Characteristic
Outputs—Internal clock delay
Symbol2
Min
Max
Unit
tHIKHOV
0
9
ns
Outputs—External clock delay
tHEKHOV
tHIKHOX
1
0
12
ns
ns
Outputs—Internal clock high impedance
5.5
MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0
32
Freescale Semiconductor
HDLC
1
Table 31. HDLC AC Timing Specifications (continued)
Characteristic
Symbol2
Min
Max
Unit
Outputs—External clock high impedance
Inputs—Internal clock input setup time
tHEKHOX
tHIIVKH
1
9
8
ns
ns
—
Inputs—External clock input setup time
Inputs—Internal clock input hold time
Inputs—External clock input hold time
Notes:
tHEIVKH
tHIIXKH
tHEIXKH
4
0
1
—
—
—
ns
ns
ns
1. Output specifications are measured from the 50% level of the rising edge of QE_CLK_IN to the 50% level of the signal.
Timings are measured at the pin.
2. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tHIKHOX symbolizes the outputs
internal timing (HI) for the time tserial memory clock reference (K) goes from the high state (H) until outputs (O) are invalid (X).
Figure 22 provides the AC test load.
OVDD/2
Output
Z0 = 50
RL = 50
Figure 22. AC Test Load
Figure 23 and Figure 24 represent the AC timing from Table 31. Note that although the specifications
generally reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge
is the active edge.
Figure 23 shows the timing with external clock.
Serial CLK (Input)
tHEIXKH
tHEIVKH
Input Signals:
(See Note)
tHEKHOV
Output Signals:
(See Note)
tHEKHOX
Note: The clock edge is selectable.
Figure 23. AC Timing (External Clock) Diagram
MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0
Freescale Semiconductor
33
USB
Figure 24 shows the timing with internal clock.
Serial CLK (Output)
tHIIXKH
tHIIVKH
Input Signals:
(See Note)
tHIKHOV
Output Signals:
(See Note)
tHIKHOX
Note: The clock edge is selectable.
Figure 24. AC Timing (Internal Clock) Diagram
11 USB
11.1 USB Controller
This section provides the AC and DC electrical specifications for the USB (ULPI) interface.
11.1.1 USB DC Electrical Characteristics
Table 32 provides the DC electrical characteristics for the USB interface.
Table 32. USB DC Electrical Characteristics
Parameter
High-level input voltage
Symbol
Min
Max
Unit
VIH
VIL
2.0
–0.3
OVDD + 0.3
V
V
Low-level input voltage
0.8
±5
Input current
IIN
—
A
V
High-level output voltage, IOH = –100 A
Low-level output voltage, IOL = 100 A
VOH
VOL
OVDD – 0.2
—
—
0.2
V
11.1.2 USB AC Electrical Specifications
Table 33 describes the general timing parameters of the USB interface.
Table 33. USB General Timing Parameters
Parameter
Symbol1
Min
Max
Unit
Notes
USB clock cycle time
tUSCK
tUSIVKH
tUSIXKH
tUSKHOV
15
4
—
—
—
7
ns
ns
ns
ns
Input setup to USB clock—all inputs
input hold to USB clock—all inputs
1
USB clock to output valid—all outputs (except
USBDR_STP_USBDR_STP)
—
MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0
34
Freescale Semiconductor
USB
Table 33. USB General Timing Parameters (continued)
Parameter
Symbol1
Min
Max
Unit
Notes
USB clock to output valid—USBDR_STP
Output hold from USB clock—all outputs
Note:
tUSKHOV
tUSKHOX
—
2
7.5
—
ns
ns
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tUSIXKH symbolizes USB timing
(USB) for the input (I) to go invalid (X) with respect to the time the USB clock reference (K) goes high (H). Also, tUSKHOX
symbolizes us timing (USB) for the USB clock reference (K) to go high (H), with respect to the output (O) going invalid (X) or
output hold time.
Figure 25 and Figure 26 provide the AC test load and signals for the USB, respectively.
Output
OVDD/2
Z0 = 50
RL = 50
Figure 25. USB AC Test Load
USBDR_CLK
tUSIXKH
tUSIVKH
Input Signals
tUSKHOV
tUSKHOX
Output Signals
Figure 26. USB Signals
MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0
Freescale Semiconductor
35
DUART
12 DUART
This section describes the DC and AC electrical specifications for the DUART interface of the MPC8306.
12.1 DUART DC Electrical Characteristics
Table 34 provides the DC electrical characteristics for the DUART interface of the MPC8306.
Table 34. DUART DC Electrical Characteristics
Parameter
Symbol
Min
Max
Unit
High-level input voltage
VIH
VIL
2
–0.3
OVDD + 0.3
V
V
Low-level input voltage OVDD
0.8
—
High-level output voltage, IOH = –100 A
VOH
VOL
IIN
OVDD – 0.2
—
V
Low-level output voltage, IOL = 100 A
0.2
±5
V
1
Input current (0 V VIN OVDD
)
—
A
Note:
1. Note that the symbol VIN, in this case, represents the OVIN symbol referenced in Table 1 and Table 2.
12.2 DUART AC Electrical Specifications
Table 35 provides the AC timing parameters for the DUART interface of the MPC8306.
Table 35. DUART AC Timing Specifications
Parameter
Value
Unit
Notes
Minimum baud rate
Maximum baud rate
Oversample rate
Notes:
256
>1,000,000
16
baud
baud
—
1
2
1. Actual attainable baud rate is limited by the latency of interrupt processing.
2. The middle of a start bit is detected as the 8th sampled 0 after the 1-to-0 transition of the start bit. Subsequent bit values are
sampled each 16th sample.
MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0
36
Freescale Semiconductor
eSDHC
13 eSDHC
This section describes the DC and AC electrical specifications for the eSDHC interface of the device.
13.1 eSDHC DC Electrical Characteristics
Table 36 provides the DC electrical characteristics for the eSDHC interface.
Table 36. eSDHC Interface DC Electrical Characteristics
At recommended operating conditions with OVDD = 3.3 V
Characteristic
Input high voltage
Symbol
Condition
Min
Max
Unit
Notes
VIH
VIL
—
—
0.625 OVDD
—
—
0.25 OVDD
—
V
V
V
1
1
Input low voltage
Output high voltage
VOH
IOH = –100 A at
0.75 OVDD
—
OVDD min
Output low voltage
VOL
IOL = 100 A at
—
0.125 OVDD
V
—
OVDD min
Output high voltage
Output low voltage
Input/output leakage current
Note:
VOH
VOL
IOH = –100 mA
IOL = 2 mA
—
OVDD – 0.2
—
0.3
10
V
V
2
2
—
IIN/IOZ
–10
A
—
1. Note that the min VILand max VIH values are based on the respective min and max OVIN values found in Table 2..
2. Open drain mode for MMC cards only.
13.2 eSDHC AC Timing Specifications
Table 37 provides the eSDHC AC timing specifications as defined in Figure 27 and Figure 28.
Table 37. eSDHC AC Timing Specifications
At recommended operating conditions with OVDD = 3.3 V
Parameter
SD_CLK clock frequency:
SD/SDIO Full-speed/High-speed mode
MMC Full-speed/High-speed mode
Symbol1
Min
Max
Unit
Notes
fSHSCK
0
25/33.25
20/52
MHz
2, 4
SD_CLK clock low time—Full-speed/High-speed mode
SD_CLK clock high time—Full-speed/High-speed mode
SD_CLK clock rise and fall times
tSHSCKL
tSHSCKH
tSHSCKR/
10/7
10/7
—
—
—
3
ns
ns
ns
4
4
4
tSHSCKF
Input setup times: SD_CMD, SD_DATx, SD_CD to
SD_CLK
tSHSIVKH
5
—
ns
4
MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0
Freescale Semiconductor
37
eSDHC
Table 37. eSDHC AC Timing Specifications (continued)
At recommended operating conditions with OVDD = 3.3 V
Parameter
Symbol1
Min
Max
Unit
Notes
Input hold times: SD_CMD, SD_DATx, SD_CD to
SD_CLK
tSHSIXKH
2.5
—
ns
3, 4
Output delay time: SD_CLK to SD_CMD, SD_DATx valid
tSHSKHOV
–3
3
ns
4
Notes:
1. The symbols used for timing specifications herein follow the pattern of t(first three letters of functional block)(signal)(state)
(reference)(state) for inputs and t(first three letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tFHSKHOV
symbolizes eSDHC high-speed mode device timing (SHS) clock reference (K) going to the high (H) state, with respect to the
output (O) reaching the invalid state (X) or output hold time. Note that in general, the clock reference symbol is based on five
letters representing the clock of a particular functional. For rise and fall times, the latter convention is used with the
appropriate letter: R (rise) or F (fall).
2. In full-speed mode, the clock freqency value can be 0–25 MHz for an SD/SDIO card and 0–20 MHz for an MMC card. In
high-speed mode, the clock freqency value can be 0–33.25 MHz for an SD/SDIO card and 0–52 MHz for an MMC card.
3. To satisfy hold timing, the delay difference between clock input and cmd/data input must not exceed 2 ns.
4. CCARD 10 pF, (1 card), and CL = CBUS + CHOST + CCARD 40 pF
Figure 27 provides the eSDHC clock input timing diagram.
eSDHC
External Clock
VM
VM
VM
operational mode
tSHSCKL
tSHSCKH
tSHSCK
tSHSCKF
tSHSCKR
VM = Midpoint Voltage (OVDD/2)
Figure 27. eSDHC Clock Input Timing Diagram
Figure 28 provides the data and command input/output timing diagram.
VM
VM
VM
VM
SD_CK
External Clock
tSHSIXKH
tSHSIVKH
SD_DAT/CMD
Inputs
SD_DAT/CMD
Outputs
tSHSKHOV
VM = Midpoint Voltage (OVDD/2)
Figure 28. eSDHC Data and Command Input/Output Timing Diagram Referenced to Clock
MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0
38
Freescale Semiconductor
FlexCAN
14 FlexCAN
This section describes the DC and AC electrical specifications for the FlexCAN interface.
14.1 FlexCAN DC Electrical Characteristics
Table 38 provides the DC electrical characteristics for the FlexCAN interface.
Table 38. FlexCAN DC Electrical Characteristics (3.3V)
For recommended operating conditions, see Table 2
Parameter
Symbol
Min
Max
Unit
Notes
Input high voltage
Input low voltage
VIH
VIL
2
—
0.8
±5
—
V
V
1
1
—
—
2.4
—
Input current (OVIN = 0 V or OVIN = OVDD
)
IIN
A
V
2
Output high voltage (OVDD = min, IOH = –2 mA)
Output low voltage (OVDD = min, IOL = 2 mA)
Note:
VOH
VOL
—
—
0.4
V
1. Note that the min VILand max VIH values are based on the respective min and max OVIN values found in Table 2.
2. Note that the symbol OVIN represents the input voltage of the supply. It is referenced in Table 2.
14.2 FlexCAN AC Timing Specifications
Table 39 provides the AC timing specifications for the FlexCAN interface.
Table 39. FlexCAN AC Timing Specifications
For recommended operating conditions, see Table 2
Parameter
Baud rate
Min
Max
Unit
Notes
10
1000
Kbps
—
MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0
Freescale Semiconductor
39
I2C
15 I2C
2
This section describes the DC and AC electrical characteristics for the I C interface of the MPC8306.
2
15.1 I C DC Electrical Characteristics
2
Table 40 provides the DC electrical characteristics for the I C interface of the MPC8306.
2
Table 40. I C DC Electrical Characteristics
At recommended operating conditions with OVDD of 3.3 V ± 300mV.
Parameter
Symbol
Min
Max
Unit
Notes
Input high voltage level
Input low voltage level
VIH
VIL
0.7 OVDD
OVDD + 0.3
0.3 OVDD
0.4
V
V
—
—
1
–0.3
0
Low level output voltage
VOL
V
Output fall time from VIH(min) to VIL(max) with a bus
capacitance from 10 to 400 pF
t
20 + 0.1 CB
250
ns
2
I2KLKV
Pulse width of spikes which must be suppressed by the
input filter
tI2KHKL
0
50
ns
3
Capacitance for each I/O pin
CI
—
—
10
±5
pF
—
4
Input current (0 V VIN OVDD
)
IIN
A
Notes:
1. Output voltage (open drain or open collector) condition = 3 mA sink current.
2. CB = capacitance of one bus line in pF.
3. Refer to the MPC8306 PowerQUICC II Pro Integrated Communications Processor Reference Manual for information on
the digital filter used.
4. I/O pins obstructs the SDA and SCL lines if OVDD is switched off.
2
15.2 I C AC Electrical Specifications
2
Table 41 provides the AC timing parameters for the I C interface of the MPC8306.
2
Table 41. I C AC Electrical Specifications
All values refer to VIH (min) and VIL (max) levels (see Table 40).
Parameter
Symbol1
Min
Max
Unit
SCL clock frequency
fI2C
tI2CL
0
400
—
kHz
s
Low period of the SCL clock
High period of the SCL clock
1.3
0.6
0.6
0.6
tI2CH
—
s
Setup time for a repeated START condition
tI2SVKH
tI2SXKL
—
s
Hold time (repeated) START condition (after this period, the first clock
pulse is generated)
—
s
Data setup time
tI2DVKH
tI2DXKL
tI2CR
100
300
—
ns
s
ns
Data hold time: I2C bus devices
0.93
4
Rise time of both SDA and SCL signals
20 + 0.1 CB
300
MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0
40
Freescale Semiconductor
I2C
2
Table 41. I C AC Electrical Specifications (continued)
All values refer to VIH (min) and VIL (max) levels (see Table 40).
Parameter
Symbol1
Min
Max
Unit
4
Fall time of both SDA and SCL signals
Setup time for STOP condition
20 + 0.1 CB
300
—
ns
s
s
V
t
I2CF
t
0.6
1.3
I2PVKH
Bus free time between a STOP and START condition
tI2KHDX
VNL
—
Noise margin at the LOW level for each connected device (including
hysteresis)
0.1 OVDD
—
Noise margin at the HIGH level for each connected device (including
hysteresis)
VNH
0.2 OVDD
—
V
Notes:
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tI2DVKH symbolizes I2C timing (I2)
with respect to the time data input signals (D) reach the valid state (V) relative to the tI2C clock reference (K) going to the high
(H) state or setup time. Also, tI2SXKL symbolizes I2C timing (I2) for the time that the data with respect to the start condition
(S) went invalid (X) relative to the tI2C clock reference (K) going to the low (L) state or hold time. Also, tI2PVKH symbolizes I2C
timing (I2) for the time that the data with respect to the stop condition (P) reaching the valid state (V) relative to the tI2C clock
reference (K) going to the high (H) state or setup time. For rise and fall times, the latter convention is used with the appropriate
letter: R (rise) or F (fall).
2. MPC8306 provides a hold time of at least 300 ns for the SDA signal (referred to the VIH(min) of the SCL signal) to bridge
the undefined region of the falling edge of SCL.
3. The maximum tI2DVKL has only to be met if the device does not stretch the LOW period (tI2CL) of the SCL signal.
4. CB = capacitance of one bus line in pF.
2
Figure 29 provides the AC test load for the I C.
OVDD/2
Output
Z0 = 50
RL = 50
2
Figure 29. I C AC Test Load
2
Figure 30 shows the AC timing diagram for the I C bus.
SDA
tI2CF
tI2CL
tI2DVKH
tI2KHKL
tI2CF
tI2SXKL
tI2CR
SCL
tI2SXKL
tI2CH
tI2SVKH
tI2PVKH
tI2DXKL
S
Sr
Figure 30. I C Bus AC Timing Diagram
P
S
2
MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0
Freescale Semiconductor
41
Timers
16 Timers
This section describes the DC and AC electrical specifications for the timers of the MPC8306.
16.1 Timer DC Electrical Characteristics
Table 42 provides the DC electrical characteristics for the MPC8306 timer pins, including TIN, TOUT,
TGATE, and RTC_PIT_CLK.
Table 42. Timer DC Electrical Characteristics
Characteristic
Output high voltage
Symbol
Condition
Min
Max
Unit
VOH
VOL
IOH = –6.0 mA
IOL = 6.0 mA
2.4
—
—
0.5
V
V
Output low voltage
Output low voltage
Input high voltage
Input low voltage
Input current
V
I
= 3.2 mA
OL
—
0.4
V
OL
VIH
VIL
IIN
—
—
2.0
–0.3
—
OVDD + 0.3
0.8
V
V
0 V VIN OVDD
±5
A
16.2 Timer AC Timing Specifications
Table 43 provides the timer input and output AC timing specifications.
1
Table 43. Timer Input AC Timing Specifications
Characteristic
Timers inputs—minimum pulse width
Notes:
Symbol2
tTIWID
Min
Unit
20
ns
1. Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of SYS_CLK_IN.
Timings are measured at the pin.
2. Timer inputs and outputs are asynchronous to any visible clock. Timer outputs should be synchronized before use by any
external synchronous logic. Timer inputs are required to be valid for at least tTIWID ns to ensure proper operation.
Figure 31 provides the AC test load for the timers.
OVDD/2
Output
Z0 = 50
RL = 50
Figure 31. Timers AC Test Load
MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0
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Freescale Semiconductor
GPIO
17 GPIO
This section describes the DC and AC electrical specifications for the GPIO of the MPC8306.
17.1 GPIO DC Electrical Characteristics
Table 11 provides the DC electrical characteristics for the MPC8306 GPIO.
Table 44. GPIO DC Electrical Characteristics
Characteristic
Output high voltage
Symbol
Condition
Min
Max
Unit
Notes
VOH
VOL
IOH = –6.0 mA
IOL = 6.0 mA
2.4
—
—
0.5
V
V
1
1
Output low voltage
Output low voltage
Input high voltage
Input low voltage
Input current
V
I
= 3.2 mA
OL
—
0.4
V
1
OL
VIH
VIL
IIN
—
—
2.0
–0.3
—
OVDD + 0.3
0.8
V
1
V
—
—
0 V VIN OVDD
±5
A
Note:
1. This specification applies when operating from 3.3-V supply.
17.2 GPIO AC Timing Specifications
Table 45 provides the GPIO input and output AC timing specifications.
1
Table 45. GPIO Input AC Timing Specifications
Characteristic
GPIO inputs—minimum pulse width
Notes:
Symbol2
Min
20
Unit
tPIWID
ns
1. Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of SYS_CLK_IN.
Timings are measured at the pin.
2. GPIO inputs and outputs are asynchronous to any visible clock. GPIO outputs should be synchronized before use by any
external synchronous logic. GPIO inputs are required to be valid for at least tPIWID ns to ensure proper operation.
Figure 32 provides the AC test load for the GPIO.
OVDD/2
Output
Z0 = 50
RL = 50
Figure 32. GPIO AC Test Load
MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0
Freescale Semiconductor
43
IPIC
18 IPIC
This section describes the DC and AC electrical specifications for the external interrupt pins of the
MPC8306.
18.1 IPIC DC Electrical Characteristics
Table 46 provides the DC electrical characteristics for the external interrupt pins of the MPC8306.
1,2
Table 46. IPIC DC Electrical Characteristics
Characteristic
Input high voltage
Symbol
Condition
Min
Max
Unit
VIH
VIL
—
—
2.0
–0.3
—
OVDD + 0.3
V
V
Input low voltage
Input current
0.8
±5
IIN
—
A
V
Output High Voltage
Output low voltage
Output low voltage
Notes:
VOH
VOL
IOL = -8.0 mA
IOL = 6.0 mA
2.4
—
—
0.5
0.4
V
V
I
= 3.2 mA
OL
—
V
OL
1. This table applies for pins IRQ, MCP_OUT, and QE ports Interrupts.
2. MCP_OUT is open drain pins, thus VOH is not relevant for those pins.
18.2 IPIC AC Timing Specifications
Table 47 provides the IPIC input and output AC timing specifications.
1
Table 47. IPIC Input AC Timing Specifications
Characteristic
Symbol2
Min
Unit
IPIC inputs—minimum pulse width
tPIWID
20
ns
Notes:
1. Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of SYS_CLK_IN.
Timings are measured at the pin.
2. IPIC inputs and outputs are asynchronous to any visible clock. IPIC outputs should be synchronized before use by any
external synchronous logic. IPIC inputs are required to be valid for at least tPIWID ns to ensure proper operation when working
in edge triggered mode.
19 SPI
This section describes the DC and AC electrical specifications for the SPI of the MPC8306.
19.1 SPI DC Electrical Characteristics
Table 48 provides the DC electrical characteristics for the MPC8306 SPI.
MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0
44
Freescale Semiconductor
SPI
Table 48. SPI DC Electrical Characteristics
Characteristic
Output high voltage
Symbol
Condition
Min
Max
Unit
VOH
VOL
IOH = –6.0 mA
IOL = 6.0 mA
2.4
—
—
0.5
V
V
Output low voltage
Output low voltage
Input high voltage
Input low voltage
Input current
V
I
= 3.2 mA
OL
—
0.4
V
OL
VIH
VIL
IIN
—
—
2.0
–0.3
—
OVDD + 0.3
0.8
V
V
0 V VIN OVDD
±5
A
19.2 SPI AC Timing Specifications
Table 49 and provide the SPI input and output AC timing specifications.
1
Table 49. SPI AC Timing Specifications
Characteristic
Symbol2
Min
Max
Unit
SPI outputs—Master mode (internal clock) delay
SPI outputs—Slave mode (external clock) delay
SPI inputs—Master mode (internal clock) input setup time
SPI inputs—Master mode (internal clock) input hold time
SPI inputs—Slave mode (external clock) input setup time
SPI inputs—Slave mode (external clock) input hold time
Notes:
tNIKHOV
tNEKHOV
tNIIVKH
0.5
2
6
ns
ns
ns
ns
ns
ns
8
6
—
—
—
—
tNIIXKH
0
tNEIVKH
tNEIXKH
4
2
1. Output specifications are measured from the 50% level of the rising edge of SPICLK to the 50% level of the signal. Timings
are measured at the pin.
2. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tNIKHOV symbolizes the NMSI
outputs internal timing (NI) for the time tSPI memory clock reference (K) goes from the high state (H) until outputs (O) are
valid (V).
3. All units of output delay must be enabled for 8306 output port spimosi (SPI Master Mode)
4. delay units must not be enabled for Slave Mode.
Figure 33 provides the AC test load for the SPI.
OVDD/2
Output
Z0 = 50
RL = 50
Figure 33. SPI AC Test Load
Figure 34 and Figure 35 represent the AC timing from Table 49. Note that although the specifications
generally reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge
is the active edge.
MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0
Freescale Semiconductor
45
JTAG
Figure 34 shows the SPI timing in slave mode (external clock).
SPICLK (Input)
tNEIXKH
tNEIVKH
Input Signals:
SPIMOSI
(See Note)
tNEKHOV
Output Signals:
SPIMISO
(See Note)
Note: The clock edge is selectable on SPI.
Figure 34. SPI AC Timing in Slave Mode (External Clock) Diagram
Figure 35 shows the SPI timing in master mode (internal clock).
SPICLK (Output)
tNIIXKH
tNIIVKH
Input Signals:
SPIMISO
(See Note)
tNIKHOV
Output Signals:
SPIMOSI
(See Note)
Note: The clock edge is selectable on SPI.
Figure 35. SPI AC Timing in Master Mode (Internal Clock) Diagram
20 JTAG
This section describes the DC and AC electrical specifications for the IEEE Std. 1149.1™ (JTAG)
interface of the MPC8306.
20.1 JTAG DC Electrical Characteristics
Table 50 provides the DC electrical characteristics for the IEEE Std. 1149.1 (JTAG) interface of the
MPC8306.
Table 50. JTAG Interface DC Electrical Characteristics
Characteristic
Output high voltage
Symbol
Condition
Min
Max
Unit
VOH
VOL
IOH = –6.0 mA
IOL = 6.0 mA
2.4
—
—
V
V
V
Output low voltage
Output low voltage
0.5
0.4
V
I
= 3.2 mA
OL
—
OL
MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0
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Freescale Semiconductor
JTAG
Table 50. JTAG Interface DC Electrical Characteristics (continued)
Characteristic
Input high voltage
Symbol
Condition
Min
Max
Unit
VIH
VIL
IIN
—
—
2.0
–0.3
—
OVDD + 0.3
V
V
Input low voltage
Input current
0.8
±5
0 V VIN OVDD
A
20.2 JTAG AC Electrical Characteristics
This section describes the AC electrical specifications for the IEEE Std. 1149.1 (JTAG) interface of the
MPC8306. Table 51 provides the JTAG AC timing specifications as defined in Figure 37 through
Figure 40.
1
Table 51. JTAG AC Timing Specifications (Independent of SYS_CLK_IN)
At recommended operating conditions (see Table 2).
Parameter
Symbol2
Min
Max
Unit
Notes
JTAG external clock frequency of operation
JTAG external clock cycle time
JTAG external clock pulse width measured at 1.4 V
JTAG external clock rise and fall times
TRST assert time
fJTG
t JTG
0
33.3
—
MHz
ns
—
—
—
—
3
30
11
0
tJTKHKL
tJTGR, tJTGF
tTRST
—
ns
2
ns
25
—
ns
Input setup times:
ns
Boundary-scan data
tJTDVKH
tJTIVKH
4
4
—
—
4
4
5
TMS, TDI
Input hold times:
Valid times:
ns
ns
Boundary-scan data
TMS, TDI
tJTDXKH
tJTIXKH
10
10
—
—
Boundary-scan data
TDO
tJTKLDV
tJTKLOV
2
2
15
15
MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0
Freescale Semiconductor
47
JTAG
1
Table 51. JTAG AC Timing Specifications (Independent of SYS_CLK_IN) (continued)
At recommended operating conditions (see Table 2).
Parameter
Symbol2
Min
Max
Unit
Notes
Output hold times:
ns
Boundary-scan data
TDO
tJTKLDX
tJTKLOX
2
2
—
—
5
JTAG external clock to output high impedance:
ns
Boundary-scan data
TDO
tJTKLDZ
tJTKLOZ
2
2
19
9
5, 6
6
Notes:
1. All outputs are measured from the midpoint voltage of the falling/rising edge of tTCLK to the midpoint of the signal in question.
The output timings are measured at the pins. All output timings assume a purely resistive 50-load (see Figure 36).
Time-of-flight delays must be added for trace lengths, vias, and connectors in the system.
2. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tJTDVKH symbolizes JTAG device
timing (JT) with respect to the time data input signals (D) reaching the valid state (V) relative to the tJTG clock reference (K)
going to the high (H) state or setup time. Also, tJTDXKH symbolizes JTAG timing (JT) with respect to the time data input signals
(D) went invalid (X) relative to the tJTG clock reference (K) going to the high (H) state. Note that, in general, the clock reference
symbol representation is based on three letters representing the clock of a particular functional. For rise and fall times, the
latter convention is used with the appropriate letter: R (rise) or F (fall).
3. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.
4. Non-JTAG signal input timing with respect to tTCLK
.
5. Non-JTAG signal output timing with respect to tTCLK
6. Guaranteed by design and characterization.
.
Figure 36 provides the AC test load for TDO and the boundary-scan outputs of the MPC8306.
OVDD/2
Output
Z0 = 50
RL = 50
Figure 36. AC Test Load for the JTAG Interface
Figure 37 provides the JTAG clock input timing diagram.
JTAG
External Clock
VM
tJTKHKL
VM
VM
tJTGR
tJTGF
tJTG
VM = Midpoint Voltage (OV /2)
DD
Figure 37. JTAG Clock Input Timing Diagram
Figure 38 provides the TRST timing diagram.
TRST
VM
VM
tTRST
VM = Midpoint Voltage (OV /2)
DD
Figure 38. TRST Timing Diagram
MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0
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Freescale Semiconductor
JTAG
Figure 39 provides the boundary-scan timing diagram.
JTAG
VM
VM
External Clock
tJTDVKH
tJTDXKH
Input
Data Valid
Boundary
Data Inputs
tJTKLDV
tJTKLDX
Boundary
Data Outputs
Output Data Valid
tJTKLDZ
Output Data Valid
Boundary
Data Outputs
VM = Midpoint Voltage (OV /2)
DD
Figure 39. Boundary-Scan Timing Diagram
Figure 40 provides the test access port timing diagram.
JTAG
VM
VM
External Clock
tJTIVKH
tJTIXKH
Input
TDI, TMS
TDO
Data Valid
tJTKLOV
tJTKLOX
Output Data Valid
tJTKLOZ
Output Data Valid
TDO
VM = Midpoint Voltage (OV /2)
DD
Figure 40. Test Access Port Timing Diagram
MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0
Freescale Semiconductor
49
Package and Pin Listings
21 Package and Pin Listings
This section details package parameters, pin assignments, and dimensions. The MPC8306 is available in
a thermally enhanced MAPBGA (mold array process-ball grid array); see Section 21.1, “Package
Parameters for the MPC8306,” and Section 21.2, “Mechanical Dimensions of the MPC8306 MAPBGA,”
for information on the MAPBGA.
21.1 Package Parameters for the MPC8306
The package parameters are as provided in the following list.
Package outline
Package Type
Interconnects
19 mm 19 mm
MAPBGA
369
Pitch
0.80 mm
Module height (typical)
Solder Balls
1.48 mm; Min = 1.31mm and Max 1.61mm
96 Sn / 3.5 Ag / 0.5 Cu (VM package)
0.40 mm
Ball diameter (typical)
21.2 Mechanical Dimensions of the MPC8306 MAPBGA
Figure below shows the mechanical dimensions and bottom surface nomenclature of the
MPC8306, 369-MAPBGA package.
MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0
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Freescale Semiconductor
Package and Pin Listings
Figure 41. Mechanical Dimensions and Bottom Surface Nomenclature of the MPC8306 MAPBGA
Notes:
1. All dimensions are in millimeters.
2. Dimensions and tolerances per ASME Y14.5M-1994.
3. Maximum solder ball diameter measured parallel to datum A.
4. Datum A, the seating plane, is determined by the spherical crowns of the solder balls.
MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0
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51
Package and Pin Listings
21.3 Pinout Listings
Following table shows the pin list of the MPC8306.
Table 52. MPC8306Pinout Listing
Signal
Package Pin Number
Pin Type
Power Supply
Notes
DDR Memory Controller Interface
MEMC_MDQ[0]
MEMC_MDQ[1]
MEMC_MDQ[2]
MEMC_MDQ[3]
MEMC_MDQ[4]
MEMC_MDQ[5]
MEMC_MDQ[6]
MEMC_MDQ[7]
MEMC_MDQ[8]
MEMC_MDQ[9]
MEMC_MDQ[10]
MEMC_MDQ[11]
MEMC_MDQ[12]
MEMC_MDQ[13]
MEMC_MDQ[14]
MEMC_MDQ[15]
MEMC_MDM[0]
MEMC_MDM[1]
MEMC_MDQS[0]
MEMC_MDQS[1]
MEMC_MBA[0]
MEMC_MBA[1]
MEMC_MBA[2]
MEMC_MA[0]
W5
V4
Y4
AB1
AA1
Y2
Y1
W2
G2
G1
F1
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
O
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
E2
E1
E4
F4
D1
AB2
G4
V5
F5
O
IO
IO
O
L2
L1
O
R4
M1
M4
N1
N2
P1
N4
P2
R1
O
O
MEMC_MA[1]
O
MEMC_MA[2]
O
MEMC_MA[3]
O
MEMC_MA[4]
O
MEMC_MA[5]
O
MEMC_MA[6]
O
MEMC_MA[7]
O
MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0
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Freescale Semiconductor
Package and Pin Listings
Table 52. MPC8306Pinout Listing (continued)
Signal
Package Pin Number
Pin Type
Power Supply
Notes
MEMC_MA[8]
T1
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
MEMC_MA[9]
P4
MEMC_MA[10]
MEMC_MA[11]
MEMC_MA[12]
MEMC_MA[13]
MEMC_MWE_B
MEMC_MRAS_B
MEMC_MCAS_B
MEMC_MCS_B[0]
MEMC_MCS_B[1]
MEMC_MCKE[0]
MEMC_MCK[0]
MEMC_MCK_B[0]
MEMC_MODT[0]
MEMC_MODT[1]
MEMC_MVREF
L4
T2
U1
U2
K1
K2
J1
J4
H1
U4
V1
W1
H2
H4
L8
Local Bus Controller Interface
LAD[0]
LAD[1]
LAD[2]
LAD[3]
LAD[4]
LAD[5]
LAD[6]
LAD[7]
LAD[8]
LAD[9]
LAD[10]
LAD[11]
LAD[12]
LAD[13]
LAD[14]
LAD[15]
LA[16]
B7
D9
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
A6
B8
A7
A8
A9
D10
B10
A10
B11
D12
D11
A11
A12
B13
A13
MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0
Freescale Semiconductor
53
Package and Pin Listings
Table 52. MPC8306Pinout Listing (continued)
Signal
Package Pin Number
Pin Type
Power Supply
Notes
LA[17]
B14
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
IO
O
O
O
O
O
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
—
—
—
—
—
—
—
—
—
3
LA[18]
A14
LA[19]
A15
LA[20]
A16
LA[21]
B16
LA[22]
A17
LA[23]
B17
LA[24]
A18
LA[25]
B19
LCS_B[0]
LCS_B[1]
LCS_B[2]
LCS_B[3]
LCLK[0]
LGPL[0]
LGPL[1]
LGPL[2]
LGPL[3]
LGPL[4]
LGPL[5]
LWE_B[0]
LWE_B[1]
LBCTL
A19
B20
3
A20
3
A21
3
D13
—
—
—
—
—
—
—
—
—
—
—
B22
D16
D19
D17
E18
E19
D15
D14
A22
LALE
B23
JTAG
TCK
A3
I
I
OVDD
OVDD
OVDD
OVDD
OVDD
—
3
TDI
B5
TDO
D7
O
I
—
3
TMS
A4
TRST_B
D8
I
3
Test Interface
TEST_MODE
A5
I
OVDD
—
System Control Signals
HRESET_B
U20
V20
IO
I
OVDD
OVDD
1
PORESET_B
—
MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0
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Freescale Semiconductor
Package and Pin Listings
Table 52. MPC8306Pinout Listing (continued)
Signal
Package Pin Number
Pin Type
Power Supply
Notes
Clock Interface
QE_CLK_IN
P23
I
I
I
OVDD
OVDD
OVDD
—
—
—
SYS_CLK_IN
RTC_PIT_CLOCK
R23
V23
Miscellaneous Signals
QUIESCE_B
THERM0
A2
D6
O
I
OVDD
OVDD
—
—
GPIO
E5
GPIO[0]/RXCAN1/SD_CLK/MSRCID0 (DDR
ID)
IO
IO
OVDD
OVDD
—
—
GPIO[1]/TXCAN1/SD_CMD/MSRCID1 (DDR
ID)
E6
GPIO[2]/RXCAN2/SD_CD/MSRCID2 (DDR ID)
GPIO[3]/TXCAN2/SD_WP/MSRCID3 (DDR ID)
D4
C2
C1
IO
IO
IO
OVDD
OVDD
OVDD
—
—
—
GPIO[4]/RXCAN3/SD_DAT0/MSRCID4 (DDR
ID)
GPIO[5]/TXCAN3/SD_DAT1/MDVAL (DDR ID)
GPIO[6]/RXCAN4/SD_DAT2/QE_EXT_REQ_3
GPIO[7]/TXCAN4/SD_DAT3/QE_EXT_REQ_1
B1
B3
IO
IO
IO
OVDD
OVDD
OVDD
—
—
—
B2
USB
AC4
Y9
USBDR_PWRFAULT/IIC_SDA2/CE_PIO_1
USBDR_CLK/UART2_SIN[2]/UART2_CTS_B[1]
USBDR_DIR/IIC_SCL2
IO
I
OVDD
OVDD
OVDD
OVDD
OVDD
2
AC3
AC2
AB3
IO
IO
IO
2
USBDR_NXT/UART2_SIN[1]/QE_EXT_REQ_4
—
—
USBDR_PCTL[0]/UART2_SOUT[1]/LB_POR_CF
G_BOOT_ECC
USBDR_PCTL[1]/UART2_SOUT[2]/UART2_RTS
_B1/LB_POR_BOOT_ERR
Y8
O
OVDD
—
USBDR_STP/QE_EXT_REQ_2
W6
IO
IO
OVDD
OVDD
—
—
USBDR_TXDRXD[0]/UART1_SOUT[1]/GPIO[32]
/QE_TRB_O
AB7
USBDR_TXDRXD[1]/UART1_SIN[1]/GPIO[33]/Q
E_TRB_I
AB8
AC6
AC5
AB5
IO
IO
IO
IO
OVDD
OVDD
OVDD
OVDD
—
—
—
—
USBDR_TXDRXD[2]/UART1_SOUT[2]/UART1_
RTS_B1/QE_BRG[1]
USBDR_TXDRXD[3]/UART1_SIN[2]/UART1_CT
S_B1/QE_BRG[2]
USBDR_TXDRXD[4]/GPIO[34]/QE_BRG[3]
MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0
Freescale Semiconductor
55
Package and Pin Listings
Table 52. MPC8306Pinout Listing (continued)
Signal
Package Pin Number
Pin Type
Power Supply
Notes
USBDR_TXDRXD[5]/GPIO[35]/QE_BRG[4]
USBDR_TXDRXD[6]/GPIO[36]/QE_BRG[9]
USBDR_TXDRXD[7]/GPIO[37]/QE_BRG[11]
Y7
IO
IO
IO
OVDD
OVDD
OVDD
—
—
—
Y6
Y5
DUART
UART1_SOUT[1]/LSRCID4/LCS_B[4]
UART1_SIN[1]/LDVAL/LCS_B[5]
C23
O
IO
O
OVDD
OVDD
OVDD
OVDD
—
—
—
—
F19
UART1_SOUT[2]/UART1_RTS_B1/LCS_B[6]
UART1_SIN[2]/UART1_CTS_B[1]/LCS_B[7]
D23
D22
IO
Interrupts
IRQ_B0_MCP_IN_B/CE_PI_0
IRQ_B1/MCP_OUT_B
E20
IO
IO
IO
I
OVDD
OVDD
OVDD
OVDD
—
—
—
—
E23
IRQ_B2/CKSTOP_OUT_B
IRQ_B3/CKSTOP_IN_B
E22
F20
I2C Interface
IIC_SDA1
G20
IO
IO
IO
IO
OVDD
OVDD
OVDD
OVDD
2
2
2
2
IIC_SCL1
J20
IIC_SDA2/CKSTOP_OUT_B
LCLK1/IIC_SCL2/CKSTOP_IN_B
F23
H20
SPI
SPIMOSI/LSRCID[2]
SPIMISO/LSRCID[3]
SPICLK/LSRCID[0]
SPISEL/LSRCID[1]
G22
IO
IO
IO
IO
OVDD
OVDD
OVDD
OVDD
—
—
—
—
K20
G23
H22
FEC Management
FEC_MDC
FEC_MDIO
H23
L20
O
OVDD
OVDD
—
—
IO
FEC1/GTM/GPIO
AB20
FEC1_COL/GTM1_TIN[1]/GPIO[16]
FEC1_CRS/GTM1_TGATE1_B/GPIO[17]
FEC1_RX_CLK/GPIO[18]
IO
IO
IO
IO
IO
IO
IO
IO
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
—
—
—
—
—
—
—
—
AC21
Y17
FEC1_RX_DV/GTM1_TIN[2]/GPIO[19]
FEC1_RX_ER/GTM1_TGATE[2]_B/GPIO[20]
FEC1_RXD0/GPIO[21]
Y18
AB19
AC20
FEC1_RXD1/GTM1_TIN[3]/GPIO[22]
FEC1_RXD2/GTM1_TGATE[3]_B/GPIO[23]
AC19
AC18
MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0
56
Freescale Semiconductor
Package and Pin Listings
Table 52. MPC8306Pinout Listing (continued)
Signal
FEC1_RXD3/GPIO[24]
Package Pin Number
Pin Type
Power Supply
Notes
AB17
Y15
IO
IO
IO
IO
IO
IO
IO
IO
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
—
—
—
—
—
—
—
—
FEC1_TX_CLK/GTM1_TIN4/GPIO[25]
FEC1_TX_EN/GTM1_TGATE[4]_B/GPIO[26]
FEC1_TX_ER/GTM1_TOUT[4]_B/GPIO[27]
FEC1_TXD0/GTM1_TOUT[1]_B/GPIO[28]
FEC1_TXD1/GTM1_TOUT[2]_B/GPIO[29]
FEC1_TXD2/GTM1_TOUT[3]_B/GPIO[30]
FEC1_TXD3/GPIO[31]
Y16
AC17
AB16
AC16
AC15
AB14
FEC2/GPIO
AC14
AB13
Y14
FEC2_COL/GPIO[32]
FEC2_CRS/GPIO[33]
FEC2_RX_CLK/GPIO[34]
FEC2_RX_DV/GPIO[35]
FEC2_RX_ER/GPIO[36]
FEC2_RXD0/GPIO[37]
FEC2_RXD1/GPIO[38]
FEC2_RXD2/GPIO[39]
FEC2_RXD3/GPIO[40]
FEC2_TX_CLK/GPIO[41]
FEC2_TX_EN/GPIO[42]
FEC2_TX_ER/GPIO[43]
FEC2_TXD0/GPIO[44]
FEC2_TXD1/GPIO[45]
FEC2_TXD2/GPIO[46]
FEC2_TXD3/GPIO[47]
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
AC13
Y13
AC12
AB11
AC11
AB10
Y12
AC10
AC9
AC8
Y11
AC7
Y10
FEC3/GPIO
J23
FEC3_COL/GPIO[48]
IO
IO
IO
IO
IO
IO
IO
IO
IO
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
—
—
—
—
—
—
—
—
—
FEC3_CRS/GPIO[49]
K23
FEC3_RX_CLK/GPIO[50]
M20
FEC3_RX_DV/FEC1_TMR_TX_ESFD/GPIO[51]
FEC3_RX_ER/FEC1_TMR_RX_ESFD/GPIO[52]
FEC3_RXD0/FEC2_TMR_TX_ESFD/GPIO[53]
FEC3_RXD1/FEC2_TMR_RX_ESFD/GPIO[54]
FEC3_RXD2/TSEC_TMR_TRIG1/GPIO[55]
FEC3_RXD3/TSEC_TMR_TRIG2/GPIO[56]
K22
L22
L23
M23
N22
N23
MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0
Freescale Semiconductor
57
Package and Pin Listings
Table 52. MPC8306Pinout Listing (continued)
Signal
Package Pin Number
Pin Type
Power Supply
Notes
FEC3_TX_CLK/TSEC_TMR_CLK/GPIO[57]
FEC3_TX_EN/TSEC_TMR_GCLK/GPIO[58]
FEC3_TX_ER/TSEC_TMR_PP1/GPIO[59]
FEC3_TXD0/TSEC_TMR_PP2/GPIO[60]
FEC3_TXD1/TSEC_TMR_PP3/GPIO[61]
FEC3_TXD2/TSEC_TMR_ALARM1/GPIO[62]
FEC3_TXD3/TSEC_TMR_ALARM2/GPIO[63]
N20
IO
IO
IO
IO
IO
IO
IO
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
—
—
—
—
—
—
—
P20
P22
R20
T22
T23
T20
HDLC/GPIO/TDM
U23
HDLC1_RXCLK/TDM1_RCK/GPIO[1]
HDLC1_RXD/TDM1_RD/GPIO[3]
IO
IO
IO
OVDD
OVDD
OVDD
—
—
—
U22
HDLC1_TXCLK/GPIO[0]/TDM1_TCK/QE_BRG[5
]
AC22
HDLC1_TXD/GPIO[2]/TDM1_TD/CFG_RESET_
SOURCE[0]
W18
IO
OVDD
—
HDLC1_CD_B/GPIO[4]/TDM1_TFS
HDLC1_CTS_B/GPIO[5]/TDM1_RFS
W19
Y20
IO
IO
IO
OVDD
OVDD
OVDD
—
—
—
HDLC1_RTS_B/GPIO[6]/TDM1_STROBE_B/CF
G_RESET_SOURCE[1]
AB22
HDLC2_TXCLK/GPIO[16]/TDM2_TCK/QE_BRG[
7]
AB23
AA23
W20
IO
IO
IO
OVDD
OVDD
OVDD
—
—
—
HDLC2_RXCLK/GPIO[17]/TDM2_RCK/QE_BRG
[8]
HDLC2_TXD/GPIO[18]/TDM2_TD/CFG_RESET
_SOURCE[2]
HDLC2_RXD/GPIO[19]/TDM2_RD
HDLC2_CD_B/GPIO[20]/TDM2_TFS
HDLC2_CTS_B/GPIO[21]/TDM2_RFS
Y23
Y22
W23
W22
IO
IO
IO
IO
OVDD
OVDD
OVDD
OVDD
—
—
—
—
HDLC2_RTS_B/GPIO[22]/TDM2_STROBE_B/C
FG_RESET_SOURCE[3]
Power
L16
AVDD1
AVDD2
AVDD3
GVDD
—
—
—
—
—
—
—
—
—
—
—
—
M16
N8
G5, H5, J5, K5, L5, M5,
N5, P5, R5, T5, U5
MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0
58
Freescale Semiconductor
Package and Pin Listings
Table 52. MPC8306Pinout Listing (continued)
Signal
Package Pin Number
Pin Type
Power Supply
Notes
OVDD
E7,E8,E9,E10,E11,E12,
E13,E14, E15,
—
—
—
E16,E17,G19,H19,J19,K
19,L19,M19,
N19,P19,R19,T19,U19,
W7,W8,W9, W10,W11,
W12,W13, W14,W15,
W16, W17
VDD
H8,H9,H10,H11,H12,H1
3,H14,H15,H16,J8,J16,K
8,K16,M8,N16,P8,P16,R
8,R16,T8,T9,T10,T11,T1
2,T13,T14,T15,T16
—
—
—
—
—
—
VSS
A1,B4,B6,B9,B12,B15,B
18,B21,C22,D2,D5,D18,
D20,F2,F22,J2,J9,J10,J
11,J12,J13,J14,J15,J22,
K4,K9,K10,K11,K12,K13
,K14,K15,L9,L10,L11,L1
2,L13,L14,L15,M2,M9,M
10,M11,M12,M13,M14,M
15,M22,N9,N10,N11,N1
2,N13,N14,N15,P9,P10,
P11,P12,P13,P14,P15,R
2,R9,R10,R11,R12,R13,
R14,R15,R22,T4,V2,V19
,V22,W4,Y19,AA2,AA22,
AB4,AB6,AB9,AB12,AB1
5,AB18,AB21,AC1,AC23
NC
A23
—
—
—
Notes
1. This pin is an open drain signal. A weak pull-up resistor (1 kΩ) should be placed on this pin to OVDD
2. This pin is an open drain signal. A weak pull-up resistor (2-10 kΩ) should be placed on this pin to OVDD
3. This pin has weak pull-up that is always enabled.
MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0
Freescale Semiconductor
59
Clocking
22 Clocking
Figure 42 shows the internal distribution of clocks within the MPC8306.
e300c3 core
MPC8306
core_clk
Core PLL
to DDR
csb_clk
memory
controller
DDR
Clock
Divider
MEMC_MCK
MEMC_MCK
DDR
Memory
Device
/2
ddr_clk
Clock
Unit
lbc_clk
System
PLL
/n
SYS_CLK_IN
LBC
Clock
Divider
Local Bus
Memory
Device
LCLK[0:1]
to local bus
csb_clk to rest
of the device
qe_clk
QE Block
CLK Gen
QE_CLK_IN
QE PLL
Figure 42. MPC8306 Clock Subsystem
The primary clock source for MPC8306 is SYS_CLK_IN.
MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0
60
Freescale Semiconductor
Clocking
22.1 System Clock Domains
As shown in Figure 42, the primary clock input (frequency) is multiplied up by the system phase-locked
loop (PLL) and the clock unit to create four major clock domains:
•
•
•
•
The coherent system bus clock (csb_clk)
The QUICC Engine clock (qe_clk)
The internal clock for the DDR controller (ddr_clk)
The internal clock for the local bus controller (lbc_clk)
The csb_clk frequency is derived from the following equation:
csb_clk = SYS_CLK_IN × SPMF
Eqn. 1
The csb_clk serves as the clock input to the e300 core. A second PLL inside the core multiplies up the
csb_clk frequency to create the internal clock for the core (core_clk). The system and core PLL multipliers
are selected by the SPMF and COREPLL fields in the reset configuration word low (RCWL) which is
loaded at power-on reset or by one of the hard-coded reset options.For more information, see the Reset
Configuration chapter in the MPC8306 PowerQUICC II Pro Communications Processor Reference
Manual.
The qe_clk frequency is determined by the QUICC Engine PLL multiplication factor (RCWL[CEPMF])
and the QUICC Engine PLL division factor (RCWL[CEPDF]) as the following equation:
qe_clk = (QE_CLK_IN × CEPMF) (1 + CEPDF)
qe_clk = (QE_CLK_IN × CEPMF) (1 + CEPDF)
Eqn. 2
Eqn. 3
For more information, see the QUICC Engine PLL Multiplication Factor section and the “QUICC Engine
PLL Division Factor” section in the MPC8306 PowerQUICC II Pro Communications Processor
Reference Manual for more information.
The DDR SDRAM memory controller operates with a frequency equal to twice the frequency of csb_clk.
Note that ddr_clk is not the external memory bus frequency; ddr_clk passes through the DDR clock divider
(2) to create the differential DDR memory bus clock outputs (MCK and MCK). However, the data rate
is the same frequency as ddr_clk.
The local bus memory controller operates with a frequency equal to the frequency of csb_clk. Note that
lbc_clk is not the external local bus frequency; lbc_clk passes through the LBC clock divider to create the
external local bus clock outputs (LCLK). The LBC clock divider ratio is controlled by LCCR[CLKDIV].
For more information, see the LBC Bus Clock and Clock Ratios section in the MPC8306 PowerQUICC
II Pro Communications Processor Reference Manual.
MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0
Freescale Semiconductor
61
Clocking
In addition, some of the internal units may be required to be shut off or operate at lower frequency than
the csb_clk frequency. These units have a default clock ratio that can be configured by a memory mapped
register after the device comes out of reset.
Table 53 specifies which units have a configurable clock frequency. For detailed description, refer to the
“System Clock Control Register (SCCR)” section in the MPC8306 PowerQUICC II Pro Communications
Processor Reference Manual.
Table 53. Configurable Clock Units
Unit
Default Frequency
Options
I2C,SDHC, USB, DMA Complex
csb_clk
Off, csb_clk, csb_clk/2, csb_clk/3
NOTE
Setting the clock ratio of these units must be performed prior to any access
to them.
Table 54 provides the maximum operating frequencies for the MPC8306 MAPBGA under recommended
operating conditions (see Table 2).
Table 54. Operating Frequencies for MAPBGA
Characteristic1
e300 core frequency (core_clk)
Max Operating Frequency
Unit
266
133
200
133
66
MHz
MHz
MHz
MHz
MHz
Coherent system bus frequency (csb_clk)
QUICC Engine frequency (qe_clk)
DDR2 memory bus frequency (MCLK)2
Local bus frequency (LCLKn)3
1
The SYS_CLK_IN frequency, RCWL[SPMF], and RCWL[COREPLL] settings must be chosen such that the resulting csb_clk,
MCLK, LCLK, and core_clk frequencies do not exceed their respective maximum or minimum operating frequencies.
The DDR2 data rate is 2× the DDR2 memory bus frequency.
The local bus frequency is 1/2, 1/4, or 1/8 of the lb_clk frequency (depending on LCCR[CLKDIV]) which is in turn 1× or 2× the
csb_clk frequency (depending on RCWL[LBCM]).
2
3
22.2 System PLL Configuration
The system PLL is controlled by the RCWL[SPMF] parameter. Table 55 shows the multiplication factor
encodings for the system PLL.
NOTE
System PLL VCO frequency = 2 × (CSB frequency) × (System PLL VCO
divider). The VCO divider needs to be set properly so that the System PLL
VCO frequency is in the range of 450–750 MHz.
As described in Section 22, “Clocking,” the LBCM, DDRCM, and SPMF parameters in the reset
configuration word low select the ratio between the primary clock input (SYS_CLK_IN) and the internal
MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0
62
Freescale Semiconductor
Clocking
Table 55. System PLL Multiplication Factors
RCWL[SPMF]
System PLL Multiplication Factor
0000
0001
Reserved
Reserved
× 2
0010
0011
× 3
0100
× 4
0101
× 5
0110
× 6
0111–1111
Reserved
coherent system bus clock (csb_clk). Table 56 shows the expected frequency values for the CSB frequency
for selected csb_clk to SYS_CLK_IN ratios.
Table 56. CSB Frequency Options
SYS_CLK_IN(MHz)
SPMF
csb_clk : sys_clk_in Ratio
25
33.33
66.67
csb_clk Frequency (MHz)
0010
0011
0100
0101
0110
2:1
3:1
4:1
5:1
6:1
133
133
125
22.3 Core PLL Configuration
RCWL[COREPLL] selects the ratio between the internal coherent system bus clock (csb_clk) and the e300
core clock (core_clk). Table 57 shows the encodings for RCWL[COREPLL]. COREPLL values not listed
in Table 57 should be considered reserved.
Table 57. e300 Core PLL Configuration
RCWL[COREPLL]
core_clk : csb_clk Ratio
VCO Divider
0-1
2-5
6
nn
0000
n
PLL bypassed
PLL bypassed
(PLL off, csb_clk clocks core directly) (PLL off, csb_clk clocks core directly)
00
01
0001
0001
0
0
1:1
1:1
2
4
MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0
Freescale Semiconductor
63
Clocking
Table 57. e300 Core PLL Configuration (continued)
RCWL[COREPLL]
2-5
core_clk : csb_clk Ratio
VCO Divider
0-1
6
10
11
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
0001
0001
0001
0001
0001
0001
0010
0010
0010
0010
0010
0010
0010
0010
0011
0011
0011
0011
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1:1
1:1
8
8
1.5:1
1.5:1
1.5:1
1.5:1
2:1
2
4
8
8
2
4
8
8
2
4
8
8
2
4
8
8
2:1
2:1
2:1
2.5:1
2.5:1
2.5:1
2.5:1
3:1
3:1
3:1
3:1
NOTE
Core VCO frequency = core frequency VCO divider. The VCO divider
(RCWL[COREPLL[0:1]]), must be set properly so that the core VCO
frequency is in the range of 400–800 MHz.
22.4 QUICC Engine PLL Configuration
The QUICC Engine PLL is controlled by the RCWL[CEPMF] and RCWL[CEPDF] parameters. Table 58
shows the multiplication factor encodings for the QUICC Engine PLL.
Table 58. QUICC Engine PLL Multiplication Factors
QUICC Engine PLL Multiplication Factor = RCWL[CEPMF]/
RCWL[CEPMF]
RCWL[CEPDF]
(1 + RCWL[CEPDF)
00000–00001
00010
0
0
0
0
Reserved
2
00011
3
00100
4
MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0
64
Freescale Semiconductor
Clocking
Table 58. QUICC Engine PLL Multiplication Factors (continued)
QUICC Engine PLL Multiplication Factor = RCWL[CEPMF]/
RCWL[CEPMF]
RCWL[CEPDF]
(1 + RCWL[CEPDF)
00101
00110
0
0
0
0
0
5
6
00111
7
01000
8
01001–11111
Reserved
The RCWL[CEVCOD] denotes the QUICC Engine PLL VCO internal frequency as shown in Table 59.
Table 59. QUICC Engine PLL VCO Divider
RCWL[CEVCOD]
VCO Divider
00
01
10
11
2
4
8
Reserved
NOTE
The VCO divider (RCWL[CEVCOD]) must be set properly so that the
QUICC Engine VCO frequency is in the range of 300–600 MHz. The
QUICC Engine frequency is not restricted by the CSB and core frequencies.
The CSB, core, and QUICC Engine frequencies should be selected
according to the performance requirements.
The QUICC Engine VCO frequency is derived from the following
equations:
qe_clk = (primary clock input × CEPMF) (1 + CEPDF)
QUICC Engine VCO Frequency = qe_clk × VCO divider × (1 + CEPDF)
22.5 Suggested PLL Configurations
To simplify the PLL configurations, the MPC8306 might be separated into two clock domains. The first
domain contains the CSB PLL and the core PLL. The core PLL is connected serially to the CSB PLL, and
has the csb_clk as its input clock. The second clock domain has the QUICC Engine PLL. The clock
domains are independent, and each of their PLLs are configured separately.
Table 60 shows suggested PLL configurations for 33, 25, and 66 MHz input clocks.
MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0
Freescale Semiconductor
65
Clocking
Table 60. Suggested PLL Configurations
QUICC
Engine
Frequency
(MHz)
Input Clock
Frequency
(MHz)
CSB
Frequency
(MHz)
Core
Frequency
(MHz)
Core
PLL
Conf No.
SPMF
CEMF
CEDF
1
2
0100
0010
0000100
0000100
0110
0011
0
0
33.33
66.67
133.33
133.33
266.66
266.66
200
200
MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0
66
Freescale Semiconductor
Thermal
23 Thermal
This section describes the thermal specifications of the MPC8306.
23.1 Thermal Characteristics
Table 61 provides the package thermal characteristics for the 369, 19 19 mm MAPBGA of the
MPC8306.
Table 61. Package Thermal Characteristics for MAPBGA
Characteristic
Board type
Symbol
Value
Unit
Notes
Junction-to-ambient natural convection
Junction-to-ambient natural convection
Junction-to-ambient (@200 ft/min)
Junction-to-ambient (@200 ft/min)
Junction-to-board
Single-layer board (1s)
Four-layer board (2s2p)
Single-layer board (1s)
Four-layer board (2s2p)
—
RJA
RJA
RJMA
RJMA
RJB
RJC
JT
39
24
32
21
14
9
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
1, 2
1, 2 ,3
1, 3
1, 3
4
Junction-to-case
—
5
Junction-to-package top
Notes:
Natural convection
2
6
1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)
temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal
resistance.
2. Per JEDEC JESD51-2 with the single layer board horizontal. Board meets JESD51-9 specification.
3. Per JEDEC JESD51-6 with the board horizontal.
4. Thermal resistance between the die and the printed-circuit board per JEDEC JESD51-8. Board temperature is measured on
the top surface of the board near the package.
5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method
1012.1).
6. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature
per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT.
23.1.1 Thermal Management Information
For the following sections, P = (V I ) + P , where P is the power dissipation of the I/O
D
DD
DD
I/O
I/O
drivers.
23.1.2 Estimation of Junction Temperature with Junction-to-Ambient
Thermal Resistance
An estimation of the chip junction temperature, T , can be obtained from the equation:
J
T = T + (R J P )
Eqn. 1
J
A
A
D
where:
T = junction temperature (C)
J
MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0
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67
Thermal
T = ambient temperature for the package (C)
A
R
= junction-to-ambient thermal resistance (C/W)
JA
P = power dissipation in the package (W)
D
The junction-to-ambient thermal resistance is an industry standard value that provides a quick and easy
estimation of thermal performance. As a general statement, the value obtained on a single layer board is
appropriate for a tightly packed printed-circuit board. The value obtained on the board with the internal
planes is usually appropriate if the board has low power dissipation and the components are well separated.
Test cases have demonstrated that errors of a factor of two (in the quantity T – T ) are possible.
J
A
23.1.3 Estimation of Junction Temperature with Junction-to-Board
Thermal Resistance
The thermal performance of a device cannot be adequately predicted from the junction-to-ambient thermal
resistance. The thermal performance of any component is strongly dependent on the power dissipation of
surrounding components. In addition, the ambient temperature varies widely within the application. For
many natural convection and especially closed box applications, the board temperature at the perimeter
(edge) of the package is approximately the same as the local air temperature near the device. Specifying
the local ambient conditions explicitly as the board temperature provides a more precise description of the
local ambient conditions that determine the temperature of the device.
At a known board temperature, the junction temperature is estimated using the following equation:
T = T + (R J P )
Eqn. 2
J
B
B
D
where:
T = junction temperature (C)
J
T = board temperature at the package perimeter (C)
B
R
= junction-to-board thermal resistance (C/W) per JESD51-8
JB
P = power dissipation in package (W)
D
When the heat loss from the package case to the air can be ignored, acceptable predictions of junction
temperature can be made. The application board should be similar to the thermal test condition: the
component is soldered to a board with internal planes.
23.1.4 Experimental Determination of Junction Temperature
To determine the junction temperature of the device in the application after prototypes are available, the
thermal characterization parameter ( ) can be used to determine the junction temperature with a
JT
measurement of the temperature at the top center of the package case using the following equation:
T = T + (JT P )
Eqn. 3
J
T
D
where:
T = junction temperature (C)
J
MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0
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Thermal
T = thermocouple temperature on top of package (C)
T
= thermal characterization parameter (C/W)
JT
P = power dissipation in package (W)
D
The thermal characterization parameter is measured per JESD51-2 specification using a 40 gauge type T
thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so
that the thermocouple junction rests on the package. A small amount of epoxy is placed over the
thermocouple junction and over about 1 mm of wire extending from the junction. The thermocouple wire
is placed flat against the package case to avoid measurement errors caused by cooling effects of the
thermocouple wire.
23.1.5 Heat Sinks and Junction-to-Case Thermal Resistance
In some application environments, a heat sink is required to provide the necessary thermal management of
the device. When a heat sink is used, the thermal resistance is expressed as the sum of a junction-to-case
thermal resistance and a case to ambient thermal resistance as shown in the following equation:
R
= R
+ R
CA
Eqn. 4
JA
JC
where:
R
R
R
= junction-to-ambient thermal resistance (C/W)
= junction-to-case thermal resistance (C/W)
= case-to-ambient thermal resistance (C/W)
JA
JC
CA
R is device related and cannot be influenced by the user. The user controls the thermal environment to
JC
change the case-to-ambient thermal resistance, R . For instance, the user can change the size of the heat
CA
sink, the air flow around the device, the interface material, the mounting arrangement on printed-circuit
board, or change the thermal dissipation on the printed-circuit board surrounding the device.
To illustrate the thermal performance of the devices with heat sinks, the thermal performance has been
simulated with a few commercially available heat sinks. The heat sink choice is determined by the
application environment (temperature, air flow, adjacent component power dissipation) and the physical
space available. Because there is not a standard application environment, a standard heat sink is not
required.
Accurate thermal design requires thermal modeling of the application environment using computational
fluid dynamics software which can model both the conduction cooling and the convection cooling of the
air moving through the application. Simplified thermal models of the packages can be assembled using the
junction-to-case and junction-to-board thermal resistances listed in the thermal resistance table. More
detailed thermal models can be made available on request.
23.2 Heat Sink Attachment
When attaching heat sinks to these devices, an interface material is required. The best method is to use
thermal grease and a spring clip. The spring clip should connect to the printed-circuit board, either to the
board itself, to hooks soldered to the board, or to a plastic stiffener. Avoid attachment forces which would
lift the edge of the package or peel the package from the board. Such peeling forces reduce the solder joint
MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0
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69
System Design Information
lifetime of the package. Recommended maximum force on the top of the package is 10 lb (4.5 kg) force.
If an adhesive attachment is planned, the adhesive should be intended for attachment to painted or plastic
surfaces and its performance verified under the application requirements.
23.2.1 Experimental Determination of the Junction Temperature with a
Heat Sink
When heat sink is used, the junction temperature is determined from a thermocouple inserted at the
interface between the case of the package and the interface material. A clearance slot or hole is normally
required in the heat sink. Minimizing the size of the clearance is important to minimize the change in
thermal performance caused by removing part of the thermal interface to the heat sink. Because of the
experimental difficulties with this technique, many engineers measure the heat sink temperature and then
back calculate the case temperature using a separate measurement of the thermal resistance of the
interface.
From this case temperature, the junction temperature is determined from the junction-to-case thermal
resistance using the following equation:
T = T + (R
P )
Eqn. 5
J
C
JC
D
where:
T = case temperature of the package (C)
C
R
= junction-to-case thermal resistance (C/W)
JC
P = power dissipation (W)
D
24 System Design Information
This section provides electrical and thermal design recommendations for successful application of the
MPC8306.
24.1 System Clocking
The MPC8306 includes three PLLs.
•
•
•
The system PLL (AV
) generates the system clock from the externally supplied SYS_CLK_IN
DD2
input. The frequency ratio between the system and SYS_CLK_IN is selected using the system PLL
ratio configuration bits as described in Section 22.2, “System PLL Configuration.”
The e300 core PLL (AV
ratio between the e300 core clock and the system clock is selected using the e300 PLL ratio
configuration bits as described in Section 22.3, “Core PLL Configuration.”
) generates the core clock as a slave to the system clock. The frequency
DD3
The QUICC Engine PLL (AV
) which uses the same reference as the system PLL. The QUICC
DD1
Engine block generates or uses external sources for all required serial interface clocks.
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System Design Information
24.2 PLL Power Supply Filtering
Each of the PLLs listed above is provided with power through independent power supply pins. The voltage
level at each AV n pin should always be equivalent to V , and preferably these voltages are derived
DD
DD
directly from V through a low frequency filter scheme such as the following.
DD
There are a number of ways to reliably provide power to the PLLs, but the recommended solution is to
provide independent filter circuits as illustrated in Figure 43, one to each of the three AV pins. By
DD
providing independent filters to each PLL the opportunity to cause noise injection from one PLL to the
other is reduced.
This circuit is intended to filter noise in the PLLs resonant frequency range from a 500 kHz to 10 MHz
range. It should be built with surface mount capacitors with minimum effective series inductance (ESL).
Consistent with the recommendations of Dr. Howard Johnson in High Speed Digital Design: A Handbook
of Black Magic (Prentice Hall, 1993), multiple small capacitors of equal value are recommended over a
single large value capacitor.
Each circuit should be placed as close as possible to the specific AV pin being supplied to minimize
DD
noise coupled from nearby circuits. It should be possible to route directly from the capacitors to the AV
pin, which is on the periphery of package, without the inductance of vias.
DD
Figure 43 shows the PLL power supply filter circuit.
10
VDD
AVDD
2.2 µF
2.2 µF
Low ESL Surface Mount Capacitors (<0.5 nH)
GND
Figure 43. PLL Power Supply Filter Circuit
24.3 Decoupling Recommendations
Due to large address and data buses, and high operating frequencies, the MPC8306 can generate transient
power surges and high frequency noise in its power supply, especially while driving large capacitive loads.
This noise must be prevented from reaching other components in the MPC8306 system, and MPC8306
itself requires a clean, tightly regulated source of power. Therefore, it is recommended that the system
designer place at least one decoupling capacitor at each V , OV , and GV pins of the MPC8306.
DD
DD
DD
These decoupling capacitors should receive their power from separate V , OV , GV , and GND
DD
DD
DD
power planes in the PCB, utilizing short traces to minimize inductance. Capacitors may be placed directly
under the device using a standard escape pattern. Others may surround the part.
These capacitors should have a value of 0.01 or 0.1 µF. Only ceramic SMT (surface mount technology)
capacitors should be used to minimize lead inductance, preferably 0402 or 0603 sizes.
In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB,
feeding the V , OV , and GV planes, to enable quick recharging of the smaller chip capacitors.
DD
DD
DD
These bulk capacitors should have a low ESR (equivalent series resistance) rating to ensure the quick
response time necessary. They should also be connected to the power and ground planes through two vias
MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0
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71
System Design Information
to minimize inductance. Suggested bulk capacitors—100 to 330 µF (AVX TPS tantalum or Sanyo
OSCON).
24.4 Output Buffer DC Impedance
2
For all buses, the driver is a push-pull single-ended driver type (open drain for I C).
To measure Z for the single-ended drivers, an external resistor is connected from the chip pad to OV
0
DD
or GND. Then, the value of each resistor is varied until the pad voltage is OV /2 (see Figure 44). The
DD
output impedance is the average of two components, the resistances of the pull-up and pull-down devices.
When data is held high, SW1 is closed (SW2 is open) and R is trimmed until the voltage at the pad equals
P
OV /2. R then becomes the resistance of the pull-up devices. R and R are designed to be close to each
DD
P
P
N
other in value. Then, Z = (R + R )/2.
0
P
N
OVDD
RN
SW2
SW1
Pad
Data
RP
OGND
Figure 44. Driver Impedance Measurement
The value of this resistance and the strength of the driver’s current source can be found by making two
measurements. First, the output voltage is measured while driving logic 1 without an external differential
termination resistor. The measured voltage is V = R
while driving logic 1 with an external precision differential termination resistor of value R . The
I
. Second, the output voltage is measured
1
source
source
term
measured voltage is V = (1/(1/R + 1/R )) I . Solving for the output impedance gives
2
1
2
source
R
= R
(V /V – 1). The drive current is then I
= V /R
.
source
term
1
2
source
1
source
MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0
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Freescale Semiconductor
Ordering Information
Table 62 summarizes the signal impedance targets. The driver impedance are targeted at minimum V
,
DD
nominal OV , 105C.
DD
Table 62. Impedance Characteristics
Local Bus, Ethernet, DUART, Control,
Configuration and Power Management
Impedance
DDR DRAM
Symbol
Unit
R
R
42 Target
42 Target
NA
20 Target
20 Target
NA
Z0
Z0
Ω
Ω
Ω
N
P
Differential
ZDIFF
Note: Nominal supply voltages. See Table 1, Tj = 105C.
24.5 Configuration Pin Multiplexing
The MPC8306 provides the user with power-on configuration options which can be set through the use of
external pull-up or pull-down resistors of 4.7 k on certain output pins (Refer to the “Reset, Clocking
and Initialization” of MPC8306S PowerQUICC II Pro Integrated Communications Processor Family
Reference Manual). These pins are generally used as output only pins in normal operation.
While HRESET is asserted however, these pins are treated as inputs. The value presented on these pins
while HRESET is asserted, is latched when HRESET deasserts, at which time the input receiver is disabled
and the I/O circuit takes on its normal function. Careful board layout with stubless connections to these
pull-up/pull-down resistors coupled with the large value of the pull-up/pull-down resistor should minimize
the disruption of signal quality or speed for output pins thus configured.
25 Ordering Information
This section presents ordering information for the devices discussed in this document, and it shows an
example of how the parts are marked. Ordering information for the devices fully covered by this document
is provided in Section 25.1, “Part Numbers Fully Addressed by This Document.”
25.1 Part Numbers Fully Addressed by This Document
Table 63 provides the Freescale part numbering nomenclature for the MPC8306 family. Note that the
individual part numbers correspond to a maximum processor core frequency. For available frequencies,
contact your local Freescale sales office. In addition to the maximum processor core frequency, the part
numbering scheme also includes the maximum effective DDR memory speed and QUICC Engine bus
frequency. Each part number also contains a revision code which refers to the die mask revision number.
MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0
Freescale Semiconductor
73
Ordering Information
Table 63. Part Numbering Nomenclature
MPC nnnn
VM
AF
D
C
A
C
QUICC
Engine
Frequency
Product
Code
Part
Identifier
Temperature
Range1
e300 Core
DDR
Frequency
Revision
Level
Package2
Frequency3
MPC
8306
Blank = 0 to
105C
C = –40 to
VM = Pb-free
AB = 133MHz D = 266 MHz C = 200 MHz Contact local
AC = 200 MHz
AD = 266 MHz
Freescale
sales office
105C
Notes:
1. Contact local Freescale office on availability of parts with C temperature range.
2. See Section 21, “Package and Pin Listings,” for more information on available package types.
3. Processor core frequencies supported by parts addressed by this specification only. Not all parts described in this
specification support all core frequencies. Additionally, parts addressed by Part Number Specifications may support other
maximum core frequencies.
25.2 Part Marking
Parts are marked as in the example shown in Figure 45.
MPCnnnnetppaaar
core/platform MHZ
ATWLYYWW
CCCCC
*MMMMM
YWWLAZ
MAPBGA
Notes:
ATWLYYWW is the traceability code.
CCCCC is the country code.
MMMMM is the mask number.
YWWLAZ is the assembly traceability code.
Figure 45. Freescale Part Marking for MAPBGA Devices
Table 64 shows the SVR Settings.
Table 64. SVR Settings
Device
MPC8306
Note: PVR = 0x8085_0020
Package
MAPBGA
SVR (Rev 1.0)
0x8110_0210
SVR (Rev 1.1)
0x8110_0211
MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0
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Freescale Semiconductor
Document Revision History
26 Document Revision History
Table 65 provides a revision history for this hardware specification.
Table 65. Document Revision History
Rev.
No.
Date
Substantive Change(s)
0
03/2011 Initial Release.
MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0
Freescale Semiconductor
75
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© 2011 Freescale Semiconductor, Inc.
Document Number: MPC8306EC
Rev. 0
03/2011
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