MSC8122TMP6400V_技术文档

MSC8122

Rev. 13, 10/2006

Freescale Semiconductor

Technical Data

MSC8122

Quad Core 16-Bit Digital Signal Processor

The raw processing power of

this highly integrated system-

on- a-chip device will enable

developers to create next-

generation networking

SC140

Extended Core

MQBus

128

products that offer

tremendous channel

SQBus

Boot

ROM

64

Local Bus

densities, while maintaining

system flexibility, scalability,

and upgradeability. The

MSC8122 is offered in three

core speed levels: 300, 400,

and 500 MHz.

IP Master

32 Timers

UART

M2

RAM

Memory

Controller

RS-232

4 TDMs

GPIO Pins

Interrupts

PLL/Clock

PLL

IPBus

32

GPIO

GIC

What’s New?

Rev. 13 includes the following:

Chapter 2 updates Table 2-13 to

add timings 17 and 18 for IRQs.

JTAG Port

JTAG

8 Hardware

Semaphores

•

MII/RMII/SMII

DSI Port

Ethernet

Internal Local Bus

SIU

64

Direct

Slave

Interface

(DSI)

32/64

System

Interface

DMA

Bridge

Registers

System Bus

32/64

64

Memory

Controller

Internal System Bus

Figure 1. MSC8122 Block Diagram

The MSC8122 is a highly integrated system-on-a-chip that combines four SC140 extended cores with an RS-232

serial interface, four time-division multiplexed (TDM) serial interfaces, thirty-two general-purpose timers, a

flexible system interface unit (SIU), an Ethernet interface, and a multi-channel DMA engine. The four extended

cores can deliver a total 4800/6400/8000 DSP MMACS performance at 300/400/500 MHz.

Each core has four arithmetic logic units (ALUs), internal memory, a write buffer, and two interrupt controllers.

The MSC8122 targets high-bandwidth highly computational DSP applications and is optimized for wireless

transcoding and packet telephony as well as high-bandwidth base station applications. The MSC8122 delivers

enhanced performance while maintaining low power dissipation and greatly reducing system cost.

Table of Contents

Features...............................................................................................................................................................iv

Product Documentation ......................................................................................................................................ix

Chapter 1

Signals/Connections

1.1

1.2

1.3

1.4

1.5

1.6

1.7

1.8

1.9

Power Signals ...................................................................................................................................................1-3

Clock Signals....................................................................................................................................................1-3

Reset and Configuration Signals.......................................................................................................................1-3

Direct Slave Interface, System Bus, Ethernet, and Interrupt Signals ...............................................................1-4

Memory Controller Signals ............................................................................................................................1-14

GPIO, TDM, UART, and Timer Signals.........................................................................................................1-16

Dedicated Ethernet Signals.............................................................................................................................1-23

EOnCE Event and JTAG Test Access Port Signals........................................................................................1-24

Reserved Signals.............................................................................................................................................1-24

Chapter 2

Specifications

2.1

2.2

2.3

2.4

2.5

Maximum Ratings.............................................................................................................................................2-1

Recommended Operating Conditions...............................................................................................................2-2

Thermal Characteristics....................................................................................................................................2-3

DC Electrical Characteristics............................................................................................................................2-3

AC Timings.......................................................................................................................................................2-4

Chapter 3

Chapter 4

Packaging

3.1

Package Description .........................................................................................................................................3-1

3.2

MSC8122 Package Mechanical Drawing.......................................................................................................3-20

Design Considerations

4.1

4.2

4.3

4.4

4.5

Start-up Sequencing Recommendations...........................................................................................................4-1

Power Supply Design Considerations...............................................................................................................4-1

Connectivity Guidelines ...................................................................................................................................4-3

External SDRAM Selection..............................................................................................................................4-4

Thermal Considerations....................................................................................................................................4-5

Data Sheet Conventions

OVERBAR

Used to indicate a signal that is active when pulled low (For example, the RESET pin is active

when low.)

“asserted”

“deasserted”

Examples:

Means that a high true (active high) signal is high or that a low true (active low) signal is low

Means that a high true (active high) signal is low or that a low true (active low) signal is high

Signal/Symbol

Logic State

True

Signal State

Asserted

Voltage

V_IL/V_OL

V_IH/V_OH

V_IL/V_OL

False

Deasserted

Asserted

True

False

Deasserted

Note: Values for V_IL, V_OL, V_IH, and V_OHare defined by individual product specifications.

MSC8122 Technical Data, Rev. 13

ii

Freescale Semiconductor

Data Sheet Conventions

Address

Register

File

Data ALU

Register

File

Program

Sequencer

Address

ALU

Data

ALU

SC140

Core

JTAG

EOnCE

Power

Management

M1

RAM

SC140 Core

64

Xa

64

Xb

P

128

Instruction

Cache

QBus

Interface

QBC

128

QBus

PIC

IRQs

QBus

Bank 1

QBus

Bank 3

LIC

IRQs

MQBus

SQBus

128

64

Local Bus

Notes: 1. The arrows show the data transfer direction.

2. The QBus interface includes a bus switch, write buffer, fetch unit, and a

control unit that defines four QBus banks. In addition, the QBC handles internal

memory contentions.

Figure 2. SC140 Extended Core Block Diagram

MSC8122 Technical Data, Rev. 13

Freescale Semiconductor

iii

Features

Feature

Description

Four SC140 cores:

•

Up to 8000 MMACS using 16 ALUs running at up to 500 MHz.

A total of 1436 KB of internal SRAM (224 KB per core + 16 KB ICache per core + the shared M2 memory).

Each SC140 core provides the following:

•

Up to 2000 MMACS using an internal 500 MHz clock. A MAC operation includes a multiply-accumulate

command with the associated data move and pointer update.

4 ALUs per SC140 core.

16 data registers, 40 bits each.

27 address registers, 32 bits each.

Hardware support for fractional and integer data types.

Very rich 16-bit wide orthogonal instruction set.

Up to six instructions executed in a single clock cycle.

Variable-length execution set (VLES) that can be optimized for code density and performance.

IEEE Std 1149.1™ JTAG port.

•

SC140 Cores

Enhanced on-device emulation (EOnCE) with real-time debugging capabilities.

Each SC140 core is embedded within an extended core that provides the following:

•

224 KB M1 memory that is accessed by the SC140 core with zero wait states.

Support for atomic accesses to the M1 memory.

16 KB instruction cache, 16 ways.

A four-entry write buffer that frees the SC140 core from waiting for a write access to finish.

External cache support by asserting the global signal (GBL) when predefined memory banks are accessed.

Programmable interrupt controller (PIC).

Extended Core

Local interrupt controller (LIC).

•

476 KB M2 memory (shared memory) working at the core frequency, accessible from the local bus, and

accessible from all four SC140 cores using the MQBus.

4 KB bootstrap ROM.

Multi-Core Shared

Memories

•

A QBus protocol multi-master bus connecting the four SC140 cores to the M2 memory.

Data bus access of up to 128-bit read and up to 64-bit write.

Operation at the SC140 core frequency.

A central efficient round-robin arbiter controlling SC140 core access on the MQBus.

Atomic operation control of access to M2 memory by the four SC140 cores and the local bus.

M2-Accessible Multi-

Core Bus (MQBus)

•

Generates up to 500 MHz core clock and up to166 MHz bus clocks for the 60x-compatible local and system

buses and other modules.

Internal PLL

•

PLL values are determined at reset based on configuration signal values.

•

64/32-bit data and 32-bit address 60x bus.

Support for multiple-master designs.

Four-beat burst transfers (eight-beat in 32-bit wide mode).

Port size of 64, 32, 16, and 8 controlled by the internal memory controller.

Bus can access external memory expansion or off-device peripherals, or it can enable an external host device to

access internal resources.

60x-Compatible

System Bus

•

Slave support, direct access by an external host to internal resources including the M1 and M2 memories.

On-device arbitration between up to four master devices.

A 32/64-bit wide slave host interface that operates only as a slave device under the control of an external host

processor.

•

21–25 bit address, 32/64-bit data.

Direct access by an external host to internal and external resources, including the M1 and the M2 memories as

well as external devices on the system bus.

•

Synchronous and asynchronous accesses, with burst capability in the synchronous mode.

Dual or Single strobe modes.

Write and read buffers improve host bandwidth.

Byte enable signals enables 1, 2, 4, and 8 byte write access granularity.

Sliding window mode enables access with reduced number of address pins.

Chip ID decoding enables using one CS signal for multiple DSPs.

Broadcast CS signal enables parallel write to multiple DSPs.

Big-endian, little-endian, and munged little-endian support.

Direct Slave

Interface (DSI)

•

64-bit DSI, 32-bit system bus.

32-bit DSI, 64-bit system bus.

32-bit DSI, 32-bit system bus.

3-Mode Signal

Multiplexing

MSC8122 Technical Data, Rev. 13

iv

Freescale Semiconductor

Features

Feature

Description

Flexible eight-bank memory controller:

•

Three user-programmable machines (UPMs), general-purpose chip-select machine (GPCM), and a page-mode

SDRAM machine.

•

Glueless interface to SRAM, page mode SDRAM, DRAM, EPROM, Flash memory, and other user-definable

peripherals.

•

Byte enables for either 64-bit or 32-bit bus width mode.

Eight external memory banks (banks 0–7). Two additional memory banks (banks 9, 11) control IPBus

peripherals and internal memories. Each bank has the following features:

—32-bit address decoding with programmable mask.

—Variable block sizes (32 KB to 4 GB).

—Selectable memory controller machine.

Memory Controller

—Two types of data errors check/correction: normal odd/even parity and read-modify-write (RMW) odd/even

parity for single accesses.

—Write-protection capability.

—Control signal generation machine selection on a per-bank basis.

—Support for internal or external masters on the system bus.

—Data buffer controls activated on a per-bank basis.

—Atomic operation.

—RMW data parity check (on system bus only).

—Extensive external memory-controller/bus-slave support.

—Parity byte select pin, which enables a fast, glueless connection to RMW-parity devices (on the system bus

only).

—Data pipeline to reduce data set-up time for synchronous devices.

•

16 time-multiplexed unidirectional channels.

Services up to four external peripherals.

Supports DONE or DRACK protocol on two external peripherals.

Each channel group services 16 internal requests generated by eight internal FIFOs. Each FIFO generates:

—A watermark request to indicate that the FIFO contains data for the DMA to empty and write to the destination.

—A hungry request to indicate that the FIFO can accept more data.

Priority-based time-multiplexing between channels using 16 internal priority levels.

Round-robin time-multiplexing between channels.

Multi-Channel DMA

Controller

•

A flexible channel configuration:

—All channels support all features.

—All channels connect to the system bus or local bus.

•

Flyby transfers in which a single data access is transferred directly from the source to the destination without

using a DMA FIFO.

Up to four independent TDM modules, each with the following features:

•

Optional operating configurations:

—Totally independent receive and transmit channels, each having one data line, one clock line, and one frame

sync line.

—Four data lines with one clock and one frame sync shared among the transmit and receive lines.

Connects gluelessly to most T1/E1 framers as well as to common buses such as the ST-BUS.

Hardware A-law/μ-law conversion.

•

Up to 62.5 Mbps per TDM (62.5 MHz bit clock if one data line is used, 31.25 MHz if two data lines are used,

15.63 MHz if four data lines are used).

•

Up to 256 channels.

Up to 16 MB per channel buffer (granularity 8 bytes), where A/μ law buffer size is double (granularity 16 byte).

Receive buffers share one global write offset pointer that is written to the same offset relative to their start

address.

Time-Division

Multiplexing (TDM)

•

Transmit buffers share one global read offset pointer that is read from the same offset relative to their start

address.

•

All channels share the same word size.

Two programmable receive and two programmable transmit threshold levels with interrupt generation that can

be used, for example, to implement double buffering.

•

Each channel can be programmed to be active or inactive.

2-, 4-, 8-, or 16-bit channels are stored in the internal memory as 2-, 4-, 8-, or 16-bit channels, respectively.

The TDM Transmitter Sync Signal (TxTSYN) can be configured as either input or output.

Frame Sync and Data signals can be programmed to be sampled either on the rising edge or on the falling edge

of the clock.

•

Frame sync can be programmed as active low or active high.

Selectable delay (0–3 bits) between the Frame Sync signal and the beginning of the frame.

MSB or LSB first support.

MSC8122 Technical Data, Rev. 13

Freescale Semiconductor

v

Features

Feature

Description

•

Designed to comply with IEEE® Std 802® including Std. 802.3™, 802.3u™, 802.3x™, and 802.3ac™.

Three Ethernet physical interfaces:

—10/100 Mbps MII.

—10/100 Mbps RMII.

—10/100 Mbps SMII.

•

Full and half-duplex support.

Full-duplex flow control (automatic PAUSE frame generation or software programmed PAUSE frame generation

and recognition).

•

Out-of-sequence transmit queue for initiating flow-control.

Programmable maximum frame length supports jumbo frames (up to 9.6k) and virtual local area network (VLAN)

tags and priority.

•

Retransmission from transmit FIFO following a collision.

CRC generation and verification of inbound/outbound packets.

Address recognition:

—Each exact match can be programmed to be accepted or rejected.

—Broadcast address (accept/reject).

—Exact match 48-bit individual (unicast) address.

—Hash (256-bit hash) check of individual (unicast) addresses.

—Hash (256-bit hash) check of group (multicast) addresses.

—Promiscuous mode.

•

Pattern matching:

—Up to 16 unique 4-byte patterns.

—Pattern match on bit-basis.

Ethernet Controller

—Matching range up to 256 bytes deep into the frame.

—Offsets to a maximum of 252 bytes.

—Programmable pattern size in 4-byte increments up to 64 bytes.

—Accept or reject frames if a match is detected.

—Up to eight unicast addresses for exact matches.

—Pattern matching accepts/rejects IP addresses.

Filing of receive frames based on pattern match; prioritization of frames.

Insertion with expansion or replacement for transmit frames; VLAN tag insertion.

RMON statistics.

Master DMA on the local bus for fetching descriptors and accessing the buffers.

Ethernet PHY can be exposed either on GPIO pins or on the high most significant bits of the DSI/system when

the DSI and the system bus are both 32 bits.

•

MPC8260 8-byte width buffer descriptor mode as well as 32 byte width buffer descriptor mode.

MII Bridge (MIIGSK):

—Programmable selection of the 50 MHz RMII reference clock source (external or internal).

—Independent 2 bit wide transmit and receive data paths.

—Six operating modes.

—Four general-purpose control signals.

—Programmable transmitted inter-frame bits to support inter-frame gap for frames in the SMII domain.

SMII features:

•

—Multiplexed only with GPIO signals

—Convey complete MII information between the PHY and MAC.

—Allow direct MAC-to-MAC communication in SMII mode.

—Can generate an interrupt request line while receiving inter-frame segments.

MSC8122 Technical Data, Rev. 13

vi

Freescale Semiconductor

Features

Feature

Description

•

Two signals for transmit data and receive data.

No clock, asynchronous mode.

Can be serviced either by the SC140 DSP cores or an external host on the system bus or the DSI.

Full-duplex operation.

Standard mark/space non-return-to-zero (NRZ) format.

13-bit baud rate selection.

Programmable 8-bit or 9-bit data format.

Separately enabled transmitter and receiver.

Programmable transmitter output polarity.

Two receiver wake-up methods:

—Idle line wake-up.

—Address mark wake-up.

•

Separate receiver and transmitter interrupt requests.

Nine flags, the first five can generate interrupt request:

—Transmitter empty.

UART

—Transmission complete.

—Receiver full.

—Idle receiver input.

—Receiver overrun.

—Receiver active.

—Noise error.

—Framing error.

—Parity error.

•

Receiver framing error detection.

Hardware parity checking.

1/16 bit-time noise detection.

Maximum bit rate 6.25 Mbps.

Single-wire and loop operations.

•

32 bidirectional signal lines that either serve the peripherals or act as programmable I/O ports.

Each port can be programmed separately to serve up to two dedicated peripherals, and each port supports

open-drain output mode.

General-Purpose I/O

(GPIO) Port

•

Booting from a serial EEPROM.

Uses GPIO timing.

2

I C Software Module

Two modules of 16 timers each.

•

Cyclic or one-shot.

Input clock polarity control.

Interrupt request when counting reaches a programmed threshold.

Pulse or level interrupts.

Dynamically updated programmed threshold.

Read counter any time.

Timers

Watchdog mode for the timers that connect to the device.

Eight coded hardware semaphores, locked by simple write access without need for read-modify-write mechanism.

Hardware

Semaphores

•

Consolidation of chip maskable interrupt and non-maskable interrupt sources and routing to INT_OUT,

NMI_OUT, and to the cores.

Global Interrupt

Controller (GIC)

•

Generation of 32 virtual interrupts (eight to each SC140 core) by a simple write access.

Generation of virtual NMI (one to each SC140 core) by a simple write access.

•

Low power CMOS design.

Separate power supply for internal logic (1.2 V or 1.1 V) and I/O (3.3 V).

Low-power standby modes.

Reduced Power

Dissipation

Optimized power management circuitry (instruction-dependent, peripheral-dependent, and mode-dependent).

•

0.8 mm pitch flip-chip plastic ball-grid array (FC-PBGA) with lead-free or lead-bearing spheres.

431-connection (ball).

20 mm × 20 mm.

Packaging

The real-time operating system (RTOS) fully supports device architecture (multi-core, memory hierarchy, ICache,

timers, DMA controller, interrupts, peripherals), as follows:

•

High-performance and deterministic, delivering predictive response time.

Optimized to provide low interrupt latency with high data throughput.

Preemptive and priority-based multitasking.

Fully interrupt/event driven.

Small memory footprint.

Comprehensive set of APIs.

Real-Time Operating

System (RTOS)

MSC8122 Technical Data, Rev. 13

Freescale Semiconductor

vii

Features

Feature

Description

One instance of kernel code in all four SC140 cores.

Dynamic and static memory allocation from local memory (M1) and shared memory (M2).

•

Multi-Core Support

Enables transparent inter-task communications between tasks running inside the SC140 cores and the other tasks

running in on-board devices or remote network devices:

Distributed System

Support

•

Messaging mechanism between tasks using mailboxes and semaphores.

Networking support; data transfer between tasks running inside and outside the device using networking

protocols.

•

Includes integrated device drivers for such peripherals as TDM, UART, and external buses.

•

Task debugging utilities integrated with compilers and vendors.

Board support package (BSP) for the application development system (ADS).

Integrated development environment (IDE):

—

C/C++ compiler with in-line assembly so developers can generate highly optimized DSP code. Translates

C/C++ code into parallel fetch sets and maintains high code density.

Librarian. User can create libraries for modularity.

A collection of C/C++ functions for developer use.

Highly efficient linker to produce executables from object code.

Seamlessly integrated real-time, non-intrusive multi-mode debugger for debugging highly optimized DSP

algorithms. The developer can choose to debug in source code, assembly code, or mixed mode.

Device simulation models enable design and simulation before hardware availability.

Profiler using a patented binary code instrumentation (BCI) technique helps developers identify program

design inefficiencies.

—

Software Support

—

Version control. Metrowerks® CodeWarrior® includes plug-ins for ClearCase, Visual SourceSafe, and

CVS.

•

External memory.

External host.

UART.

Boot Options

TDM.

2

I C

•

Host debug through single JTAG connector supports both processors.

MSC8103 as the MSC8122 host with both devices on the board. The MSC8103 system bus connects to the

MSC8122 DSI.

•

Flash memory for stand-alone applications.

Communications ports:

—10/100Base-T.

—155 Mbit ATM over Optical.

—T1/E1 TDM interface.

MSC8122ADS

—H.110.

—Voice codec.

—RS-232.

—High-density (MICTOR) logic analyzer connectors to monitor MSC8122 signals

—6U CompactPCI form factor.

•

Emulates MSC8122 DSP farm by connecting to three other ADS boards.

MSC8122 Technical Data, Rev. 13

viii

Freescale Semiconductor

Product Documentation

The documents listed in Table 1 are required for a complete description of the MSC8122 and are necessary to

design properly with the part. Documentation is available from a local Freescale distributor, a Freescale

semiconductor sales office, or a Freescale Literature Distribution Center. For documentation updates, visit the

Freescale DSP website. See the contact information on the back of this document.

Table 1. MSC8122 Documentation

Name

Description

Order Number

MSC8122

Technical Data

MSC8122 features list and physical, electrical, timing, and package specifications

MSC8122

User’s Guide

User information includes system functionality, getting started, and programming

topics

Availability TBD

MSC8122

Reference Manual

Detailed functional description of the MSC8122 memory and peripheral configuration, MSC8122RM

operation, and register programming

StarCore™ SC140 DSP

Core Reference Manual

Detailed description of the SC140 family processor core and instruction set

MNSC140CORE

Application Notes

Documents describing specific applications or optimized device operation including

code examples

Refer to the MSC8122

product page.

MSC8122 Technical Data, Rev. 13

Freescale Semiconductor

ix

MSC8122 Technical Data, Rev. 13

x

Freescale Semiconductor

Signals/Connections

1

The MSC8122 external signals are organized into functional groups, as shown in Table 1-1 and Figure 1-1.

Table 1-1 lists the functional groups, the number of signal connections in each group, and references the table that

gives a detailed listing of multiplexed signals within each group. Figure 1-1 shows MSC8122 external signals

organized by function.

Table 1-1. MSC8122 Functional Signal Groupings

Number of

Functional Group

Signal

Description

Connections

Power (V , V , and GND)

155

3

Table 1-2 on page 1-3

Table 1-3 on page 1-3

Table 1-4 on page 1-3

Table 1-5 on page 1-4

Table 1-6 on page 1-14

Table 1-7 on page 1-16

DD

CC

Clock

Reset and configuration

4

DSI, system bus, Ethernet, and interrupts

Memory controller

210

16

32

General-purpose input/output (GPIO), time-division multiplexed (TDM) interface,

universal asynchronous receiver/ transmitter (UART), Ethernet, and timers

Dedicated Ethernet signals

3

7

1

Table 1-8 on page 1-23

Table 1-9 on page 1-24

Table 1-10 on page 1-24

EOnCE and JTAG test access port

Reserved (denotes connections that are always reserved)

MSC8122 Technical Data, Rev. 13

Freescale Semiconductor

1-1

Signals/Connections

HD0/SWTE

HD1/DSISYNC

HD2/DSI64

HD3/MODCK1

HD4/MODCK2

HD5/CNFGS

↔

→

↔

1

26

8

1

2

1

4

1

3

1

19

4

32 ↔ A[0–31]

1

3

5

4

1

↔ TT0/HA7

↔ TT1

D

S

I

↔ TT[2–4]/CS[5–7]

→ CS[0–4]

↔ TSZ[0–3]

↔ TBST

/

HD[6–31]

S

Y

S.

B

U

S

/

E

T

H

E

R

N

E

T

HD[32-39]/D[32-39]/reserved

HD40/D40/ETHRXD0

HD41/D41/ETHRXD1

HD42/D42/ETHRXD2/reserved

HD43/D43/ETHRXD3/reserved

HD[44-45]/D[44-45]/reserved

HD46/D46/ETHTXD0

HD47/D47/ETHTXD1

HD48/D48/ETHTXD2/reserved

HD49/D49/ETHTXD3/reserved

HD[50-53]/D[50-53]/reserved

HD54/D54/ETHTX_EN

HD55/D55/ETHTX_ER/reserved

↔

IRQ1/GBL

IRQ3/BADDR31

IRQ2/BADDR30

IRQ5/BADDR29

→ BADDR28

→ BADDR27

↔ BR

↔ BG

↔ DBG

S

Y

S

T

E

M

↔

ABB/IRQ4

DBB/IRQ5

↔ TS

↔ AACK

↔ ARTRY

HD56/D56/ETHRX_DV/ETHCRS_DV

HD57/D57/ETHRX_ER

32 ↔ D[0–31]

HD58/D58/ETHMDC

HD59/D59/ETHMDIO

HD60/D60/ETHCOL/reserved

HD[61–63]/D[61-63]/reserved

HCID[0–2]

1

↔ reserved/DP0/DREQ1/EXT_BR2

↔

IRQ1/DP1/DACK1/EXT_BG2

IRQ2/DP2/DACK2/EXT_DBG2

IRQ3/DP3/DREQ2/EXT_BR3

IRQ4/DP4/DACK3/EXT_DBG3

IRQ5/DP5/DACK4/EXT_BG3

IRQ6/DP6/DREQ3

B

U

S

HCID3/HA8

HA[11–29]

M

E

M

C

HWBS[0–3]/HDBS[0–3]/HWBE[0–3]/HDBE[0–3]

HWBS[4–7]/HDBS[4–7]/HWBE[4–7]/HDBE[4–7]/

IRQ7/DP7/DREQ4

↔ TA

PWE[4–7]/PSDDQM[4–7]/PBS[4–7]

HRDS/HRW/HRDE

→

←

→

↔

1

2

1

3

1

4

1

↔ TEA

HBRST

HDST[0–1]/HA[9–10]

← NMI

D

S

I

→ NMI_OUT

↔ PSDVAL

HCS

HBCS

HTA

HCLKIN

↔

→

IRQ7/INT_OUT

BCTL0

BCTL1/CS5

M

E

M

C

GPIO0/CHIP_ID0/IRQ4/ETHTXD0

GPIO1/TIMER0/CHIP_ID1/IRQ5/ETHTXD1

GPIO2/TIMER1/CHIP_ID2/IRQ6

GPIO3/TDM3TSYN/IRQ1/ETHTXD2

GPIO4/TDM3TCLK/IRQ2/ETHTX_ER

GPIO5/TDM3TDAT/IRQ3/ETHRXD3

GPIO6/TDM3RSYN/IRQ4/ETHRXD2

GPIO7/TDM3RCLK/IRQ5/ETHTXD3

GPIO8/TDM3RDAT/IRQ6/ETHCOL

GPIO9/TDM2TSYN/IRQ7/ETHMDIO

GPIO10/TDM2TCLK/IRQ8/ETHRX_DV/ETHCRS_DV/NC

GPIO11/TDM2TDAT/IRQ9/ETHRX_ER/ETHTXD

GPIO12/TDM2RSYN/IRQ10/ETHRXD1/ETHSYNC

GPIO13/TDM2RCLK/IRQ11/ETHMDC

GPIO14/TDM2RDAT/IRQ12/ETHRXD0/NC

↔ BM[0–2]/TC[0–2]/BNKSEL[0–2]

→ ALE

G

P

I

O

/

→

PWE[0–3]/PSDDQM[0–3]/PBS[0–3]

→ PSDA10/PGPL0

→

↔

PSDWE/PGPL1

S

Y

S

POE/PSDRAS/PGPL2

PSDCAS/PGPL3

PGTA/PUPMWAIT/PGPL4/PPBS

T

D

M

/

E

T

H

E

R

N

E

T

/

→ PSDAMUX/PGPL5

De

bug

C

1

← EE0

→ EE1

→ CLKOUT

← Reserved

← CLKIN

L

K

R

E

S

E

T

GPIO15/TDM1TSYN/DREQ1

GPIO16/TDM1TCLK/DONE1/DRACK1

GPIO17/TDM1TDAT/DACK1

GPIO18/TDM1RSYN/DREQ2

GPIO19/TDM1RCLK/DACK2

GPIO20/TDM1RDAT

1

← PORESET

↔ HRESET

SRESET

↔

← RSTCONF

← TMS

J

T

A

G

← TDI

← TCK

← TRST

→ TDO

T

I

GPIO21/TDM0TSYN

GPIO22/TDM0TCLK/DONE2/DRACK2

GPIO23/TDM0TDAT/IRQ13

GPIO24/TDM0RSYN/IRQ14

GPIO25/TDM0RCLK/IRQ15

GPIO26/TDM0RDAT

M

E

R

S

/

I

2

C

GPIO27/URXD/DREQ1

GPIO28/UTXD/DREQ2

GPIO29/CHIP_ID3/ETHTX_EN

GPIO30/TIMER2/TMCLK/SDA

GPIO31/TIMER3/SCL

Ded.

Eth.

Net

1

← ETHRX_CLK/ETHSYNC_IN

← ETHTX_CLK/ETHREF_CLK/ETHCLOCK

← ETHCRS/ETHRXD

Power signals are: V , V

DD

, V

, GND, GND , and GND

. Reserved signals can be left unconnected. NC signals must not be connected.

SYN

DDH

CCSYN

H

Figure 1-1. MSC8122 External Signals

MSC8122 Technical Data, Rev. 13

1-2

Freescale Semiconductor

Power Signals

1.1 Power Signals

Table 1-2. Power and Ground Signal Inputs

Signal Name

Description

V

Internal Logic Power

dedicated for use with the device core. The voltage should be well-regulated and the input should be provided with

DD

V

DD

an extremely low impedance path to the V power rail.

DD

V

Input/Output Power

DDH

This source supplies power for the I/O buffers. The user must provide adequate external decoupling capacitors.

System PLL Power

CCSYN

V

dedicated for use with the system Phase Lock Loop (PLL). The voltage should be well-regulated and the input

CC

should be provided with an extremely low impedance path to the V power rail.

CC

GND

System Ground

An isolated ground for the internal processing logic and I/O buffers. This connection must be tied externally to all chip

ground connections, except GND

. The user must provide adequate external decoupling capacitors.

SYN

System PLL Ground

SYN

Ground dedicated for system PLL use. The connection should be provided with an extremely low-impedance path to

ground.

1.2 Clock Signals

Table 1-3. Clock Signals

Signal Description

Signal Name

Type

CLKIN

Input

Clock In

Primary clock input to the MSC8122 PLL.

CLKOUT

Reserved

Output

Input

Clock Out

The bus clock.

Reserved. Pull down to ground.

1.3 Reset and Configuration Signals

Table 1-4. Reset and Configuration Signals

Signal Name

Type

Signal Description

PORESET

Input

Power-On Reset

When asserted, this line causes the MSC8122 to enter power-on reset state.

RSTCONF

Input

Reset Configuration

Used during reset configuration sequence of the chip. A detailed explanation of its function is provided in

the MSC8122 Reference Manual. This signal is sampled upon deassertion of PORESET.

Note:

When PORESET is deasserted, the MSC8122 also samples the following signals:

• BM[0–2]—Selects the boot mode.

• MODCK[1–2]—Selects the clock configuration.

• SWTE—Enables the software watchdog timer.

• DSISYNC, DSI64, CNFGS, and CHIP_ID[0–3]—Configures the DSI.

Refer to Table 1-5 for details on these signals.

HRESET

SRESET

Input/Output Hard Reset

When asserted as an input, this signal causes the MSC8122 to enter hard reset state. After the device

enters a hard reset state, it drives the signal as an open-drain output.

Input/Output Soft Reset

When asserted as an input, this signal causes the MSC8122 to enter soft reset state. After the device

enters a soft reset state, it drives the signal as an open-drain output.

MSC8122 Technical Data, Rev. 13

Freescale Semiconductor

1-3

Signals/Connections

1.4 Direct Slave Interface, System Bus, Ethernet, and

Interrupt Signals

The direct slave interface (DSI) is combined with the system bus because they share some common signal lines.

Individual assignment of a signal to a specific signal line is configured through internal registers. Table 1-5

describes the signals in this group.

Note: Although there are fifteen interrupt request (IRQ) connections to the core processors, there are multiple

external lines that can connect to these internal signal lines. After reset, the default configuration enables

only IRQ[1–7], but includes two input lines each for IRQ[1–3] and IRQ7. The designer must select one line for

each required interrupt and reconfigure the other external signal line or lines for alternate functions.

Additional alternate IRQ lines and IRQ[8–15] are enabled through the GPIO signal lines.

Table 1-5. DSI, System Bus, Ethernet, and Interrupt Signals

Signal Name

Type

Description

HD0

Input/ Output Host Data Bus 0

Bit 0 of the DSI data bus.

SWTE

Input

Software Watchdog Timer Disable.

It is sampled on the rising edge of PORESET signal.

HD1

Input/ Output Host Data Bus 1

Bit 1 of the DSI data bus.

DSISYNC

Input

DSI Synchronous

Distinguishes between synchronous and asynchronous operation of the DSI. It is sampled on the rising

edge of PORESET signal.

HD2

Input/ Output Host Data Bus 2

Bit 2 of the DSI data bus.

DSI64

Input

DSI 64

Defines the width of the DSI and SYSTEM Data buses. It is sampled on the rising edge of PORESET

signal.

HD3

Input/ Output Host Data Bus 3

Bit 3 of the DSI data bus.

MODCK1

Input

Clock Mode 1

Defines the clock frequencies. It is sampled on the rising edge of PORESET signal.

HD4

Input/ Output Host Data Bus 4

Bit 4 of the DSI data bus.

MODCK2

Input

Clock Mode 2

Defines the clock frequencies. It is sampled on the rising edge of PORESET signal.

HD5

Input/ Output Host Data Bus 5

Bit 5 of the DSI data bus.

CNFGS

Input

Configuration Source

One signal out of two that indicates reset configuration mode. It is sampled on the rising edge of

PORESET signal.

HD[6–31]

Input/ Output Host Data Bus 6–31

Bits 6–31 of the DSI data bus.

MSC8122 Technical Data, Rev. 13

1-4

Freescale Semiconductor

Direct Slave Interface, System Bus, Ethernet, and Interrupt Signals

Table 1-5. DSI, System Bus, Ethernet, and Interrupt Signals (Continued)

Signal Name

Type

Description

HD[32–39]

Input/ Output Host Data Bus 32–39

Bits 32–39 of the DSI data bus.

D[32–39]

Input/ Output System Bus Data 32–39

For write transactions, the bus master drives valid data on this bus. For read transactions, the slave drives

valid data on this bus.

Reserved

Input

If the Ethernet port is enabled and multiplexed with the DSI/System bus, these pins are reserved and can

be left unconnected.

HD40

Input/ Output Host Data Bus 40

Bit 40 of the DSI data bus.

D40

Input/ Output System Bus Data 40

For write transactions, the bus master drives valid data on this line. For read transactions, the slave drives

valid data on this bus.

ETHRXD0

Input

Ethernet Receive Data 0

In MII and RMII modes, bit 0 of the Ethernet receive data.

HD41

Input/ Output Host Data Bus 41

Bit 41 of the DSI data bus.

D41

Input/ Output System Bus Data 41

For write transactions, the bus master drives valid data on this line. For read transactions, the slave drives

valid data on this bus.

ETHRXD1

Input

Ethernet Receive Data 1

In MII and RMII modes, bit 1 of the Ethernet receive data.

HD42

Input/ Output Host Data Bus 42

Bit 42 of the DSI data bus.

D42

Input/ Output System Bus Data 42

For write transactions, the bus master drives valid data on this line. For read transactions, the slave drives

valid data on this bus.

ETHRXD2

Input

Ethernet Receive Data 2

In MII mode only, bit 2 of the Ethernet receive data.

Reserved

In RMII mode, this pin is reserved and can be left unconnected.

HD43

Input/ Output Host Data Bus 43

Bit 43 of the DSI data bus.

D43

Input/ Output System Bus Data 43

For write transactions, the bus master drives valid data on this line. For read transactions, the slave drives

valid data on this bus.

ETHRXD3

Input

Ethernet Receive Data 3

In MII mode only, bit 3 of the Ethernet receive data.

Reserved

In RMII mode, this pin is reserved and can be left unconnected.

HD[44–45]

Input/ Output Host Data Bus 44–45

Bits 44–45 of the DSI data bus.

D[44–56]

Reserved

Input/ Output System Bus Data 44–45

For write transactions, the bus master drives valid data on this bus. For read transactions, the slave drives

valid data on this bus.

Input

If the Ethernet port is enabled and multiplexed with the DSI/System bus, these pins are reserved and can

be left unconnected.

MSC8122 Technical Data, Rev. 13

Freescale Semiconductor

1-5

Signals/Connections

Signal Name

Table 1-5. DSI, System Bus, Ethernet, and Interrupt Signals (Continued)

Type Description

HD46

Input/ Output Host Data Bus 46

Bit 46 of the DSI data bus.

D46

Input/ Output System Bus Data 46

For write transactions, the bus master drives valid data on this line. For read transactions, the slave drives

valid data on this bus.

ETHTXD0

Output

Ethernet Transmit Data 0

In MII and RMII modes, bit 0 of the Ethernet transmit data.

HD47

Input/ Output Host Data Bus 47

Bit 47 of the DSI data bus.

D47

Input/ Output System Bus Data 47

For write transactions, the bus master drives valid data on this line. For read transactions, the slave drives

valid data on this bus.

ETHTXD1

Output

Ethernet Transmit Data 1

In MII and RMII modes, bit 1 of the Ethernet transmit data.

HD48

Input/ Output Host Data Bus 48

Bit 48 of the DSI data bus.

D48

Input/ Output System Bus Data 48

For write transactions, the bus master drives valid data on this line. For read transactions, the slave drives

valid data on this bus.

ETHTXD2

Output

Input

Ethernet Transmit Data 2

In MII mode only, bit 2 of the Ethernet transmit data.

Reserved

In RMII mode, this pin is reserved and can be left unconnected.

HD49

Input/ Output Host Data Bus 49

Bit 49 of the DSI data bus.

D49

Input/ Output System Bus Data 49

For write transactions, the bus master drives valid data on this line. For read transactions, the slave drives

valid data on this bus.

ETHTXD3

Output

Input

Ethernet Transmit Data 3

In MII mode only, bit 3 of the Ethernet transmit data.

Reserved

In RMII mode, this pin is reserved and can be left unconnected.

HD[50–53]

Input/ Output Host Data Bus 50–53

Bits 50–53 of the DSI data bus.

D[50–53]

Input/ Output System Bus Data 50–53

For write transactions, the bus master drives valid data on this bus. For read transactions, the slave drives

valid data on this bus.

Reserved

Input

If the Ethernet port is enabled and multiplexed with the DSI/System bus, these pins are reserved and can

be left unconnected.

HD54

Input/ Output Host Data Bus 54

Bit 54 of the DSI data bus.

D54

Input/ Output System Bus Data 54

For write transactions, the bus master drives valid data on this line. For read transactions, the slave drives

valid data on this bus.

ETHTX_EN

Output

Ethernet Transmit Data Enable

In MII and RMII modes, indicates that the transmit data is valid.

MSC8122 Technical Data, Rev. 13

1-6

Freescale Semiconductor

Direct Slave Interface, System Bus, Ethernet, and Interrupt Signals

Table 1-5. DSI, System Bus, Ethernet, and Interrupt Signals (Continued)

Signal Name

Type

Description

HD55

Input/ Output Host Data Bus 55

Bit 55 of the DSI data bus.

D55

Input/ Output System Bus Data 55

For write transactions, the bus master drives valid data on this line. For read transactions, the slave drives

valid data on this bus.

ETHTX_ER

Output

Input

Ethernet Transmit Data Error

In MII mode only, indicates a transmit data error.

Reserved

In RMII mode, this pin is reserved and can be left unconnected.

HD56

Input/ Output Host Data Bus 56

Bit 56 of the DSI data bus.

D56

Input/ Output System Bus Data 56

For write transactions, the bus master drives valid data on this line. For read transactions, the slave drives

valid data on this bus.

ETHRX_DV

Input

Ethernet Receive Data Valid

Indicates that the receive data is valid.

ETHCRS_DV

Ethernet Carrier Sense/Receive Data Valid

In RMII mode, indicates that a carrier is detected and after the connection is established that the receive

data is valid.

HD57

Input/ Output Host Data Bus 57

Bit 57 of the DSI data bus.

D57

Input/ Output System Bus Data 57

For write transactions, the bus master drives valid data on this line. For read transactions, the slave drives

valid data on this bus.

ETHRX_ER

Input

Ethernet Receive Data Error

In MII and RMII modes, indicates a receive data error.

HD58

Input/ Output Host Data Bus 58

Bit 58 of the DSI data bus.

D58

Input/ Output System Bus Data 58

For write transactions, the bus master drives valid data on this line. For read transactions, the slave drives

valid data on this bus.

ETHMDC

Output

Ethernet Management Clock

In MII and RMII modes, used for the MDIO reference clock.

HD59

Input/ Output Host Data Bus 59

Bit 59 of the DSI data bus.

D59

Input/ Output System Bus Data 59

For write transactions, the bus master drives valid data on this line. For read transactions, the slave drives

valid data on this bus.

ETHMDIO

Input/ Output Ethernet Management Data

In MII and RMII modes, used for station management data input/output.

MSC8122 Technical Data, Rev. 13

Freescale Semiconductor

1-7

Signals/Connections

Signal Name

Table 1-5. DSI, System Bus, Ethernet, and Interrupt Signals (Continued)

Type Description

HD60

Input/ Output Host Data Bus 60

Bit 60 of the DSI data bus.

D60

Input/ Output System Bus Data 60

For write transactions, the bus master drives valid data on this line. For read transactions, the slave drives

valid data on this bus.

ETHCOL

Input/ Output Ethernet Collision

In MII mode only, indicates that a collision was detected.

Reserved

Input

In RMII mode, this pin is reserved and can be left unconnected.

HD[61–63]

Input/ Output Host Data Bus 61–63

Bits 61–63 of the DSI data bus.

D[61–63]

Input/ Output System Bus Data 61–63

For write transactions, the bus master drives valid data on this bus. For read transactions, the slave drives

valid data on this bus.

Reserved

HCID[0–2]

Input

If the Ethernet port is enabled and multiplexed with the DSI/System bus, these pins are reserved and can

be left unconnected.

Host Chip ID 0–2

With HCID3, carries the chip ID of the DSI. The DSI is accessed only if HCS is asserted and HCID[0–3]

matches the Chip_ID, or if HBCS is asserted.

HCID3

Input

Host Chip ID 3

With HCI[0–2], carries the chip ID of the DSI. The DSI is accessed only if HCS is asserted and HCID[0–3]

matches the Chip_ID, or if HBCS is asserted.

HA8

Input

Host Bus Address 8

Used by an external host to access the internal address space.

HA[11–29]

HWBS[0–3]

Host Bus Address 11–29

Used by external host to access the internal address space.

Host Write Byte Strobes (In Asynchronous dual mode)

One bit per byte is used as a strobe for host write accesses.

HDBS[0–3]

HWBE[0–3]

HDBE[0–3]

Input

Host Data Byte Strobe (in Asynchronous single mode)

One bit per byte is used as a strobe for host read or write accesses

Host Write Byte Enable (In Synchronous dual mode)

One bit per byte is used to indicate a valid data byte for host read or write accesses.

Host Data Byte Enable (in Synchronous single mode)

One bit per byte is used as a strobe enable for host write accesses

MSC8122 Technical Data, Rev. 13

1-8

Freescale Semiconductor

Direct Slave Interface, System Bus, Ethernet, and Interrupt Signals

Table 1-5. DSI, System Bus, Ethernet, and Interrupt Signals (Continued)

Signal Name

HWBS[4–7]

Type

Description

Input

Host Write Byte Strobes (In Asynchronous dual mode)

One bit per byte is used as a strobe for host write accesses.

HDBS[4–7]

HWBE[4–7]

HDBE[4–7]

PWE[4–7]

Input

Host Data Byte Strobe (in Asynchronous single mode)

One bit per byte is used as a strobe for host read or write accesses

Host Write Byte Enable (In Synchronous dual mode)

One bit per byte is used to indicate a valid data byte for host write accesses.

Input

Host Data Byte Enable (in Synchronous single mode)

One bit per byte is used as a strobe enable for host read or write accesses

Output

System Bus Write Enable

Outputs of the bus general-purpose chip-select machine (GPCM). These pins select byte lanes for write

operations.

PSDDQM[4–7]

PBS[4–7]

Output

System Bus SDRAM DQM

From the SDRAM control machine. These pins select specific byte lanes of SDRAM devices.

System Bus UPM Byte Select

From the UPM in the memory controller, these signals select specific byte lanes during memory

operations. The timing of these pins is programmed in the UPM. The actual driven value depends on the

address and size of the transaction and the port size of the accessed device.

HRDS

Input

Host Read Data Strobe (In Asynchronous dual mode)

Used as a strobe for host read accesses.

HRW

Host Read/Write Select (in Asynchronous/Synchronous single mode)

Host read/write select.

HRDE

Input

Host Read Data Enable (In Synchronous dual mode)

Indicates valid data for host read accesses.

HBRST

Host Burst

The host asserts this pin to indicate that the current transaction is a burst transaction in synchronous

mode only.

HDST[0–1]

Input

Host Data Structure 0–1

Defines the data structure of the host access in DSI little-endian mode.

HA[9–10]

HCS

Host Bus Address 9–10

Used by an external host to access the internal address space.

Input

Host Chip Select

DSI chip select. The DSI is accessed only if HCS is asserted and HCID[0–3] matches the Chip_ID.

HBCS

Host Broadcast Chip Select

DSI chip select for broadcast mode. Enables more than one DSI to share the same host chip-select pin for

broadcast write accesses.

HTA

Output

Input

Host Transfer Acknowledge

Upon a read access, indicates to the host when the data on the data bus is valid. Upon a write access,

indicates to the host that the data on the data bus was written to the DSI write buffer.

HCLKIN

A[0–31]

Host Clock Input

Host clock signal for DSI synchronous mode.

Input/ Output Address Bus

When the MSC8122 is in external master bus mode, these pins function as the system address bus. The

MSC8122 drives the address of its internal bus masters and responds to addresses generated by external

bus masters. When the MSC8122 is in internal master bus mode, these pins are used as address lines

connected to memory devices and are controlled by the MSC8122 memory controller.

TT0

Input/ Output Bus Transfer Type 0

The bus master drives this pins during the address tenure to specify the type of the transaction.

HA7

Host Bus Address 7

Used by an external host to access the internal address space.

MSC8122 Technical Data, Rev. 13

Freescale Semiconductor

1-9

Signals/Connections

Signal Name

Table 1-5. DSI, System Bus, Ethernet, and Interrupt Signals (Continued)

Type Description

TT1

Input/ Output Bus Transfer Type 1

The bus master drives this pins during the address tenure to specify the type of the transaction. Some

applications use only the TT1 signal, for example, from MSC8122 to MSC8122 or MSC8122 to MSC8101

and vice versa. In these applications, TT1 functions as read/write signal.

TT[2–4]

Input/ Output Bus Transfer Type 2–4

The bus master drives these pins during the address tenure to specify the type of the transaction.

CS[5–7]

CS[0–4]

TSZ[0–3]

Output

Chip Select 5–7

Enables specific memory devices or peripherals connected to the system bus.

Chip Select 0–4

Enables specific memory devices or peripherals connected to the system bus.

Input/ Output Transfer Size 0–3

The bus master drives these pins with a value indicating the number of bytes transferred in the current

transaction.

TBST

Input/ Output Bus Transfer Burst

The bus master asserts this pin to indicate that the current transaction is a burst transaction (transfers

eight words).

1

IRQ1

Input

Interrupt Request 1

One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the

SC140 core.

1

GBL

Output

Input

Global

When a master within the MSC8122 initiates a bus transaction, it drives this pin. Assertion of this pin

indicates that the transfer is global and should be snooped by caches in the system.

1

IRQ3

Interrupt Request 3

One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the

SC140 core.

1

BADDR31

Output

Burst Address 31

Five burst address output pins are outputs of the memory controller. These pins connect directly to

burstable memory devices without internal address incrementors controlled by the MSC8122 memory

controller.

1

IRQ2

Input

Interrupt Request 2

One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the

SC140 core.

1

BADDR30

Output

Burst Address 30

Five burst address output pins are outputs of the memory controller. These pins connect directly to

burstable memory devices without internal address incrementors controlled by the MSC8122 memory

controller.

1

IRQ5

Input

Interrupt Request 5

One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the

SC140 core.

1

BADDR29

Output

Bus Burst Address 29

Five burst address output pins are outputs of the memory controller. These pins connect directly to

burstable memory devices without internal address incrementors controlled by the MSC8122 memory

controller.

BADDR28

BADDR27

Output

Burst Address 28

Five burst address output pins are outputs of the memory controller. These pins connect directly to

burstable memory devices without internal address incrementors controlled by the MSC8122 memory

controller.

Burst Address 27

Five burst address output pins are outputs of the memory controller. These pins connect directly to

burstable memory devices without internal address incrementors controlled by the MSC8122 memory

controller.

MSC8122 Technical Data, Rev. 13

1-10

Freescale Semiconductor

Direct Slave Interface, System Bus, Ethernet, and Interrupt Signals

Table 1-5. DSI, System Bus, Ethernet, and Interrupt Signals (Continued)

Signal Name

Type

Description

2

BR

Input/ Output Bus Request

When an external arbiter is used, the MSC8122 asserts this pin as an output to request ownership of the

bus. When the MSC8122 controller is used as an internal arbiter, an external master asserts this pin as an

input to request bus ownership.

2

BG

Input/ Output Bus Grant

When the MSC8122 acts as an internal arbiter, it asserts this pin as an output to grant bus ownership to

an external bus master. When an external arbiter is used, it asserts this pin as an input to grant bus

ownership to the MSC8122.

2

DBG

ABB

Input/ Output Data Bus Grant

When the MSC8122 acts as an internal arbiter, it asserts this pin as an output to grant data bus ownership

to an external bus master. When an external arbiter is used, it asserts this pin as an input to grant data

bus ownership to the MSC8122.

1

Input/ Output Address Bus Busy

The MSC8122 asserts this pin as an output for the duration of the address bus tenure. Following an

AACK, which terminates the address bus tenure, the MSC8122 deasserts ABB for a fraction of a bus

cycle and then stops driving this pin. The MSC8122 does not assume bus ownership as long as it senses

this pin is asserted as an input by an external bus master.

IRQ4

Input

Interrupt Request 4

One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the

SC140 core.

1

DBB

Input/ Output Data Bus Busy

The MSC8122 asserts this pin as an output for the duration of the data bus tenure. Following a TA, which

terminates the data bus tenure, the MSC8122 deasserts DBB for a fraction of a bus cycle and then stops

driving this pin. The MSC8122 does not assume data bus ownership as long as it senses that this pin is

asserted as an input by an external bus master.

IRQ5

TS

Input

Interrupt Request 5

One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the

SC140 core.

Input/ Output Bus Transfer Start

Assertion of this pin signals the beginning of a new address bus tenure. The MSC8122 asserts this signal

when one of its internal bus masters begins an address tenure. When the MSC8122 senses that this pin is

asserted by an external bus master, it responds to the address bus tenure as required (snoop if enabled,

access internal MSC8122 resources, memory controller support).

AACK

Input/ Output Address Acknowledge

A bus slave asserts this signal to indicate that it has identified the address tenure. Assertion of this signal

terminates the address tenure.

ARTRY

D[0–31]

Input/ Output Address Retry

Assertion of this signal indicates that the bus master should retry the bus transaction. An external master

asserts this signal to enforce data coherency with its caches and to prevent deadlock situations.

Input/ Output Data Bus Bits 0–31

In write transactions, the bus master drives the valid data on this bus. In read transactions, the slave

drives the valid data on this bus.

Reserved

Input

The primary configuration selection (default after reset) is reserved.

DP0

Input/ Output System Bus Data Parity 0

The agent that drives the data bus also drives the data parity signals. The value driven on the data parity

0 pin should give odd parity (odd number of ones) on the group of signals that includes data parity 0 and

D[0–7].

DREQ1

Input

DMA Request 1

Used by an external peripheral to request DMA service.

EXT_BR2

External Bus Request 2

An external master asserts this pin to request bus ownership from the internal arbiter.

MSC8122 Technical Data, Rev. 13

Freescale Semiconductor

1-11

Signals/Connections

Table 1-5. DSI, System Bus, Ethernet, and Interrupt Signals (Continued)

Signal Name

IRQ1

Type

Description

Input

Interrupt Request 1

One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the

SC140 core.

DP1

Input/ Output System Bus Data Parity 1

The agent that drives the data bus also drives the data parity signals. The value driven on the data parity

1 pin should give odd parity (odd number of ones) on the group of signals that includes data parity 1 and

D[8–15].

DACK1

Output

DMA Acknowledge 1

The DMA controller drives this output to acknowledge the DMA transaction on the bus.

2

EXT_BG2

Output

Input

External Bus Grant 2

The MSC8122 asserts this pin to grant bus ownership to an external bus master.

IRQ2

Interrupt Request 2

One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the

SC140 core.

DP2

Input/ Output System Bus Data Parity 2

The agent that drives the data bus also drives the data parity signals. The value driven on the data parity

2 pin should give odd parity (odd number of ones) on the group of signals that includes data parity 2 and

D[16–23].

DACK2

Output

DMA Acknowledge 2

The DMA controller drives this output to acknowledge the DMA transaction on the bus.

2

EXT_DBG2

Output

Input

External Data Bus Grant 2

The MSC8122 asserts this pin to grant data bus ownership to an external bus master.

IRQ3

Interrupt Request 3

One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the

SC140 core.

DP3

Input/ Output System Bus Data Parity 3

The agent that drives the data bus also drives the data parity signals. The value driven on the data parity

3 pin should give odd parity (odd number of ones) on the group of signals that includes data parity 3 and

D[24–31].

DREQ2

Input

DMA Request 2

Used by an external peripheral to request DMA service.

2

EXT_BR3

Input

External Bus Request 3

An external master should assert this pin to request bus ownership from the internal arbiter.

IRQ4

Interrupt Request 4

One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the

SC140 core.

DP4

Input/ Output System Bus Data Parity 4

The agent that drives the data bus also drives the data parity signals. The value driven on the data parity

4 pin should give odd parity (odd number of ones) on the group of signals that includes data parity 4 and

D[32–39].

DACK3

Output

DMA Acknowledge 3

The DMA controller drives this output to acknowledge the DMA transaction on the bus.

2

EXT_DBG3

External Data Bus Grant 3

The MSC8122 asserts this pin to grant data bus ownership to an external bus master.

MSC8122 Technical Data, Rev. 13

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Freescale Semiconductor

Direct Slave Interface, System Bus, Ethernet, and Interrupt Signals

Table 1-5. DSI, System Bus, Ethernet, and Interrupt Signals (Continued)

Signal Name

Type

Description

IRQ5

Input

Interrupt Request 5

One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the

SC140 core.

DP5

Input/ Output System Bus Data Parity 5

The agent that drives the data bus also drives the data parity signals. The value driven on the data parity

5 pin should give odd parity (odd number of ones) on the group of signals that includes data parity 5 and

D[40–47].

DACK4

Output

DMA Acknowledge 4

The DMA controller drives this output to acknowledge the DMA transaction on the bus.

2

EXT_BG3

Output

Input

External Bus Grant 3

The MSC8122 asserts this pin to grant bus ownership to an external bus.

IRQ6

Interrupt Request 6

One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the

SC140 core.

DP6

Input/ Output System Bus Data Parity 6

The agent that drives the data bus also drives the data parity signals. The value driven on the data parity

6 pin should give odd parity (odd number of ones) on the group of signals that includes data parity 6 and

D[48–55].

DREQ3

Input

DMA Request 3

Used by an external peripheral to request DMA service.

IRQ7

Interrupt Request 7

One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the

SC140 core.

DP7

Input/ Output System Bus Data Parity 7

The agent that drives the data bus also drives the data parity signals. The value driven on the data parity

7 pin should give odd parity (odd number of ones) on the group of signals that includes data parity 7 and

D[56–63].

DREQ4

TA

Input

DMA Request 4

Used by an external peripheral to request DMA service.

Input/ Output Transfer Acknowledge

Indicates that a data beat is valid on the data bus. For single-beat transfers, TA assertion indicates the

termination of the transfer. For burst transfers, TA is asserted eight times to indicate the transfer of eight

data beats, with the last assertion indicating the termination of the burst transfer.

TEA

Input/ Output Transfer Error Acknowledge

Indicates a failure of the data tenure transaction.The masters within the MSC8122 monitor the state of this

pin. The MSC8122 internal bus monitor can assert this pin if it identifies a bus transfer that does not

complete.

NMI

Input

Non-Maskable Interrupt

When an external device asserts this line, it generates an non-maskable interrupt in the MSC8122, which

is processed internally (default) or is directed to an external host for processing (see NMI_OUT).

NMI_OUT

Output

Non-Maskable Interrupt Output

An open-drain pin driven from the MSC8122 internal interrupt controller. Assertion of this output indicates

that a non-maskable interrupt is pending in the MSC8122 internal interrupt controller, waiting to be

handled by an external host.

PSDVAL

Input/ Output Port Size Data Valid

Indicates that a data beat is valid on the data bus. The difference between the TA pin and the PSDVAL pin

is that the TA pin is asserted to indicate data transfer terminations, while the PSDVAL signal is asserted

with each data beat movement. When TA is asserted, PSDVAL is always asserted. However, when

PSDVAL is asserted, TA is not necessarily asserted. For example, if the DMA controller initiates a double

word (2 × 64 bits) transaction to a memory device with a 32-bit port size, PSDVAL is asserted three times

without TA and, finally, both pins are asserted to terminate the transfer.

MSC8122 Technical Data, Rev. 13

Freescale Semiconductor

1-13

Signals/Connections

Table 1-5. DSI, System Bus, Ethernet, and Interrupt Signals (Continued)

Signal Name

IRQ7

Type

Description

Input

Interrupt Request 7

One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the

SC140 core.

INT_OUT

Output

Interrupt Output

Assertion of this output indicates that an unmasked interrupt is pending in the MSC8122 internal interrupt

controller.

Notes: 1. See the System Interface Unit (SIU) chapter in the MSC8122 Reference Manual for details on how to configure these pins.

2. When used as the bus control arbiter, the MSC8122 can support up to three external bus masters. Each master uses its own

set of Bus Request, Bus Grant, and Data Bus Grant signals (BR/BG/DBG, EXT_BR2/EXT_BG2/EXT_DBG2, and

EXT_BR3/EXT_BG3/EXT_DBG3). Each of these signal sets must be configured to indicate whether the external master is or

is not a MSC8122 master device. See the Bus Configuration Register (BCR) description in the System Interface Unit (SIU)

chapter in the MSC8122 Reference Manual for details on how to configure these pins. The second and third set of pins is

defined by EXT_xxx to indicate that they can only be used with external master devices. The first set of pins (BR/BG/DBG)

have a dual function. When the MSC8122 is not the bus arbiter, it uses these signals (BR/BG/DBG) to obtain master control of

the bus.

1.5 Memory Controller Signals

Refer to the Memory Controller chapter in the MSC8122 Reference Manual for details on configuring these

signals.

Table 1-6. Memory Controller Signals

Signal Name

Type

Description

BCTL0

Output

System Bus Buffer Control 0

Controls buffers on the data bus. Usually used with BCTL1. The exact function of this pin is defined by the

value of SIUMCR[BCTLC].

BCTL1

Output

System Bus Buffer Control 1

Controls buffers on the data bus. Usually used with BCTL0. The exact function of this pin is defined by the

value of SIUMCR[BCTLC].

CS5

Output

Input

System and Local Bus Chip Select 5

Enables specific memory devices or peripherals connected to MSC8122 buses.

BM[0–2]

Boot Mode 0–2

Defines the boot mode of the MSC8122. This signal is sampled on PORESET deassertion.

TC[0–2]

Input/ Output Transfer Code 0–2

The bus master drives these pins during the address tenure to specify the type of the code.

BNKSEL[0–2]

ALE

Output

Bank Select 0–2

Selects the SDRAM bank when the MSC8122 is in 60x-compatible bus mode.

Address Latch Enable

Controls the external address latch used in an external master bus.

PWE[0–3]

System Bus Write Enable

Outputs of the bus general-purpose chip-select machine (GPCM). These pins select byte lanes for write

operations.

PSDDQM[0–3]

PBS[0–3]

Output

System Bus SDRAM DQM

From the SDRAM control machine. These pins select specific byte lanes of SDRAM devices.

System Bus UPM Byte Select

From the UPM in the memory controller, these signals select specific byte lanes during memory

operations. The timing of these pins is programmed in the UPM. The actual driven value depends on the

address and size of the transaction and the port size of the accessed device.

MSC8122 Technical Data, Rev. 13

1-14

Freescale Semiconductor

Memory Controller Signals

Table 1-6. Memory Controller Signals (Continued)

Signal Name

PSDA10

Type

Description

Output

System Bus SDRAM A10

From the bus SDRAM controller. The precharge command defines which bank is precharged. When the

row address is driven, it is a part of the row address. When column address is driven, it is a part of column

address.

PGPL0

Output

System Bus UPM General-Purpose Line 0

One of six general-purpose output lines from the UPM. The values and timing of this pin are programmed

in the UPM.

PSDWE

Output

System Bus SDRAM Write Enable

From the bus SDRAM controller. Should connect to SDRAM WE input.

PGPL1

System Bus UPM General-Purpose Line 1

One of six general-purpose output lines from the UPM. The values and timing of this pin are programmed

in the UPM.

POE

Output

System Bus Output Enable

From the bus GPCM. Controls the output buffer of memory devices during read operations.

PSDRAS

PGPL2

System Bus SDRAM RAS

From the bus SDRAM controller. Should connect to SDRAM RAS input.

System Bus UPM General-Purpose Line 2

One of six general-purpose output lines from the UPM. The values and timing of this pin are programmed

in the UPM.

PSDCAS

Output

System Bus SDRAM CAS

From the bus SDRAM controller. Should connect to SDRAM CAS input.

PGPL3

System Bus UPM General-Purpose Line 3

One of six general-purpose output lines from the UPM. The values and timing of this pin are programmed

in the UPM.

PGTA

Input

System GPCM TA

Terminates external transactions during GPCM operation. Requires an external pull-up resistor for proper

operation.

PUPMWAIT

PGPL4

System Bus UPM Wait

An external device holds this pin low to force the UPM to wait until the device is ready to continue the

operation.

Output

System Bus UPM General-Purpose Line 4

One of six general-purpose output lines from the UPM. The values and timing of this pin are programmed

in the UPM.

PPBS

Output

System Bus Parity Byte Select

In systems that store data parity in a separate chip, this output is used as the byte-select for that chip.

PSDAMUX

System Bus SDRAM Address Multiplexer

Controls the system bus SDRAM address multiplexer when the MSC8122 is in external master mode.

PGPL5

Output

System Bus UPM General-Purpose Line 5

One of six general-purpose output lines from the UPM. The values and timing of this pin are programmed

in the UPM.

MSC8122 Technical Data, Rev. 13

Freescale Semiconductor

1-15

Signals/Connections

1.6 GPIO, TDM, UART, and Timer Signals

The general-purpose input/output (GPIO), time-division multiplexed (TDM), universal asynchronous

receiver/transmitter (UART), and timer signals are grouped together because they use a common set of signal lines.

Individual assignment of a signal to a specific signal line is configured through internal registers. Table 1-7

describes the signals in this group.

Table 1-7. GPIO, TDM, UART, Ethernet, and Timer Signals

Signal Name

GPIO0

Type

Description

Input/ Output General-Purpose Input Output 0

One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs.

CHIP_ID0

IRQ4

Input

Chip ID 0

Determines the chip ID of the MSC8122 DSI. It is sampled on the rising edge of PORESET signal.

Interrupt Request 4

One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the

SC140 core.

ETHTXD0

Output

Ethernet Transmit Data 0

For MII or RMII mode, bit 0 of the Ethernet transmit data.

GPIO1

Input/ Output General-Purpose Input Output 1

One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs.

Input/ Output Timer 0

Each signal is configured as either input to or output from the counter. See the MSC8122 Reference

TIMER0

CHIP_ID1

IRQ5

Manual for configuration details.

Input

Chip ID 1

Determines the chip ID of the MSC8122 DSI. It is sampled on the rising edge of PORESET signal.

Interrupt Request 5

One of the fifteen external lines that can request a service routine, via the internal interrupt controller, from

the SC140 core.

ETHTXD1

Output

Ethernet Transmit Data 1

For MII or RMII mode, bit 1 of the Ethernet transmit data.

GPIO2

Input/ Output General-Purpose Input Output 2

One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For

details, refer to the MSC8122 Reference Manual.

TIMER1

Input/ Output Timer 1

Each signal is configured as either input to or output from the counter. For the configuration of the pin

direction, refer to the MSC8122 Reference Manual.

CHIP_ID2

IRQ6

Input

Chip ID 2

Determines the chip ID of the MSC8122 DSI. It is sampled on the rising edge of PORESET signal.

Interrupt Request 6

One of the fifteen external lines that can request a service routine, via the internal interrupt controller, from

the SC140 core.

MSC8122 Technical Data, Rev. 13

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Freescale Semiconductor

GPIO, TDM, UART, and Timer Signals

Table 1-7. GPIO, TDM, UART, Ethernet, and Timer Signals (Continued)

Signal Name

GPIO3

Type

Description

Input/ Output General-Purpose Input Output 3

One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For

details, refer to the MSC8122 Reference Manual GPIO programming model.

TDM3TSYN

IRQ1

Input/ Output TDM3 Transmit Frame Sync

Transmit frame sync for TDM 3.

Input

Interrupt Request 1

One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the

SC140 core.

ETHTXD2

Output

Ethernet Transmit Data 2

For MII mode only, bit 2 of the Ethernet transmit data.

GPIO4

Input/ Output General-Purpose Input Output 4

One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For

details, refer to the MSC8122 Reference Manual GPIO programming model.

TDM3TCLK

IRQ2

Input

TDM3 Transmit Clock

Transmit Clock for TDM 3

Interrupt Request 2

One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the

SC140 core.

ETHTX_ER

Output

Ethernet Transmit Data Error

For MII mode only, indicates whether a transmit data error occurred.

GPIO5

Input/ Output General-Purpose Input/Output 5

One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For

details, refer to the MSC8122 Reference Manual GPIO programming model.

TDM3TDAT

IRQ3

Input/ Output TDM3 Serial Transmitter Data

The serial transmit data signal for TDM 3. As an output, it provides the DATA_D signal for TDM 3. For

configuration details, refer to the MSC8122 Reference Manual chapter describing TDM operation.

Input

Interrupt Request 3

One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the

SC140 core.

ETHRXD3

Ethernet Receive Data 3

For MII mode only, bit 3 of the Ethernet receive data.

GPIO6

Input/ Output General-Purpose Input Output 6

One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For

details, refer to the MSC8122 Reference Manual GPIO programming model.

TDM3RSYN

IRQ4

Input/ Output TDM3 Receive Frame Sync

The receive sync signal for TDM 3. As an input, this can be the DATA_B data signal for TDM 3.For

configuration details, refer to the MSC8122 Reference Manual chapter describing TDM operation.

Input

Interrupt Request 4

One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the

SC140 core.

ETHRXD2

Ethernet Receive Data 2

For MII mode only, bit 2 of the Ethernet receive data.

MSC8122 Technical Data, Rev. 13

Freescale Semiconductor

1-17

Signals/Connections

Signal Name

Table 1-7. GPIO, TDM, UART, Ethernet, and Timer Signals (Continued)

Type Description

GPIO7

Input/ Output General-Purpose Input Output 7

One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For

details, refer to the MSC8122 Reference Manual GPIO programming model.

TDM3RCLK

IRQ5

Input/ Output TDM3 Receive Clock

The receive clock signal for TDM 3. As an output, this can be the DATA_C data signal for TDM 3. For

configuration details, refer to the MSC8122 Reference Manual chapter describing TDM operation.

Input

Interrupt Request 5

One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the

SC140 core.

ETHTXD3

Output

Ethernet Transmit Data 3

For MII mode only, bit 3 of the Ethernet transmit data.

GPIO8

Input/ Output General-Purpose Input Output 8

One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For

details, refer to the MSC8122 Reference Manual GPIO programming model.

TDM3RDAT

IRQ6

Input/ Output TDM3 Serial Receiver Data

The receive data signal for TDM 3. As an input, this can be the DATA_A data signal for TDM 3. For

configuration details, refer to the MSC8122 Reference Manual chapter describing TDM operation.

Input

Interrupt Request 6

One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the

SC140 core.

ETHCOL

Ethernet Collision

For MII mode only, indicates whether a collision was detected.

GPIO9

Input/ Output General-Purpose Input Output 9

One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For

details, refer to the MSC8122 Reference Manual GPIO programming model.

TDM2TSYN

IRQ7

Input/ Output TDM2 Transmit frame Sync

Transmit Frame Sync for TDM 2.

Input

Interrupt Request 7

One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the

SC140 core.

ETHMDIO

Input/ Output Ethernet Management Data

Station management data input/output line in MII, RMII, and SMII modes.

GPIO10

Input/ Output General-Purpose Input Output 10

One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For

details, refer to the MSC8122 Reference Manual GPIO programming model.

TDM2TCLK

IRQ8

Input

TDM 2 Transmit Clock

Transmit Clock for TDM 2.

Interrupt Request 8

One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the

SC140 core.

ETHRX_DV

ETHCRS_DV

NC

Input

Ethernet Receive Data Valid

In MII mode, this signal indicates that the receive data is valid.

Ethernet Carrier Sense/Receive Data Valid

In RMII mode, this signal indicates that a carrier is sense or that the receive data is valid.

Not Connected

For SMII mode, this signal must be left unconnected.

MSC8122 Technical Data, Rev. 13

1-18

Freescale Semiconductor

GPIO, TDM, UART, and Timer Signals

Table 1-7. GPIO, TDM, UART, Ethernet, and Timer Signals (Continued)

Signal Name

GPIO11

Type

Description

Input/ Output General-Purpose Input Output 11

One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For

details, refer to the MSC8122 Reference Manual GPIO programming model.

TDM2TDAT

IRQ9

Input/ Output TDM2 Serial Transmitter Data

The transmit data signal for TDM 2. As an output, this can be the DATA_D data signal for TDM 2. For

configuration details, refer to the MSC8122 Reference Manual chapter describing TDM operation.

Input

Interrupt Request 9

One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the

SC140 core.

ETHRX_ER

Input

Ethernet Receive Data Error

In MII and RMII modes, indicates a receive data error.

ETHTXD

Output

Ethernet Transmit Data

In SMII, used as the Ethernet transmit data line.

GPIO12

Input/ Output General-Purpose Input Output 12

One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For

details, refer to the MSC8122 Reference Manual GPIO programming model.

TDM2RSYN

IRQ10

Input/ Output TDM2 Receive Frame Sync

The receive sync signal for TDM 2. As an input, this can be the DATA_B data signal for TDM 2. For

configuration details, refer to the MSC8122 Reference Manual chapter describing TDM operation.

Input

Interrupt Request 10

One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the

SC140 core.

ETHRXD1

Input

Ethernet Receive Data 1

Bit 1 of the Ethernet receive data (MII and RMII mode).

ETHSYNC

Output

Ethernet Sync Signal

In SMII mode, this is the Ethernet sync signal input.

GPIO13

Input/ Output General-Purpose Input Output 13

One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For

details, refer to the MSC8122 Reference Manual GPIO programming model.

TDM2RCLK

IRQ11

Input/ Output TDM2 Receive Clock

The receive clock signal for TDM 2. As an input, this can be the DATA_C data signal for TDM 2. For

configuration details, refer to the MSC8122 Reference Manual chapter describing TDM operation.

Input

Interrupt Request 11

One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the

SC140 core.

ETHMDC

Output

Ethernet Management Clock

Used for the MDIO reference clock for MII, RMII, and SMII modes.

MSC8122 Technical Data, Rev. 13

Freescale Semiconductor

1-19

Signals/Connections

Signal Name

Table 1-7. GPIO, TDM, UART, Ethernet, and Timer Signals (Continued)

Type Description

GPIO14

Input/ Output General-Purpose Input Output 14

One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For

details, refer to the MSC8122 Reference Manual GPIO programming model.

TDM2RDAT

IRQ12

Input/ Output TDM2 Serial Receiver Data

Input

The receive data signal for TDM 2. As an input, this can be the DATA_A data signal for TDM 2. For

configuration details, refer to the MSC8122 Reference Manual chapter describing TDM operation.

Input

Interrupt Request 12

One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the

SC140 core.

ETHRXD0

Input

Ethernet Receive Data 0

Bit 0 of the Ethernet receive data (MII and RMII).

NC

Not Connected

For SMII mode, this signal must be left unconnected.

GPIO15

Input/ Output General-Purpose Input Output 15

One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For

details, refer to the MSC8122 Reference Manual GPIO programming model.

TDM1TSYN

Input/ Output TDM1 Transmit frame Sync

Transmit Frame Sync for TDM 1.

DREQ1

Input

DMA Request 1

Used by an external peripheral to request DMA service.

GPIO16

Input/ Output General-Purpose Input Output 16

One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For

details, refer to the MSC8122 Reference Manual GPIO programming model.

TDM1TCLK

DONE1

Input

TDM1 Transmit Clock

Transmit Clock for TDM 1.

Input/ Output DMA Done 1

Signifies that the channel must be terminated. If the DMA controller generates DONE, the channel

handling this peripheral is inactive. As an input to the DMA controller, DONE closes the channel much like

a normal channel closing.

See the MSC8122 Reference Manual chapters on DMA controller and GPIO for information on

configuring the DRACK or DONE mode and pin direction.

DRACK1

Output

DMA Data Request Acknowledge 1

Asserted by the DMA controller to indicate that the DMA controller has sampled the peripheral request.

GPIO17

Input/ Output General-Purpose Input Output 17

One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For

details, refer to the MSC8122 Reference Manual GPIO programming model.

TDM1TDAT

DACK1

Input/ Output TDM1 Serial Transmitter Data

The transmit data signal for TDM 1. As an output, this can be the DATA_D data signal for TDM 1.For

configuration details, refer to the MSC8122 Reference Manual chapter describing TDM operation.

Output

DMA Acknowledge 1

The DMA controller drives this output to acknowledge the DMA transaction on the bus.

MSC8122 Technical Data, Rev. 13

1-20

Freescale Semiconductor

GPIO, TDM, UART, and Timer Signals

Table 1-7. GPIO, TDM, UART, Ethernet, and Timer Signals (Continued)

Signal Name

GPIO18

Type

Description

Input/ Output General-Purpose Input Output 18

One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For

details, refer to the MSC8122 Reference Manual GPIO programming model.

TDM1RSYN

Input/ Output TDM1 Receive Frame Sync

The receive sync signal for TDM 1. As an input, this can be the DATA_B data signal for TDM 1. For

configuration details, refer to the MSC8122 Reference Manual.

DREQ2

Input

DMA Request 1

Used by an external peripheral to request DMA service.

GPIO19

Input/ Output General-Purpose Input Output 19

One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For

details, refer to the MSC8122 Reference Manual GPIO programming model.

TDM1RCLK

Input/ Output TDM1 Receive Clock

The receive clock signal for TDM 1. As an input, this can be the DATA_C data signal for TDM 1. For

configuration details, refer to the MSC8122 Reference Manual chapter describing TDM operation.

DACK2

Output

DMA Acknowledge 2

The DMA controller drives this output to acknowledge the DMA transaction on the bus.

GPIO20

Input/ Output General-Purpose Input Output 20

One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For

details, refer to the MSC8122 Reference Manual GPIO programming model.

TDM1RDAT

Input/ Output TDM1 Serial Receiver Data

The receive data signal for TDM 1. As an input, this can be the DATA_A data signal for TDM 1. For

configuration details, refer to the MSC8122 Reference Manual.

GPIO21

Input/ Output General-Purpose Input Output 21

One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For

details, refer to the MSC8122 Reference Manual GPIO programming model.

TDM0TSYN

Input/ Output TDM0 Transmit frame Sync

Transmit Frame Sync for TDM 0.

GPIO22

Input/ Output General-Purpose Input Output 22

One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs.For

details, refer to the MSC8122 Reference Manual GPIO programming model.

TDM0TCLK

DONE2

Input

TDM 0 Transmit Clock

Transmit Clock for TDM 0.

Input/ Output DMA Done 2

Signifies that the channel must be terminated. If the DMA generates DONE, the channel handling this

peripheral is inactive. As an input to the DMA, DONE closes the channel much like a normal channel

closing.

Note:

See the MSC8122 Reference Manual chapters on DMA and GPIO for information on

configuring the DRACK or DONE mode and pin direction.

DRACK2

Output

DMA Data Request Acknowledge 2

Asserted by the DMA controller to indicate that the DMA controller has sampled the peripheral request.

MSC8122 Technical Data, Rev. 13

Freescale Semiconductor

1-21

Signals/Connections

Signal Name

Table 1-7. GPIO, TDM, UART, Ethernet, and Timer Signals (Continued)

Type Description

GPIO23

Input/ Output General-Purpose Input Output 23

One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For

details, refer to the MSC8122 Reference Manual GPIO programming model.

TDM0TDAT

Input/ Output TDM0 Serial Transmitter Data

The transmit data signal for TDM 0. As an output, this can be the DATA_D data signal for TDM 0. For

configuration details, refer to the MSC8122 Reference Manual chapter describing TDM operation.

IRQ13

Input

Interrupt Request 13

One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the

SC140 core.

GPIO24

Input/ Output General-Purpose Input Output 24

One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For

details, refer to the MSC8122 Reference Manual GPIO programming model.

TDM0RSYN

Input/ Output TDM0 Receive Frame Sync

The receive sync signal for TDM 0. As an input, this can be the DATA_B data signal for TDM 0. For

configuration details, refer to the MSC8122 Reference Manual chapter describing TDM operation.

IRQ14

Input

Interrupt Request 14

One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the

SC140 core.

GPIO25

Input/ Output General-Purpose Input Output 25

One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For

details, refer to the MSC8122 Reference Manual GPIO programming model.

TDM0RCLK

Input/ Output TDM0 Receive Clock

The receive clock signal for TDM 0. As an input, this can be the DATA_C data signal for TDM 0. For

configuration details, refer to the MSC8122 Reference Manual chapter describing TDM operation.

IRQ15

Input

Interrupt Request 15

One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the

SC140 core.

GPIO26

Input/ Output General-Purpose Input Output 26

One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For

details, refer to the MSC8122 Reference Manual GPIO programming model.

TDM0RDAT

Input/ Output TDM0 Serial Receiver Data

The receive data signal for TDM 0. As an input, this can be the DATA_A data signal for TDM 0. For

configuration details, refer to the MSC8122 Reference Manual chapter describing TDM operation.

GPIO27

Input/ Output General-Purpose Input Output 27

One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For

details, refer to the MSC8122 Reference Manual GPIO programming model.

DREQ1

Input

DMA Request 1

Used by an external peripheral to request DMA service.

URXD

UART Receive Data

GPIO28

Input/ Output General-Purpose Input Output 28

One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For

details, refer to the MSC8122 Reference Manual GPIO programming model.

DREQ2

UTXD

Input

DMA Request 2

Used by an external peripheral to request DMA service.

Output

UART Transmit Data

MSC8122 Technical Data, Rev. 13

1-22

Freescale Semiconductor

Dedicated Ethernet Signals

Table 1-7. GPIO, TDM, UART, Ethernet, and Timer Signals (Continued)

Signal Name

GPIO29

Type

Description

Input/ Output General-Purpose Input Output 29

One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For

details, refer to the MSC8122 Reference Manual GPIO programming model.

CHIP_ID3

Input

Chip ID 3

Determines the chip ID of the MSC8122 DSI. It is sampled on the rising edge of PORESET signal.

ETHTX_EN

Output

Ethernet Transmit Enable

Used to enable the Ethernet transmit controller for MII and RMII modes.

GPIO30

Input/ Output General-Purpose Input Output 30

One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs.For

details, refer to the MSC8122 Reference Manual GPIO programming model.

TIMER2

TMCLK

Input/ Output Timer 2

Each signal is configured as either input to the counter or output from the counter. For the configuration of

the pin direction, refer to the MSC8122 Reference Manual.

Input

External TIMER Clock

An external timer can connect directly to the SIU as the SIU clock.

2

SDA

Input/ Output I C-Bus Data Line

2

This is the data line for the I C bus.

GPIO31

Input/ Output General-Purpose Input Output 31

One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For

details, refer to the MSC8122 Reference Manual GPIO programming model.

TIMER3

SCL

Input/ Output Timer 3

Each signal is configured as either input to or output from the counter. For the configuration of the pin

direction, refer to the MSC8122 Reference Manual.

2

Input/ Output I C-Bus Clock Line

2

This the clock line for the I C bus.

1.7 Dedicated Ethernet Signals

Most Ethernet signals are multiplexed with the DSI/system bus and the GPIO ports. In addition to the multiplexed

signals, there are three dedicated Ethernet signals that are described in Table 1-8.

Table 1-8. Dedicated Ethernet Signals

Signal Name

ETHRX_CLK

Type

Signal Description

Input

Receive Clock

In MII mode, provides the timing reference for the receive signals.

ETHSYNC_IN

Input

Sync Input

In SMII mode, is the sync signal input line.

ETHTX_CLK

Transmit Clock

In MII mode, provides the timing reference for transmit signals.

ETHREF_CLK

ETHCLOCK

Input

Reference Clock

In RMII mode, provides the timing reference.

Ethernet Clock

In SMII mode, provides the Ethernet clock signal.

MSC8122 Technical Data, Rev. 13

Freescale Semiconductor

1-23

Signals/Connections

Table 1-8. Dedicated Ethernet Signals

Signal Name

ETHCRS

Type

Signal Description

Input

Carrier Sense

In MII mode, indicates that either the transmit or receive medium is non-idle.

ETHRXD

Input

Ethernet Receive Data

In SMII mode, used for the Ethernet receive data.

1.8 EOnCE Event and JTAG Test Access Port Signals

The MSC8122 uses two sets of debugging signals for the two types of internal debugging modules: EOnCE and the

JTAG TAP controller. Each internal SC140 core has an EOnce module, but they are all accessed externally by the

same two signals EE0 and EE1. The MSC8122 supports the standard set of test access port (TAP) signals defined by

IEEE 1149.1 Standard Test Access Port and Boundary-Scan Architecture specification and described in Table 1-9.

Table 1-9. JTAG TAP Signals

Signal Name

Type

Signal Description

EE0

Input

EOnCE Event Bit 0

Puts the internal SC140 cores into Debug mode.

EE1

Output

EOnCE Event Bit 1

Indicates that at least one on-device SC140 core is in Debug mode.

TCK

TDI

Input

Test Clock—Synchronizes JTAG test logic.

Test Data Input—A test data serial signal for test instructions and data. TDI is sampled on the rising edge

of TCK and has an internal pull-up resistor.

TDO

Output

Test Data Output—A test data serial signal for test instructions and data. TDO can be tri-stated. The

signal is actively driven in the shift-IR and shift-DR controller states and changes on the falling edge of

TCK.

TMS

Input

Test Mode Select—Sequences the test controller state machine, is sampled on the rising edge of TCK,

and has an internal pull-up resistor.

TRST

Test Reset—Asynchronously initializes the test controller; must be asserted during power up.

1.9 Reserved Signals

Table 1-10. Reserved Signals

Signal Name

Type

Signal Description

TEST

Input

Test

For manufacturing testing. You must connect this pin to GND.

MSC8122 Technical Data, Rev. 13

1-24

Freescale Semiconductor

Specifications

2

This document contains detailed information on power considerations, DC/AC electrical characteristics, and AC

timing specifications. For additional information, see the MSC8122 User’s Guide and MSC8122 Reference

Manual.

2.1 Maximum Ratings

CAUTION

This device contains circuitry protecting against damage

due to high static voltage or electrical fields; however,

normal precautions should be taken to avoid exceeding

maximum voltage ratings. Reliability is enhanced if unused

inputs are tied to an appropriate logic voltage level (for

example, either GND or V ).

DD

In calculating timing requirements, adding a maximum value of one specification to a minimum value of another

specification does not yield a reasonable sum. A maximum specification is calculated using a worst case variation

of process parameter values in one direction. The minimum specification is calculated using the worst case for the

same parameters in the opposite direction. Therefore, a “maximum” value for a specification never occurs in the

same device with a “minimum” value for another specification; adding a maximum to a minimum represents a

condition that can never exist.

MSC8122 Technical Data, Rev. 13

Freescale Semiconductor

2-1

Specifications

Table 2-1 describes the maximum electrical ratings for the MSC8122.

Table 2-1. Absolute Maximum Ratings

Rating

Symbol

Value

Unit

Core and PLL supply voltage

I/O supply voltage

V

–0.2 to 1.6

–0.2 to 4.0

V

DD

V

DDH

Input voltage

V

IN

Maximum operating temperature:

• Standard range

• Extended range

T

J

90

105

°C

Minimum operating temperature

• Standard range

• Extended range

T

0

–40

°C

Storage temperature range

T

–55 to +150

°C

STG

Notes: 1. Functional operating conditions are given in Table 2-2.

2. Absolute maximum ratings are stress ratings only, and functional operation at the maximum is not guaranteed. Stress beyond

the listed limits may affect device reliability or cause permanent damage.

3. Section 4.5, Thermal Considerations includes a formula for computing the chip junction temperature (T ).

J

2.2 Recommended Operating Conditions

Table 2-2 lists recommended operating conditions. Proper device operation outside of these conditions is not

guaranteed.

Table 2-2. Recommended Operating Conditions

Rating

Symbol

Value

Unit

Core and PLL supply voltage:

• Standard

V

DD

V

CCSYN

— 400 MHz

— 500 MHz

• Reduced (300 and 400 MHz)

1.14 to 1.26

1.16 to 1.24

1.07 to 1.13

V

I/O supply voltage

Input voltage

V

3.135 to 3.465

V

DDH

V

–0.2 to V

+0.2

DDH

IN

Operating temperature range:

• Standard

• Extended

T

0 to 90

–40 to 105

°C

J

MSC8122 Technical Data, Rev. 13

2-2

Freescale Semiconductor

Thermal Characteristics

2.3 Thermal Characteristics

Table 2-3 describes thermal characteristics of the MSC8122 for the FC-PBGA packages.

Table 2-3. Thermal Characteristics for the MSC8122

FC-PBGA

20 × 20 mm⁵

Characteristic

Symbol

Unit

Natural

200 ft/min

Convection

(1 m/s) airflow

1, 2

Junction-to-ambient

R

26

19

9

21

15

°C/W

θJA

θJB

θJC

1, 3

Junction-to-ambient, four-layer board

4

Junction-to-board (bottom)

5

Junction-to-case

0.9

1

6

Junction-to-package-top

Ψ

JT

Notes: 1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)

temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal

resistance.

2. Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal.

3. Per JEDEC JESD51-6 with the board horizontal.

4. Thermal resistance between the die and the printed circuit board per JEDEC JESD 51-8. Board temperature is measured on

the top surface of the board near the package.

5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method

1012.1).

6. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature

per JEDEC JESD51-2.

Section 4.5, Thermal Considerations provides a detailed explanation of these characteristics.

2.4 DC Electrical Characteristics

This section describes the DC electrical characteristics for the MSC8122. The measurements in Table 2-4 assume

the following system conditions:

•

T = 25 °C

A

V_DD

=

— 300/400 MHz 1.1 V nominal = 1.07–1.13 V

DC

— 400 MHz 1.2 V nominal = 1.14–1.26 V

— 500 MHz 1.2 V nominal = 1.16–1.24 V

DC

•

V_DDH= 3.3 V ± 5% V

DC

GND = 0 V

DC

Note: The leakage current is measured for nominal V_DDHand V_DD

.

MSC8122 Technical Data, Rev. 13

Freescale Semiconductor

2-3

Specifications

Table 2-4. DC Electrical Characteristics

Characteristic

Symbol

Min

Typical

Max

Unit

1

Input high voltage , all inputs except CLKIN

V

2.0

GND

2.4

—

0

3.465

0.4

3.465

0.4

1

V

IH

1

Input low voltage

V

IL

CLKIN input high voltage

CLKIN input low voltage

V

3.0

0

V

IHC

V

I

GND

–1.0

2.0

V

ILC

Input leakage current, V = V

0.09

3.0

µA

V

IN

DDH

IN

Tri-state (high impedance off state) leakage current, V = V

I

1

IN

DDH

OZ

2

Signal low input current, V = 0.4 V

I

1

IL

L

2

Signal high input current, V = 2.0 V

I

1

IH

H

Output high voltage, I = –2 mA,

V

—

OH

except open drain pins

Output low voltage, I = 3.2 mA

V

—

0

0.4

V

OL

Internal supply current:

3

•

Wait mode

Stop mode

I

—

375

290

—

mA

DDW

3

DDS

4

Typical power 400 MHz at 1.2 V

P

—

1.15

—

W

Notes: 1. See Figure 2-1 for undershoot and overshoot voltages.

2. Not tested. Guaranteed by design.

3. Measured for 1.2 V core at 25°C junction temperature.

4. The typical power values were measured using an EFR code with the device running at a junction temperature of 25°C. No

peripherals were enabled and the ICache was not enabled. The source code was optimized to use all the ALUs and AGUs and

®

all four cores. It was created using CodeWarrior 2.5. These values are provided as examples only. Power consumption is

application dependent and varies widely. To assure proper board design with regard to thermal dissipation and maintaining

proper operating temperatures, evaluate power consumption for your application and use the design guidelines in Chapter 4 of

this document and in MSC8102, MSC8122, and MSC8126 Thermal Management Design Guidelines (AN2601).

V_DDH+ 17%

V_IH

V

_DDH+ 8%

V_DDH

GND

GND – 0.3 V

GND – 0.7 V

V_IL

Must not exceed 10% of clock period

Figure 2-1. Overshoot/Undershoot Voltage for V_IHand V_IL

2.5 AC Timings

The following sections include illustrations and tables of clock diagrams, signals, and parallel I/O outputs and

inputs. When systems such as DSP farms are developed using the DSI, use a device loading of 4 pF per pin. AC

timings are based on a 20 pF load, except where noted otherwise, and a 50 Ω transmission line. For loads smaller

than 20 pF, subtract 0.06 ns per pF down to 10 pF load. For loads larger than 20 pF, add 0.06 ns for

SIU/Ethernet/DSI delay and 0.07 ns for GPIO/TDM/timer delay. When calculating overall loading, also consider

additional RC delay.

MSC8122 Technical Data, Rev. 13

2-4

Freescale Semiconductor

AC Timings

2.5.1 Output Buffer Impedances

Table 2-5. Output Buffer Impedances

Output Buffers

Typical Impedance (Ω)

System bus

50

Memory controller

Parallel I/O

Note:

These are typical values at 65°C. The impedance may vary by ±25% depending on device process and operating temperature.

2.5.2 Start-Up Timing

Starting the device requires coordination among several input sequences including clocking, reset, and power.

Section 2.5.3 describes the clocking characteristics. Section 2.5.4 describes the reset and power-up characteristics.

You must use the following guidelines when starting up an MSC8122 device:

•

PORESET and TRST must be asserted externally for the duration of the power-up sequence. See Table 2-10

for timing.

If possible, bring up the V_DDand V_DDHlevels together. For designs with separate power supplies, bring up

the V_DDlevels and then the V_DDHlevels (see Figure 2-3).

CLKIN should start toggling at least 16 cycles (starting after V_DDHreaches its nominal level) before

PORESET deassertion to guarantee correct device operation (see Figure 2-2 and Figure 2-3).

CLKIN must not be pulled high during V_DDHpower-up. CLKIN can toggle during this period.

The following figures show acceptable start-up sequence examples. Figure 2-2 shows a sequence in which V_DDand

V_DDHare raised together. Figure 2-3 shows a sequence in which V_DDHis raised after V_DDand CLKIN begins to toggle

as V_DDHrises.

V

= Nominal Value

DDH

= Nominal Value

DD

1

V

Nominal Level

3.3 V

2.2 V

DDH

1.2 V

o.5 V

V

Nominal Level

DD

Time

PORESET/TRST Deasserted

CLKIN Starts Toggling

PORESET/TRST Asserted

V

/V

Applied

DD DDH

Figure 2-2. Start-Up Sequence with V_DDand V_DDHRaised Together

MSC8122 Technical Data, Rev. 13

Freescale Semiconductor

2-5

Specifications

V

= Nominal

DDH

DD

1

V

Nominal

3.3 V

DDH

1.2 V

o.5 V

V

Nominal

DD

Time

PORESET/TRST asserted

applied

PORESET/TRST deasserted

CLKIN starts toggling

applied

V

DD

V

DDH

Figure 2-3. Start-Up Sequence with V_DDRaised Before V_DDHwith CLKIN Started with V_DDH

2.5.3 Clock and Timing Signals

The following sections include a description of clock signal characteristics. Table 2-6 shows the maximum

frequency values for internal (Core, Reference, Bus, and DSI) and external (CLKIN and CLKOUT) clocks. The user

must ensure that maximum frequency values are not exceeded.

Table 2-6. Maximum Frequencies

Characteristic

Maximum in MHz

Core frequency

300/400/500

100/133/166

Reference frequency (REFCLK)

Internal bus frequency (BLCK)

DSI clock frequency (HCLKIN)

•

Core frequency = 300 MHz

Core frequency = 400/500 MHz

HCLKIN ≤ (min{70 MHz, CLKOUT})

HCLKIN ≤ (min{100 MHz, CLKOUT})

External clock frequency (CLKIN or CLKOUT)

100/133/166

Table 2-7. Clock Frequencies

300 MHz Device

400 MHz Device

500 MHz Device

Characteristics

Symbol

Min

Max

Min

Max

Min

Max

CLKIN frequency

F

20

40

100

300

20

40

133.3

400

20

40

166.7

500

CLKIN

BCLK frequency

F

BCLK

Reference clock (REFCLK) frequency

Output clock (CLKOUT) frequency

SC140 core clock frequency

F

40

REFCLK

CLKOUT

F

40

F

200

CORE

Note:

The rise and fall time of external clocks should be 3 ns maximum

Table 2-8. System Clock Parameters

Characteristic

Min

Max

Unit

Phase jitter between BCLK and CLKIN

CLKIN frequency

—

20

—

20

0.3

ns

MHz

ns

see Table 2-7

CLKIN slope

3

PLL input clock (after predivider)

100

MHz

MSC8122 Technical Data, Rev. 13

2-6

Freescale Semiconductor

AC Timings

Unit

Table 2-8. System Clock Parameters

Characteristic

Min

Max

PLL output frequency (VCO output)

800

MHz

•

300 MHz core

400 MHz core

500 MHz core

1200

1600

2000

1

CLKOUT frequency jitter

—

200

500

ps

1

CLKOUT phase jitter with CLKIN phase jitter of ±100 ps.

Notes: 1. Peak-to-peak.

2. Not tested. Guaranteed by design.

2.5.4 Reset Timing

The MSC8122 has several inputs to the reset logic:

•

Power-on reset (PORESET)

External hard reset (HRESET)

External soft reset (SRESET)

Software watchdog reset

Bus monitor reset

Host reset command through JTAG

All MSC8122 reset sources are fed into the reset controller, which takes different actions depending on the source

of the reset. The reset status register indicates the most recent sources to cause a reset. Table 2-9 describes the reset

sources.

Table 2-9. Reset Sources

Name

Direction

Description

Power-on reset

(PORESET)

Input

Initiates the power-on reset flow that resets the MSC8122 and configures various attributes of the

MSC8122. On PORESET, the entire MSC8122 device is reset. SPLL states is reset, HRESET and

SRESET are driven, the SC140 extended cores are reset, and system configuration is sampled. The

clock mode (MODCK bits), reset configuration mode, boot mode, Chip ID, and use of either a DSI 64

bits port or a System Bus 64 bits port are configured only when PORESET is asserted.

External hard

reset (HRESET)

Input/ Output

Initiates the hard reset flow that configures various attributes of the MSC8122. While HRESET is

asserted, SRESET is also asserted. HRESET is an open-drain pin. Upon hard reset, HRESET and

SRESET are driven, the SC140 extended cores are reset, and system configuration is sampled. The

most configurable features are reconfigured. These features are defined in the 32-bit hard reset

configuration word described in Hard Reset Configuration Word section of the Reset chapter in the

MSC8122 Reference Manual.

External soft reset

(SRESET)

Input/ Output

Initiates the soft reset flow. The MSC8122 detects an external assertion of SRESET only if it occurs

while the MSC8122 is not asserting reset. SRESET is an open-drain pin. Upon soft reset, SRESET is

driven, the SC140 extended cores are reset, and system configuration is maintained.

Software

watchdog reset

Internal

When the MSC8122 watchdog count reaches zero, a software watchdog reset is signalled. The

enabled software watchdog event then generates an internal hard reset sequence.

Bus monitor reset

When the MSC8122 bus monitor count reaches zero, a bus monitor hard reset is asserted. The

enabled bus monitor event then generates an internal hard reset sequence.

Host reset

command through

the TAP

When a host reset command is written through the Test Access Port (TAP), the TAP logic asserts the

soft reset signal and an internal soft reset sequence is generated.

Table 2-10 summarizes the reset actions that occur as a result of the different reset sources.

MSC8122 Technical Data, Rev. 13

Freescale Semiconductor

2-7

Specifications

Table 2-10. Reset Actions for Each Reset Source

Power-On

Reset

(PORESET)

Hard Reset (HRESET)

Soft Reset (SRESET)

JTAG Command:

Reset Action/Reset Source

External or Internal

External only (SoftwareWatchdogor

Bus Monitor)

External

EXTEST, CLAMP, or

HIGHZ

Configuration pins sampled (Refer to

Yes

No

Section 2.5.4.1 for details).

SPLL state reset

Yes

No

System reset configuration write through

the DSI

System reset configuration write though

the system bus

Yes

No

HRESET driven

Yes

No

SIU registers reset

IPBus modules reset (TDM, UART,

Timers, DSI, IPBus master, GIC, HS, and

GPIO)

Yes

SRESET driven

Yes

Depends on command

SC140 extended cores reset

MQBS reset

Yes

2.5.4.1 Power-On Reset (PORESET) Pin

Asserting PORESET initiates the power-on reset flow. PORESET must be asserted externally for at least 16 CLKIN

cycles after V_DDand V_DDHare both at their nominal levels.

2.5.4.2 Reset Configuration

The MSC8122 has two mechanisms for writing the reset configuration:

•

Through the direct slave interface (DSI)

Through the system bus. When the reset configuration is written through the system bus, the MSC8122

acts as a configuration master or a configuration slave. If configuration slave is selected, but no special

configuration word is written, a default configuration word is applied.

Fourteen signal levels (see Chapter 1 for signal description details) are sampled on PORESET deassertion to define

the Reset Configuration Mode and boot and operating conditions:

•

RSTCONF

CNFGS

DSISYNC

DSI64

CHIP_ID[0–3]

BM[0–2]

SWTE

MODCK[1–2]

MSC8122 Technical Data, Rev. 13

2-8

Freescale Semiconductor

AC Timings

2.5.4.3 Reset Timing Tables

Table 2-11 and Figure 2-4 describe the reset timing for a reset configuration write through the direct slave

interface (DSI) or through the system bus.

Table 2-11. Timing for a Reset Configuration Write through the DSI or System Bus

No.

Characteristics

Expression

Min

Max

Unit

1

Required external PORESET duration minimum

16/CLKIN

•

CLKIN = 20 MHz

800

160

120

96

—

ns

CLKIN = 100 MHz (300 MHz core)

CLKIN = 133 MHz (400 MHz core)

CLKIN = 166 MHz (500 MHz core)

2

3

Delay from deassertion of external PORESET to deassertion of internal

PORESET

1024/CLKIN

•

CLKIN = 20 MHz to 166 MHz

6.17

51.2

µs

Delay from de-assertion of internal PORESET to SPLL lock

6400/(CLKIN/RDF)

(PLL reference clock-

division factor)

•

CLKIN = 20 MHz (RDF = 1)

320

64

96

320

64

96

µs

CLKIN = 100 MHz (RDF = 1) (300 MHz core)

CLKIN = 133 MHz (RDF = 2) (400 MHz core)

CLKIN = 166 MHz (RDF = 2) (500 MHz core)

77

5

6

7

Delay from SPLL to HRESET deassertion

REFCLK = 40 MHz to 166 MHz

•

512/REFCLK

515/REFCLK

3.08

12.8

µs

Delay from SPLL lock to SRESET deassertion

REFCLK = 40 MHz to 166 MHz

•

3.10

3

12.88

—

µs

ns

Setup time from assertion of RSTCONF, CNFGS, DSISYNC, DSI64,

CHIP_ID[0–3], BM[0–2], SWTE, and MODCK[1–2] before deassertion of

PORESET

8

Hold time from deassertion of PORESET to deassertion of RSTCONF,

CNFGS, DSISYNC, DSI64, CHIP_ID[0–3], BM[0–2], SWTE, and

MODCK[1–2]

5

—

ns

Note:

Timings are not tested, but are guaranteed by design.

RSTCONF, CNFGS, DSISYNC, DSI64

CHIP_ID[0–3], BM[0–2], SWTE, MODCK[1–2]

pins are sampled

1

PORESET

Input

Host programs

Reset Configuration

Word

PORESET

Internal

SPLL is locked

(no external indication)

1 + 2

MODCK[3–5]

HRESET

Output (I/O)

3

2

SRESET

Output (I/O)

SPLL

locking period

Reset configuration write

sequence during this

period.

5

6

Figure 2-4. Timing Diagram for a Reset Configuration Write

MSC8122 Technical Data, Rev. 13

Freescale Semiconductor

2-9

Specifications

2.5.5 System Bus Access Timing

2.5.5.1 Core Data Transfers

Generally, all MSC8122 bus and system output signals are driven from the rising edge of the reference clock

(REFCLK). The REFCLK is the CLKIN signal. Memory controller signals, however, trigger on four points within a

REFCLK cycle. Each cycle is divided by four internal ticks: T1, T2, T3, and T4. T1 always occurs at the rising

edge of REFCLK (and T3 at the falling edge), but the spacing of T2 and T4 depends on the PLL clock ratio

selected, as Table 2-12 shows.

Table 2-12. Tick Spacing for Memory Controller Signals

Tick Spacing (T1 Occurs at the Rising Edge of REFCLK)

BCLK/SC140 clock

T2

T3

T4

1:4, 1:6, 1:8, 1:10

1/4 REFCLK

1/6 REFCLK

2/10 REFCLK

1/2 REFCLK

3/4 REFCLK

4/6 REFCLK

7/10 REFCLK

1:3

1:5

Figure 2-5 is a graphical representation of Table 2-12.

REFCLK

for 1:4, 1:6, 1:8, 1:10

T1

T2

T3

T4

REFCLK

for 1:3

T2

T4

for 1:5

T2

T4

Figure 2-5. Internal Tick Spacing for Memory Controller Signals

MSC8122 Technical Data, Rev. 13

2-10

Freescale Semiconductor

AC Timings

The UPM machine and GPCM machine outputs change on the internal tick selected by the memory controller

configuration. The AC timing specifications are relative to the internal tick. SDRAM machine outputs change only

on the REFCLK rising edge.

Table 2-13. AC Timing for SIU Inputs

Value for Bus Speed in MHz

Ref = CLKIN

1.2 V

Ref = CLKOUT

1.2 V

No.

Characteristic

Units

1.1 V

1.2 V

166

100/

133

10

Hold time for all signals after the 50% level of the REFCLK rising edge

0.5

3.1

0.5

3.0

0.5

3.0

0.5

3.0

ns

11a

ARTRY/ABB set-up time before the 50% level of the REFCLK rising

edge

11b

DBG/DBB/BG/BR/TC set-up time before the 50% level of the REFCLK

rising edge

3.6

3.0

3.3

2.9

3.3

2.9

3.3

2.9

ns

11c

11d

AACK set-up time before the 50% level of the REFCLK rising edge

TA/TEA/PSDVAL set-up time before the 50% level of the REFCLK

rising edge

•

Data-pipeline mode

Non-pipeline mode

3.5

4.4

3.4

4.0

3.4

4.0

3.4

4.0

ns

12

Data bus set-up time before REFCLK rising edge in Normal mode

•

Data-pipeline mode

Non-pipeline mode

1.9

4.2

1.8

4.0

1.7

4.0

1.8

4.0

ns

1

13

Data bus set-up time before the 50% level of the REFCLK rising edge

in ECC and PARITY modes

•

Data-pipeline mode

Non-pipeline mode

2.0

8.2

2.0

7.3

2.0

7.3

2.0

7.3

ns

1

14

DP set-up time before the 50% level of the REFCLK rising edge

•

Data-pipeline mode

Non-pipeline mode

2.0

7.9

2.0

6.1

2.0

6.1

2.0

6.1

ns

15a

15b

16

TS and Address bus set-up time before the 50% level of the REFCLK

rising edge

•

Extra cycle mode (SIUBCR[EXDD] = 0)

No extra cycle mode (SIUBCR[EXDD] = 1)

4.2

5.5

3.8

5.0

3.8

5.0

3.8

5.0

ns

Address attributes: TT/TBST/TSZ/GBL set-up time before the 50%

level of the REFCLK rising edge

•

Extra cycle mode (SIUBCR[EXDD] = 0)

No extra cycle mode (SIUBCR[EXDD] = 1)

3.7

4.8

3.5

4.4

3.5

4.4

3.5

4.4

ns

PUPMWAIT signal set-up time before the 50% level of the REFCLK

rising edge

3.7

ns

3

17

18

IRQx setup time before the 50% level; of the REFCLK rising edge

4.0

ns

3

IRQx minimum pulse width

6.0 +

6.0 + T

REFCLK

T

REFCLK

REFCLK REFCLK

Notes: 1. Timings specifications 13 and 14 in non-pipeline mode are more restrictive than MSC8102 timings.

2. Values are measured from the 50% TTL transition level relative to the 50% level of the REFCLK rising edge.

3. Guaranteed by design.

MSC8122 Technical Data, Rev. 13

Freescale Semiconductor

2-11

Specifications

Table 2-14. AC Timing for SIU Outputs

Value for Bus Speed in MHz³

Ref = CLKIN

1.2 V

Ref = CLKOUT

1.2 V

No.

Characteristic

Units

1.1 V

1.2 V

166

100/

133

100/133

2

30

31

Minimum delay from the 50% level of the REFCLK for all signals

0.9

6.0

0.8

4.9

0.8

4.9

1.0

5.8

ns

PSDVAL/TEA/TA max delay from the 50% level of the REFCLK

rising edge

32a

Address bus max delay from the 50% level of the REFCLK rising

edge

•

Multi-master mode (SIUBCR[EBM] = 1)

Single-master mode (SIUBCR[EBM] = 0)

6.4

5.3

5.5

4.2

5.5

3.9

6.4

5.1

ns

32b

32c

Address attributes: TT[0–1]/TBST/TSZ/GBL max delay from the 50%

level of the REFCLK rising edge

6.4

6.9

5.2

5.1

5.7

4.2

5.1

5.7

4.2

6.0

6.6

5.1

ns

Address attributes: TT[2–4]/TC max delay from the 50% level of the

REFCLK rising edge

32d

33a

BADDR max delay from the 50% level of the REFCLK rising edge

Data bus max delay from the 50% level of the REFCLK rising edge

•

Data-pipeline mode

Non-pipeline mode

4.8

7.1

3.9

6.1

3.7

6.1

4.8

7.0

ns

33b

DP max delay from the 50% level of the REFCLK rising edge

•

Data-pipeline mode

Non-pipeline mode

6.0

7.5

5.3

6.5

5.3

6.5

6.2

7.4

ns

34

Memory controller signals/ALE/CS[0–4] max delay from the 50%

level of the REFCLK rising edge

5.1

6.0

5.5

4.2

4.7

4.5

3.9

4.7

4.5

5.1

5.6

5.4

ns

35a

35b

DBG/BG/BR/DBB max delay from the 50% level of the REFCLK

rising edge

AACK/ABB/TS/CS[5–7] max delay from the 50% level of the

REFCLK rising edge

Notes: 1. Values are measured from the 50% level of the REFCLK rising edge to the 50% signal level and assume a 20 pF load except

where otherwise specified.

2. The load for specification 30 is 10 pF. The load for the other specifications in this table is 20 pF. For a 15 pF load, subtract 0.3

ns from the listed value.

3. The maximum bus frequency depends on the mode:

• In 60x-compatible mode connected to another MSC8122 device, the frequency is determined by adding the input and output

longest timing values, which results in the total delay for 20 pF output capacitance. You must also account for other

influences that can affect timing, such as on-board clock skews, on-board noise delays, and so on.

• In single-master mode, the frequency depends on the timing of the devices connected to the MSC8122.

• To achieve maximum performance on the bus in single-master mode, disable the DBB signal by writing a 1 to the

SIUMCR[BDD] bit. See the SIU chapter in the MSC8122 Reference Manual for details.

MSC8122 Technical Data, Rev. 13

2-12

Freescale Semiconductor

AC Timings

REFCLK

10

11

AACK/ARTRY/TA/TEA/DBG/BG/BR

PSDVAL/ABB/DBB inputs

10

12

13

Data bus inputs—normal mode

10

Data bus inputs—ECC and parity modes

DP inputs

14

15

10

18

Address bus/TS /TT[0–4]/TC[0–2]/

TBST/TSZ[0–3]/GBL inputs

PUPMWAIT input

16

17

IRQx inputs

30

Min delay for all output pins

31

PSDVAL/TEA/TA outputs

32a/b

Address bus/TT[0–4]/TC[0–2]/TBST/TSZ[0–3]/GBL outputs

32c

33a

BADDR outputs

Data bus outputs

DP outputs

33b

34

Memory controller/ALE outputs

35

AACK/ABB/TS/DBG/BG/BR/DBB/CS outputs

MSC8122 Technical Data, Rev. 13

Freescale Semiconductor

2-13

Specifications

2.5.5.2 CLKIN to CLKOUT Skew

Table 2-16 describes the CLKOUT-to-CLKIN skew timing.

Table 2-15. CLKOUT Skew

Characteristic

No.

Min¹

Max¹

Units

20

Rise-to-rise skew

•

V

= 1.1 V

= 1.2 V

0.0

0.95

0.85

ns

DD

21

22

23

24

Fall-to-fall skew

•

V

= 1.1 V

= 1.2 V

–1.5

–0.8

1.0

ns

DD

CLKOUT phase (1.2 V, 133 MHz)

•

Phase high

Phase low

2.8

—

ns

CLKOUT phase (1.1 V, 133 MHz)

•

Phase high

Phase low

2.2

—

ns

CLKOUT phase (1.1 V, 100 MHz)

•

Phase high

Phase low

3.3

—

ns

Notes: 1. A positive number indicates that CLKOUT precedes CLKIN, A negative number indicates that CLKOUT follows CLKIN.

2. Skews are measured in clock mode 29, with a CLKIN:CLKOUT ratio of 1:1. The same skew is valid for all clock modes.

3. CLKOUT skews are measured using a load of 10 pF.

4. CLKOUT skews and phase are not measured for 500/166 Mhz parts because these parts only use CLKIN mode.

For designs that use the CLKOUT synchronization mode, use the skew values listed in Table 2-15 to adjust the rise-

to-fall timing values specified for CLKIN synchronization. Figure 2-6 shows the relationship between the CLKOUT

and CLKIN timings.

CLKIN

CLKOUT

21

20

Figure 2-6. CLKOUT and CLKIN Signals.

MSC8122 Technical Data, Rev. 13

2-14

Freescale Semiconductor

AC Timings

2.5.5.3 DMA Data Transfers

Table 2-16 describes the DMA signal timing.

Table 2-16. DMA Signals

Ref = CLKOUT

(1.2 V only)

Ref = CLKIN

No.

Characteristic

Units

Min

Max

Min

Max

37

38

39

40

41

DREQ set-up time before the 50% level of the falling edge of REFCLK

DREQ hold time after the 50% level of the falling edge of REFCLK

DONE set-up time before the 50% level of the rising edge of REFCLK

DONE hold time after the 50% level of the rising edge of REFCLK

DACK/DRACK/DONE delay after the 50% level of the REFCLK rising edge

5.0

0.5

5.0

0.5

—

5.0

0.5

5.0

0.5

—

ns

—

7.5

8.4

The DREQ signal is synchronized with REFCLK. To achieve fast response, a synchronized peripheral should assert

DREQ according to the timings in Table 2-16. Figure 2-7 shows synchronous peripheral interaction.

REFCLK

38

37

DREQ

40

39

DONE

41

DACK/DONE/DRACK

Figure 2-7. DMA Signals

MSC8122 Technical Data, Rev. 13

Freescale Semiconductor

2-15

Specifications

2.5.6 DSI Timing

The timings in the following sections are based on a 20 pF capacitive load.

2.5.6.1 DSI Asynchronous Mode

Table 2-17. DSI Asynchronous Mode Timing

No.

Characteristics

Min

Max

Unit

1

100

101

102

Attributes set-up time before strobe (HWBS[n]) assertion

1.5

1.3

—

ns

1

Attributes hold time after data strobe deassertion

Read/Write data strobe deassertion width:

•

DCR[HTAAD] = 1

— Consecutive access to the same DSI

— Different device with DCR[HTADT] = 01

— Different device with DCR[HTADT] = 10

— Different device with DCR[HTADT] = 11

DCR[HTAAD] = 0

1.8 + T

5 + T

5 + (1.5 × T

5 + (2.5 × T

1.8 + T

ns

REFCLK

)

REFCLK

•

REFCLK

103

104

105

106

107

108

Read data strobe deassertion to output data high impedance

Read data strobe assertion to output data active from high impedance

Output data hold time after read data strobe deassertion

Read/Write data strobe assertion to HTA active from high impedance

Output data valid to HTA assertion

—

8.5

—

ns

2.0

2.2

3.2

2

Read/Write data strobe assertion to HTA valid

•

1.1 V core

1.2 V core

—

7.4

6.7

ns

109

110

111

Read/Write data strobe deassertion to output HTA high impedance.

(DCR[HTAAD] = 0, HTA at end of access released at logic 0)

—

6.5

ns

Read/Write data strobe deassertion to output HTA deassertion.

(DCR[HTAAD] = 1, HTA at end of access released at logic 1)

6.5

ns

Read/Write data strobe deassertion to output HTA high impedance.

(DCR[HTAAD] = 1, HTA at end of access released at logic 1

•

DCR[HTADT] = 01

DCR[HTADT] = 10

DCR[HTADT] = 11

5 + T

5 + (1.5 × T

5 + (2.5 × T

ns

REFCLK

)

REFCLK

112

201

202

Read/Write data strobe assertion width

1.8 + T

—

ns

REFCLK

Host data input set-up time before write data strobe deassertion

1.0

Host data input hold time after write data strobe deassertion

•

1.1 V core

1.2 V core

1.7

1.5

—

ns

Notes: 1. Attributes refers to the following signals: HCS, HA[11–29], HCID[0–4], HDST, HRW, HRDS, and HWBSn.

2. This specification is tested in dual-strobe mode. Timing in single-strobe mode is guaranteed by design.

3. All values listed in this table are tested or guaranteed by design.

MSC8122 Technical Data, Rev. 13

2-16

Freescale Semiconductor

AC Timings

Figure 2-8 shows DSI asynchronous read signals timing.

HCS

HA[11–29]

HCID[0–4]

HDST

1

HRW

HWBSn

2

100

101

112

1

HDBSn

2

HRDS

102

103

107

105

104

HD[0–63]

109

106

3

HTA

108

110

4

HTA

111

Notes: 1. Used for single-strobe mode access.

2. Used for dual-strobe mode access.

3. HTA released at logic 0 (DCR[HTAAD] = 0) at end of access; used with pull-

down implementation.

4. HTA released at logic 1 (DCR[HTAAD] = 1) at end of access; used with pull-up

implementation.

Figure 2-8. Asynchronous Single- and Dual-Strobe Modes Read Timing Diagram

MSC8122 Technical Data, Rev. 13

Freescale Semiconductor

2-17

Specifications

Figure 2-9 shows DSI asynchronous write signals timing.

HCS

HA[11–29]

HCID[0–4]

HDST

1

101

102

HRW

100

2

HRDS

112

1

2

HDBSn

HWBSn

201

202

HD[0–63]

109

106

108

3

HTA

110

4

HTA

111

Notes: 1. Used for single-strobe mode access.

2. Used for dual-strobe mode access.

3. HTA released at logic 0 (DCR[HTAAD] = 0) at end of access; used with pull-down implementation.

4. HTA released at logic 1 (DCR[HTAAD] = 1) at end of access; used with pull-up implementation.

Figure 2-9. Asynchronous Single- and Dual-Strobe Modes Write Timing Diagram

Figure 2-10 shows DSI asynchronous broadcast write signals timing.

HCS

HA[11–29]

HCID[0–4]

HDST

1

101

102

HRW

100

2

HRDS

112

1

2

HDBSn

HWBSn

201

202

HD[0–63]

Notes: 1. Used for single-strobe mode access.

2. Used for dual-strobe mode access.

Figure 2-10. Asynchronous Broadcast Write Timing Diagram

MSC8122 Technical Data, Rev. 13

2-18

Freescale Semiconductor

AC Timings

2.5.6.2 DSI Synchronous Mode

Table 2-18. DSI Inputs in Synchronous Mode

1.1 V Core

1.2 V Core

No.

Characteristic

Expression

Units

Min

Max

Min

Max

1,2

120

121

122

123

124

125

126

127

HCLKIN cycle time

HTC

10.0

4.0

1.2

0.6

1.3

1.2

1.5

55.6

33.3

—

10.0

4.0

1.2

0.4

1.3

1.2

1.5

55.6

ns

HCLKIN high pulse width

HCLKIN low pulse width

HA[11–29] inputs set-up time

HD[0–63] inputs set-up time

HCID[0–4] inputs set-up time

All other inputs set-up time

All inputs hold time

(0.5 0.1) × HTC

33.3

—

Notes: 1. Values are based on a frequency range of 18–100 MHz.

2. Refer to Table 2-6 for HCLKIN frequency limits.

Table 2-19. DSI Outputs in Synchronous Mode

1.1 V Core

1.2 V Core

No.

Characteristic

Units

Min

Max

Min

Max

128

129

130

131

132

133

134

135

HCLKIN high to HD[0–63] output active

2.0

—

7.6

—

2.0

—

6.3

—

ns

HCLKIN high to HD[0–63] output valid

HD[0–63] output hold time

1.7

—

1.7

—

HCLKIN high to HD[0–63] output high impedance

HCLKIN high to HTA output active

HCLKIN high to HTA output valid

HTA output hold time

8.3

—

7.6

—

2.2

—

2.0

—

7.4

—

5.9

—

1.7

—

1.7

—

HCLKIN high to HTA high impedance

7.5

6.3

120

122

121

127

HCLKIN

123

HA[11–29] input signals

127

124

HD[0–63] input signals

125

HCID[0–4] input signals

127

126

All other input signals

131

130

129

128

HD[0–63] output signals

135

134

133

132

HTA output signal

Figure 2-11. DSI Synchronous Mode Signals Timing Diagram

MSC8122 Technical Data, Rev. 13

Freescale Semiconductor

2-19

Specifications

2.5.7 TDM Timing

Table 2-20. TDM Timing

1.1 V Core

1.2 V Core

No.

Characteristic

Expression

Units

Min

Max

Min

Max

1

300

301

302

303

304

305

TDMxRCLK/TDMxTCLK

TC

16

7

—

16

7

—

ns

TDMxRCLK/TDMxTCLK high pulse width

TDMxRCLK/TDMxTCLK low pulse width

TDM receive all input set-up time

TDM receive all input hold time

(0.5 0.1) × TC

7

1.3

1.0

2.8

1.3

1.0

2.8

TDMxTCLK high to TDMxTDAT/TDMxRCLK output

2,3

active

306

307

308

TDMxTCLK high to TDMxTDAT/TDMxRCLK output

—

2.5

—

10.0

—

2.5

—

8.8

—

ns

4

All output hold time

TDMxTCLK high to TDmXTDAT/TDMxRCLK output high

10.7

10.5

2,3

impedance

2

309

310

TDMxTCLK high to TDMXTSYN output valid

—

9.7

—

8.5

—

ns

4

TDMxTSYN output hold time

2.5

Notes: 1. Values are based on a a maximum frequency of 62.5 MHz. The TDM interface supports any frequency below 62.5 MHz.

Devices operating at 300 MHz are limited to a maximum TDMxRCLK/TDMxTCLK frequency of 50 MHz.

2. Values are based on 20 pF capacitive load.

3. When configured as an output, TDMxRCLK acts as a second data link. See the MSC8122 Reference Manual for details.

4. Values are based on 10 pF capacitive load.

300

302

301

304

TDMxRCLK

TDMxRDAT

303

304

303

TDMxRSYN

Figure 2-12. TDM Inputs Signals

300

302

301

TDMxTCLK

308

307

306

305

TDMxTDAT

TDMxRCLK

309

310

TDMxTSYN

Figure 2-13. TDM Output Signals

MSC8122 Technical Data, Rev. 13

2-20

Freescale Semiconductor

AC Timings

2.5.8 UART Timing

Table 2-21. UART Timing

Un

No.

Characteristics

Expression

Min

Max

it

400

401

402

URXD and UTXD inputs high/low duration

URXD and UTXD inputs rise/fall time

UTXD output rise/fall time

16 × T

160.0

—

10

ns

REFCLK

401

UTXD, URXD

inputs

400

Figure 2-14. UART Input Timing

402

UTXD output

Figure 2-15. UART Output Timing

MSC8122 Technical Data, Rev. 13

Freescale Semiconductor

2-21

Specifications

2.5.9 Timer Timing

Table 2-22. Timer Timing

Ref = CLKIN

No.

Characteristics

Unit

Min

Max

500

501

502

503

TIMERx frequency

10.0

4.0

—

ns

TIMERx Input high period

TIMERx Output low period

4.0

TIMERx Propagations delay from its clock input

•

1.1 V core

1.2 V core

3.1

2.8

9.5

8.1

ns

500

501

502

TIMERx (Input)

503

TIMERx (Output)

Figure 2-16. Timer Timing

2.5.10 Ethernet Timing

2.5.10.1 Management Interface Timing

Table 2-23. Ethernet Controller Management Interface Timing

Characteristics

No.

Min

Max

Unit

801

802

ETHMDIO to ETHMDC rising edge set-up time

ETHMDC rising edge to ETHMDIO hold time

10

—

ns

ETHMDC

801

802

Valid

ETHMDIO

Figure 2-17. MDIO Timing Relationship to MDC

MSC8122 Technical Data, Rev. 13

2-22

Freescale Semiconductor

AC Timings

2.5.10.2 MII Mode Timing

Table 2-24. MII Mode Signal Timing

No.

Characteristics

Min

Max

Unit

803

804

805

ETHRX_DV, ETHRXD[0–3], ETHRX_ER to ETHRX_CLK rising edge set-up time

3.5

—

ns

ETHRX_CLK rising edge to ETHRX_DV, ETHRXD[0–3], ETHRX_ER hold time

ETHTX_CLK to ETHTX_EN, ETHTXD[0–3], ETHTX_ER output delay

•

1.1 V core

1.2 V core

1

14.6

12.6

ns

ETHRX_CLK

803

804

ETHRX_DV

ETHRXD[0–3]

ETHRX_ER

Valid

ETHTX_CLK

805

ETHTX_EN

Valid

ETHTXD[0–3]

ETHTX_ER

Figure 2-18. MII Mode Signal Timing

2.5.10.3 RMII Mode

Table 2-25. RMII Mode Signal Timing

1.1 V Core

1.2 V Core

No.

Characteristics

Unit

ns

Min

Max

Min

Max

806

807

811

ETHTX_EN,ETHRXD[0–1], ETHCRS_DV, ETHRX_ER to ETHREF_CLK rising

edge set-up time

1.6

—

2

—

11

ETHREF_CLK rising edge to ETHRXD[0–1], ETHCRS_DV, ETHRX_ER hold

time

1.6

3

—

1.6

3

ns

ETHREF_CLK rising edge to ETHTXD[0–1], ETHTX_EN output delay.

ETHREF_CLK

12.5

ns

806

807

ETHCRS_DV

ETHRXD[0–1]

ETHRX_ER

Valid

811

ETHTX_EN

ETHTXD[0–1]

Valid

Figure 2-19. RMII Mode Signal Timing

MSC8122 Technical Data, Rev. 13

Freescale Semiconductor

2-23

Specifications

2.5.10.4 SMII Mode

Table 2-26. SMII Mode Signal Timing

No.

Characteristics

Min

Max

Unit

808

809

810

ETHSYNC_IN, ETHRXD to ETHCLOCK rising edge set-up time

ETHCLOCK rising edge to ETHSYNC_IN, ETHRXD hold time

ETHCLOCK rising edge to ETHSYNC, ETHTXD output delay

1.0

—

ns

1

2

•

1.1 V core.

1.2 V core.

1.5

6.0

ns

1

2

1.5

5.0

Notes: 1. Measured using a 5 pF load.

2. Measured using a 15 pF load.

ETHCLOCK

808

809

ETHSYNC_IN

ETHRXD

Valid

810

ETHSYNC

ETHTXD

Valid

Figure 2-20. SMII Mode Signal Timing

2.5.11 GPIO Timing

Table 2-27. GPIO Timing

Ref = CLKOUT

(1.2 V only)

Ref = CLKIN

No.

Characteristics

Unit

Min

Max

Min

Max

601

602

603

604

605

REFCLK edge to GPIO out valid (GPIO out delay time)

REFCLK edge to GPIO out not valid (GPIO out hold time)

REFCLK edge to high impedance on GPIO out

—

1.1

—

6.1

—

1.3

—

6.9

—

ns

5.4

—

6.2

—

GPIO in valid to REFCLK edge (GPIO in set-up time)

REFCLK edge to GPIO in not valid (GPIO in hold time)

3.5

0.5

3.7

0.5

—

MSC8122 Technical Data, Rev. 13

2-24

Freescale Semiconductor

AC Timings

REFCLK

601

603

602

GPIO

(Output)

High Impedance

604

605

GPIO

(Input)

Valid

Figure 2-21. GPIO Timing

2.5.12 EE Signals

Table 2-28. EE Pin Timing

Number

Characteristics

Type

Min

65

66

EE0 (input)

Asynchronous

4 core clock periods

1 core clock period

EE1 (output)

Synchronous to Core clock

Notes: 1. The core clock is the SC140 core clock. The ratio between the core clock and CLKOUT is configured during power-on-reset.

2. Refer to Table 1-4 on page 1-6 for details on EE pin functionality.

Figure 2-22 shows the signal behavior of the EE pins.

65

EE0 in

66

EE1 out

Figure 2-22. EE Pin Timing

2.5.13 JTAG Signals

Table 2-29. JTAG Timing

All

frequencies

No.

Characteristics

Unit

Min

Max

700

701

702

TCK frequency of operation (1/(T × 4); maximum 25 MHz)

TCK cycle time

0.0

25

—

MHz

ns

C

40.0

TCK clock pulse width measured at V = 1.6 V

M

•

High

Low

20.0

16.0

—

ns

703

TCK rise and fall times

0.0

3.0

ns

MSC8122 Technical Data, Rev. 13

Freescale Semiconductor

2-25

Specifications

Table 2-29. JTAG Timing (Continued)

All

frequencies

No.

Characteristics

Unit

Min

Max

704

705

706

707

708

709

710

711

712

713

Note:

Boundary scan input data set-up time

5.0

20.0

0.0

—

ns

Boundary scan input data hold time

TCK low to output data valid

TCK low to output high impedance

TMS, TDI data set-up time

TMS, TDI data hold time

30.0

—

0.0

5.0

20.0

0.0

—

TCK low to TDO data valid

TCK low to TDO high impedance

TRST assert time

20.0

—

0.0

100.0

30.0

TRST set-up time to TCK low

—

All timings apply to OnCE module data transfers as well as any other transfers via the JTAG port.

701

702

V

M

V

M

V

TCK

(Input)

IH

V

IL

703

Figure 2-23. Test Clock Input Timing Diagram

V

TCK

(Input)

IH

V

IL

704

705

Data

Inputs

Input Data Valid

706

Data

Outputs

Output Data Valid

707

Data

Outputs

Figure 2-24. Boundary Scan (JTAG) Timing Diagram

MSC8122 Technical Data, Rev. 13

2-26

Freescale Semiconductor

AC Timings

V

IH

TCK

(Input)

V

IL

709

708

Input Data Valid

TDI

TMS

(Input)

710

TDO

(Output)

Output Data Valid

711

TDO

(Output)

Figure 2-25. Test Access Port Timing Diagram

TCK

(Input)

713

TRST

(Input)

712

Figure 2-26. TRST Timing Diagram

MSC8122 Technical Data, Rev. 13

Freescale Semiconductor

2-27

Specifications

MSC8122 Technical Data, Rev. 13

2-28

Freescale Semiconductor

Packaging

3

This section provides information on the MSC8122 package, including diagrams of the package pinouts and tables

showing how the signals discussed in Chapter 1 are allocated. The MSC8122 is available in a 431-pin flip chip-

plastic ball grid array (FC-PBGA).

3.1 Package Description

Figure 3-1 and Figure 3-2 show top and bottom views of the package, including pinouts. To conform to JEDEC

requirements, the package is based on a 23 × 23 position (20 × 20 mm) layout with the outside perimeter

depopulated. Therefore, ball position numbering starts with B2. Signal names shown in the figures are typically the

signal assigned after reset. Signals that are only used during power-on reset (SWTE, DSISYNC, DSI64, MODCK[1–2],

CNFGS, and CHIP_ID[0–3]) are not shown in these figures if there is another signal assigned to the pin after reset.

Also, there are several signals that are designated as IRQ lines immediately after reset, but represent duplicate IRQ

lines that should be reconfigured by the user. To represent these signals uniquely in the figures, the second

functions (BADDR[29–31], DP[1–7], and INT_OUT) are used.

Table 3-1 lists the MSC8122 signals alphabetically by signal name. Connections with multiple names are listed

individually by each name. Signals with programmable polarity are shown both as signals which are asserted low

(default) and high (that is, NAME/NAME). Table 3-2 lists the signals numerically by pin number. Each pin number is

listed once with the various signals that are multiplexed to it. For simplicity, signals with programmable polarity

are shown in this table only with their default name (asserted low).

Note: For Ethernet signals multiplexed with the DSI/system Bus (MII and RMII modes only), signals not used by

the RMII mode are reserved when the Ethernet controller is multiplexed with the DSI/system bus and

RMII mode is selected. These reserved signals can be left unconnected. These RMII reserved signals are

not included in Table 3-1, but are indicated in Table 3-2.

Note: For Ethernet signals multiplexed with the GPIO/TDM signals, signals not used by the RMII or SMII mode

can be assigned to their alternate GPIO or dedicated function, except for GPIO10 and GPIO14. If the

Ethernet controller is enabled and multiplexed with the GPIO signals and SMII mode is selected, GPIO10

and GPIO14 (E21 and F21, respectively) must be left unconnected. These signals are designated as NC (no

connect) in Table 3-1 and Table 3-2.

MSC8122 Technical Data, Rev. 13

Freescale Semiconductor

3-1

Packaging

Top View

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

NMI_

OUT

V_DD

B

C

D

GND

V_DD

GND

GPIO0

GND

S

V_DD

EE0

V_DD

GND

TDI

TDO

EE1

GPIO28 HCID1 GND

GND

V_DD

GND

V_DD

GND

V_DD

GND GPIO30 GPIO2 GPIO1 GPIO7 GPIO3 GPIO5 GPIO6

RESET

V_DDH

V_DD

V_DDH

GND

HCID2 HCID3 GND

GND

V_DD

GND

V_DD

GPIO31 GPIO29

GPIO4

GND GPIO8

V_DD

TCK

PO

TRST

RST

TMS HRESET GPIO27 HCID0 GND

GND

V_DD

GND

V_DD

GND

V_DD

GND

GND GPIO9 GPIO13 GPIO10 GPIO12

E

F

ETHRX_ ETHTX_

V_DD

NMI

HA25

V_DD

HA29

HA23

HA19

HA13

HA22

GND

BM0

GND

V_DD

GPIO20 GPIO18 GPIO16 GPIO11 GPIO14 GPIO19

RESET CONF

CLK

BADDR

31

INT_ ETHCR

OUT

V_DD

G

H

J

HA24

HA20

HA18

HA15

HA12

HD28

HD26

HD20

HD18

HA27

HA28

HA26

HA21

HA14

HD31

HD30

HD27

V_DDH

HA17 PWE0

ABB

CS1

BCTL0 GPIO15 GND GPIO17 GPIO22

S

PSD

TEST

V_DD

V_DDH

PGTA

BM1 ARTRY AACK

DBB

V_DD

HTA

TT4

CS4 GPIO24 GPIO21

A31

CAS

PSDA BADDR

V_DD

GND

CLKIN

GND

BM2

GND

DBG

GND

TT3 PSDA10 BCTL1 GPIO23 GND GPIO25 A30

MUX

27

BADDR

30

V_DD

K

HA16 PWE3 PWE1

POE

Res.

GND

V_DDH

GND CLKOUT

GND

TT2

ALE

GND

V_DDH

CS2

CS3

GND

V_DDH

A26

A27

A29

A25

A24

A28

A22

A21

A20

A19

A16

BADDR BADDR

V_DDH

GND

V_DDH

GND

V_DDH

HRDS

TA

L

HA11

V_DDH

GND

28

29

HB

RST

V_DD

V_DDH

M

N

P

GND

HWBS

0

V_DDH

HD29

HD25

HD24 PWE2

HBCS

GND

BG

BR

HCS

TEA

DP3

CS0 PSDWE GPIO26 A23

PSD

HWBS HWBS HWBS

3

GND_SYNV_CCSYN

V_DDH

HD23

HD22

HD0

D2

HCLKIN GND

GND

V_DD

GND

TT0

DP0

DP2

D30

GND

A18

A15

A12

A10

A7

2

1

VAL

HWBS HWBS

6

V_DD

D14

D12

V_DD

R

T

GND

HD1

HD2

GND

HD4

V_DDH

TSZ1

TSZ3

TSZ2

D9

GBL

TBST

D11

DP7

DP6

DP5

D25

TS

A17

GND

V_DDH

4

HWBS HWBS

7

HD17

HD16

HD3

HD6

HD7

V_DD

HD21

HD19

V_DDH

TSZ0

D8

D16

D15

TT1

D17

D21

D19

D23

D22

DP4

D26

DP1

D28

A14

A13

A11

A6

5

U

V

D3

D6

D31

D0

D1

D4

D5

D7

D10

D13

D18

D20

GND

V_DDH

D24

D27

D29

A8

A9

V_DDH

W

Y

HD5

HD15

HD14

HD13

GND

HD9

HD10

HD8

GND

V_DD

GND HDST1 HDST0

GND

V_DDH

HD40

HD43

V_DDH

HD33

V_DDH

HD32

HD37

HD38

HD41

GND

HD34

HD35

HD39

GND

V_DDH

HD54

HD55

HD60

HD59

HD61

HD58

GND

V_DDH

HD51

HD52

HD53

GND

V_DDH

GND

HD46

HD47

GND

HD42

HD44

A4

A5

AA

HD12

HD11

HD63

HD62

GND

A0

A2

A3

V_DD

AB GND

HD57

HD56

HD50

HD49

HD48

HD45

HD36

A1

Figure 3-1. MSC8122 Package, Top View

MSC8122 Technical Data, Rev. 13

3-2

Freescale Semiconductor

Package Description

Bottom View

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

NMI_

OUT

V_DD

B

C

D

GND

GPIO0

GND

S

V_DD

EE0

GPIO6 GPIO5 GPIO3 GPIO7 GPIO1 GPIO2 GPIO30 GND

GND

V_DD

GND

V_DD

GND

V_DD

GND HCID1 GPIO28

TDO

EE1

GND

TDI

RESET

V_DDH

V_DD

V_DDH

GPIO8 GND

GPIO4

GPIO29 GPIO31

GND

V_DD

GND

V_DD

GND HCID3 HCID2

GND

V_DD

GPIO12 GPIO10 GPIO13 GPIO9 GND

GND

V_DD

GND

V_DD

GND

V_DD

GND HCID0 GPIO27 HRESET TMS

TRST

RST

TCK

PO

E

F

ETHTX_ ETHRX_

CLK

V_DD

GPIO19 GPIO14 GPIO11 GPIO16 GPIO18 GPIO20

GND

V_DD

GND

BM0

GND

HA22

HA29

HA23

HA19

HA13

NMI

HA25

V_DD

CLK

CONF RESET

ETHCR INT_

BADDR

31

V_DD

G

H

GPIO22 GPIO17 GND GPIO15 BCTL0

CS1

ABB

PWE0 HA17

HA27

HA28

HA26

HA21

HA14

HD31

HD30

HD27

V_DDH

HA24

HA20

HA18

HA15

HA12

HD28

HD26

HD20

HD18

S

OUT

PSD

TEST

CAS

V_DDH

V_DD

A31

GPIO21 GPIO24 CS4

TT4

HTA

DBB

V_DD

AACK ARTRY BM1

PGTA

BADDR PSDA

27

V_DD

J

A30 GPIO25 GND GPIO23 BCTL1 PSDA10 TT3

GND

DBG

GND

BM2

GND

CLKIN

GND

MUX

BADDR

30

V_DD

K

A28

A22

A21

A20

A19

A16

A29

A25

A24

A26

A27

GND

V_DDH

CS2

CS3

ALE

GND

V_DDH

TT2

CLKOUT GND

GND

Res.

GND

V_DDH

POE

PWE1 PWE3 HA16

BADDR BADDR

29

V_DDH

HRDS

TA

V_DDH

GND

V_DDH

GND

L

GND

HA11

V_DDH

28

HB

RST

V_DDH

V_DD

M

N

GND

HWBS

0

V_DDH

A23 GPIO26 PSDWE CS0

PSD

HCS

TEA

DP3

BG

BR

GND

HBCS

PWE2 HD24

HD29

HD25

HWBS HWBS HWBS

V_DDH

V_CCSYNGND_SYN

P

GND

A18

A15

A12

A10

A7

DP0

DP2

D30

GND

TT0

GND

V_DD

GND HCLKIN

HD23

HD22

HD0

D2

VAL

1

2

3

HWBS HWBS

V_DD

D14

D12

R

A17

GND

V_DDH

TS

DP6

DP5

D25

DP7

GBL

TBST

D11

TSZ3

TSZ2

D9

TSZ1

GND

HD1

HD2

GND

HD4

V_DDH

4

6

HWBS HWBS

T

A14

A13

A11

A6

DP1

D28

DP4

D26

D23

D22

D21

D19

TT1

D17

D16

D15

TSZ0

D8

HD21

HD19

V_DDH

HD17

HD16

HD3

HD6

HD7

V_DD

5

7

U

D31

D6

D3

V

A9

A8

D29

D27

D24

GND

V_DDH

D20

D18

D13

D10

D7

D5

D4

D1

D0

V_DDH

W

Y

GND

V_DDH

GND

HD34

HD35

HD39

HD32

HD37

HD38

HD41

HD33

V_DDH

HD40

HD43

V_DDH

GND

V_DDH

HDST0 HDST1 GND

GND

V_DD

GND

HD9

HD10

HD8

HD5

HD15

HD14

HD13

V_DDH

HD54

HD55

A5

A4

GND

HD42

HD44

GND

HD46

HD47

GND

V_DDH

HD51

HD52

HD53

GND

V_DDH

HD58

GND

HD60

HD59

HD61

AA

AB

A3

A2

A0

GND

HD63

HD62

HD12

HD11

V_DD

A1

HD36

HD45

HD48

HD49

HD50

HD56

HD57

GND

Figure 3-2. MSC8122 Package, Bottom View

MSC8122 Technical Data, Rev. 13

Freescale Semiconductor

3-3

Packaging

Table 3-1. MSC8122 Signal Listing By Name

Location

Designator

Location

Designator

Signal Name

A0

A1

AA20

AB21

AA21

AA22

Y21

Y22

W22

W21

V19

V20

V21

V22

U21

U22

T22

T21

R22

R20

R21

P22

N22

M22

L22

BADDR27

BADDR28

BADDR29

BADDR30

BADDR31

BCTL0

BCTL1

BG

J8

L7

A2

L8

A3

K8

A4

G10

G18

J18

N16

G11

H10

J11

G11

H10

J11

P16

B19

C18

C17

D17

J10

K14

W3

N18

G17

K18

L18

H17

K16

J18

J16

H16

V5

A5

A6

A7

A8

BNKSEL0

BNKSEL1

BNKSEL2

BM0

A9

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24

A25

A26

A27

A28

A29

A30

A31

AACK

ABB

ALE

ARTRY

BM1

BM2

BR

CHIP_ID0

CHIP_ID1

CHIP_ID2

CHIP_ID3

CLKIN

CLKOUT

CNFGS

CS0

N21

M21

L21

CS1

CS2

CS3

K20

L20

CS4

CS5

K22

K21

J22

CS5

CS6

CS7

H22

H12

G12

K17

H11

D0

D1

V6

D2

U5

D3

U6

D4

V7

MSC8122 Technical Data, Rev. 13

3-4

Freescale Semiconductor

Package Description

Table 3-1. MSC8122 Signal Listing By Name (Continued)

Location

Designator

Location

Designator

Signal Name

D5

V8

U7

D41

D42

AB18

AA17

Y14

D6

D7

V9

D43

D8

U8

D44

AB17

AB16

AA15

AB15

AB14

AB13

AB12

Y11

D9

U9

D45

D10

D11

D12

D13

D14

D15

D16

D17

D18

D19

D20

D21

D22

D23

D24

D25

D26

D27

D28

D29

D30

D31

D32

D33

D34

D35

D36

D37

D38

D39

D40

V10

U10

V11

V12

U11

U12

T12

U13

V13

U14

V14

T14

U15

T15

V16

U16

U17

V17

U18

V18

T19

U19

W18

W16

Y19

AA19

AB20

Y18

AA18

AB19

W14

D46

D47

D48

D49

D50

D51

D52

AA11

AB11

AA10

AB10

AB9

AB8

Y8

D53

D54

D55

D56

D57

D58

D59

AA7

Y7

D60

D61

AB7

AB6

AA6

G21

T18

D62

D63

DACK1

DACK2

DACK3

DACK4

DBB

DBG

DONE1

DONE2

DP0

F22

R19

T17

T16

H13

J12

F19

G22

P19

DP1

T18

DP2

R19

MSC8122 Technical Data, Rev. 13

Freescale Semiconductor

3-5

Packaging

Table 3-1. MSC8122 Signal Listing By Name (Continued)

Location

Designator

Location

Designator

Signal Name

DP3

DP4

R17

T17

T16

R16

R15

F19

G22

E6

ETHRXD0

ETHRXD1

ETHRXD2

ETHRXD3

ETHSYNC

ETHSYNC_IN

ETHTX_CLK

ETHTX_EN

ETHTX_ER

ETHTXD

ETHTXD0

ETHTXD1

ETHTXD2

ETHTXD3

EXT_BG2

EXT_BG3

EXT_BR2

EXT_BR3

EXT_DBG2

EXT_DBG3

GBL

F21

W14

E22

AB18

C22

AA17

C21

Y14

E22

F15

DP5

DP6

DP7

DRACK1

DRACK2

DREQ1

G19

P19

C6

DREQ1

DREQ2

F16

DREQ2

F18

R17

R16

R15

U4

D17

AA10

D19

AB10

F20

DREQ2

DREQ3

DREQ4

DSI64

DSISYNC

EE0

T4

B19

AA15

C18

AB15

C20

AB14

C19

AB13

T18

D3

EE1

D4

ETHCLOCK

ETHCOL

ETHCRS

ETHCRS_DV

ETHMDC

ETHMDIO

ETHREF_CLK

ETHRX_CLK

ETHRX_DV

ETHRX_ER

ETHRXD

F16

D22

Y7

G15

E21

AB9

E20

Y8

T16

P19

R17

R19

T17

E19

AA7

F16

F15

E21

AB9

F20

AB8

G15

R10

B4

GND

B5

GND

B7

GND

B9

GND

B11

MSC8122 Technical Data, Rev. 13

3-6

Freescale Semiconductor

Package Description

Table 3-1. MSC8122 Signal Listing By Name (Continued)

Location

Designator

Location

Designator

Signal Name

GND

B13

B15

B17

B22

C2

GND

L14

L16

L17

M5

M6

C8

M7

C10

C12

C14

C15

D5

M10

M14

M19

N10

N14

P10

P13

P14

P21

R4

D9

D11

D13

D21

E8

E10

E12

E14

E15

E17

E18

F7

T20

V4

V15

W5

W6

W9

W13

W19

W20

Y9

F11

F13

G20

J6

Y12

Y15

Y17

AA8

AA13

AA16

AB2

P11

B19

C18

J14

J20

K10

K11

K12

K13

K19

L9

GND

SYN

GPIO0

GPIO1

L10

MSC8122 Technical Data, Rev. 13

Freescale Semiconductor

3-7

Packaging

Table 3-1. MSC8122 Signal Listing By Name (Continued)

Location

Designator

Location

Designator

Signal Name

GPIO2

GPIO3

GPIO4

GPIO5

GPIO6

GPIO7

GPIO8

GPIO9

GPIO10

GPIO11

GPIO12

GPIO13

GPIO14

GPIO15

GPIO16

GPIO17

GPIO18

GPIO19

GPIO20

GPIO21

GPIO22

GPIO23

GPIO24

GPIO25

GPIO26

GPIO27

GPIO28

GPIO29

GPIO30

GPIO31

HA7

C17

C20

D19

C21

C22

C19

D22

E19

E21

F20

E22

E20

F21

G19

F19

G21

F18

F22

F17

H19

G22

J19

H18

J21

N20

E6

HA13

HA14

HA15

HA16

HA17

HA18

HA19

HA20

HA21

HA22

HA23

HA24

HA25

HA26

HA27

HA28

HA29

HBCS

HBRST

HCID0

HCID1

HCID2

HCID3

HCLKIN

HCS

J5

L3

K2

K4

G6

J2

H5

H2

K3

F6

G5

G2

G4

J3

G3

H3

F5

N9

M16

E7

C7

D7

D8

P9

N17

T5

HD0

C6

HD1

T4

D17

C16

D16

R14

D8

HD2

U4

V2

W4

W3

W2

Y2

AB5

Y5

AA5

HD3

HD4

HD5

HA8

HD6

HA9

W11

W10

L4

HD7

HA10

HD8

HA11

HD9

HA12

L2

HD10

MSC8122 Technical Data, Rev. 13

3-8

Freescale Semiconductor

Package Description

Table 3-1. MSC8122 Signal Listing By Name (Continued)

Location

Designator

Location

Designator

Signal Name

HD11

HD12

HD13

HD14

HD15

HD16

HD17

HD18

HD19

HD20

HD21

HD22

HD23

HD24

HD25

HD26

HD27

HD28

HD29

HD30

HD31

HD32

HD33

HD34

HD35

HD36

HD37

HD38

HD39

HD40

HD41

HD42

HD43

HD44

HD45

HD46

AB4

AA4

AB3

AA3

Y3

HD47

HD48

AB15

AB14

AB13

AB12

Y11

AA11

AB11

AA10

AB10

AB9

AB8

Y8

HD49

HD50

HD51

U2

HD52

T2

HD53

R2

HD54

U3

HD55

P2

HD56

T3

HD57

R5

HD58

P5

HD59

AA7

Y7

N5

HD60

P4

HD61

AB7

AB6

AA6

N8

N2

HD62

P3

HD63

M2

HDBE0

HDBE1

HDBE2

HDBE3

HDBE4

HDBE5

HDBE6

HDBE7

HDBS0

HDBS1

HDBS2

HDBS3

HDBS4

HDBS5

HDBS6

HDBS7

HDST0

HDST1

HRDE

N4

P8

N3

P7

M3

P6

W18

W16

Y19

AA19

AB20

Y18

AA18

AB19

W14

AB18

AA17

Y14

AB17

AB16

AA15

R7

T7

R6

T6

N8

P8

P7

P6

R7

T7

R6

T6

W11

W10

N15

MSC8122 Technical Data, Rev. 13

Freescale Semiconductor

3-9

Packaging

Table 3-1. MSC8122 Signal Listing By Name (Continued)

Location

Designator

Location

Designator

Signal Name

HRDS

HRESET

HRW

N15

E5

IRQ5

H13

L8

N15

H14

N8

IRQ5

T16

C17

D22

R16

E19

G14

R15

E21

F20

E22

E20

F21

J19

H18

J21

V2

HTA

IRQ6

HWBE0

HWBE1

HWBE2

HWBE3

HWBE4

HWBE5

HWBE6

HWBE7

HWBS0

HWBS1

HWBS2

HWBS3

HWBS4

HWBS5

HWBS6

HWBS7

INT_OUT

IRQ1

IRQ6

P8

IRQ6

P7

IRQ7

P6

IRQ7

R7

IRQ7

T7

IRQ8

R6

IRQ9

T6

IRQ10

IRQ11

IRQ12

IRQ13

IRQ14

IRQ15

MODCK1

MODCK2

NC

N8

P8

P7

P6

R7

T7

R6

W4

E21

F21

F4

T6

G14

C20

R10

T18

D19

K8

NC

NMI

IRQ1

NMI_OUT

PBS0

PBS1

PBS2

PBS3

PBS4

PBS5

PBS6

PBS7

PGPL0

PGPL1

PGPL2

PGPL3

PGPL4

B6

IRQ1

G7

IRQ2

K6

IRQ2

N6

IRQ2

R19

C21

G10

R17

B19

C22

G12

T17

C18

C19

K5

IRQ3

R7

IRQ3

T7

IRQ3

R6

IRQ4

T6

IRQ4

J17

N19

K7

IRQ4

IRQ5

H7

IRQ5

H8

MSC8122 Technical Data, Rev. 13

3-10

Freescale Semiconductor

Package Description

Table 3-1. MSC8122 Signal Listing By Name (Continued)

Location

Designator

Location

Designator

Signal Name

PGPL5

PGTA

J7

H8

K7

F2

TC0

G11

H10

J11

E2

TC1

POE

TC2

PORESET

PPBS

TCK

H8

J17

J7

TDI

D2

PSDA10

PSDAMUX

PSDCAS

PSDDQM0

PSDDQM1

PSDDQM2

PSDDQM3

PSDDQM4

PSDDQM5

PSDDQM6

PSDDQM7

PSDRAS

PSDVAL

PSDWE

PWE0

TDM0RCLK

TDM0RDAT

TDM0RSYN

TDM0TCLK

TDM0TDAT

TDM0TSYN

TDM1RCLK

TDM1RDAT

TDM1RSYN

TDM1TCLK

TDM1TDAT

TDM1TSYN

TDM2RCLK

TDM2RDAT

TDM2RSYN

TDM2TCLK

TDM2TDAT

TDM2TSYN

TDM3RCLK

TDM3RDAT

TDM3RSYN

TDM3TCLK

TDM3TDAT

TDM3TSYN

TDO

J21

N20

H18

G22

J19

H19

F22

F17

F18

F19

G21

G19

E20

F21

E22

E21

F20

E19

C19

D22

C22

D19

C21

C20

C4

H7

G7

K6

N6

K5

R7

T7

R6

T6

K7

P18

N19

G7

K6

N6

K5

R7

T7

PWE1

PWE2

PWE3

PWE4

PWE5

PWE6

R6

T6

PWE7

PUPMWAIT

Reserved

RSTCONF

SCL

H8

K9

F3

D16

C16

C5

T5

TEA

P17

H6

SDA

TEST

SRESET

SWTE

TIMER0

C18

C17

C16

D16

TIMER1

TA

P15

T10

TIMER2

TBST

TIMER3

MSC8122 Technical Data, Rev. 13

Freescale Semiconductor

3-11

Packaging

Table 3-1. MSC8122 Signal Listing By Name (Continued)

Location

Designator

Location

Designator

Signal Name

TMCLK

TMS

TRST

TS

C16

E4

V

F8

F9

DD

E3

F10

F12

F14

G8

R18

T8

TSZ0

TSZ1

TSZ2

TSZ3

TT0

R8

T9

G9

R9

G13

G16

H4

R14

T13

K16

J16

H16

E6

TT1

TT2

H9

TT3

H15

H20

J4

TT4

URXD

UTXD

C6

J9

V

P12

B8

J13

J15

K15

M8

CCSYN

V

DD

B10

B12

B14

B16

B18

B20

B21

C3

R11

R12

R13

T11

Y6

AA2

B3

C9

C11

C13

D10

D12

D14

D15

E9

AB22

D6

V

DDH

D18

D20

H21

L5

L6

E11

E13

E16

L15

L19

M4

MSC8122 Technical Data, Rev. 13

3-12

Freescale Semiconductor

Package Description

Table 3-1. MSC8122 Signal Listing By Name (Continued)

Location

Designator

Location

Designator

Signal Name

V

M9

M15

M17

M18

M20

N7

V

W12

W15

W17

Y4

DDH

Y10

Y13

P20

R3

Y16

Y20

U20

V3

AA9

AA12

AA14

W7

W8

Note: This table lists every signal name. Because many signals are multiplexed, an individual ball designator number may be listed

several times.

MSC8122 Technical Data, Rev. 13

Freescale Semiconductor

3-13

Packaging

Des.

Table 3-2. MSC8122 Signal Listing by Ball Designator

Signal Name

Des.

Signal Name

B3

B4

V

C18

C19

C20

C21

C22

D2

GPIO1/TIMER0/CHIP_ID1/IRQ5/ETHTXD1

DD

GND

GPIO7/TDM3RCLK/IRQ5/ETHTXD3

B5

GPIO3/TDM3TSYN/IRQ1/ETHTXD2

B6

NMI_OUT

GND

GPIO5/TDM3TDAT/IRQ3/ETHRXD3

B7

GPIO6/TDM3RSYN/IRQ4/ETHRXD2

B8

V

TDI

EE0

EE1

GND

DD

B9

GND

D3

B10

B11

B12

B13

B14

B15

B16

B17

B18

B19

B20

B21

B22

C2

V

D4

DD

GND

D5

V

D6

V

DDH

DD

GND

D7

HCID2

HCID3/HA8

GND

V

D8

DD

GND

D9

V

D10

D11

D12

D13

D14

D15

D16

D17

D18

D19

D20

D21

D22

E2

V

DD

GND

V

DD

GPIO0/CHIP_ID0/IRQ4/ETHTXD0

GND

V

DD

GND

GPIO31/TIMER3/SCL

GPIO29/CHIP_ID3/ETHTX_EN

C3

V

DDH

DD

C4

TDO

SRESET

GPIO4/TDM3TCLK/IRQ2/ETHTX_ER

C5

V

DDH

C6

GPIO28/UTXD/DREQ2

HCID1

GND

C7

GPIO8/TDM3RDAT/IRQ6/ETHCOL

C8

GND

TCK

TRST

C9

V

E3

DD

C10

C11

C12

C13

C14

C15

C16

C17

GND

E4

TMS

V

E5

HRESET

GPIO27/URXD/DREQ1

HCID0

DD

GND

E6

V

E7

DD

GND

E8

GND

E9

V

DD

GPIO30/TIMER2/TMCLK/SDA

GPIO2/TIMER1/CHIP_ID2/IRQ6

E10

E11

GND

V

DD

MSC8122 Technical Data, Rev. 13

3-14

Freescale Semiconductor

Package Description

Table 3-2. MSC8122 Signal Listing by Ball Designator (Continued)

Des.

Signal Name

Des.

Signal Name

E12

E13

E14

E15

E16

E17

E18

E19

E20

E21

E22

F2

GND

G6

G7

HA17

V

PWE0/PSDDQM0/PBS0

DD

GND

G8

V

DD

G9

V

G10

G11

G12

G13

G14

G15

G16

G17

G18

G19

G20

G21

G22

H2

IRQ3/BADDR31

BM0/TC0/BNKSEL0

ABB/IRQ4

DD

GND

GPIO9/TDM2TSYN/IRQ7/ETHMDIO

V

DD

GPIO13/TDM2RCLK/IRQ11/ETHMDC

IRQ7/INT_OUT

GPIO10/TDM2TCLK/IRQ8/ETHRX_DV/ETHCRS_DV/NC

ETHCRS/ETHRXD

GPIO12/TDM2RSYN/IRQ10/ETHRXD1/ETHSYNC

V

DD

PORESET

RSTCONF

NMI

CS1

F3

BCTL0

F4

GPIO15/TDM1TSYN/DREQ1

F5

HA29

GND

GPIO17/TDM1TDAT/DACK1

GPIO22/TDM0TCLK/DONE2/DRACK2

HA20

F6

HA22

F7

GND

F8

V

DD

F9

H3

HA28

F10

F11

F12

F13

F14

F15

F16

F17

F18

F19

F20

F21

F22

G2

H4

V

DD

GND

H5

HA19

TEST

V

H6

DD

GND

H7

PSDCAS/PGPL3

V

H8

PGTA/PUPMWAIT/PGPL4/PPBS

DD

ETHRX_CLK/ETHSYNC_IN

ETHTX_CLK/ETHREF_CLK/ETHCLOCK

GPIO20/TDM1RDAT

H9

V

DD

H10

H11

H12

H13

H14

H15

H16

H17

H18

H19

H20

BM1/TC1/BNKSEL1

ARTRY

GPIO18/TDM1RSYN/DREQ2

GPIO16/TDM1TCLK/DONE1/DRACK1

GPIO11/TDM2TDAT/IRQ9/ETHRX_ER/ETHTXD

GPIO14/TDM2RDAT/IRQ12/ETHRXD0/NC

GPIO19/TDM1RCLK/DACK2

HA24

AACK

DBB/IRQ5

HTA

V

DD

TT4/CS7

CS4

G3

HA27

GPIO24/TDM0RSYN/IRQ14

GPIO21/TDM0TSYN

G4

HA25

G5

HA23

V

DD

MSC8122 Technical Data, Rev. 13

Freescale Semiconductor

3-15

Packaging

Des.

Table 3-2. MSC8122 Signal Listing by Ball Designator (Continued)

Signal Name

Des.

Signal Name

H21

H22

J2

V

K15

K16

K17

K18

K19

K20

K21

K22

L2

V

DD

DDH

A31

TT2/CS5

ALE

HA18

HA26

J3

CS2

J4

V

GND

A26

DD

J5

HA13

GND

J6

A29

J7

PSDAMUX/PGPL5

BADDR27

A28

J8

HA12

HA14

HA11

J9

V

L3

DD

J10

J11

J12

J13

J14

J15

J16

J17

J18

J19

J20

J21

J22

K2

CLKIN

BM2/TC2/BNKSEL2

DBG

L4

L5

V

DDH

L6

V

L7

BADDR28

IRQ5/BADDR29

GND

DD

GND

L8

V

L9

DD

TT3/CS6

L10

L14

L15

L16

L17

L18

L19

L20

L21

L22

M2

M3

M4

M5

M6

M7

M8

M9

M10

M14

GND

PSDA10/PGPL0

GND

BCTL1/CS5

V

DDH

GPIO23/TDM0TDAT/IRQ13

GND

CS3

GND

GPIO25/TDM0RCLK/IRQ15

A30

V

DDH

HA15

HA21

A27

A25

K3

K4

HA16

A22

K5

PWE3/PSDDQM3/PBS3

PWE1/PSDDQM1/PBS1

POE/PSDRAS/PGPL2

IRQ2/BADDR30

Reserved

HD28

HD31

K6

K7

V

DDH

K8

GND

K9

K10

K11

K12

K13

K14

GND

V

DD

GND

V

DDH

GND

CLKOUT

MSC8122 Technical Data, Rev. 13

3-16

Freescale Semiconductor

Package Description

Table 3-2. MSC8122 Signal Listing by Ball Designator (Continued)

Des.

Signal Name

Des.

Signal Name

M15

M16

M17

M18

M19

M20

M21

M22

N2

V

P12

P13

P14

P15

P16

P17

P18

P19

P20

P21

P22

R2

V

CCSYN

DDH

HBRST

GND

V

GND

TA

DDH

GND

BR

V

TEA

DDH

A24

PSDVAL

A21

DP0/DREQ1/EXT_BR2

HD26

V

DDH

N3

HD30

HD29

GND

A19

N4

N5

HD24

HD18

N6

PWE2/PSDDQM2/PBS2

R3

V

DDH

N7

V

R4

GND

DDH

N8

HWBS0/HDBS0/HWBE0/HDBE0

R5

HD22

N9

HBCS

R6

HWBS6/HDBS6/HWBE6/HDBE6/PWE6/PSDDQM6/PBS6

N10

N14

N15

N16

N17

N18

N19

N20

N21

N22

P2

GND

R7

HWBS4/HDBS4/HWBE4/HDBE4/PWE4/PSDDQM4/PBS4

GND

R8

TSZ1

TSZ3

HRDS/HRW/HRDE

R9

BG

R10

R11

R12

R13

R14

R15

R16

R17

R18

R19

R20

R21

R22

T2

IRQ1/GBL

HCS

V

DD

CS0

PSDWE/PGPL1

GPIO26/TDM0RDAT

TT0/HA7

A23

IRQ7/DP7/DREQ4

A20

IRQ6/DP6/DREQ3

HD20

IRQ3/DP3/DREQ2/EXT_BR3

P3

HD27

TS

P4

HD25

HD23

IRQ2/DP2/DACK2/EXT_DBG2

P5

A17

A18

P6

HWBS3/HDBS3/HWBE3/HDBE3

HWBS2/HDBS2/HWBE2/HDBE2

HWBS1/HDBS1/HWBE1/HDBE1

HCLKIN

P7

A16

P8

HD17

P9

T3

HD21

P10

P11

GND

T4

HD1/DSISYNC

HD0/SWTE

GND

T5

SYN

MSC8122 Technical Data, Rev. 13

Freescale Semiconductor

3-17

Packaging

Des.

Table 3-2. MSC8122 Signal Listing by Ball Designator (Continued)

Signal Name

Des.

Signal Name

T6

T7

HWBS7/HDBS7/HWBE7/HDBE7/PWE7/PSDDQM7/PBS7

U21

U22

V2

A12

A13

HWBS5/HDBS5/HWBE5/HDBE5/PWE5/PSDDQM5/PBS5

T8

TSZ0

TSZ2

TBST

HD3/MODCK1

T9

V3

V

DDH

T10

T11

T12

T13

T14

T15

T16

T17

T18

T19

T20

T21

T22

U2

V4

GND

D0

V

V5

DD

D16

V6

D1

TT1

V7

D4

D21

V8

D5

D23

V9

D7

IRQ5/DP5/DACK4/EXT_BG3

V10

V11

V12

V13

V14

V15

V16

V17

V18

V19

V20

V21

V22

W2

D10

IRQ4/DP4/DACK3/EXT_DBG3

D12

IRQ1/DP1/DACK1/EXT_BG2

D13

D30

GND

A15

D18

D20

GND

D24

A14

HD16

HD19

HD2/DSI64

D2

D27

U3

D29

U4

A8

U5

A9

U6

D3

A10

U7

D6

A11

U8

D8

HD6

HD5/CNFGS

HD4/MODCK2

GND

U9

D9

W3

U10

U11

U12

U13

U14

U15

U16

U17

U18

U19

U20

D11

D14

D15

D17

D19

D22

D25

D26

D28

D31

W4

W5

W6

W7

V

DDH

W8

W9

GND

W10

W11

W12

W13

W14

HDST1/HA10

HDST0/HA9

V

DDH

GND

V

HD40/D40/ETHRXD0

DDH

MSC8122 Technical Data, Rev. 13

3-18

Freescale Semiconductor

Package Description

Table 3-2. MSC8122 Signal Listing by Ball Designator (Continued)

Des.

Signal Name

Des.

Signal Name

W15

W16

W17

W18

W19

W20

W21

W22

Y2

V

AA9

AA10

AA11

AA12

AA13

AA14

AA15

AA16

AA17

AA18

AA19

AA20

AA21

AA22

AB2

V

DDH

HD33/D33/reserved

HD54/D54/ETHTX_EN

HD52/D52

V

DDH

HD32/D32/reserved

V

DDH

GND

A7

GND

V

DDH

HD46/D46/ETHTXT0

A6

GND

HD7

HD15

HD42/D42/ETHRXD2/reserved

Y3

HD38/D38/reserved

Y4

V

HD35/D35/reserved

DDH

Y5

HD9

A0

Y6

V

A2

DD

Y7

HD60/D60/ETHCOL/reserved

HD58/D58/ETHMDC

GND

A3

GND

Y8

Y9

AB3

HD13

Y10

Y11

Y12

Y13

Y14

Y15

Y16

Y17

Y18

Y19

Y20

Y21

Y22

AA2

AA3

AA4

AA5

AA6

AA7

AA8

V

AB4

HD11

DDH

HD51/D51

GND

AB5

HD8

AB6

HD62/D62

V

AB7

HD61/D61

DDH

HD43/D43/ETHRXD3/reserved

GND

AB8

HD57/D57/ETHRX_ER

HD56/D56/ETHRX_DV/ETHCRS_DV

HD55/D55/ETHTX_ER/reserved

HD53/D53

AB9

V

AB10

AB11

AB12

AB13

AB14

AB15

AB16

AB17

AB18

AB19

AB20

AB21

AB22

DDH

GND

HD37/D37/reserved

HD34/D34/reserved

HD50/D50

HD49/D49/ETHTXD3/reserved

HD48/D48/ETHTXD2/reserved

HD47/D47/ETHTXD1

HD45/D45

V

DDH

A4

A5

V

HD44/D44

DD

HD14

HD12

HD41/D41/ETHRXD1

HD39/D39/reserved

HD36/D36/reserved

A1

HD10

HD63/D63

HD59/D59/ETHMDIO

GND

V

DD

MSC8122 Technical Data, Rev. 13

Freescale Semiconductor

3-19

Packaging

3.2 MSC8122 Package Mechanical Drawing

Notes:

1. All dimensions in millimeters.

2. Dimensioning and tolerancing

per ASME Y14.5M–1994.

3. Features are symmetrical about

the package center lines unless

dimensioned otherwise.

4. Maximum solder ball diameter

measured parallel to Datum A.

5. Datum A, the seating plane, is

determined by the spherical

crowns of the solder balls.

6. Parallelism measurement shall

exclude any effect of mark on

top surface of package.

7. Capacitors may not be present

on all devices.

8. Caution must be taken not to

short capacitors or exposed

metal capacitor pads on

package top.

9. FC CBGA (Ceramic) package

code: 5238.

FC PBGA (Plastic) package

code: 5263.

10.Pin 1 indicator can be in the

form of number 1 marking or an

“L” shape marking.

Figure 3-3. MSC8122 Mechanical Information, 431-pin FC-PBGA Package

MSC8122 Technical Data, Rev. 13

3-20

Freescale Semiconductor

Design Considerations

4

The following sections discuss areas to consider when the MSC8122 device is designed into a system.

4.1 Start-up Sequencing Recommendations

Use the following guidelines for start-up and power-down sequences:

•

Assert PORESET and TRST before applying power and keep the signals driven low until the power reaches the

required minimum power levels. This can be implemented via weak pull-down resistors.

CLKIN can be held low or allowed to toggle during the beginning of the power-up sequence. However, CLKIN

must start toggling before the deassertion of PORESET and after both power supplies have reached nominal

voltage levels.

•

If possible, bring up V_DD/V_CCSYNand V_DDHtogether. If it is not possible, raise V_DD/V_CCSYNfirst and then bring up

V_DDH. V_DDHshould not exceed V_DD/V_CCSYNuntil V_DD/V_CCSYNreaches its nominal voltage level. Similarly, bring

both voltage levels down together. If that is not possible reverse the power-up sequence, with V_DDHgoing down

first and then V_DD/V_CCSYN

.

Note: This recommended power sequencing for the MSC8122 is different from the MSC8102.

External voltage applied to any input line must not exceed the I/O supply V_DDHby more than 0.8 V at any time,

including during power-up. Some designs require pull-up voltages applied to selected input lines during power-up

for configuration purposes. This is an acceptable exception to the rule. However, each such input can draw up to 80

mA per input pin per device in the system during start-up.

After power-up, V_DDHmust not exceed V_DD/V_CCSYNby more than 2.6 V.

4.2 Power Supply Design Considerations

When used as a drop-in replacement in MSC8102 applications or when implementing a new design, use the

guidelines described in Migrating Designs from the MSC8102 to the MSC8122 (AN2716) and the MSC8122

Design Checklist (AN2787) for optimal system performance. MSC8122 and MSC8126 Power Circuit Design

Recommendations and Examples (AN2937) provides detailed design information.

Figure 4-1 shows the recommended power decoupling circuit for the core power supply. The voltage regulator and

the decoupling capacitors should supply the required device current without any drop in voltage on the device pins.

The voltage on the package pins should not drop below the minimum specified voltage level even for a very short

spikes. This can be achieved by using the following guidelines:

•

For the core supply, use a voltage regulator rated at 1.2 V with nominal rating of at least 3 A. This rating does

not reflect actual average current draw, but is recommended because it resists changes imposed by transient

spikes and has better voltage recovery time than supplies with lower current ratings.

MSC8122 Technical Data, Rev. 13

Freescale Semiconductor

4-1

Design Considerations

•

Decouple the supply using low-ESR capacitors mounted as close as possible to the socket. Figure 4-1 shows

three capacitors in parallel to reduce the resistance. Three capacitors is a recommended minimum number. If

possible, mount at least one of the capacitors directly below the MSC8122 device.

Maximum IR drop

of 15 mV at 1 A

L

= 2 cm

max

1.2 V

One 0.01 µF capacitor

for every 3 core supply

pads.

Power supply

or

MSC8122

Voltage Regulator

+

-

Bulk/Tantalum capacitors

with low ESR and ESL

(I

= 3 A)

min

High frequency capacitors

(very low ESR and ESL)

Note: Use at least three capacitors.

Each capacitor must be at least 150 μF.

Figure 4-1. Core Power Supply Decoupling

Each V_CCand V_DDpin on the MSC8122 device should have a low-impedance path to the board power supply.

Similarly, each GND pin should have a low-impedance path to the ground plane. The power supply pins drive

distinct groups of logic on the chip. The V_CCpower supply should have at least four 0.1 µF by-pass capacitors to

ground located as closely as possible to the four sides of the package. The capacitor leads and associated printed

circuit traces connecting to chip V_CC, V_DD, and GND should be kept to less than half an inch per capacitor lead. A

four-layer board is recommended, employing two inner layers as V_CCand GND planes.

All output pins on the MSC8122 have fast rise and fall times. PCB trace interconnection length should be

minimized to minimize undershoot and reflections caused by these fast output switching times. This

recommendation particularly applies to the address and data buses. Maximum PCB trace lengths of six inches are

recommended. For the DSI control signals in synchronous mode, ensure that the layout supports the DSI AC

timing requirements and minimizes any signal crosstalk. Capacitance calculations should consider all device loads

as well as parasitic capacitances due to the PCB traces. Attention to proper PCB layout and bypassing becomes

especially critical in systems with higher capacitive loads because these loads create higher transient currents in the

V_CC, V_DD, and GND circuits. Pull up all unused inputs or signals that will be inputs during reset.

Special care should be taken to minimize the noise levels on the PLL supply pins. There is one pair of PLL supply

pins: V_CCSYN-GND_SYN. To ensure internal clock stability, filter the power to the V_CCSYNinput with a circuit similar to

the one in Figure 4-2. For optimal noise filtering, place the circuit as close as possible to V_CCSYN. The 0.01-µF

capacitor should be closest to V_CCSYN, followed by the 10-µF capacitor, the 10-nH inductor, and finally the 10-Ω

resistor to V_DD. These traces should be kept short and direct. Provide an extremely low impedance path to the

ground plane for GND_SYN. Bypass GND_SYNto V_CCSYNby a 0.01-µF capacitor located as close as possible to the chip

package. For best results, place this capacitor on the backside of the PCB aligned with the depopulated void on the

MSC8122 located in the square defined by positions, L11, L12, L13, M11, M12, M13, N11, N12, and N13.

V_CCSYN

V_DD

10nH

10Ω

10 µF

0.01 µF

Figure 4-2. V_CCSYNBypass

MSC8122 Technical Data, Rev. 13

4-2

Freescale Semiconductor

Connectivity Guidelines

4.3 Connectivity Guidelines

Unused output pins can be disconnected, and unused input pins should be connected to the non-active value, via

resistors to V_DDHor GND, except for the following:

•

If the DSI is unused (DDR[DSIDIS] is set), HCS and HBCS must pulled up and all the rest of the DSI signals

can be disconnected.

When the DSI uses synchronous mode, HTA must be pulled up. In asynchronous mode, HTA should be pulled

either up or down, depending on design requirements.

HDST can be disconnected if the DSI is in big-endian mode, or if the DSI is in little-endian mode and the

DCR[DSRFA] bit is set.

When the DSI is in 64-bit data bus mode and DCR[BEM] is cleared, pull up HWBS[1–3]/HDBS[1–3]/HWBE[1–3]/

HDBE[1–3] and HWBS[4–7]/HDBS[4–7]/HWBE[4–7]/HDBE[4–7]/PWE[4–7]/PSDDQM[4–7]/PBS[4–7].

When the DSI is in 32-bit data bus mode and DCR[BEM] is cleared,

HWBS[1–3]/HDBS[1–3]/HWBE[1–3]/HDBE[1–3] must be pulled up.

•

When the DSI is in asynchronous mode, HBRST and HCLKIN should either be disconnected or pulled up.

The following signals must be pulled up: HRESET, SRESET, ARTRY, TA, TEA, PSDVAL, and AACK.

In single-master mode (BCR[EBM] = 0) with internal arbitration (PPC_ACR[EARB] = 0):

— BG, DBG, and TS can be left unconnected.

— EXT_BG[2–3], EXT_DBG[2–3], and GBL can be left unconnected if they are multiplexed to the system bus

functionality. For any other functionality, connect the signal lines based on the multiplexed functionality.

— BR must be pulled up.

— EXT_BR[2–3] must be pulled up if multiplexed to the system bus functionality.

•

If there is an external bus master (BCR[EBM] = 1):

— BR, BG, DBG, and TS must be pulled up.

— EXT_BR[2–3], EXT_BG[2–3], and EXT_DBG[2–3] must be pulled up if multiplexed to the system bus

functionality.

In single-master mode, ABB and DBB can be selected as IRQ inputs and be connected to the non-active value. In

other modes, they must be pulled up.

Note: The MSC8122 does not support DLL-enabled mode. For the following two clock schemes, ensure that the

DLL is disabled (that is, the DLLDIS bit in the Hard Reset Configuration Word is set).

•

If no system synchronization is required (for example, the design does not use SDRAM), you can use any of

the available clock modes.

In the CLKIN synchronization mode, use the following connections:

— Connect the oscillator output through a buffer to CLKIN.

— Connect the CLKIN buffer output to the slave device (for example, SDRAM) making sure that the delay

path between the clock buffer to the MSC8122 and the SDRAM is equal (that is, has a skew less than 100

ps).

— Valid clock modes in this scheme are: 0, 7, 15, 19, 21, 23, 28, 29, 30, and 31.

MSC8122 Technical Data, Rev. 13

Freescale Semiconductor

4-3

Design Considerations

•

In CLKOUT synchronization mode (for 1.2 V devices), CLKOUT is the main clock to SDRAM. Use the

following connections:

— Connect the oscillator output through a buffer to CLKIN.

— Connect CLKOUT through a zero-delay buffer to the slave device (for example, SDRAM) using the

following guidelines:

•

The maximum delay between the slave and CLKOUT must not exceed 0.7 ns.

The maximum load on CLKOUT must not exceed 10 pF.

Use a zero-delay buffer with a jitter less than 0.3 ns.

— All clock modes are valid in this clock scheme.

Note: See the Clock chapter in the MSC8122 Reference Manual for details.

•

If the 60x-compatible system bus is not used and SIUMCR[PBSE] is set, PPBS can be disconnected.

Otherwise, it should be pulled up.

The following signals: SWTE, DSISYNC, DSI64, MODCK[1–2], CNFGS, CHIPID[0–3], RSTCONF and BM[0–2] are

used to configure the MSC8122 and are sampled on the deassertion of the PORESET signal. Therefore, they

should be tied to GND or V_DDHor through a pull-down or a pull-up resistor until the deassertion of the PORESET

signal.

•

When they are used, INT_OUT (if SIUMCR[INTODC] is cleared), NMI_OUT, and IRQxx (if not full drive)

signals must be pulled up.

When the Ethernet controller is enabled and the SMII mode is selected, GPIO10 and GPIO14 must not be

connected externally to any signal line.

Note: For details on configuration, see the MSC8122 User’s Guide and MSC8122 Reference Manual. For

additional information, refer to the MSC8122 Design Checklist (AN2787).

4.4 External SDRAM Selection

The external bus speed implemented in a system determines the speed of the SDRAM used on that bus. However,

because of differences in timing characteristics among various SDRAM manufacturers, you may have use a faster

speed rated SDRAM to assure efficient data transfer across the bus. For example, for 166 MHz operation, you may

have to use 183 or 200 MHz SDRAM. Always perform a detailed timing analysis using the MSC8122 bus timing

values and the manufacturer specifications for the SDRAM to ensure correct operation within your system design.

The output delay listed in SDRAM specifications is usually given for a load of 30 pF. Scale the number to your

specific board load using the typical scaling number provided by the SDRAM manufacturer.

MSC8122 Technical Data, Rev. 13

4-4

Freescale Semiconductor

Thermal Considerations

4.5 Thermal Considerations

An estimation of the chip-junction temperature, T , in °C can be obtained from the following:

J

T_J= T_A+ (R _JA× P_D)

Equation 1

θ

where

T = ambient temperature near the package (°C)

A

R

= junction-to-ambient thermal resistance (°C/W)

JA

θ

P = P

+ P = power dissipation in the package (W)

D

INT

I/O

P

= I × V = internal power dissipation (W)

INT

I/O

DD DD

= power dissipated from device on output pins (W)

The power dissipation values for the MSC8122 are listed in Table 2-3. The ambient temperature for the device is

the air temperature in the immediate vicinity that would cool the device. The junction-to-ambient thermal

resistances are JEDEC standard values that provide a quick and easy estimation of thermal performance. There are

two values in common usage: the value determined on a single layer board and the value obtained on a board with

two planes. The value that more closely approximates a specific application depends on the power dissipated by

other components on the printed circuit board (PCB). The value obtained using a single layer board is appropriate

for tightly packed PCB configurations. The value obtained using a board with internal planes is more appropriate

2

for boards with low power dissipation (less than 0.02 W/cm with natural convection) and well separated

components. Based on an estimation of junction temperature using this technique, determine whether a more

detailed thermal analysis is required. Standard thermal management techniques can be used to maintain the device

thermal junction temperature below its maximum. If T appears to be too high, either lower the ambient

J

temperature or the power dissipation of the chip. You can verify the junction temperature by measuring the case

temperature using a small diameter thermocouple (40 gauge is recommended) or an infrared temperature sensor on

a spot on the device case that is painted black. The MSC8122 device case surface is too shiny (low emissivity) to

yield an accurate infrared temperature measurement. Use the following equation to determine T :

J

T_J= T_T+ (θ_JA× P_D)

Equation 2

where

T = thermocouple (or infrared) temperature on top of the package (°C)

T

θ

= thermal characterization parameter (°C/W)

JA

P = power dissipation in the package (W)

D

Note: See MSC8102, MSC8122, and MSC8126 Thermal Management Design Guidelines (AN2601/D).

MSC8122 Technical Data, Rev. 13

Freescale Semiconductor

4-5

Ordering Information

Consult a Freescale Semiconductor sales office or authorized distributor to determine product availability and

place an order.

Core

Frequency

(MHz)

Order Number

Core

Operating

Part

Package Type

Voltage Temperature

Lead-Free

Lead-Bearing

MSC8122 Flip Chip Plastic Ball Grid Array (FC-PBGA)

1.1 V

1.2 V

–40° to 105°C

300

400

500

MSC8122TVT4800V

MSC8122TVT6400V

MSC8122TVT6400

MSC8122VT8000

MSC8122TMP4800V

MSC8122TMP6400V

MSC8122TMP6400

MSC8122MP8000

–40° to 105°C

0° to 90°C

Information in this document is provided solely to enable system and software implementers to

use Freescale Semiconductor products. There are no express or implied copyright licenses

granted hereunder to design or fabricate any integrated circuits or integrated circuits based on

the information in this document.

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MSC8122

Rev. 13

10/2006


型号：	MSC8122TMP6400V
厂家：	Freescale
描述：	Quad Core 16-Bit Digital Signal Processor 四核的16位数字信号处理器数字信号处理器
文件：	总88页 (文件大小：2993K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MSC8122TMP6400V [FREESCALE]

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