MSC8122TVT4800 [NXP]
IC,DSP,16-BIT,CMOS,BGA,431PIN,PLASTIC;型号: | MSC8122TVT4800 |
厂家: | NXP |
描述: | IC,DSP,16-BIT,CMOS,BGA,431PIN,PLASTIC |
文件: | 总88页 (文件大小:1698K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
MSC8122
Rev. 4, 1/2005
Freescale Semiconductor
Technical Data Advance Information
MSC8122
Quad Core 16-Bit Digital Signal Processor
The raw processing power of
this highly integrated system-
on- a-chip device will enable
developers to create next-
generation networking
SC140
SC140
SC140
Extended Core
SC140
products that offer
Extended Core
Extended Core
Extended Core
tremendous channel
MQBus
128
128
densities, while maintaining
system flexibility, scalability,
and upgradeability. The
MSC8122 is offered in three
core speed levels: 300, 400,
and 500 MHz.
SQBus
Boot
ROM
64
Local Bus
IP Master
32 Timers
UART
Memory
Controller
M2
RAM
RS-232
What’s New?
Rev. 4 includes the following
changes:
4 TDMs
GPIO Pins
Interrupts
PLL/Clock
PLL
IPBus
32
•
•
•
Package type is FC-PBGA for
all frequencies.
GPIO
GIC
Changes the low voltage 300
MHz core power to 1.1 V.
Table 1-4 updates the
definitions of HRESET and
SRESET.
JTAG Port
JTAG
8 Hardware
Semaphores
MII/RMII/SMII
DSI Port
Ethernet
Internal Local Bus
SIU
64
Direct
Slave
Interface
(DSI)
•
•
•
Figure 2-1 adds undershoot
and overshoot values for VDDH
Table 2-24 updates the RMII
timing.
Updates and rearranges
Chapter 4.
.
System
Interface
32/64
DMA
Bridge
Registers
System Bus
32/64
64
Memory
Controller
Internal System Bus
Figure 1. MSC8122 Block Diagram
The MSC8122 is a highly integrated system-on-a-chip that combines four SC140 extended cores with an RS-232
serial interface, four time-division multiplexed (TDM) serial interfaces, thirty-two general-purpose timers, a
flexible system interface unit (SIU), an Ethernet interface, and a multi-channel DMA engine. The four extended
cores can deliver a total 4800/6400/8000 DSP MMACS performance at 300/400/500 MHz.
Each core has four arithmetic logic units (ALUs), internal memory, a write buffer, and two interrupt controllers.
The MSC8122 targets high-bandwidth highly computational DSP applications and is optimized for wireless
transcoding and packet telephony as well as high-bandwidth base station applications. The MSC8122 delivers
enhanced performance while maintaining low power dissipation and greatly reducing system cost.
Note: This document contains information on a new product. Specifications and information herein are subject to change without notice.
© Freescale Semiconductor, Inc., 2004, 2005. All rights reserved.
Table of Contents
Table of Contents
Features...............................................................................................................................................................iv
Product Documentation ......................................................................................................................................ix
Chapter 1
Signals/Connections
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
Power Signals ...................................................................................................................................................1-3
Clock Signals ....................................................................................................................................................1-3
Reset and Configuration Signals.......................................................................................................................1-3
Direct Slave Interface, System Bus, Ethernet, and Interrupt Signals ...............................................................1-4
Memory Controller Signals ............................................................................................................................1-14
GPIO, TDM, UART, and Timer Signals.........................................................................................................1-16
Dedicated Ethernet Signals.............................................................................................................................1-23
EOnCE Event and JTAG Test Access Port Signals ........................................................................................1-24
Reserved Signals.............................................................................................................................................1-24
Chapter 2
Specifications
2.1
2.2
2.3
2.4
2.5
Maximum Ratings.............................................................................................................................................2-2
Recommended Operating Conditions...............................................................................................................2-3
Thermal Characteristics ....................................................................................................................................2-3
DC Electrical Characteristics............................................................................................................................2-4
AC Timings.......................................................................................................................................................2-5
Chapter 3
Chapter 4
Packaging
3.1
Package Description .........................................................................................................................................3-1
3.2
MSC8122 Package Mechanical Drawing .......................................................................................................3-20
Design Considerations
4.1
4.2
4.3
4.4
4.5
Power Supply Design Considerations...............................................................................................................4-1
Connectivity Guidelines ...................................................................................................................................4-3
External SDRAM Selection..............................................................................................................................4-4
Power Considerations .......................................................................................................................................4-5
Thermal Considerations....................................................................................................................................4-6
Data Sheet Conventions
OVERBAR
Used to indicate a signal that is active when pulled low (For example, the RESET pin is active
when low.)
“asserted”
“deasserted”
Examples:
Means that a high true (active high) signal is high or that a low true (active low) signal is low
Means that a high true (active high) signal is low or that a low true (active low) signal is high
Signal/Symbol
Logic State
True
Signal State
Asserted
Voltage
PIN
PIN
PIN
PIN
V /V
IL OL
False
Deasserted
Asserted
V /V
IH OH
True
V /V
IH OH
False
Deasserted
V /V
IL OL
Note: Values for V , VOL, V , and VOH are defined by individual product specifications.
IL
IH
MSC8122 Technical Data, Rev. 4
ii
Freescale Semiconductor
Data Sheet Conventions
Address
Register
File
Data ALU
Register
File
Program
Sequencer
Address
ALU
Data
ALU
SC140
Core
JTAG
EOnCE
Power
Management
M1
RAM
SC140 Core
64
Xa
Xb
P
64
128
Instruction
Cache
QBus
Interface
QBC
128
QBus
PIC
IRQs
QBus
Bank 1
QBus
Bank 3
LIC
IRQs
MQBus
SQBus
128
128
64
Local Bus
Notes: 1. The arrows show the data transfer direction.
2. The QBus interface includes a bus switch, write buffer, fetch unit, and a
control unit that defines four QBus banks. In addition, the QBC handles internal
memory contentions.
Figure 2. SC140 Extended Core Block Diagram
MSC8122 Technical Data, Rev. 4
Freescale Semiconductor
iii
Features
Features
Feature
Description
Four SC140 cores:
• Up to 8000 MMACS using 16 ALUs running at up to 500 MHz.
• A total of 1436 KB of internal SRAM (224 KB per core).
Each SC140 core provides the following:
•
Up to 2000 MMACS using an internal 500 MHz clock. A MAC operation includes a multiply-accumulate
command with the associated data move and pointer update.
• 4 ALUs per SC140 core.
SC140 Cores
• 16 data registers, 40 bits each.
•
•
•
•
•
•
27 address registers, 32 bits each.
Hardware support for fractional and integer data types.
Very rich 16-bit wide orthogonal instruction set.
Up to six instructions executed in a single clock cycle.
Variable-length execution set (VLES) that can be optimized for code density and performance.
IEEE Std 1149.1™ JTAG port.
• Enhanced on-device emulation (EOnCE) with real-time debugging capabilities.
Each SC140 core is embedded within an extended core that provides the following:
• 224 KB M1 memory that is accessed by the SC140 core with zero wait states.
•
•
Support for atomic accesses to the M1 memory.
16 KB instruction cache, 16 ways.
Extended Core
• A four-entry write buffer that frees the SC140 core from waiting for a write access to finish.
•
•
•
External cache support by asserting the global signal (GBL) when predefined memory banks are accessed.
Programmable interrupt controller (PIC).
Local interrupt controller (LIC).
•
475 KB M2 memory (shared memory) working at the core frequency, accessible from the local bus, and
accessible from all four SC140 cores using the MQBus.
Multi-Core Shared
Memories
• 4 KB bootstrap ROM.
•
•
A QBus protocol multi-master bus connecting the four SC140 coresto the M2 memory.
Data bus access of up to 128-bit read and up to 64-bit write.
M2-Accessible Multi-
Core Bus (MQBus)
• Operation at the SC140 core frequency.
• A central efficient round-robin arbiter controlling SC140 core access on the MQBus.
•
Atomic operation control of access to M2 memory by the four SC140 cores and the local bus.
•
Generates up to 500 MHz core clock and up to166 MHz bus clocks for the 60x-compatible local and system
buses and other modules.
Internal PLL
•
PLL values are determined at reset based on configuration signal values.
• 64/32-bit data and 32-bit address 60x bus.
• Support for multiple-master designs.
•
•
•
Four-beat burst transfers (eight-beat in 32-bit wide mode).
60x-Compatible
System Bus
Port size of 64, 32, 16, and 8 controlled by the internal memory controller.
Bus can access external memory expansion or off-device peripherals, or it can enable an external host device to
access internal resources.
•
•
Slave support, direct access by an external host to internal resources including the M1 and M2 memories.
On-device arbitration between up to four master devices.
A 32/64-bit wide slave host interface that operates only as a slave device under the control of an external host
processor.
• 21–25 bit address, 32/64-bit data.
• Direct access by an external host to internal and external resources, including the M1 and the M2 memories as
well as external devices on the system bus.
•
Synchronous and asynchronous accesses, with burst capability in the synchronous mode.
Direct Slave
Interface (DSI)
• Dual or Single strobe modes.
•
•
•
Write and read buffers improve host bandwidth.
Byte enable signals enables 1, 2, 4, and 8 byte write access granularity.
Sliding window mode enables access with reduced number of address pins.
• Chip ID decoding enables using one CS signal for multiple DSPs.
•
•
Broadcast CS signal enables parallel write to multiple DSPs.
Big-endian, little-endian, and munged little-endian support.
•
•
64-bit DSI, 32-bit system bus.
32-bit DSI, 64-bit system bus.
3-Mode Signal
Multiplexing
• 32-bit DSI, 32-bit system bus, and Ethernet (MII/RMII).
MSC8122 Technical Data, Rev. 4
iv
Freescale Semiconductor
Features
Feature
Description
Flexible eight-bank memory controller:
• Three user-programmable machines (UPMs), general-purpose chip-select machine (GPCM), and a page-mode
SDRAM machine.
• Glueless interface to SRAM, 133 MHz page mode SDRAM, DRAM, EPROM, Flash memory, and other user-
definable peripherals.
•
Byte enables for either 64-bit or 32-bit bus width mode.
• Eight external memory banks (banks 0–7). Two additional memory banks (banks 9, 11) control IPBus
peripherals and internal memories. Each bank has the following features:
—32-bit address decoding with programmable mask.
—Variable block sizes (32 KB to 4 GB).
—Selectable memory controller machine.
Memory Controller
—Two types of data errors check/correction: normal odd/even parity and read-modify-write (RMW) odd/even
parity for single accesses.
—Write-protection capability.
—Control signal generation machine selection on a per-bank basis.
—Support for internal or external masters on the system bus.
—Data buffer controls activated on a per-bank basis.
—Atomic operation.
—RMW data parity check (on system bus only).
—Extensive external memory-controller/bus-slave support.
—Parity byte select pin, which enables a fast, glueless connection to RMW-parity devices (on the system bus
only).
—Data pipeline to reduce data set-up time for synchronous devices.
•
•
•
16 time-multiplexed unidirectional channels.
Services up to four external peripherals.
Supports DONE or DRACK protocol on two external peripherals.
• Each channel group services 16 internal requests generated by eight internal FIFOs. Each FIFO generates:
—A watermark request to indicate that the FIFO contains data for the DMA to empty and write to the destination.
—A hungry request to indicate that the FIFO can accept more data.
Multi-Channel DMA
Controller
•
Priority-based time-multiplexing between channels using 16 internal priority levels.
• Round-robin time-multiplexing between channels.
•
•
A flexible channel configuration:
—All channels support all features.
—All channels connect to the system bus or local bus.
Flyby transfers in which a single data access is transferred directly from the source to the destination without
using a DMA FIFO.
Up to four independent TDM modules, each with the following features:
•
Optional operating configurations:
—Totally independent receive and transmit channels, each having one data line, one clock line, and one frame
sync line.
—Four data lines with one clock and one frame sync shared among the transmit and receive lines.
• Glueless interface to E1/T1 framers and MVIP, SCAS, and H.110 buses.
•
•
Hardware A-law/µ-law conversion.
Up to 66 Mbps per TDM (66 MHz bit clock if one data line is used, 33 MHz if two data lines are used, 16.7 MHz
if four data lines are used).
•
•
•
Up to 256 channels.
Up to 16 MB per channel buffer (granularity 8 bytes), where A/µ law buffer size is double (granularity 16 byte).
Receive buffers share one global write offset pointer that is written to the same offset relative to their start
address.
Time-Division
Multiplexing (TDM)
• Transmit buffers share one global read offset pointer that is read from the same offset relative to their start
address.
•
All channels share the same word size.
• Two programmable receive and two programmable transmit threshold levels with interrupt generation that can
be used, for example, to implement double buffering.
• Each channel can be programmed to be active or inactive.
• 2-, 4-, 8-, or 16-bit channels are stored in the internal memory as 2-, 4-, 8-, or 16-bit channels, respectively.
•
The TDM Transmitter Sync Signal (TxTSYN) can be configured as either input or output.
• Frame Sync and Data signals can be programmed to be sampled either on the rising edge or on the falling edge
of the clock.
•
Frame sync can be programmed as active low or active high.
• Selectable delay (0–3 bits) between the Frame Sync signal and the beginning of the frame.
MSB or LSB first support.
•
MSC8122 Technical Data, Rev. 4
Freescale Semiconductor
v
Features
Feature
Description
•
Designed to comply with IEEE® Std 802® including Std. 802.3™, 802.3u™, 802.3x™, and 802.3ac™.
• Three Ethernet physical interfaces:
—10/100 Mbps MII.
—10/100 Mbps RMII.
—10/100 Mbps SMII.
•
•
Full and half-duplex support.
Full-duplex flow control (automatic PAUSE frame generation or software programmed PAUSE frame generation
and recognition).
• Out-of-sequence transmit queue for initiating flow-control.
• Programmable maximum frame length supports jumbo frames (up to 9.6k) and virtual local area network (VLAN)
tags and priority.
• Retransmission from transmit FIFO following a collision.
•
CRC generation and verification of inbound/outbound packets.
• Address recognition:
—Each exact match can be programmed to be accepted or rejected.
—Broadcast address (accept/reject).
—Exact match 48-bit individual (unicast) address.
—Hash (256-bit hash) check of individual (unicast) addresses.
—Hash (256-bit hash) check of group (multicast) addresses.
—Promiscuous mode.
•
Pattern matching:
—Up to 16 unique 4-byte patterns.
—Pattern match on bit-basis.
Ethernet Controller
—Matching range up to 256 bytes deep into the frame.
—Offsets to a maximum of 252 bytes.
—Programmable pattern size in 4-byte increments up to 64 bytes.
—Accept or reject frames if a match is detected.
—Up to eight unicast addresses for exact matches.
—Pattern matching accepts/rejects IP addresses.
Filing of receive frames based on pattern match; prioritization of frames.
Insertion with expansion or replacement for transmit frames; VLAN tag insertion.
RMON statistics.
•
•
•
• Master DMA on the local bus for fetching descriptors and accessing the buffers.
• Serial interface can be exposed either on GPIO pins or on the high most significant bits of the DSI/system when
the DSI and the system bus are both 32 bits.
•
MPC8260 8-byte width buffer descriptor mode as well as 32 byte width buffer descriptor mode.
• MII Bridge (MIIGSK):
—Programmable selection of the 50 MHz RMII reference clock source (external or internal).
—Independent 2 bit wide transmit and receive data paths.
—Six operating modes.
—Four general-purpose control signals.
—Programmable transmitted inter-frame bits to support inter-frame gap for frames in the SMII domain.
• SMII features:
—Multiplexed only with GPIO signals
—Convey complete MII information between the PHY and MAC.
—Allow direct MAC-to-MAC communication in SMII mode.
—Can generate an interrupt request line while receiving inter-frame segments.
MSC8122 Technical Data, Rev. 4
vi
Freescale Semiconductor
Features
Feature
Description
•
Two signals for transmit data and receive data.
• No clock, asynchronous mode.
• Can be serviced either by the SC140 DSP cores or an external host on the system bus or the DSI.
• Full-duplex operation.
•
Standard mark/space non-return-to-zero (NRZ) format.
• 13-bit baud rate selection.
• Programmable 8-bit or 9-bit data format.
•
•
•
Separately enabled transmitter and receiver.
Programmable transmitter output polarity.
Two receiver wake-up methods:
—Idle line wake-up.
—Address mark wake-up.
•
Separate receiver and transmitter interrupt requests.
UART
• Eight flags, the first five can generate interrupt request:
—Transmitter empty.
—Transmission complete.
—Receiver full.
—Idle receiver input.
—Receiver overrun.
—Noise error.
—Framing error.
—Parity error.
• Receiver framing error detection.
• Hardware parity checking.
• 1/16 bit-time noise detection.
• Maximum bit rate 6.25 Mbps.
•
Single-wire and loop operations.
•
•
32 bidirectional signal lines that either serve the peripherals or act as programmable I/O ports.
Each port can be programmed separately to serve up to two dedicated peripherals, and each port supports
open-drain output mode.
General-Purpose I/O
(GPIO) Port
•
•
Booting from a serial EEPROM.
Uses GPIO timing.
I2C Software Module
Two modules of 16 timers each.
• Cyclic or one-shot.
• Input clock polarity control.
• Interrupt request when counting reaches a programmed threshold.
• Pulse or level interrupts.
Timers
•
•
Dynamically updated programmed threshold.
Read counter any time.
Watchdog mode for the timers that connect to the device.
Eight coded hardware semaphores, locked by simple write access without need for read-modify-write mechanism.
Hardware
Semaphores
• Consolidation of chip maskable interrupt and non-maskable interrupt sources and routing to INT_OUT,
NMI_OUT, and to the cores.
Global Interrupt
Controller (GIC)
•
•
Generation of 32 virtual interrupts (eight to each SC140 core) by a simple write access.
Generation of virtual NMI (one to each SC140 core) by a simple write access.
• Low power CMOS design.
Reduced Power
Dissipation
• Separate power supply for internal logic (1.2 V or 1.1 V for 300 MHz only) and I/O (3.3 V).
•
Low-power standby modes.
• Optimized power management circuitry (instruction-dependent, peripheral-dependent, and mode-dependent).
0.8 mm pitch flip-chip plastic ball-grid array (FC-PBGA) with lead-free or lead-bearing spheres.
• 431-connection (ball).
20 mm × 20 mm.
•
Packaging
•
The real-time operating system (RTOS) fully supports device architecture (multi-core, memory hierarchy, ICache,
timers, DMA controller, interrupts, peripherals), as follows:
•
•
High-performance and deterministic, delivering predictive response time.
Optimized to provide low interrupt latency with high data throughput.
Real-Time Operating
System (RTOS)
• Preemptive and priority-based multitasking.
Fully interrupt/event driven.
•
• Small memory footprint.
• Comprehensive set of APIs.
MSC8122 Technical Data, Rev. 4
Freescale Semiconductor
vii
Features
Feature
Description
• One instance of kernel code in all four SC140 cores.
Dynamic and static memory allocation from local memory (M1) and shared memory (M2).
Multi-Core Support
•
Enables transparent inter-task communications between tasks running inside the SC140 cores and the other tasks
running in on-board devices or remote network devices:
Distributed System
Support
•
•
Messaging mechanism between tasks using mailboxes and semaphores.
Networking support; data transfer between tasks running inside and outside the device using networking
protocols.
•
•
Includes integrated device drivers for such peripherals as TDM, UART, and external buses.
Task debugging utilities integrated with compilers and vendors.
• Board support package (BSP) for the application development system (ADS).
• Integrated development environment (IDE):
—
C/C++ compiler with in-line assembly so developers can generate highly optimized DSP code. Translates
C/C++ code into parallel fetch sets and maintains high code density.
Librarian. User can create libraries for modularity.
A collection of C/C++ functions for developer use.
Highly efficient linker to produce executables from object code.
Seamlessly integrated real-time, non-intrusive multi-mode debugger for debugging highly optimized DSP
algorithms. The developer can choose to debug in source code, assembly code, or mixed mode.
Device simulation models enable design and simulation before hardware availability.
Profiler using a patented binary code instrumentation (BCI) technique helps developers identify program
design inefficiencies.
—
—
—
—
Software Support
—
—
—
Version control. Metrowerks® CodeWarrior® includes plug-ins for ClearCase, Visual SourceSafe, and
CVS.
•
External memory.
• External host.
Boot Options
•
•
•
UART.
TDM.
I2C
• Host debug through single JTAG connector supports both processors.
• MSC8103 as the MSC8122 host with both devices on the board. The MSC8103 system bus connects to the
MSC8122 DSI.
•
Flash memory for stand-alone applications.
• Communications ports:
—10/100Base-T.
—155 Mbit ATM over Optical.
—T1/E1 TDM interface.
MSC8122ADS
—H.110.
—Voice codec.
—RS-232.
—High-density (MICTOR) logic analyzer connectors to monitor MSC8122 signals
—6U CompactPCI form factor.
•
Emulates MSC8122 DSP farm by connecting to three other ADS boards.
MSC8122 Technical Data, Rev. 4
viii
Freescale Semiconductor
Product Documentation
Product Documentation
The documents listed in Table 1 are required for a complete description of the MSC8122 and are necessary to
design properly with the part. Documentation is available from a local Freescale distributor, a Freescale
semiconductor sales office, or a Freescale Literature Distribution Center. For documentation updates, visit the
Freescale DSP website. See the contact information on the back of this document.
Table 1. MSC8122 Documentation
Name
Description
Order Number
MSC8122
MSC8122
Technical Data
MSC8122 features list and physical, electrical, timing, and package specifications
MSC8122
User’s Guide
User information includes system functionality, getting started, and programming
topics
Availability TBD
MSC8122
Reference Manual
Detailed functional description of the MSC8122 memory and peripheral configuration, MSC8122RM
operation, and register programming
StarCore™ SC140 DSP
Core Reference Manual
Detailed description of the SC140 family processor core and instruction set
MNSC140CORE
Application Notes
Documents describing specific applications or optimized device operation including
code examples
Refer to the MSC8122
product page.
MSC8122 Technical Data, Rev. 4
Freescale Semiconductor
ix
MSC8122 Technical Data, Rev. 4
x
Freescale Semiconductor
Signals/Connections
1
The MSC8122 external signals are organized into functional groups, as shown in Table 1-1 and Figure 1-1.
Table 1-1 lists the functional groups, the number of signal connections in each group, and references the table that
gives a detailed listing of multiplexed signals within each group. Figure 1-1 shows MSC8122 external signals
organized by function.
Table 1-1. MSC8122 Functional Signal Groupings
Number of
Functional Group
Signal
Description
Connections
Power (VDD, VCC, and GND)
Clock
155
3
Table 1-2 on page 1-3
Table 1-3 on page 1-3
Table 1-4 on page 1-3
Table 1-5 on page 1-4
Table 1-6 on page 1-14
Table 1-7 on page 1-16
Reset and configuration
4
DSI, system bus, Ethernet, and interrupts
Memory controller
210
16
32
General-purpose input/output (GPIO), time-division multiplexed (TDM) interface,
universal asynchronous receiver/ transmitter (UART), Ethernet, and timers
Dedicated Ethernet signals
3
7
1
Table 1-8 on page 1-23
Table 1-9 on page 1-24
Table 1-10 on page 1-24
EOnCE and JTAG test access port
Reserved (denotes connections that are always reserved)
MSC8122 Technical Data, Rev. 4
Freescale Semiconductor
1-1
Signals/Connections
HD0/SWTE
HD1/DSISYNC
HD2/DSI64
HD3/MODCK1
HD4/MODCK2
HD5/CNFGS
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
→
→
→
→
↔
1
1
1
1
1
1
26
8
1
1
1
1
2
1
1
1
1
4
1
1
1
1
1
1
1
3
3
1
19
4
4
32 ↔ A[0–31]
1
1
3
5
4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
↔ TT0/HA7
↔ TT1
D
S
I
↔ TT[2–4]/CS[5–7]
→ CS[0–4]
↔ TSZ[0–3]
↔ TBST
/
HD[6–31]
S
Y
S.
B
U
S
/
E
T
H
E
R
N
E
T
HD[32-39]/D[32-39]/reserved
HD40/D40/ETHRXD0
HD41/D41/ETHRXD1
HD42/D42/ETHRXD2/reserved
HD43/D43/ETHRXD3/reserved
HD[44-45]/D[44-45]/reserved
HD46/D46/ETHTXD0
HD47/D47/ETHTXD1
HD48/D48/ETHTXD2/reserved
HD49/D49/ETHTXD3/reserved
HD[50-53]/D[50-53]/reserved
HD54/D54/ETHTX_EN
HD55/D55/ETHTX_ER/reserved
↔
↔
↔
↔
IRQ1/GBL
IRQ3/BADDR31
IRQ2/BADDR30
IRQ5/BADDR29
→ BADDR28
→ BADDR27
↔ BR
↔ BG
↔ DBG
S
Y
S
T
E
M
↔
↔
ABB/IRQ4
DBB/IRQ5
↔ TS
↔ AACK
↔ ARTRY
HD56/D56/ETHRX_DV/ETHCRS_DV
HD57/D57/ETHRX_ER
32 ↔ D[0–31]
HD58/D58/ETHMDC
HD59/D59/ETHMDIO
HD60/D60/ETHCOL/reserved
HD[61–63]/D[61-63]/reserved
HCID[0–2]
1
1
1
1
1
1
1
1
1
↔ reserved/DP0/DREQ1/EXT_BR2
↔
↔
↔
↔
↔
↔
↔
IRQ1/DP1/DACK1/EXT_BG2
IRQ2/DP2/DACK2/EXT_DBG2
IRQ3/DP3/DREQ2/EXT_BR3
IRQ4/DP4/DACK3/EXT_DBG3
IRQ5/DP5/DACK4/EXT_BG3
IRQ6/DP6/DREQ3
B
U
S
HCID3/HA8
HA[11–29]
M
E
M
C
HWBS[0–3]/HDBS[0–3]/HWBE[0–3]/HDBE[0–3]
HWBS[4–7]/HDBS[4–7]/HWBE[4–7]/HDBE[4–7]/
IRQ7/DP7/DREQ4
↔ TA
PWE[4–7]/PSDDQM[4–7]/PBS[4–7]
HRDS/HRW/HRDE
→
→
→
→
→
←
→
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
3
1
4
1
1
1
1
1
1
↔ TEA
HBRST
HDST[0–1]/HA[9–10]
← NMI
D
S
I
→ NMI_OUT
↔ PSDVAL
HCS
HBCS
HTA
HCLKIN
↔
→
IRQ7/INT_OUT
BCTL0
→ BCTL1/CS5
M
E
M
C
GPIO0/CHIP_ID0/IRQ4/ETHTXD0
GPIO1/TIMER0/CHIP_ID1/IRQ5/ETHTXD1
GPIO2/TIMER1/CHIP_ID2/IRQ6
GPIO3/TDM3TSYN/IRQ1/ETHTXD2
GPIO4/TDM3TCLK/IRQ2/ETHTX_ER
GPIO5/TDM3TDAT/IRQ3/ETHRXD3
GPIO6/TDM3RSYN/IRQ4/ETHRXD2
GPIO7/TDM3RCLK/IRQ5/ETHTXD3
GPIO8/TDM3RDAT/IRQ6/ETHCOL
GPIO9/TDM2TSYN/IRQ7/ETHMDIO
GPIO10/TDM2TCLK/IRQ8/ETHRX_DV/ETHCRS_DV/NC
GPIO11/TDM2TDAT/IRQ9/ETHRX_ER/ETHTXD
GPIO12/TDM2RSYN/IRQ10/ETHRXD1/ETHSYNC
GPIO13/TDM2RCLK/IRQ11/ETHMDC
GPIO14/TDM2RDAT/IRQ12/ETHRXD0/NC
↔ BM[0–2]/TC[0–2]/BNKSEL[0–2]
→ ALE
→ PWE[0–3]/PSDDQM[0–3]/PBS[0–3]
→ PSDA10/PGPL0
G
P
I
O
/
→ PSDWE/PGPL1
→ POE/PSDRAS/PGPL2
→ PSDCAS/PGPL3
S
Y
S
T
D
M
/
E
T
H
E
R
N
E
T
/
↔
PGTA/PUPMWAIT/PGPL4/PPBS
→ PSDAMUX/PGPL5
De
bug
C
1
1
1
1
1
← EE0
→ EE1
→ CLKOUT
← Reserved
← CLKIN
L
K
R
E
S
E
T
GPIO15/TDM1TSYN/DREQ1
GPIO16/TDM1TCLK/DONE1/DRACK1
GPIO17/TDM1TDAT/DACK1
GPIO18/TDM1RSYN/DREQ2
GPIO19/TDM1RCLK/DACK2
GPIO20/TDM1RDAT
1
1
1
1
1
1
1
1
1
← PORESET
↔ HRESET
SRESET
↔
← RSTCONF
← TMS
← TDI
← TCK
← TRST
→ TDO
J
J
T
A
G
T
I
GPIO21/TDM0TSYN
GPIO22/TDM0TCLK/DONE2/DRACK2
GPIO23/TDM0TDAT/IRQ13
GPIO24/TDM0RSYN/IRQ14
GPIO25/TDM0RCLK/IRQ15
GPIO26/TDM0RDAT
M
E
R
S
/
I
2
C
GPIO27/URXD/DREQ1
GPIO28/UTXD/DREQ2
GPIO29/CHIP_ID3/ETHTX_EN
GPIO30/TIMER2/TMCLK/SDA
GPIO31/TIMER3/SCL
Ded.
Eth.
Net
1
1
1
← ETHRX_CLK/ETHSYNC_IN
← ETHTX_CLK/ETHREF_CLK/ETHCLOCK
← ETHCRS/ETHRXD
Power signals are: V , V
DD
, V
, GND, GND , and GND
. Reserved signals can be left unconnected. NC signals must not be connected.
SYN
DDH
CCSYN
H
Figure 1-1. MSC8122 External Signals
MSC8122 Technical Data, Rev. 4
1-2
Freescale Semiconductor
Power Signals
1.1 Power Signals
Table 1-2. Power and Ground Signal Inputs
Signal Name
VDD
Description
Internal Logic Power
DD dedicated for use with the device core. The voltage should be well-regulated and the input should be provided with
V
an extremely low impedance path to the VDD power rail.
VDDH
Input/Output Power
This source supplies power for the I/O buffers. The user must provide adequate external decoupling capacitors.
VCCSYN
System PLL Power
V
CC dedicated for use with the system Phase Lock Loop (PLL). The voltage should be well-regulated and the input
should be provided with an extremely low impedance path to the VCC power rail.
GND
System Ground
An isolated ground for the internal processing logic and I/O buffers. This connection must be tied externally to all chip
ground connections, except GNDSYN. The user must provide adequate external decoupling capacitors.
GNDSYN
System PLL Ground
Ground dedicated for system PLL use. The connection should be provided with an extremely low-impedance path to
ground.
1.2 Clock Signals
Table 1-3. Clock Signals
Signal Description
Signal Name
CLKIN
Type
Input
Clock In
Primary clock input to the MSC8122 PLL.
CLKOUT
Reserved
Output
Input
Clock Out
The bus clock.
Reserved. Pull down to ground.
1.3 Reset and Configuration Signals
Table 1-4. Reset and Configuration Signals
Signal Name
Type
Signal Description
PORESET
Input
Power-On Reset
When asserted, this line causes the MSC8122 to enter power-on reset state.
RSTCONF
Input
Reset Configuration
Used during reset configuration sequence of the chip. A detailed explanation of its function is provided in
the MSC8122 Reference Manual. This signal is sampled upon deassertion of PORESET.
Note:
When PORESET is deasserted, the MSC8122 also samples the following signals:
• BM[0–2]—Selects the boot mode.
• MODCK[1–2]—Selects the clock configuration.
• SWTE—Enables the software watchdog timer.
• DSISYNC, DSI64, CNFGS, and CHIP_ID[0–3]—Configures the DSI.
Refer to Table 1-5 for details on these signals.
HRESET
SRESET
Input/Output Hard Reset
When asserted as an input, this signal causes the MSC8122 to enter hard reset state. After the device
enters a hard reset state, it drives the signal as an open-drain output.
Input/Output Soft Reset
When asserted as an input, this signal causes the MSC8122 to enter soft reset state. After the device
enters a soft reset state, it drives the signal as an open-drain output.
MSC8122 Technical Data, Rev. 4
Freescale Semiconductor
1-3
Signals/Connections
1.4 Direct Slave Interface, System Bus, Ethernet, and
Interrupt Signals
The direct slave interface (DSI) is combined with the system bus because they share some common signal lines.
Individual assignment of a signal to a specific signal line is configured through internal registers. Table 1-5
describes the signals in this group.
Note: Although there are fifteen interrupt request (IRQ) connections to the core processors, there are multiple
external lines that can connect to these internal signal lines. After reset, the default configuration enables
only IRQ[1–7], but includes two input lines each for IRQ[1–3] and IRQ7. The designer must select one line for
each required interrupt and reconfigure the other external signal line or lines for alternate functions.
Additional alternate IRQ lines and IRQ[8–15] are enabled through the GPIO signal lines.
Table 1-5. DSI, System Bus, Ethernet, and Interrupt Signals
Signal Name
HD0
Type
Description
Input/ Output Host Data Bus 0
Bit 0 of the DSI data bus.
SWTE
Input
Software Watchdog Timer Disable.
It is sampled on the rising edge of PORESET signal.
HD1
Input/ Output Host Data Bus 1
Bit 1 of the DSI data bus.
DSISYNC
Input
DSI Synchronous
Distinguishes between synchronous and asynchronous operation of the DSI. It is sampled on the rising
edge of PORESET signal.
HD2
Input/ Output Host Data Bus 2
Bit 2 of the DSI data bus.
DSI64
Input
DSI 64
Defines the width of the DSI and SYSTEM Data buses. It is sampled on the rising edge of PORESET
signal.
HD3
Input/ Output Host Data Bus 3
Bit 3 of the DSI data bus.
MODCK1
Input
Clock Mode 1
Defines the clock frequencies. It is sampled on the rising edge of PORESET signal.
HD4
Input/ Output Host Data Bus 4
Bit 4 of the DSI data bus.
MODCK2
Input
Clock Mode 2
Defines the clock frequencies. It is sampled on the rising edge of PORESET signal.
HD5
Input/ Output Host Data Bus 5
Bit 5 of the DSI data bus.
CNFGS
Input
Configuration Source
One signal out of two that indicates reset configuration mode. It is sampled on the rising edge of
PORESET signal.
HD[6–31]
Input/ Output Host Data Bus 6–31
Bits 6–31 of the DSI data bus.
MSC8122 Technical Data, Rev. 4
1-4
Freescale Semiconductor
Direct Slave Interface, System Bus, Ethernet, and Interrupt Signals
Table 1-5. DSI, System Bus, Ethernet, and Interrupt Signals (Continued)
Signal Name
Type
Description
HD[32–39]
Input/ Output Host Data Bus 32–39
Bits 32–39 of the DSI data bus.
D[32–39]
Input/ Output System Bus Data 32–39
For write transactions, the bus master drives valid data on this bus. For read transactions, the slave drives
valid data on this bus.
Reserved
Input
If the Ethernet port is enabled and multiplexed with the DSI/System bus, these pins are reserved and can
be left unconnected.
HD40
Input/ Output Host Data Bus 40
Bit 40 of the DSI data bus.
D40
Input/ Output System Bus Data 40
For write transactions, the bus master drives valid data on this line. For read transactions, the slave drives
valid data on this bus.
ETHRXD0
Input
Ethernet Receive Data 0
In MII and RMII modes, bit 0 of the Ethernet receive data.
HD41
Input/ Output Host Data Bus 41
Bit 41 of the DSI data bus.
D41
Input/ Output System Bus Data 41
For write transactions, the bus master drives valid data on this line. For read transactions, the slave drives
valid data on this bus.
ETHRXD1
Input
Ethernet Receive Data 1
In MII and RMII modes, bit 1 of the Ethernet receive data.
HD42
Input/ Output Host Data Bus 42
Bit 42 of the DSI data bus.
D42
Input/ Output System Bus Data 42
For write transactions, the bus master drives valid data on this line. For read transactions, the slave drives
valid data on this bus.
ETHRXD2
Input
Ethernet Receive Data 2
In MII mode only, bit 2 of the Ethernet receive data.
Reserved
Input
In RMII mode, this pin is reserved and can be left unconnected.
HD43
Input/ Output Host Data Bus 43
Bit 43 of the DSI data bus.
D43
Input/ Output System Bus Data 43
For write transactions, the bus master drives valid data on this line. For read transactions, the slave drives
valid data on this bus.
ETHRXD3
Input
Input
Ethernet Receive Data 3
In MII mode only, bit 3 of the Ethernet receive data.
Reserved
In RMII mode, this pin is reserved and can be left unconnected.
HD[44–45]
Input/ Output Host Data Bus 44–45
Bits 44–45 of the DSI data bus.
D[44–56]
Reserved
Input/ Output System Bus Data 44–45
For write transactions, the bus master drives valid data on this bus. For read transactions, the slave drives
valid data on this bus.
Input
If the Ethernet port is enabled and multiplexed with the DSI/System bus, these pins are reserved and can
be left unconnected.
MSC8122 Technical Data, Rev. 4
Freescale Semiconductor
1-5
Signals/Connections
Signal Name
Table 1-5. DSI, System Bus, Ethernet, and Interrupt Signals (Continued)
Type
Input/ Output Host Data Bus 46
Description
HD46
Bit 46 of the DSI data bus.
D46
Input/ Output System Bus Data 46
For write transactions, the bus master drives valid data on this line. For read transactions, the slave drives
valid data on this bus.
ETHTXD0
Output
Ethernet Transmit Data 0
In MII and RMII modes, bit 0 of the Ethernet transmit data.
HD47
Input/ Output Host Data Bus 47
Bit 47 of the DSI data bus.
D47
Input/ Output System Bus Data 47
For write transactions, the bus master drives valid data on this line. For read transactions, the slave drives
valid data on this bus.
ETHTXD1
Output
Ethernet Transmit Data 1
In MII and RMII modes, bit 1 of the Ethernet transmit data.
HD48
Input/ Output Host Data Bus 48
Bit 48 of the DSI data bus.
D48
Input/ Output System Bus Data 48
For write transactions, the bus master drives valid data on this line. For read transactions, the slave drives
valid data on this bus.
ETHTXD2
Output
Input
Ethernet Transmit Data 2
In MII mode only, bit 2 of the Ethernet transmit data.
Reserved
In RMII mode, this pin is reserved and can be left unconnected.
HD49
Input/ Output Host Data Bus 49
Bit 49 of the DSI data bus.
D49
Input/ Output System Bus Data 49
For write transactions, the bus master drives valid data on this line. For read transactions, the slave drives
valid data on this bus.
ETHTXD3
Output
Input
Ethernet Transmit Data 3
In MII mode only, bit 3 of the Ethernet transmit data.
Reserved
In RMII mode, this pin is reserved and can be left unconnected.
HD[50–53]
Input/ Output Host Data Bus 50–53
Bits 50–53 of the DSI data bus.
D[50–53]
Input/ Output System Bus Data 50–53
For write transactions, the bus master drives valid data on this bus. For read transactions, the slave drives
valid data on this bus.
Reserved
Input
If the Ethernet port is enabled and multiplexed with the DSI/System bus, these pins are reserved and can
be left unconnected.
HD54
Input/ Output Host Data Bus 54
Bit 54 of the DSI data bus.
D54
Input/ Output System Bus Data 54
For write transactions, the bus master drives valid data on this line. For read transactions, the slave drives
valid data on this bus.
ETHTX_EN
Output
Ethernet Transmit Data Enable
In MII and RMII modes, indicates that the transmit data is valid.
MSC8122 Technical Data, Rev. 4
1-6
Freescale Semiconductor
Direct Slave Interface, System Bus, Ethernet, and Interrupt Signals
Table 1-5. DSI, System Bus, Ethernet, and Interrupt Signals (Continued)
Signal Name
HD55
Type
Description
Input/ Output Host Data Bus 55
Bit 55 of the DSI data bus.
D55
Input/ Output System Bus Data 55
For write transactions, the bus master drives valid data on this line. For read transactions, the slave drives
valid data on this bus.
ETHTX_ER
Output
Input
Ethernet Transmit Data Error
In MII mode only, indicates a transmit data error.
Reserved
In RMII mode, this pin is reserved and can be left unconnected.
HD56
Input/ Output Host Data Bus 56
Bit 56 of the DSI data bus.
D56
Input/ Output System Bus Data 56
For write transactions, the bus master drives valid data on this line. For read transactions, the slave drives
valid data on this bus.
ETHRX_DV
Input
Input
Ethernet Receive Data Valid
Indicates that the receive data is valid.
ETHCRS_DV
Ethernet Carrier Sense/Receive Data Valid
In RMII mode, indicates that a carrier is detected and after the connection is established that the receive
data is valid.
HD57
Input/ Output Host Data Bus 57
Bit 57 of the DSI data bus.
D57
Input/ Output System Bus Data 57
For write transactions, the bus master drives valid data on this line. For read transactions, the slave drives
valid data on this bus.
ETHRX_ER
Input
Ethernet Receive Data Error
In MII and RMII modes, indicates a receive data error.
HD58
Input/ Output Host Data Bus 58
Bit 58 of the DSI data bus.
D58
Input/ Output System Bus Data 58
For write transactions, the bus master drives valid data on this line. For read transactions, the slave drives
valid data on this bus.
ETHMDC
Output
Ethernet Management Clock
In MII and RMII modes, used for the MDIO reference clock.
HD59
Input/ Output Host Data Bus 59
Bit 59 of the DSI data bus.
D59
Input/ Output System Bus Data 59
For write transactions, the bus master drives valid data on this line. For read transactions, the slave drives
valid data on this bus.
ETHMDIO
Input/ Output Ethernet Management Data
In MII and RMII modes, used for station management data input/output.
MSC8122 Technical Data, Rev. 4
Freescale Semiconductor
1-7
Signals/Connections
Signal Name
Table 1-5. DSI, System Bus, Ethernet, and Interrupt Signals (Continued)
Type
Input/ Output Host Data Bus 60
Description
HD60
Bit 60 of the DSI data bus.
D60
Input/ Output System Bus Data 60
For write transactions, the bus master drives valid data on this line. For read transactions, the slave drives
valid data on this bus.
ETHCOL
Input/ Output Ethernet Collision
In MII mode only, indicates that a collision was detected.
Reserved
Input
In RMII mode, this pin is reserved and can be left unconnected.
HD[61–63]
Input/ Output Host Data Bus 61–63
Bits 61–63 of the DSI data bus.
D[61–63]
Input/ Output System Bus Data 61–63
For write transactions, the bus master drives valid data on this bus. For read transactions, the slave drives
valid data on this bus.
Reserved
HCID[0–2]
Input
Input
If the Ethernet port is enabled and multiplexed with the DSI/System bus, these pins are reserved and can
be left unconnected.
Host Chip ID 0–2
With HCID3, carries the chip ID of the DSI. The DSI is accessed only if HCS is asserted and HCID[0–3]
matches the Chip_ID, or if HBCS is asserted.
HCID3
Input
Host Chip ID 3
With HCI[0–2], carries the chip ID of the DSI. The DSI is accessed only if HCS is asserted and HCID[0–3]
matches the Chip_ID, or if HBCS is asserted.
HA8
Input
Input
Input
Host Bus Address 8
Used by an external host to access the internal address space.
HA[11–29]
HWBS[0–3]
Host Bus Address 11–29
Used by external host to access the internal address space.
Host Write Byte Strobes (In Asynchronous dual mode)
One bit per byte is used as a strobe for host write accesses.
HDBS[0–3]
HWBE[0–3]
HDBE[0–3]
Input
Input
Input
Host Data Byte Strobe (in Asynchronous single mode)
One bit per byte is used as a strobe for host read or write accesses
Host Write Byte Enable (In Synchronous dual mode)
One bit per byte is used to indicate a valid data byte for host read or write accesses.
Host Data Byte Enable (in Synchronous single mode)
One bit per byte is used as a strobe enable for host write accesses
MSC8122 Technical Data, Rev. 4
1-8
Freescale Semiconductor
Direct Slave Interface, System Bus, Ethernet, and Interrupt Signals
Table 1-5. DSI, System Bus, Ethernet, and Interrupt Signals (Continued)
Signal Name
HWBS[4–7]
Type
Description
Host Write Byte Strobes (In Asynchronous dual mode)
Input
One bit per byte is used as a strobe for host write accesses.
HDBS[4–7]
HWBE[4–7]
HDBE[4–7]
PWE[4–7]
Input
Input
Host Data Byte Strobe (in Asynchronous single mode)
One bit per byte is used as a strobe for host read or write accesses
Host Write Byte Enable (In Synchronous dual mode)
One bit per byte is used to indicate a valid data byte for host write accesses.
Input
Host Data Byte Enable (in Synchronous single mode)
One bit per byte is used as a strobe enable for host read or write accesses
Output
System Bus Write Enable
Outputs of the bus general-purpose chip-select machine (GPCM). These pins select byte lanes for write
operations.
PSDDQM[4–7]
PBS[4–7]
Output
Output
System Bus SDRAM DQM
From the SDRAM control machine. These pins select specific byte lanes of SDRAM devices.
System Bus UPM Byte Select
From the UPM in the memory controller, these signals select specific byte lanes during memory
operations. The timing of these pins is programmed in the UPM. The actual driven value depends on the
address and size of the transaction and the port size of the accessed device.
HRDS
Input
Input
Host Read Data Strobe (In Asynchronous dual mode)
Used as a strobe for host read accesses.
HRW
Host Read/Write Select (in Asynchronous/Synchronous single mode)
Host read/write select.
HRDE
Input
Input
Host Read Data Enable (In Synchronous dual mode)
Indicates valid data for host read accesses.
HBRST
Host Burst
The host asserts this pin to indicate that the current transaction is a burst transaction in synchronous
mode only.
HDST[0–1]
Input
Host Data Structure 0–1
Defines the data structure of the host access in DSI little-endian mode.
HA[9–10]
HCS
Host Bus Address 9–10
Used by an external host to access the internal address space.
Input
Input
Host Chip Select
DSI chip select. The DSI is accessed only if HCS is asserted and HCID[0–3] matches the Chip_ID.
HBCS
Host Broadcast Chip Select
DSI chip select for broadcast mode. Enables more than one DSI to share the same host chip-select pin for
broadcast write accesses.
HTA
Output
Input
Host Transfer Acknowledge
Upon a read access, indicates to the host when the data on the data bus is valid. Upon a write access,
indicates to the host that the data on the data bus was written to the DSI write buffer.
HCLKIN
A[0–31]
Host Clock Input
Host clock signal for DSI synchronous mode.
Input/ Output Address Bus
When the MSC8122 is in external master bus mode, these pins function as the system address bus. The
MSC8122 drives the address of its internal bus masters and responds to addresses generated by external
bus masters. When the MSC8122 is in internal master bus mode, these pins are used as address lines
connected to memory devices and are controlled by the MSC8122 memory controller.
TT0
Input/ Output Bus Transfer Type 0
The bus master drives this pins during the address tenure to specify the type of the transaction.
HA7
Host Bus Address 7
Used by an external host to access the internal address space.
MSC8122 Technical Data, Rev. 4
Freescale Semiconductor
1-9
Signals/Connections
Signal Name
Table 1-5. DSI, System Bus, Ethernet, and Interrupt Signals (Continued)
Type
Input/ Output Bus Transfer Type 1
Description
TT1
The bus master drives this pins during the address tenure to specify the type of the transaction. Some
applications use only the TT1 signal, for example, from MSC8122 to MSC8122 or MSC8122 to MSC8101
and vice versa. In these applications, TT1 functions as read/write signal.
TT[2–4]
Input/ Output Bus Transfer Type 2–4
The bus master drives these pins during the address tenure to specify the type of the transaction.
CS[5–7]
CS[0–4]
TSZ[0–3]
Output
Output
Chip Select 5–7
Enables specific memory devices or peripherals connected to the system bus.
Chip Select 0–4
Enables specific memory devices or peripherals connected to the system bus.
Input/ Output Transfer Size 0–3
The bus master drives these pins with a value indicating the number of bytes transferred in the current
transaction.
TBST
Input/ Output Bus Transfer Burst
The bus master asserts this pin to indicate that the current transaction is a burst transaction (transfers
eight words).
IRQ1
Input
Interrupt Request 11
One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the
SC140 core.
GBL
Output
Input
Global1
When a master within the MSC8122 initiates a bus transaction, it drives this pin. Assertion of this pin
indicates that the transfer is global and should be snooped by caches in the system.
Interrupt Request 31
IRQ3
One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the
SC140 core.
BADDR31
Output
Burst Address 311
Five burst address output pins are outputs of the memory controller. These pins connect directly to
burstable memory devices without internal address incrementors controlled by the MSC8122 memory
controller.
IRQ2
Input
Interrupt Request 21
One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the
SC140 core.
BADDR30
Output
Burst Address 301
Five burst address output pins are outputs of the memory controller. These pins connect directly to
burstable memory devices without internal address incrementors controlled by the MSC8122 memory
controller.
IRQ5
Input
Interrupt Request 51
One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the
SC140 core.
BADDR29
Output
Bus Burst Address 291
Five burst address output pins are outputs of the memory controller. These pins connect directly to
burstable memory devices without internal address incrementors controlled by the MSC8122 memory
controller.
BADDR28
BADDR27
Output
Output
Burst Address 28
Five burst address output pins are outputs of the memory controller. These pins connect directly to
burstable memory devices without internal address incrementors controlled by the MSC8122 memory
controller.
Burst Address 27
Five burst address output pins are outputs of the memory controller. These pins connect directly to
burstable memory devices without internal address incrementors controlled by the MSC8122 memory
controller.
MSC8122 Technical Data, Rev. 4
1-10
Freescale Semiconductor
Direct Slave Interface, System Bus, Ethernet, and Interrupt Signals
Table 1-5. DSI, System Bus, Ethernet, and Interrupt Signals (Continued)
Signal Name
BR
Type
Description
Input/ Output Bus Request2
When an external arbiter is used, the MSC8122 asserts this pin as an output to request ownership of the
bus. When the MSC8122 controller is used as an internal arbiter, an external master asserts this pin as an
input to request bus ownership.
BG
Input/ Output Bus Grant2
When the MSC8122 acts as an internal arbiter, it asserts this pin as an output to grant bus ownership to
an external bus master. When an external arbiter is used, it asserts this pin as an input to grant bus
ownership to the MSC8122.
DBG
ABB
Input/ Output Data Bus Grant2
When the MSC8122 acts as an internal arbiter, it asserts this pin as an output to grant data bus ownership
to an external bus master. When an external arbiter is used, it asserts this pin as an input to grant data
bus ownership to the MSC8122.
Input/ Output Address Bus Busy1
The MSC8122 asserts this pin as an output for the duration of the address bus tenure. Following an
AACK, which terminates the address bus tenure, the MSC8122 deasserts ABB for a fraction of a bus
cycle and then stops driving this pin. The MSC8122 does not assume bus ownership as long as it senses
this pin is asserted as an input by an external bus master.
IRQ4
Input
Interrupt Request 4
One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the
SC140 core.
DBB
Input/ Output Data Bus Busy1
The MSC8122 asserts this pin as an output for the duration of the data bus tenure. Following a TA, which
terminates the data bus tenure, the MSC8122 deasserts DBB for a fraction of a bus cycle and then stops
driving this pin. The MSC8122 does not assume data bus ownership as long as it senses that this pin is
asserted as an input by an external bus master.
IRQ5
TS
Input
Interrupt Request 5
One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the
SC140 core.
Input/ Output Bus Transfer Start
Assertion of this pin signals the beginning of a new address bus tenure. The MSC8122 asserts this signal
when one of its internal bus masters begins an address tenure. When the MSC8122 senses that this pin is
asserted by an external bus master, it responds to the address bus tenure as required (snoop if enabled,
access internal MSC8122 resources, memory controller support).
AACK
Input/ Output Address Acknowledge
A bus slave asserts this signal to indicate that it has identified the address tenure. Assertion of this signal
terminates the address tenure.
ARTRY
D[0–31]
Input/ Output Address Retry
Assertion of this signal indicates that the bus master should retry the bus transaction. An external master
asserts this signal to enforce data coherency with its caches and to prevent deadlock situations.
Input/ Output Data Bus Bits 0–31
In write transactions, the bus master drives the valid data on this bus. In read transactions, the slave
drives the valid data on this bus.
Reserved
Input
The primary configuration selection (default after reset) is reserved.
DP0
Input/ Output System Bus Data Parity 0
The agent that drives the data bus also drives the data parity signals. The value driven on the data parity
0 pin should give odd parity (odd number of ones) on the group of signals that includes data parity 0 and
D[0–7].
DREQ1
Input
Input
DMA Request 1
Used by an external peripheral to request DMA service.
EXT_BR2
External Bus Request 2
An external master asserts this pin to request bus ownership from the internal arbiter.
MSC8122 Technical Data, Rev. 4
Freescale Semiconductor
1-11
Signals/Connections
Table 1-5. DSI, System Bus, Ethernet, and Interrupt Signals (Continued)
Signal Name
IRQ1
Type
Description
Input
Interrupt Request 1
One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the
SC140 core.
DP1
Input/ Output System Bus Data Parity 1
The agent that drives the data bus also drives the data parity signals. The value driven on the data parity
1 pin should give odd parity (odd number of ones) on the group of signals that includes data parity 1 and
D[8–15].
DACK1
Output
DMA Acknowledge 1
The DMA controller drives this output to acknowledge the DMA transaction on the bus.
EXT_BG2
Output
Input
External Bus Grant 22
The MSC8122 asserts this pin to grant bus ownership to an external bus master.
IRQ2
Interrupt Request 2
One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the
SC140 core.
DP2
Input/ Output System Bus Data Parity 2
The agent that drives the data bus also drives the data parity signals. The value driven on the data parity
2 pin should give odd parity (odd number of ones) on the group of signals that includes data parity 2 and
D[16–23].
DACK2
Output
DMA Acknowledge 2
The DMA controller drives this output to acknowledge the DMA transaction on the bus.
EXT_DBG2
Output
Input
External Data Bus Grant 22
The MSC8122 asserts this pin to grant data bus ownership to an external bus master.
IRQ3
Interrupt Request 3
One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the
SC140 core.
DP3
Input/ Output System Bus Data Parity 3
The agent that drives the data bus also drives the data parity signals. The value driven on the data parity
3 pin should give odd parity (odd number of ones) on the group of signals that includes data parity 3 and
D[24–31].
DREQ2
Input
DMA Request 2
Used by an external peripheral to request DMA service.
EXT_BR3
Input
Input
External Bus Request 32
An external master should assert this pin to request bus ownership from the internal arbiter.
IRQ4
Interrupt Request 4
One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the
SC140 core.
DP4
Input/ Output System Bus Data Parity 4
The agent that drives the data bus also drives the data parity signals. The value driven on the data parity
4 pin should give odd parity (odd number of ones) on the group of signals that includes data parity 4 and
D[32–39].
DACK3
Output
Output
DMA Acknowledge 3
The DMA controller drives this output to acknowledge the DMA transaction on the bus.
EXT_DBG3
External Data Bus Grant 32
The MSC8122 asserts this pin to grant data bus ownership to an external bus master.
MSC8122 Technical Data, Rev. 4
1-12
Freescale Semiconductor
Direct Slave Interface, System Bus, Ethernet, and Interrupt Signals
Table 1-5. DSI, System Bus, Ethernet, and Interrupt Signals (Continued)
Signal Name
IRQ5
Type
Description
Input
Interrupt Request 5
One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the
SC140 core.
DP5
Input/ Output System Bus Data Parity 5
The agent that drives the data bus also drives the data parity signals. The value driven on the data parity
5 pin should give odd parity (odd number of ones) on the group of signals that includes data parity 5 and
D[40–47].
DACK4
Output
DMA Acknowledge 4
The DMA controller drives this output to acknowledge the DMA transaction on the bus.
EXT_BG3
Output
Input
External Bus Grant 32
The MSC8122 asserts this pin to grant bus ownership to an external bus.
IRQ6
Interrupt Request 6
One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the
SC140 core.
DP6
Input/ Output System Bus Data Parity 6
The agent that drives the data bus also drives the data parity signals. The value driven on the data parity
6 pin should give odd parity (odd number of ones) on the group of signals that includes data parity 6 and
D[48–55].
DREQ3
Input
Input
DMA Request 3
Used by an external peripheral to request DMA service.
IRQ7
Interrupt Request 7
One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the
SC140 core.
DP7
Input/ Output System Bus Data Parity 7
The agent that drives the data bus also drives the data parity signals. The value driven on the data parity
7 pin should give odd parity (odd number of ones) on the group of signals that includes data parity 7 and
D[56–63].
DREQ4
TA
Input
DMA Request 4
Used by an external peripheral to request DMA service.
Input/ Output Transfer Acknowledge
Indicates that a data beat is valid on the data bus. For single-beat transfers, TA assertion indicates the
termination of the transfer. For burst transfers, TA is asserted eight times to indicate the transfer of eight
data beats, with the last assertion indicating the termination of the burst transfer.
TEA
Input/ Output Transfer Error Acknowledge
Indicates a failure of the data tenure transaction.The masters within the MSC8122 monitor the state of this
pin. The MSC8122 internal bus monitor can assert this pin if it identifies a bus transfer that does not
complete.
NMI
Input
Non-Maskable Interrupt
When an external device asserts this line, it generates an non-maskable interrupt in the MSC8122, which
is processed internally (default) or is directed to an external host for processing (see NMI_OUT).
NMI_OUT
Output
Non-Maskable Interrupt Output
An open-drain pin driven from the MSC8122 internal interrupt controller. Assertion of this output indicates
that a non-maskable interrupt is pending in the MSC8122 internal interrupt controller, waiting to be
handled by an external host.
PSDVAL
Input/ Output Port Size Data Valid
Indicates that a data beat is valid on the data bus. The difference between the TA pin and the PSDVAL pin
is that the TA pin is asserted to indicate data transfer terminations, while the PSDVAL signal is asserted
with each data beat movement. When TA is asserted, PSDVAL is always asserted. However, when
PSDVAL is asserted, TA is not necessarily asserted. For example, if the DMA controller initiates a double
word (2 × 64 bits) transaction to a memory device with a 32-bit port size, PSDVAL is asserted three times
without TA and, finally, both pins are asserted to terminate the transfer.
MSC8122 Technical Data, Rev. 4
Freescale Semiconductor
1-13
Signals/Connections
Table 1-5. DSI, System Bus, Ethernet, and Interrupt Signals (Continued)
Signal Name
IRQ7
Type
Description
Input
Interrupt Request 7
One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the
SC140 core.
INT_OUT
Output
Interrupt Output
Assertion of this output indicates that an unmasked interrupt is pending in the MSC8122 internal interrupt
controller.
Notes: 1. See the System Interface Unit (SIU) chapter in the MSC8122 Reference Manual for details on how to configure these pins.
2. When used as the bus control arbiter, the MSC8122 can support up to three external bus masters. Each master uses its own
set of Bus Request, Bus Grant, and Data Bus Grant signals (BR/BG/DBG, EXT_BR2/EXT_BG2/EXT_DBG2, and
EXT_BR3/EXT_BG3/EXT_DBG3). Each of these signal sets must be configured to indicate whether the external master is or
is not a MSC8122 master device. See the Bus Configuration Register (BCR) description in the System Interface Unit (SIU)
chapter in the MSC8122 Reference Manual for details on how to configure these pins. The second and third set of pins is
defined by EXT_xxx to indicate that they can only be used with external master devices. The first set of pins (BR/BG/DBG)
have a dual function. When the MSC8122 is not the bus arbiter, it uses these signals (BR/BG/DBG) to obtain master control of
the bus.
1.5 Memory Controller Signals
Refer to the Memory Controller chapter in the MSC8122 Reference Manual for details on configuring these
signals.
Table 1-6. Memory Controller Signals
Signal Name
BCTL0
Type
Description
Output
System Bus Buffer Control 0
Controls buffers on the data bus. Usually used with BCTL1. The exact function of this pin is defined by the
value of SIUMCR[BCTLC].
BCTL1
Output
System Bus Buffer Control 1
Controls buffers on the data bus. Usually used with BCTL0. The exact function of this pin is defined by the
value of SIUMCR[BCTLC].
CS5
Output
Input
System and Local Bus Chip Select 5
Enables specific memory devices or peripherals connected to MSC8122 buses.
BM[0–2]
Boot Mode 0–2
Defines the boot mode of the MSC8122. This signal is sampled on PORESET deassertion.
TC[0–2]
Input/ Output Transfer Code 0–2
The bus master drives these pins during the address tenure to specify the type of the code.
BNKSEL[0–2]
ALE
Output
Output
Output
Bank Select 0–2
Selects the SDRAM bank when the MSC8122 is in 60x-compatible bus mode.
Address Latch Enable
Controls the external address latch used in an external master bus.
PWE[0–3]
System Bus Write Enable
Outputs of the bus general-purpose chip-select machine (GPCM). These pins select byte lanes for write
operations.
PSDDQM[0–3]
PBS[0–3]
Output
Output
System Bus SDRAM DQM
From the SDRAM control machine. These pins select specific byte lanes of SDRAM devices.
System Bus UPM Byte Select
From the UPM in the memory controller, these signals select specific byte lanes during memory
operations. The timing of these pins is programmed in the UPM. The actual driven value depends on the
address and size of the transaction and the port size of the accessed device.
MSC8122 Technical Data, Rev. 4
1-14
Freescale Semiconductor
Memory Controller Signals
Table 1-6. Memory Controller Signals (Continued)
Signal Name
PSDA10
Type
Description
Output
System Bus SDRAM A10
From the bus SDRAM controller. The precharge command defines which bank is precharged. When the
row address is driven, it is a part of the row address. When column address is driven, it is a part of column
address.
PGPL0
Output
System Bus UPM General-Purpose Line 0
One of six general-purpose output lines from the UPM. The values and timing of this pin are programmed
in the UPM.
PSDWE
Output
Output
System Bus SDRAM Write Enable
From the bus SDRAM controller. Should connect to SDRAM WE input.
PGPL1
System Bus UPM General-Purpose Line 1
One of six general-purpose output lines from the UPM. The values and timing of this pin are programmed
in the UPM.
POE
Output
Output
Output
System Bus Output Enable
From the bus GPCM. Controls the output buffer of memory devices during read operations.
PSDRAS
PGPL2
System Bus SDRAM RAS
From the bus SDRAM controller. Should connect to SDRAM RAS input.
System Bus UPM General-Purpose Line 2
One of six general-purpose output lines from the UPM. The values and timing of this pin are programmed
in the UPM.
PSDCAS
Output
Output
System Bus SDRAM CAS
From the bus SDRAM controller. Should connect to SDRAM CAS input.
PGPL3
System Bus UPM General-Purpose Line 3
One of six general-purpose output lines from the UPM. The values and timing of this pin are programmed
in the UPM.
PGTA
Input
Input
System GPCM TA
Terminates external transactions during GPCM operation. Requires an external pull-up resistor for proper
operation.
PUPMWAIT
PGPL4
System Bus UPM Wait
An external device holds this pin low to force the UPM to wait until the device is ready to continue the
operation.
Output
System Bus UPM General-Purpose Line 4
One of six general-purpose output lines from the UPM. The values and timing of this pin are programmed
in the UPM.
PPBS
Output
Output
System Bus Parity Byte Select
In systems that store data parity in a separate chip, this output is used as the byte-select for that chip.
PSDAMUX
System Bus SDRAM Address Multiplexer
Controls the system bus SDRAM address multiplexer when the MSC8122 is in external master mode.
PGPL5
Output
System Bus UPM General-Purpose Line 5
One of six general-purpose output lines from the UPM. The values and timing of this pin are programmed
in the UPM.
MSC8122 Technical Data, Rev. 4
Freescale Semiconductor
1-15
Signals/Connections
1.6 GPIO, TDM, UART, and Timer Signals
The general-purpose input/output (GPIO), time-division multiplexed (TDM), universal asynchronous
receiver/transmitter (UART), and timer signals are grouped together because they use a common set of signal lines.
Individual assignment of a signal to a specific signal line is configured through internal registers. Table 1-7
describes the signals in this group.
Table 1-7. GPIO, TDM, UART, Ethernet, and Timer Signals
Signal Name
GPIO0
Type
Description
Input/ Output General-Purpose Input Output 0
One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs.
CHIP_ID0
IRQ4
Input
Input
Chip ID 0
Determines the chip ID of the MSC8122 DSI. It is sampled on the rising edge of PORESET signal.
Interrupt Request 4
One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the
SC140 core.
ETHTXD0
Output
Ethernet Transmit Data 0
For MII or RMII mode, bit 0 of the Ethernet transmit data.
GPIO1
Input/ Output General-Purpose Input Output 1
One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs.
Input/ Output Timer 0
Each signal is configured as either input to or output from the counter. See the MSC8122 Reference
TIMER0
CHIP_ID1
IRQ5
Manual for configuration details.
Input
Input
Chip ID 1
Determines the chip ID of the MSC8122 DSI. It is sampled on the rising edge of PORESET signal.
Interrupt Request 5
One of the fifteen external lines that can request a service routine, via the internal interrupt controller, from
the SC140 core.
ETHTXD1
Output
Ethernet Transmit Data 1
For MII or RMII mode, bit 1 of the Ethernet transmit data.
GPIO2
Input/ Output General-Purpose Input Output 2
One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For
details, refer to the MSC8122 Reference Manual.
TIMER1
Input/ Output Timer 1
Each signal is configured as either input to or output from the counter. For the configuration of the pin
direction, refer to the MSC8122 Reference Manual.
CHIP_ID2
IRQ6
Input
Input
Chip ID 2
Determines the chip ID of the MSC8122 DSI. It is sampled on the rising edge of PORESET signal.
Interrupt Request 6
One of the fifteen external lines that can request a service routine, via the internal interrupt controller, from
the SC140 core.
MSC8122 Technical Data, Rev. 4
1-16
Freescale Semiconductor
GPIO, TDM, UART, and Timer Signals
Table 1-7. GPIO, TDM, UART, Ethernet, and Timer Signals (Continued)
Signal Name
GPIO3
Type
Description
Input/ Output General-Purpose Input Output 3
One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For
details, refer to the MSC8122 Reference Manual GPIO programming model.
TDM3TSYN
IRQ1
Input/ Output TDM3 Transmit Frame Sync
Transmit frame sync for TDM 3.
Input
Interrupt Request 1
One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the
SC140 core.
ETHTXD2
Output
Ethernet Transmit Data 2
For MII mode only, bit 2 of the Ethernet transmit data.
GPIO4
Input/ Output General-Purpose Input Output 4
One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For
details, refer to the MSC8122 Reference Manual GPIO programming model.
TDM3TCLK
IRQ2
Input
Input
TDM3 Transmit Clock
Transmit Clock for TDM 3
Interrupt Request 2
One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the
SC140 core.
ETHTX_ER
Output
Ethernet Transmit Data Error
For MII mode only, indicates whether a transmit data error occurred.
GPIO5
Input/ Output General-Purpose Input/Output 5
One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For
details, refer to the MSC8122 Reference Manual GPIO programming model.
TDM3TDAT
IRQ3
Input/ Output TDM3 Serial Transmitter Data
The serial transmit data signal for TDM 3. As an output, it provides the DATA_D signal for TDM 3. For
configuration details, refer to the MSC8122 Reference Manual chapter describing TDM operation.
Input
Input
Interrupt Request 3
One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the
SC140 core.
ETHRXD3
Ethernet Receive Data 3
For MII mode only, bit 3 of the Ethernet receive data.
GPIO6
Input/ Output General-Purpose Input Output 6
One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For
details, refer to the MSC8122 Reference Manual GPIO programming model.
TDM3RSYN
IRQ4
Input/ Output TDM3 Receive Frame Sync
The receive sync signal for TDM 3. As an input, this can be the DATA_B data signal for TDM 3.For
configuration details, refer to the MSC8122 Reference Manual chapter describing TDM operation.
Input
Input
Interrupt Request 4
One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the
SC140 core.
ETHRXD2
Ethernet Receive Data 2
For MII mode only, bit 2 of the Ethernet receive data.
MSC8122 Technical Data, Rev. 4
Freescale Semiconductor
1-17
Signals/Connections
Signal Name
Table 1-7. GPIO, TDM, UART, Ethernet, and Timer Signals (Continued)
Type Description
Input/ Output General-Purpose Input Output 7
GPIO7
One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For
details, refer to the MSC8122 Reference Manual GPIO programming model.
TDM3RCLK
IRQ5
Input/ Output TDM3 Receive Clock
The receive clock signal for TDM 3. As an output, this can be the DATA_C data signal for TDM 3. For
configuration details, refer to the MSC8122 Reference Manual chapter describing TDM operation.
Input
Interrupt Request 5
One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the
SC140 core.
ETHTXD3
Output
Ethernet Transmit Data 3
For MII mode only, bit 3 of the Ethernet transmit data.
GPIO8
Input/ Output General-Purpose Input Output 8
One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For
details, refer to the MSC8122 Reference Manual GPIO programming model.
TDM3RDAT
IRQ6
Input/ Output TDM3 Serial Receiver Data
The receive data signal for TDM 3. As an input, this can be the DATA_A data signal for TDM 3. For
configuration details, refer to the MSC8122 Reference Manual chapter describing TDM operation.
Input
Input
Interrupt Request 6
One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the
SC140 core.
ETHCOL
Ethernet Collision
For MII mode only, indicates whether a collision was detected.
GPIO9
Input/ Output General-Purpose Input Output 9
One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For
details, refer to the MSC8122 Reference Manual GPIO programming model.
TDM2TSYN
IRQ7
Input/ Output TDM2 Transmit frame Sync
Transmit Frame Sync for TDM 2.
Input
Interrupt Request 7
One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the
SC140 core.
ETHMDIO
Input/ Output Ethernet Management Data
Station management data input/output line in MII, RMII, and SMII modes.
GPIO10
Input/ Output General-Purpose Input Output 10
One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For
details, refer to the MSC8122 Reference Manual GPIO programming model.
TDM2TCLK
IRQ8
Input
Input
TDM 2 Transmit Clock
Transmit Clock for TDM 2.
Interrupt Request 8
One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the
SC140 core.
ETHRX_DV
ETHCRS_DV
NC
Input
Input
Input
Ethernet Receive Data Valid
In MII mode, this signal indicates that the receive data is valid.
Ethernet Carrier Sense/Receive Data Valid
In RMII mode, this signal indicates that a carrier is sense or that the receive data is valid.
Not Connected
For SMII mode, this signal must be left unconnected.
MSC8122 Technical Data, Rev. 4
1-18
Freescale Semiconductor
GPIO, TDM, UART, and Timer Signals
Table 1-7. GPIO, TDM, UART, Ethernet, and Timer Signals (Continued)
Signal Name
GPIO11
Type
Description
Input/ Output General-Purpose Input Output 11
One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For
details, refer to the MSC8122 Reference Manual GPIO programming model.
TDM2TDAT
IRQ9
Input/ Output TDM2 Serial Transmitter Data
The transmit data signal for TDM 2. As an output, this can be the DATA_D data signal for TDM 2. For
configuration details, refer to the MSC8122 Reference Manual chapter describing TDM operation.
Input
Interrupt Request 9
One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the
SC140 core.
ETHRX_ER
Input
Ethernet Receive Data Error
In MII and RMII modes, indicates a receive data error.
ETHTXD
Output
Ethernet Transmit Data
In SMII, used as the Ethernet transmit data line.
GPIO12
Input/ Output General-Purpose Input Output 12
One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For
details, refer to the MSC8122 Reference Manual GPIO programming model.
TDM2RSYN
IRQ10
Input/ Output TDM2 Receive Frame Sync
The receive sync signal for TDM 2. As an input, this can be the DATA_B data signal for TDM 2. For
configuration details, refer to the MSC8122 Reference Manual chapter describing TDM operation.
Input
Interrupt Request 10
One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the
SC140 core.
ETHRXD1
Input
Ethernet Receive Data 1
Bit 1 of the Ethernet receive data (MII and RMII mode).
ETHSYNC
Output
Ethernet Sync Signal
In SMII mode, this is the Ethernet sync signal input.
GPIO13
Input/ Output General-Purpose Input Output 13
One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For
details, refer to the MSC8122 Reference Manual GPIO programming model.
TDM2RCLK
IRQ11
Input/ Output TDM2 Receive Clock
The receive clock signal for TDM 2. As an input, this can be the DATA_C data signal for TDM 2. For
configuration details, refer to the MSC8122 Reference Manual chapter describing TDM operation.
Input
Interrupt Request 11
One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the
SC140 core.
ETHMDC
Output
Ethernet Management Clock
Used for the MDIO reference clock for MII, RMII, and SMII modes.
MSC8122 Technical Data, Rev. 4
Freescale Semiconductor
1-19
Signals/Connections
Signal Name
Table 1-7. GPIO, TDM, UART, Ethernet, and Timer Signals (Continued)
Type Description
Input/ Output General-Purpose Input Output 14
GPIO14
One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For
details, refer to the MSC8122 Reference Manual GPIO programming model.
TDM2RDAT
IRQ12
Input/ Output TDM2 Serial Receiver Data
Input
The receive data signal for TDM 2. As an input, this can be the DATA_A data signal for TDM 2. For
configuration details, refer to the MSC8122 Reference Manual chapter describing TDM operation.
Input
Interrupt Request 12
One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the
SC140 core.
ETHRXD0
Input
Input
Ethernet Receive Data 0
Bit 0 of the Ethernet receive data (MII and RMII).
NC
Not Connected
For SMII mode, this signal must be left unconnected.
GPIO15
Input/ Output General-Purpose Input Output 15
One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For
details, refer to the MSC8122 Reference Manual GPIO programming model.
TDM1TSYN
Input/ Output TDM1 Transmit frame Sync
Transmit Frame Sync for TDM 1.
DREQ1
Input
DMA Request 1
Used by an external peripheral to request DMA service.
GPIO16
Input/ Output General-Purpose Input Output 16
One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For
details, refer to the MSC8122 Reference Manual GPIO programming model.
TDM1TCLK
DONE1
Input
TDM1 Transmit Clock
Transmit Clock for TDM 1.
Input/ Output DMA Done 1
Signifies that the channel must be terminated. If the DMA controller generates DONE, the channel
handling this peripheral is inactive. As an input to the DMA controller, DONE closes the channel much like
a normal channel closing.
See the MSC8122 Reference Manual chapters on DMA controller and GPIO for information on
configuring the DRACK or DONE mode and pin direction.
DRACK1
Output
DMA Data Request Acknowledge 1
Asserted by the DMA controller to indicate that the DMA controller has sampled the peripheral request.
GPIO17
Input/ Output General-Purpose Input Output 17
One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For
details, refer to the MSC8122 Reference Manual GPIO programming model.
TDM1TDAT
DACK1
Input/ Output TDM1 Serial Transmitter Data
The transmit data signal for TDM 1. As an output, this can be the DATA_D data signal for TDM 1.For
configuration details, refer to the MSC8122 Reference Manual chapter describing TDM operation.
Output
DMA Acknowledge 1
The DMA controller drives this output to acknowledge the DMA transaction on the bus.
MSC8122 Technical Data, Rev. 4
1-20
Freescale Semiconductor
GPIO, TDM, UART, and Timer Signals
Table 1-7. GPIO, TDM, UART, Ethernet, and Timer Signals (Continued)
Signal Name
GPIO18
Type
Description
Input/ Output General-Purpose Input Output 18
One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For
details, refer to the MSC8122 Reference Manual GPIO programming model.
TDM1RSYN
Input/ Output TDM1 Receive Frame Sync
The receive sync signal for TDM 1. As an input, this can be the DATA_B data signal for TDM 1. For
configuration details, refer to the MSC8122 Reference Manual.
DREQ2
Input
DMA Request 1
Used by an external peripheral to request DMA service.
GPIO19
Input/ Output General-Purpose Input Output 19
One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For
details, refer to the MSC8122 Reference Manual GPIO programming model.
TDM1RCLK
Input/ Output TDM1 Receive Clock
The receive clock signal for TDM 1. As an input, this can be the DATA_C data signal for TDM 1. For
configuration details, refer to the MSC8122 Reference Manual chapter describing TDM operation.
DACK2
Output
DMA Acknowledge 2
The DMA controller drives this output to acknowledge the DMA transaction on the bus.
GPIO20
Input/ Output General-Purpose Input Output 20
One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For
details, refer to the MSC8122 Reference Manual GPIO programming model.
TDM1RDAT
Input/ Output TDM1 Serial Receiver Data
The receive data signal for TDM 1. As an input, this can be the DATA_A data signal for TDM 1. For
configuration details, refer to the MSC8122 Reference Manual.
GPIO21
Input/ Output General-Purpose Input Output 21
One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For
details, refer to the MSC8122 Reference Manual GPIO programming model.
TDM0TSYN
Input/ Output TDM0 Transmit frame Sync
Transmit Frame Sync for TDM 0.
GPIO22
Input/ Output General-Purpose Input Output 22
One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs.For
details, refer to the MSC8122 Reference Manual GPIO programming model.
TDM0TCLK
DONE2
Input
TDM 0 Transmit Clock
Transmit Clock for TDM 0.
Input/ Output DMA Done 2
Signifies that the channel must be terminated. If the DMA generates DONE, the channel handling this
peripheral is inactive. As an input to the DMA, DONE closes the channel much like a normal channel
closing.
Note:
See the MSC8122 Reference Manual chapters on DMA and GPIO for information on
configuring the DRACK or DONE mode and pin direction.
DRACK2
Output
DMA Data Request Acknowledge 2
Asserted by the DMA controller to indicate that the DMA controller has sampled the peripheral request.
MSC8122 Technical Data, Rev. 4
Freescale Semiconductor
1-21
Signals/Connections
Signal Name
Table 1-7. GPIO, TDM, UART, Ethernet, and Timer Signals (Continued)
Type Description
Input/ Output General-Purpose Input Output 23
GPIO23
One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For
details, refer to the MSC8122 Reference Manual GPIO programming model.
TDM0TDAT
Input/ Output TDM0 Serial Transmitter Data
The transmit data signal for TDM 0. As an output, this can be the DATA_D data signal for TDM 0. For
configuration details, refer to the MSC8122 Reference Manual chapter describing TDM operation.
IRQ13
Input
Interrupt Request 13
One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the
SC140 core.
GPIO24
Input/ Output General-Purpose Input Output 24
One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For
details, refer to the MSC8122 Reference Manual GPIO programming model.
TDM0RSYN
Input/ Output TDM0 Receive Frame Sync
The receive sync signal for TDM 0. As an input, this can be the DATA_B data signal for TDM 0. For
configuration details, refer to the MSC8122 Reference Manual chapter describing TDM operation.
IRQ14
Input
Interrupt Request 14
One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the
SC140 core.
GPIO25
Input/ Output General-Purpose Input Output 25
One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For
details, refer to the MSC8122 Reference Manual GPIO programming model.
TDM0RCLK
Input/ Output TDM0 Receive Clock
The receive clock signal for TDM 0. As an input, this can be the DATA_C data signal for TDM 0. For
configuration details, refer to the MSC8122 Reference Manual chapter describing TDM operation.
IRQ15
Input
Interrupt Request 15
One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the
SC140 core.
GPIO26
Input/ Output General-Purpose Input Output 26
One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For
details, refer to the MSC8122 Reference Manual GPIO programming model.
TDM0RDAT
Input/ Output TDM0 Serial Receiver Data
The receive data signal for TDM 0. As an input, this can be the DATA_A data signal for TDM 0. For
configuration details, refer to the MSC8122 Reference Manual chapter describing TDM operation.
GPIO27
Input/ Output General-Purpose Input Output 27
One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For
details, refer to the MSC8122 Reference Manual GPIO programming model.
DREQ1
Input
Input
DMA Request 1
Used by an external peripheral to request DMA service.
URXD
UART Receive Data
GPIO28
Input/ Output General-Purpose Input Output 28
One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For
details, refer to the MSC8122 Reference Manual GPIO programming model.
DREQ2
UTXD
Input
DMA Request 2
Used by an external peripheral to request DMA service.
Output
UART Transmit Data
MSC8122 Technical Data, Rev. 4
1-22
Freescale Semiconductor
Dedicated Ethernet Signals
Table 1-7. GPIO, TDM, UART, Ethernet, and Timer Signals (Continued)
Signal Name
GPIO29
Type
Description
Input/ Output General-Purpose Input Output 29
One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For
details, refer to the MSC8122 Reference Manual GPIO programming model.
CHIP_ID3
Input
Chip ID 3
Determines the chip ID of the MSC8122 DSI. It is sampled on the rising edge of PORESET signal.
Ethernet Transmit Enable
ETHTX_EN
Input
Used to enable the Ethernet transmit controller for MII and RMII modes.
GPIO30
Input/ Output General-Purpose Input Output 30
One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs.For
details, refer to the MSC8122 Reference Manual GPIO programming model.
TIMER2
TMCLK
Input/ Output Timer 2
Each signal is configured as either input to the counter or output from the counter. For the configuration of
the pin direction, refer to the MSC8122 Reference Manual.
Input
External TIMER Clock
An external timer can connect directly to the SIU as the SIU clock.
SDA
Input/ Output I2C-Bus Data Line
This is the data line for the I2C bus.
GPIO31
Input/ Output General-Purpose Input Output 31
One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For
details, refer to the MSC8122 Reference Manual GPIO programming model.
TIMER3
SCL
Input/ Output Timer 3
Each signal is configured as either input to or output from the counter. For the configuration of the pin
direction, refer to the MSC8122 Reference Manual.
Input/ Output I2C-Bus Clock Line
This the clock line for the I2C bus.
1.7 Dedicated Ethernet Signals
Most Ethernet signals are multiplexed with the DSI/system bus and the GPIO ports. In addition to the multiplexed
signals, there are three dedicated Ethernet signals that are described in Table 1-8.
Table 1-8. Dedicated Ethernet Signals
Signal Name
ETHRX_CLK
Type
Signal Description
Input
Receive Clock
In MII mode, provides the timing reference for the receive signals.
ETHSYNC_IN
Input
Input
Sync Input
In SMII mode, is the sync signal input line.
ETHTX_CLK
Transmit Clock
In MII mode, provides the timing reference for transmit signals.
ETHREF_CLK
ETHCLOCK
Input
Input
Reference Clock
In RMII mode, provides the timing reference.
Ethernet Clock
In SMII mode, provides the Ethernet clock signal.
MSC8122 Technical Data, Rev. 4
Freescale Semiconductor
1-23
Signals/Connections
Table 1-8. Dedicated Ethernet Signals
Signal Name
ETHCRS
Type
Signal Description
Input
Carrier Sense
In MII mode, indicates that either the transmit or receive medium is non-idle.
ETHRXD
Input
Ethernet Receive Data
In SMII mode, used for the Ethernet receive data.
1.8 EOnCE Event and JTAG Test Access Port Signals
The MSC8122 uses two sets of debugging signals for the two types of internal debugging modules: EOnCE and the
JTAG TAP controller. Each internal SC140 core has an EOnce module, but they are all accessed externally by the
same two signals EE0 and EE1. The MSC8122 supports the standard set of test access port (TAP) signals defined by
IEEE 1149.1 Standard Test Access Port and Boundary-Scan Architecture specification and described in Table 1-9.
Table 1-9. JTAG TAP Signals
Signal Name
EE0
Type
Signal Description
Input
EOnCE Event Bit 0
Puts the internal SC140 cores into Debug mode.
EE1
Output
EOnCE Event Bit 1
Indicates that at least one on-device SC140 core is in Debug mode.
TCK
TDI
Input
Input
Test Clock—Synchronizes JTAG test logic.
Test Data Input—A test data serial signal for test instructions and data. TDI is sampled on the rising edge
of TCK and has an internal pull-up resistor.
TDO
Output
Test Data Output—A test data serial signal for test instructions and data. TDO can be tri-stated. The
signal is actively driven in the shift-IR and shift-DR controller states and changes on the falling edge of
TCK.
TMS
Input
Input
Test Mode Select—Sequences the test controller state machine, is sampled on the rising edge of TCK,
and has an internal pull-up resistor.
TRST
Test Reset—Asynchronously initializes the test controller, has an internal pull-up resistor, and must be
asserted after power up.
1.9 Reserved Signals
Table 1-10. Reserved Signals
Signal Name
TEST
Type
Signal Description
Input
Test
For manufacturing testing. You must connect this pin to GND.
MSC8122 Technical Data, Rev. 4
1-24
Freescale Semiconductor
Specifications
2
This document contains detailed information on power considerations, DC/AC electrical characteristics, and AC
timing specifications. For additional information, see the MSC8122 User’s Guide and MSC8122 Reference
Manual.
Note: The MSC8122 electrical specifications are preliminary and many are from design simulations. These
specifications may not be fully tested or guaranteed at this early stage of the product life cycle. Finalized
specifications will be published after thorough characterization and device qualifications have been
completed.
MSC8122 Technical Data, Rev. 4
Freescale Semiconductor
2-1
Specifications
2.1 Maximum Ratings
CAUTION
This device contains circuitry protecting against damage
due to high static voltage or electrical fields; however,
normal precautions should be taken to avoid exceeding
maximum voltage ratings. Reliability is enhanced if unused
inputs are tied to an appropriate logic voltage level (for
example, either GND or V ).
DD
In calculating timing requirements, adding a maximum value of one specification to a minimum value of another
specification does not yield a reasonable sum. A maximum specification is calculated using a worst case variation
of process parameter values in one direction. The minimum specification is calculated using the worst case for the
same parameters in the opposite direction. Therefore, a “maximum” value for a specification never occurs in the
same device with a “minimum” value for another specification; adding a maximum to a minimum represents a
condition that can never exist.
Table 2-1 describes the maximum electrical ratings for the MSC8122.
Table 2-1. Absolute Maximum Ratings
Rating
Symbol
Value
Unit
Core and PLL supply voltage
I/O supply voltage
VDD
VDDH
VIN
–0.2 to 1.6
–0.2 to 4.0
–0.2 to 4.0
V
V
V
Input voltage
Maximum operating temperature:
• Commercial range
• Industrial range
TJ
90
105
°C
°C
Minimum operating temperature
• Commercial range
• Industrial range
TJ
0
–40
°C
°C
Storage temperature range
TSTG
–55 to +150
°C
Notes: 1. Functional operating conditions are given in Table 2-2.
2. Absolute maximum ratings are stress ratings only, and functional operation at the maximum is not guaranteed. Stress beyond
the listed limits may affect device reliability or cause permanent damage.
3. Section 4.5, Thermal Considerations includes a formula for computing the chip junction temperature (TJ).
MSC8122 Technical Data, Rev. 4
2-2
Freescale Semiconductor
Recommended Operating Conditions
2.2 Recommended Operating Conditions
Table 2-2 lists recommended operating conditions. Proper device operation outside of these conditions is not
guaranteed.
Table 2-2. Recommended Operating Conditions
Rating
Symbol
Value
Unit
Core supply voltage:
• Standard
VDD
— 300 and 400 MHz
— 500 MHz
• Reduced (300 MHz only)
1.14 to 1.26
1.16 to 1.24
1.07 to 1.13
V
V
V
PLL supply voltage:
• Standard
VCCSYN
— 300 and 400 MHz
— 500 MHz
Reduced (300 MHz only)
1.14 to 1.26
1.16 to 1.24
1.05 to 1.15
V
V
V
I/O supply voltage
Input voltage
VDDH
VIN
3.135 to 3.465
V
V
–0.2 to VDDH+0.2
Operating temperature range:
• Commercial
• Industrial
TJ
TJ
0 to 90
–40 to 105
°C
°C
2.3 Thermal Characteristics
Table 2-3 describes thermal characteristics of the MSC8122 for the FC-PBGA packages.
Table 2-3. Thermal Characteristics for the MSC8122
FC-PBGA
20 × 20 mm
5
Characteristic
Symbol
Unit
Natural
200 ft/min
Convection
(1 m/s) airflow
Junction-to-ambient1, 2
RθJA
RθJA
RθJB
RθJC
26
19
9
21
15
°C/W
°C/W
°C/W
°C/W
°C/W
Junction-to-ambient, four-layer board1, 3
Junction-to-board (bottom)4
Junction-to-case5
0.9
1
Junction-to-package-top6
Ψ
JT
Notes: 1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)
temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal
resistance.
2. Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal.
3. Per JEDEC JESD51-6 with the board horizontal.
4. Thermal resistance between the die and the printed circuit board per JEDEC JESD 51-8. Board temperature is measured on
the top surface of the board near the package.
5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method
1012.1).
6. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature
per JEDEC JESD51-2.
Section 4.5, Thermal Considerations provides a detailed explanation of these characteristics.
MSC8122 Technical Data, Rev. 4
Freescale Semiconductor
2-3
Specifications
2.4 DC Electrical Characteristics
This section describes the DC electrical characteristics for the MSC8122. The measurements in Table 2-4 assume
the following system conditions:
• T = 25 °C
A
• VDD = 1.14–1.26 V or 1.05–1.15 V or 1.16–1.23 V
DC
DC
DC
• VDDH = 3.3 V 5ꢀ V
DC
• GND = 0 V
DC
Note: The leakage current is measured for nominal VDDH and V
.
DD
Table 2-4. DC Electrical Characteristics
Characteristic
Symbol
Min
Typical
Max
Unit
Input high voltage1, all inputs except CLKIN
Input low voltage1
VIH
VIL
VIHC
VILC
IIN
2.0
GND
2.4
—
0
3.465
0.4
3.465
0.4
1
V
V
CLKIN input high voltage
3.0
0
V
CLKIN input low voltage
GND
–1.0
–1.0
–1.0
–1.0
2.0
V
Input leakage current, VIN = VDDH
Tri-state (high impedance off state) leakage current, VIN = VDDH
Signal low input current, VIL = 0.4 V2
Signal high input current, VIH = 2.0 V2
0.09
0.09
0.09
0.09
3.0
µA
µA
µA
µA
V
IOZ
IL
1
1
IH
1
Output high voltage, IOH = –2 mA,
except open drain pins
VOH
—
Output low voltage, IOL= 3.2 mA
VOL
—
0
0.4
V
Internal supply current:
•
•
Wait mode
Stop mode
IDDW
IDDS
—
—
375
TBD
—
—
mA
mA
Typical power 400 MHz at 1.2 V3
P
—
1.15
—
W
Notes: 1. See Figure 2-1 for undershoot and overshoot voltages.
2. Not tested. Guaranteed by design.
3. The typical power values were measured using an EFR code with the device running at a junction temperature of 25°C. No
peripherals were enabled and the ICache was not enabled. The source code was optimized to use all the ALUs and AGUs and
all four cores. It was created using CodeWarrior® 2.5 by Metrowerks®. These values are provided as examples only. Power
consumption is application dependent and varies widely. To assure proper board design with regard to thermal dissipation and
maintaining proper operating temperatures, evaluate power consumption for your application and use the design guidelines in
Chapter 4 of this document and in MSC8102, MSC8122, and MSC8126 Thermal Management Design Guidelines (AN2601).
V
V
+ 20%
+ 10%
DDH
DDH
V
IH
V
DDH
GND
GND – 0.3 V
GND – 0.7 V
V
IL
Must not exceed 10% of clock period
Figure 2-1. Overshoot/Undershoot Voltage for V
DDH
MSC8122 Technical Data, Rev. 4
2-4
Freescale Semiconductor
AC Timings
2.5 AC Timings
2.5.1 Load Assumptions
The following sections include illustrations and tables of clock diagrams, signals, and parallel I/O outputs and
inputs. When systems such as DSP farms are developed using the DSI, use a device loading of 4 pF per pin. AC
timings are based on a 20 pF load, except where noted otherwise, and a 50 Ω transmission line. For any additional
pF, add 0.06 ns for SIU/Ethernet/DSI delay and 0.07 ns for GPIO/TDM/timer delay. When calculating overall
loading, also consider additional RC delay.
2.5.2 Output Buffer Impedances
Table 2-5. Output Buffer Impedances
Output Buffers
Typical Impedance (Ω)
System bus
50
50
50
Memory controller
Parallel I/O
Note:
These are typical values at 65°C. The impedance may vary by 25% depending on device process and operating temperature.
2.5.3 Clock and Timing Signals
The following sections include a description of clock signal characteristics. Table 2-6 shows the maximum
frequency values for internal (Core, Reference, Bus, and DSI) and external (CLKIN and CLKOUT) clocks. The user
must ensure that maximum frequency values are not exceeded.
Table 2-6. Maximum Frequencies
Characteristic
Maximum in MHz
Core frequency
300/400/500
100/133/166
100/133/166
Reference frequency (REFCLK)
Internal bus frequency (BLCK)
DSI clock frequency (HCLKIN)
if REFCLK ≤100, HCLKIN ≤ CLKOUT
if REFCLK > 100, HCLKIN ≤100
External clock frequency (CLKIN or CLKOUT)
100/133/166
Note:
The REFCLK is CLKIN.
Table 2-7. Clock Frequencies
300 MHz Device
400 MHz Device
500 MHz Device
Characteristics
Symbol
Min
Max
Min
Max
Min
Max
CLKIN frequency
FCLKIN
FBCLK
20
40
100
100
100
100
300
20
40
133.3
133.3
133.3
133.3
400
20
40
166.7
166.7
166.7
166.7
500
BCLK frequency
Reference clock (REFCLK) frequency
Output clock (CLKOUT) frequency
SC140 core clock frequency
FREFCLK
FCLKOUT
FCORE
40
40
40
40
40
40
200
200
200
Note:
The rise and fall time of external clocks should be 3 ns maximum
MSC8122 Technical Data, Rev. 4
Freescale Semiconductor
2-5
Specifications
Table 2-8. System Clock Parameters
Characteristic
Min
Max
Unit
CLKIN frequency
20
see Table 2-7
MHz
ns
CLKIN slope
—
3
66.7
PLL input clock (after predivider)
PLL output frequency (VCO output)
CLKOUT frequency jitter1
CLKOUT phase jitter1
20
MHz
MHz
ps
CLKOUT × 2
CLKOUT × 4
400
—
—
0.5 + CLKIN jitter
ns
Notes: 1. Peak-to-peak.
2. Not tested. Guaranteed by design.
2.5.4 Reset Timing
The MSC8122 has several inputs to the reset logic:
• Power-on reset (PORESET)
• External hard reset (HRESET)
• External soft reset (SRESET)
• Software watchdog reset
• Bus monitor reset
• Host reset command through JTAG
All MSC8122 reset sources are fed into the reset controller, which takes different actions depending on the source
of the reset. The reset status register indicates the most recent sources to cause a reset. Table 2-9 describes the reset
sources.
Table 2-9. Reset Sources
Name
Direction
Description
Power-on reset
(PORESET)
Input
Initiates the power-on reset flow that resets the MSC8122 and configures various attributes of the
MSC8122. On PORESET, the entire MSC8122 device is reset. SPLL states is reset, HRESET and
SRESET are driven, the SC140 extended cores are reset, and system configuration is sampled. The
clock mode (MODCK bits), reset configuration mode, boot mode, Chip ID, and use of either a DSI 64
bits port or a System Bus 64 bits port are configured only when PORESET is asserted.
External hard
reset (HRESET)
Input/ Output
Initiates the hard reset flow that configures various attributes of the MSC8122. While HRESET is
asserted, SRESET is also asserted. HRESET is an open-drain pin. Upon hard reset, HRESET and
SRESET are driven, the SC140 extended cores are reset, and system configuration is sampled. The
most configurable features are reconfigured. These features are defined in the 32-bit hard reset
configuration word described in Hard Reset Configuration Word section of the Reset chapter in the
MSC8122 Reference Manual.
External soft reset
(SRESET)
Input/ Output
Initiates the soft reset flow. The MSC8122 detects an external assertion of SRESET only if it occurs
while the MSC8122 is not asserting reset. SRESET is an open-drain pin. Upon soft reset, SRESET is
driven, the SC140 extended cores are reset, and system configuration is maintained.
Software
watchdog reset
Internal
Internal
Internal
When the MSC8122 watchdog count reaches zero, a software watchdog reset is signalled. The
enabled software watchdog event then generates an internal hard reset sequence.
Bus monitor reset
When the MSC8122 bus monitor count reaches zero, a bus monitor hard reset is asserted. The
enabled bus monitor event then generates an internal hard reset sequence.
Host reset
command through
the TAP
When a host reset command is written through the Test Access Port (TAP), the TAP logic asserts the
soft reset signal and an internal soft reset sequence is generated.
Table 2-10 summarizes the reset actions that occur as a result of the different reset sources.
MSC8122 Technical Data, Rev. 4
2-6
Freescale Semiconductor
AC Timings
Table 2-10. Reset Actions for Each Reset Source
Power-On
Reset
(PORESET)
Hard Reset (HRESET)
Soft Reset (SRESET)
JTAG Command:
Reset Action/Reset Source
External or Internal
External only (Software Watchdog or
Bus Monitor)
External
EXTEST, CLAMP, or
HIGHZ
Configuration pins sampled (Refer to
Yes
No
No
No
Section 2.5.4.1 for details).
SPLL state reset
Yes
Yes
No
No
No
No
No
No
System reset configuration write through
the DSI
System reset configuration write though
the system bus
Yes
Yes
No
No
HRESET driven
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
SIU registers reset
IPBus modules reset (TDM, UART,
Timers, DSI, IPBus master, GIC, HS, and
GPIO)
Yes
Yes
SRESET driven
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Depends on command
SC140 extended cores reset
MQBS reset
Yes
Yes
2.5.4.1 Power-On Reset (PORESET) Pin
Asserting PORESET initiates the power-on reset flow. PORESET must be asserted externally for at least 16 CLKIN
cycles after external power to the MSC8122 reaches at least 2/3 V
.
DD
2.5.4.2 Reset Configuration
The MSC8122 has two mechanisms for writing the reset configuration:
• Through the direct slave interface (DSI)
• Through the system bus. When the reset configuration is written through the system bus, the MSC8122 acts as a
configuration master or a configuration slave. If configuration slave is selected, but no special configuration
word is written, a default configuration word is applied.
Fourteen signal levels (see Chapter 1 for signal description details) are sampled on PORESET deassertion to define
the Reset Configuration Mode and boot and operating conditions:
• RSTCONF
• CNFGS
• DSISYNC
• DSI64
• CHIP_ID[0–3]
• BM[0–2]
• SWTE
• MODCK[1–2]
MSC8122 Technical Data, Rev. 4
Freescale Semiconductor
2-7
Specifications
2.5.4.3 Reset Timing Tables
Table 2-11 and Figure 2-2 describe the reset timing for a reset configuration write through the direct slave
interface (DSI) or through the system bus.
Table 2-11. Timing for a Reset Configuration Write through the DSI or System Bus
No.
Characteristics
Expression
Min
Max
Unit
1
Required external PORESET duration minimum
16/CLKIN
•
•
CLKIN = 20 MHz
CLKIN = 166 MHz
800
96
—
—
ns
ns
2
3
Delay from deassertion of external PORESET to deassertion of internal
PORESET
1024/CLKIN
•
CLKIN = 20 MHz to 166 MHz
6.17
51.2
320
us
Delay from de-assertion of internal PORESET to SPLL lock
6400/(CLKIN/RDF)
(PLL reference clock-
division factor)
•
•
CLKIN = 20 MHz (RDF = 1)
CLKIN = 166 MHz (RDF = 2)
us
us
39
5
6
Delay from SPLL to HRESET deassertion
REFCLK = 40 MHz to166 MHz
•
512/REFCLK
515/REFCLK
3.08
3.10
12.8
us
Delay from SPLL lock to SRESET deassertion
•
•
REFCLK = 40 MHz
REFCLK = 166 MHz
us
us
12.88
Note:
Timings are not tested, but are guaranteed by design.
RSTCONF, CNFGS, DSISYNC, DSI64
CHIP_ID[0–3], BM[0–2], SWTE, MODCK[1–2]
pins are sampled
1
PORESET
Input
Host programs
Reset Configuration
Word
PORESET
Internal
SPLL is locked
(no external indication)
1 + 2
MODCK[3–5]
HRESET
Output (I/O)
3
2
SRESET
Output (I/O)
SPLL
locking period
5
6
Reset configuration write
sequence during this
period.
Figure 2-2. Timing Diagram for a Reset Configuration Write
MSC8122 Technical Data, Rev. 4
2-8
Freescale Semiconductor
AC Timings
2.5.5 System Bus Access Timing
2.5.5.1 Core Data Transfers
Generally, all MSC8122 bus and system output signals are driven from the rising edge of the reference clock
(REFCLK). The REFCLK is the CLKIN signal. Memory controller signals, however, trigger on four points within a
REFCLK cycle. Each cycle is divided by four internal ticks: T1, T2, T3, and T4. T1 always occurs at the rising
edge of REFCLK (and T3 at the falling edge), but the spacing of T2 and T4 depends on the PLL clock ratio
selected, as Table 2-12 shows.
Table 2-12. Tick Spacing for Memory Controller Signals
Tick Spacing (T1 Occurs at the Rising Edge of REFCLK)
BCLK/SC140 clock
T2
T3
T4
1:4, 1:6, 1:8, 1:10
1/4 REFCLK
1/6 REFCLK
2/10 REFCLK
1/2 REFCLK
1/2 REFCLK
1/2 REFCLK
3/4 REFCLK
4/6 REFCLK
7/10 REFCLK
1:3
1:5
Figure 2-3 is a graphical representation of Table 2-12.
REFCLK
for 1:4, 1:6, 1:8, 1:10
T1
T1
T1
T2
T3
T3
T3
T4
REFCLK
REFCLK
for 1:3
T2
T4
for 1:5
T2
T4
Figure 2-3. Internal Tick Spacing for Memory Controller Signals
The UPM machine and GPCM machine outputs change on the internal tick selected by the memory controller
configuration. The AC timing specifications are relative to the internal tick. SDRAM machine outputs change only
on the REFCLK rising edge.
Table 2-13. AC Timing for SIU Inputs
Value for Bus
Speed in MHz
No.
Characteristic
Units
133
166
10
11a
11b
11c
11d
12
Hold time for all signals after the 50% level of the REFCLK rising edge
ARTRY/ABB set-up time before the 50% level of the REFCLK rising edge
DBG/DBB/BG/BR/TC set-up time before the 50% level of the REFCLK rising edge
AACK set-up time before the 50% level of the REFCLK rising edge
TA/TEA/PSDVAL set-up time before the 50% level of the REFCLK rising edge
Data bus set-up time before REFCLK rising edge in Normal mode
0.5
3.0
3.2
2.8
3.8
0.5
3.0
3.2
2.8
3.8
ns
ns
ns
ns
ns
•
•
Data-pipeline mode
Non-pipeline mode
1.8
4.0
1.6
4.0
ns
ns
MSC8122 Technical Data, Rev. 4
Freescale Semiconductor
2-9
Specifications
Table 2-13. AC Timing for SIU Inputs (Continued)
Value for Bus
Speed in MHz
No.
Characteristic
Units
133
166
13
14
Data bus set-up time before the 50% level of the REFCLK rising edge in ECC and PARITY modes
•
•
Data-pipeline mode
Non-pipeline mode
2.0
5.0
2.0
5.0
ns
ns
DP set-up time before the 50% level of the REFCLK rising edge
•
•
Data-pipeline mode
Non-pipeline mode
2.0
4.7
2.0
4.7
ns
ns
15a
15b
TS and Address bus set-up time before the 50% level of the REFCLK rising edge
•
•
Extra cycle mode (SIUBCR[EXDD] = 0)
No extra cycle mode (SIUBCR[EXDD] = 1)
3.4
4.8
3.4
4.8
ns
ns
Address attributes: TT/TBST/TSZ/GBL set-up time before the 50% level of the REFCLK rising edge
•
•
Extra cycle mode (SIUBCR[EXDD] = 0)
No extra cycle mode (SIUBCR[EXDD] = 1)
3.5
4.2
3.5
4.2
ns
ns
161
PUPMWAIT signal set-up time before the 50% level of the REFCLK rising edge
3.7
3.7
ns
Note:
Values are measured from the 50% TTL transition level relative to the 50% level of the REFCLK rising edge.
Table 2-14. AC Timing for SIU Outputs
Value for Bus
Speed in MHz
No.
Characteristic
Units
133
166
302
31
Minimum delay from the 50% level of the REFCLK for all signals
PSDVAL/TEA/TA max delay from the 50% level of the REFCLK rising edge
Address bus max delay from the 50% level of the REFCLK rising edge
0.8
5.0
0.8
5.0
ns
ns
32a
•
•
Multi-master mode (SIUBCR[EBM] = 1)
Single-master mode (SIUBCR[EBM] = 0)
5.4
4.5
5.4
4.2
ns
ns
32b
Address attributes: TT[0–1]/TBST/TSZ/GBL max delay from the 50% level of the REFCLK rising
edge
5.3
5.3
ns
32c
32d
33a
Address attributes: TT[2–4]/TC max delay from the 50% level of the REFCLK rising edge
BADDR max delay from the 50% level of the REFCLK rising edge
5.7
4.3
5.7
4.3
ns
ns
Data bus max delay from the 50% level of the REFCLK rising edge
•
•
Data-pipeline mode
Non-pipeline mode
4.1
6.0
3.8
6.0
ns
ns
33b
DP max delay from the 50% level of the REFCLK rising edge
•
•
Data-pipeline mode
Non-pipeline mode
5.2
6.2
5.2
6.2
ns
ns
34
Memory controller signals/ALE/CS[0–4] max delay from the 50% level of the REFCLK rising edge
DBG/BG/BR/DBB max delay from the 50% level of the REFCLK rising edge
4.3
4.9
5.0
4.0
4.9
5.0
ns
ns
ns
35a
35b
AACK/ABB/TS/CS[5–7] max delay from the 50% level of the REFCLK rising edge
Notes: 1. Values are measured from the 50% level of the REFCLK rising edge to the 50% signal level and assume a 20 pF load except
where otherwise specified.
2. The load for specification 30 is 10 pF.
3. The maximum bus frequency depends on the mode:
• In 60x-compatible mode connected to another MSC8122 device, the frequency is determined by adding the input and output
longest timing values, which results in the total delay for 20 pF output capacitance. You must also account for other
influences that can affect timing, such as on-board clock skews, on-board noise delays, and so on.
• In single-master mode, the frequency depends on the timing of the devices connected to the MSC8122.
• To achieve maximum performance on the bus in single-master mode, disable the DBB signal by writing a 1 to the
SIUMCR[BDD] bit. See the SIU chapter in the MSC8122 Reference Manual for details.
MSC8122 Technical Data, Rev. 4
2-10
Freescale Semiconductor
AC Timings
REFCLK
10
11
AACK/ARTRY/TA/TEA/DBG/BG/BR
PSDVAL/ABB/DBB inputs
10
12
13
Data bus inputs—normal mode
10
10
Data bus inputs—ECC and parity modes
DP inputs
14
15
Address bus/TS /TT[0–4]/TC[0–2]/
TBST/TSZ[0–3]/GBL inputs
PUPMWAIT input
16
30
Min delay for all output pins
31
PSDVAL/TEA/TA outputs
Address bus/TT[0–4]/TC[0–2]/TBST/TSZ[0–3]/GBL outputs
BADDR outputs
32a/b
32c
33a
Data bus outputs
DP outputs
33b
34
Memory controller/ALE outputs
35
AACK/ABB/TS/DBG/BG/BR/DBB/CS outputs
Figure 2-4. Bus Signal Timing
MSC8122 Technical Data, Rev. 4
Freescale Semiconductor
2-11
Specifications
2.5.5.2 DMA Data Transfers
Table 2-15 describes the DMA signal timing.
Table 2-15. DMA Signals
No.
Characteristic
Min
Max
Units
37
38
39
40
41
DREQ set-up time before the 50% level of the falling edge of REFCLK
DREQ hold time after the 50% level of the falling edge of REFCLK
DONE set-up time before the 50% level of the rising edge of REFCLK
DONE hold time after the 50% level of the rising edge of REFCLK
DACK/DRACK/DONE delay after the 50% level of the REFCLK rising edge
5.0
0.5
5.0
0.5
0.5
—
—
ns
ns
ns
ns
ns
—
—
7.5
The DREQ signal is synchronized with REFCLK. To achieve fast response, a synchronized peripheral should assert
DREQ according to the timings in Table 2-15. Figure 2-5 shows synchronous peripheral interaction.
REFCLK
38
37
DREQ
40
39
DONE
41
DACK/DONE/DRACK
Figure 2-5. DMA Signals
MSC8122 Technical Data, Rev. 4
2-12
Freescale Semiconductor
AC Timings
2.5.6 DSI Timing
The timings in the following sections are based on a 20 pF capacitive load. See Section 2.5.1, AC Timings, on page
2-5 for details.
2.5.6.1 DSI Asynchronous Mode
Table 2-16. DSI Asynchronous Mode Timing
No.
Characteristics
Min
Max
Unit
100
101
102
Attributes1 set-up time before strobe (HWBS[n]) assertion
Attributes1 hold time after data strobe deassertion
Read/Write data strobe deassertion width:
1.5
1.3
—
—
—
ns
ns
•
DCR[HTAAD] = 1
— Consecutive access to the same DSI
— Different device with DCR[HTADT] = 01
— Different device with DCR[HTADT] = 10
— Different device with DCR[HTADT] = 11
DCR[HTAAD] = 0
1.8 + TREFCLK
5 + TREFCLK
5 + (1.5 × TREFCLK
5 + (2.5 × TREFCLK
1.8 + TREFCLK
ns
ns
ns
ns
ns
)
)
•
103
104
105
106
107
108
109
Read data strobe deassertion to output data high impedance
Read data strobe assertion to output data active from high impedance
Output data hold time after read data strobe deassertion
Read/Write data strobe assertion to HTA active from high impedance
Output data valid to HTA assertion
—
2.0
2.2
2.2
3.2
—
8.5
—
ns
ns
ns
ns
ns
ns
ns
—
—
—
Read/Write data strobe assertion to HTA valid2
6.5
6.5
Read/Write data strobe deassertion to output HTA high impedance.
(DCR[HTAAD] = 0, HTA at end of access released at logic 0)
—
110
111
Read/Write data strobe deassertion to output HTA deassertion.
(DCR[HTAAD] = 1, HTA at end of access released at logic 1)
—
—
6.5
ns
Read/Write data strobe deassertion to output HTA high impedance.
(DCR[HTAAD] = 1, HTA at end of access released at logic 1
•
•
•
DCR[HTADT] = 01
DCR[HTADT] = 10
DCR[HTADT] = 11
5 + TREFCLK
5 + (1.5 × TREFCLK
5 + (2.5 × TREFCLK
ns
ns
ns
)
)
112
201
202
Read/Write data strobe assertion width
1.8 + TREFCLK
—
—
—
ns
ns
ns
Host data input set-up time before write data strobe deassertion
Host data input hold time after write data strobe deassertion
1.0
2.0
Notes: 1. Attributes refers to the following signals: HCS, HA[11–29], HCID[0–4], HDST, HRW, HRDS, and HWBSn.
2. This specification is tested in dual-strobe mode. Timing in single-strobe mode is guaranteed by design.
3. All values listed in this table are tested or guaranteed by design.
MSC8122 Technical Data, Rev. 4
Freescale Semiconductor
2-13
Specifications
Figure 2-6 shows DSI asynchronous read signals timing.
HCS
HA[11–29]
HCID[0–4]
HDST
HRW1
HWBSn2
100
101
112
HDBSn1
HRDS2
102
103
107
105
104
HD[0–63]
109
106
HTA3
108
110
HTA4
111
Notes: 1. Used for single-strobe mode access.
2. Used for dual-strobe mode access.
3. HTA released at logic 0 (DCR[HTAAD] = 0) at end of access; used with pull-
down implementation.
4. HTA released at logic 1 (DCR[HTAAD] = 1) at end of access; used with pull-up
implementation.
Figure 2-6. Asynchronous Single- and Dual-Strobe Modes Read Timing Diagram
MSC8122 Technical Data, Rev. 4
2-14
Freescale Semiconductor
AC Timings
Figure 2-7 shows DSI asynchronous write signals timing.
HCS
HA[11–29]
HCID[0–4]
HDST
HRW1
100
101
102
HRDS2
112
HDBSn1
HWBSn2
201
202
HD[0–63]
HTA3
109
106
108
110
HTA4
111
Notes: 1. Used for single-strobe mode access.
2. Used for dual-strobe mode access.
3. HTA released at logic 0 (DCR[HTAAD] = 0) at end of access; used with pull-down implementation.
4. HTA released at logic 1 (DCR[HTAAD] = 1) at end of access; used with pull-up implementation.
Figure 2-7. Asynchronous Single- and Dual-Strobe Modes Write Timing Diagram
Figure 2-8 shows DSI asynchronous broadcast write signals timing.
HCS
HA[11–29]
HCID[0–4]
HDST
HRW1
101
100
HRDS2
112
HDBSn1
HWBSn2
102
201
202
HD[0–63]
Notes: 1. Used for single-strobe mode access.
2. Used for dual-strobe mode access.
Figure 2-8. Asynchronous Broadcast Write Timing Diagram
MSC8122 Technical Data, Rev. 4
Freescale Semiconductor
2-15
Specifications
2.5.6.2 DSI Synchronous Mode
Table 2-17. DSI Inputs in Synchronous Mode
No.
Characteristic
HCLKIN cycle time1,2
Expression
Min
Max
Units
120
121
122
123
124
125
126
127
HTC
10.0
4.0
4.0
1.2
0.6
1.8
1.4
1.5
55.6
33.3
33.3
—
ns
ns
ns
ns
ns
ns
ns
ns
HCLKIN high pulse width
HCLKIN low pulse width
HA[11–29] inputs set-up time
HD[0–63] inputs set-up time
HCID[0–4] inputs set-up time
All other inputs set-up time
All inputs hold time
(0.5 0.1) × HTC
(0.5 0.1) × HTC
—
—
—
—
—
—
—
—
—
Notes: 1. Values are based on a frequency range of 18–100 MHz.
2. Refer to Table 2-6 for HCLKIN frequency limits.
Table 2-18. DSI Outputs in Synchronous Mode
No.
Characteristic
Min
Max
Units
128
129
130
131
132
133
134
135
HCLKIN high to HD[0–63] output active
2.0
—
—
6.5
—
ns
ns
ns
ns
ns
ns
ns
ns
HCLKIN high to HD[0–63] output valid
HD[0–63] output hold time
1.7
—
HCLKIN high to HD[0–63] output high impedance
HCLKIN high to HTA output active
HCLKIN high to HTA output valid
HTA output hold time
8.0
—
1.8
—
6.3
—
1.7
—
HCLKIN high to HTA high impedance
6.0
120
122
121
127
HCLKIN
123
HA[11–29] input signals
127
127
124
HD[0–63] input signals
125
HCID[0–4] input signals
127
126
All other input signals
131
130
129
128
HD[0–63] output signals
135
134
133
132
HTA output signal
Figure 2-9. DSI Synchronous Mode Signals Timing Diagram
MSC8122 Technical Data, Rev. 4
2-16
Freescale Semiconductor
AC Timings
2.5.7 TDM Timing
Table 2-19. TDM Timing
No.
Characteristic
Expression
Min
Max
Units
300
301
302
303
304
305
306
307
308
TDMxRCLK/TDMxTCLK
TC1
16
7
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
TDMxRCLK/TDMxTCLK high pulse width
TDMxRCLK/TDMxTCLK low pulse width
TDM receive all input set-up time
TDM receive all input hold time
TDMxTCLK high to TDMxTDAT/TDMxRCLK output active2,3
TDMxTCLK high to TDMxTDAT/TDMxRCLK output valid2,3
All output hold time2
(0.5 0.1) × TC
(0.5 0.1) × TC
7
—
1.5
1.0
2.8
—
2.7
—
—
—
—
8.5
—
TDMxTCLK high to TDmXTDAT/TDMxRCLK output high
impedance2,3
10.5
309
310
TDMxTCLK high to TDMXTSYN output valid2
TDMxTSYN output hold time2
—
8.3
—
ns
ns
2.7
Notes: 1. Values are based on a a maximum frequency of 62.5 MHz. The TDM interface supports any frequency below 62.5 MHz.
2. Values are based on 20 pF capacitive load.
3. When configured as an output, TDMxRCLK acts as a second data link. See the MSC8122 Reference Manual for details.
300
302
301
304
TDMxRCLK
TDMxRDAT
303
304
303
TDMxRSYN
Figure 2-10. TDM Inputs Signals
300
302
301
TDMxTCLK
308
307
306
305
TDMxTDAT
TDMxRCLK
309
310
TDMxTSYN
Figure 2-11. TDM Output Signals
MSC8122 Technical Data, Rev. 4
Freescale Semiconductor
2-17
Specifications
2.5.8 UART Timing
Table 2-20. UART Timing
No.
Characteristics
Expression
Min
Max Unit
400
401
402
URXD and UTXD inputs high/low duration
URXD and UTXD inputs rise/fall time
UTXD output rise/fall time
16 × TREFCLK
160.0
—
10
10
ns
ns
ns
401
401
UTXD, URXD
inputs
400
400
Figure 2-12. UART Input Timing
402
402
UTXD output
Figure 2-13. UART Output Timing
MSC8122 Technical Data, Rev. 4
2-18
Freescale Semiconductor
AC Timings
2.5.9 Timer Timing
Table 2-21. Timer Timing
No.
Characteristics
Min
Max
Unit
500
501
502
503
TIMERx frequency
10.0
4.0
—
—
ns
ns
ns
ns
TIMERx Input high period
TIMERx Output low period
4.0
—
TIMERx Propagations delay from its clock input
3.1
8.0
500
501
502
TIMERx (Input)
503
TIMERx (Output)
Figure 2-14. Timer Timing
MSC8122 Technical Data, Rev. 4
Freescale Semiconductor
2-19
Specifications
2.5.10 Ethernet Timing
2.5.10.1 Management Interface Timing
Table 2-22. Ethernet Controller Management Interface Timing
No.
Characteristics
ETHMDIO to ETHMDC rising edge set-up time
ETHMDC rising edge to ETHMDIO hold time
Min
Max
Unit
801
802
10
10
—
—
ns
ns
ETHMDC
801
802
Valid
ETHMDIO
Figure 2-15. MDIO Timing Relationship to MDC
2.5.10.2 MII Mode Timing
Table 2-23. MII Mode Signal Timing
No.
Characteristics
Min
Max
Unit
803
804
805
ETHRX_DV, ETHRXD[0–3], ETHRX_ER to ETHRX_CLK rising edge set-up time
5
5
1
—
—
15
ns
ns
ns
ETHRX_CLK rising edge to ETHRX_DV, ETHRXD[0–3], ETHRX_ER hold time
ETHTX_CLK to ETHTX_EN, ETHTXD[0–3], ETHTX_ER output delay
ETHRX_CLK
803
804
ETHRX_DV
ETHRXD[0–3]
ETHRX_ER
Valid
ETHTX_CLK
805
ETHTX_EN
Valid
Valid
ETHTXD[0–3]
ETHTX_ER
Figure 2-16. MII Mode Signal Timing
MSC8122 Technical Data, Rev. 4
2-20
Freescale Semiconductor
AC Timings
2.5.10.3 RMII Mode
Table 2-24. RMII Mode Signal Timing
No.
Characteristics
Min
Max
Unit
806
807
811
ETHTX_EN,ETHRXD[0–1], ETHCRS_DV, ETHRX_ER to ETHREF_CLK rising edge set-up time
ETHREF_CLK rising edge to ETHRXD[0–1], ETHCRS_DV, ETHRX_ER hold time
ETHREF_CLK rising edge to ETHTXD[0–1], ETHTX_EN output delay.
3
2
3
—
—
11
ns
ns
ns
ETHREF_CLK
806
807
ETHCRS_DV
ETHRXD[0–1]
ETHRX_ER
Valid
811
ETHTX_EN
ETHTXD[0–1]
Valid
Valid
Figure 2-17. RMII Mode Signal Timing
2.5.10.4 SMII Mode
Table 2-25. SMII Mode Signal Timing
No.
Characteristics
Min
Max
Unit
808
809
810
ETHSYNC_IN, ETHRXD to ETHCLOCK rising edge set-up time
ETHCLOCK rising edge to ETHSYNC_IN, ETHRXD hold time
ETHCLOCK rising edge to ETHSYNC, ETHTXD output delay
1.5
1
—
—
ns
ns
ns
1.51
5.52
Notes: 1. Measured using a 5 pF load.
2. Measured using a 15 pF load.
ETHCLOCK
808
809
ETHSYNC_IN
ETHRXD
Valid
810
ETHSYNC
ETHTXD
Valid
Valid
Figure 2-18. SMII Mode Signal Timing
MSC8122 Technical Data, Rev. 4
Freescale Semiconductor
2-21
Specifications
2.5.11 GPIO Timing
Table 2-26. GPIO Timing
No.
Characteristics
Min
Max
Unit
601
602
603
604
605
REFCLK edge to GPIO out valid (GPIO out delay time)
REFCLK edge to GPIO out not valid (GPIO out hold time)
—
1.15
—
6.5
—
ns
ns
ns
ns
ns
REFCLK edge to high impedance on GPIO out
GPIO in valid to REFCLK edge (GPIO in set-up time)
REFCLK edge to GPIO in not valid (GPIO in hold time)
5.4
—
3.7
0.5
—
REFCLK
601
603
602
GPIO
(Output)
High Impedance
604
605
GPIO
(Input)
Valid
Figure 2-19. GPIO Timing
2.5.12 EE Signals
Table 2-27. EE Pin Timing
Number
Characteristics
Type
Min
65
66
EE0 (input)
Asynchronous
4 core clock periods
1 core clock period
EE1 (output)
Synchronous to Core clock
Notes: 1. The core clock is the SC140 core clock. The ratio between the core clock and CLKOUT is configured during power-on-reset.
2. Refer to Table 1-4 on page 1-6 for details on EE pin functionality.
Figure 2-20 shows the signal behavior of the EE pins.
65
EE0 in
66
EE1 out
Figure 2-20. EE Pin Timing
MSC8122 Technical Data, Rev. 4
2-22
Freescale Semiconductor
AC Timings
2.5.13 JTAG Signals
Table 2-28. JTAG Timing
All
frequencies
No.
Characteristics
Unit
Min
Max
700
701
702
TCK frequency of operation (1/(TC × 4); maximum 25 MHz)
TCK cycle time
TCK clock pulse width measured at VM = 1.6 V
0.0
25
—
MHz
ns
40.0
•
•
High
Low
20.0
15.0
—
—
ns
ns
703
704
705
706
707
708
709
710
711
712
713
Note:
TCK rise and fall times
0.0
5.0
3.0
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Boundary scan input data set-up time
Boundary scan input data hold time
TCK low to output data valid
TCK low to output high impedance
TMS, TDI data set-up time
TMS, TDI data hold time
20.0
0.0
—
30.0
30.0
—
0.0
5.0
20.0
0.0
—
TCK low to TDO data valid
TCK low to TDO high impedance
TRST assert time
20.0
20.0
—
0.0
100.0
30.0
TRST set-up time to TCK low
—
All timings apply to OnCE module data transfers as the OnCE module uses the JTAG port as an interface.
701
702
VM
VM
VIH
TCK
(Input)
VIL
703
703
Figure 2-21. Test Clock Input Timing Diagram
MSC8122 Technical Data, Rev. 4
Freescale Semiconductor
2-23
Specifications
VIH
TCK
(Input)
VIL
704
705
Data
Inputs
Input Data Valid
706
707
Data
Outputs
Output Data Valid
Data
Outputs
Figure 2-22. Boundary Scan (JTAG) Timing Diagram
VIH
TCK
(Input)
VIL
709
708
Input Data Valid
TDI
TMS
(Input)
710
TDO
(Output)
Output Data Valid
711
TDO
(Output)
Figure 2-23. Test Access Port Timing Diagram
TCK
(Input)
713
TRST
(Input)
712
Figure 2-24. TRST Timing Diagram
MSC8122 Technical Data, Rev. 4
2-24
Freescale Semiconductor
Packaging
3
This section provides information on the MSC8122 package, including diagrams of the package pinouts and tables
showing how the signals discussed in Chapter 1 are allocated. The MSC8122 is available in a 431-pin flip chip-
plastic ball grid array (FC-PBGA).
3.1 Package Description
Figure 3-1 and Figure 3-2 show top and bottom views of the package, including pinouts. To conform to JEDEC
requirements, the package is based on a 23 × 23 position (20 × 20 mm) layout with the outside perimeter
depopulated. Therefore, ball position numbering starts with B2. Signal names shown in the figures are typically the
signal assigned after reset. Signals that are only used during power-on reset (SWTE, DSISYNC, DSI64, MODCK[1–2],
CNFGS, and CHIP_ID[0–3]) are not shown in these figures if there is another signal assigned to the pin after reset.
Also, there are several signals that are designated as IRQ lines immediately after reset, but represent duplicate IRQ
lines that should be reconfigured by the user. To represent these signals uniquely in the figures, the second
functions (BADDR[29–31], DP[1–7], and INT_OUT) are used.
Table 3-1 lists the MSC8122 signals alphabetically by signal name. Connections with multiple names are listed
individually by each name. Signals with programmable polarity are shown both as signals which are asserted low
(default) and high (that is, NAME/NAME). Table 3-2 lists the signals numerically by pin number. Each pin number is
listed once with the various signals that are multiplexed to it. For simplicity, signals with programmable polarity
are shown in this table only with their default name (asserted low).
Note: For Ethernet signals multiplexed with the DSI/system Bus (MII and RMII modes only), signals not used by
the RMII mode are reserved when the Ethernet controller is multiplexed with the DSI/system bus and
RMII mode is selected. These reserved signals can be left unconnected. These RMII reserved signals are
not included in Table 3-1, but are indicated in Table 3-2.
Note: For Ethernet signals multiplexed with the GPIO/TDM signals, signals not used by the RMII or SMII mode
can be assigned to their alternate GPIO or dedicated function, except for GPIO10 and GPIO14. If the
Ethernet controller is enabled and multiplexed with the GPIO signals and SMII mode is selected, GPIO10
and GPIO14 (E21 and F21, respectively) must be left unconnected. These signals are designated as NC (no
connect) in Table 3-1 and Table 3-2.
MSC8122 Technical Data, Rev. 4
Freescale Semiconductor
3-1
Packaging
Top View
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
NMI_
OUT
V
V
V
V
V
V
V
V
V
B
C
D
GND
GND
GND
GND
GND
GND
GND
GND
GPIO0
GND
DD
DD
DD
DD
DD
DD
DD
DD
DD
S
V
V
V
V
GND
TDI
TDO
EE1
GPIO28 HCID1 GND
GND
GND
GND
GND GPIO30 GPIO2 GPIO1 GPIO7 GPIO3 GPIO5 GPIO6
DD
DD
DD
DD
RESET
V
V
V
V
V
V
V
DDH
EE0
GND
HCID2 HCID3 GND
GND
GND
GPIO31 GPIO29
GPIO4
GND GPIO8
DDH
DD
DD
DD
DD
DDH
V
V
V
V
V
V
V
V
DD
TCK
PO
TRST
RST
TMS HRESET GPIO27 HCID0 GND
GND
GND
GND
GND
GND
GND GPIO9 GPIO13 GPIO10 GPIO12
DD
DD
DD
DD
DD
DD
DD
E
F
ETHRX_ ETHTX_
V
V
V
V
NMI
HA29
HA23
HA19
HA13
HA22
GND
GND
BM0
GND
GPIO20 GPIO18 GPIO16 GPIO11 GPIO14 GPIO19
DD
DD
DD
DD
DD
RESET CONF
CLK
CLK
BADDR
31
INT_ ETHCR
OUT
V
V
V
G
H
J
HA24
HA20
HA18
HA15
HA12
HD28
HD26
HD20
HD18
HD17
HD16
HD3
HA27
HA28
HA26
HA21
HA14
HD31
HD30
HD27
HA25
HA17 PWE0
ABB
CS1
BCTL0 GPIO15 GND GPIO17 GPIO22
DD
DD
S
PSD
TEST
V
V
V
V
DDH
PGTA
BM1 ARTRY AACK
DBB
HTA
TT4
CS4 GPIO24 GPIO21
A31
DD
DD
DD
DD
DD
CAS
PSDA BADDR
V
V
V
V
GND
CLKIN
GND
GND
GND
GND
BM2
GND
DBG
GND
GND
TT3 PSDA10 BCTL1 GPIO23 GND GPIO25 A30
DD
DD
MUX
27
BADDR
30
K
HA16 PWE3 PWE1
POE
Res.
GND
GND CLKOUT
GND
TT2
ALE
CS2
CS3
GND
A26
A27
A29
A25
A24
A28
A22
A21
A20
A19
A16
A14
A13
A11
A6
BADDR BADDR
V
V
V
V
V
L
HA11
GND
GND
DDH
DDH
DDH
DDH
DDH
28
29
HB
RST
V
V
V
V
V
V
DDH
M
N
P
GND
GND
GND
GND
GND
DDH
DD
DDH
DDH
DDH
HWBS
0
V
HD29
HD25
GND
HD1
HD24 PWE2
HBCS
GND
HRDS
TA
BG
BR
HCS
TEA
DP3
DP4
D26
D27
CS0 PSDWE GPIO26 A23
PSD
DDH
HWBS HWBS HWBS
GND
V
V
V
DDH
HD23
HD22
HD0
D2
HCLKIN GND
GND
GND
TT0
DP0
DP2
D30
GND
A18
A15
A12
A10
A7
SYN CCSYN
3
2
1
VAL
HWBS HWBS
V
V
V
R
T
TSZ1
TSZ3
TSZ2
D9
GBL
TBST
D11
DP7
D23
D22
GND
DP6
DP5
D25
D24
HD33
TS
A17
DDH
DD
DD
D16
D15
D13
DD
6
4
HWBS HWBS
V
HD21
HD19
TSZ0
D8
TT1
D17
D18
GND
D21
DP1
D28
GND
DD
7
5
V
U
V
HD2
D3
D6
D14
D12
D19
D31
DDH
V
GND
HD4
D0
D1
D4
D5
D7
D10
D20
D29
A8
A9
DDH
V
V
V
V
V
W
Y
HD6
HD5
HD15
HD14
HD13
GND
HD9
HD10
HD8
GND
GND HDST1 HDST0
HD40
HD43
HD32
HD37
HD38
HD41
GND
HD34
HD35
HD39
GND
DDH
HD60
HD59
HD61
DDH
DDH
DDH
DDH
V
V
V
V
V
V
HD7
HD58
GND
HD57
GND
HD51
HD52
HD53
GND
GND
HD46
HD47
GND
HD42
HD44
A4
A5
DDH
DD
DDH
DDH
DDH
DDH
V
V
V
V
AA
HD12
HD11
HD63
HD62
HD54
HD55
GND
GND
A0
A2
A3
DD
DDH
DDH
DDH
V
AB GND
HD56
HD50
HD49
HD48
HD45
HD36
A1
DD
Figure 3-1. MSC8122 Package, Top View
MSC8122 Technical Data, Rev. 4
3-2
Freescale Semiconductor
Package Description
Bottom View
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
NMI_
OUT
V
V
V
V
V
V
V
V
V
B
C
D
GND
GPIO0
GND
GND
GND
GND
GND
GND
GND
GND
DD
DD
DD
DD
DD
DD
DD
DD
DD
S
V
V
V
V
GPIO6 GPIO5 GPIO3 GPIO7 GPIO1 GPIO2 GPIO30 GND
GND
GND
GND
GND HCID1 GPIO28
TDO
EE1
GND
TDI
DD
DD
DD
DD
RESET
V
V
V
V
V
V
V
DDH
GPIO8 GND
GPIO4
GPIO29 GPIO31
GND
GND
GND HCID3 HCID2
GND
EE0
DDH
DDH
DD
DD
DD
DD
V
V
V
V
V
V
V
V
GPIO12 GPIO10 GPIO13 GPIO9 GND
GND
GND
GND
GND
GND
GND HCID0 GPIO27 HRESET TMS
TRST
RST
TCK
PO
DD
DD
DD
DD
DD
DD
DD
DD
E
F
ETHTX_ ETHRX_
CLK
V
V
V
V
GPIO19 GPIO14 GPIO11 GPIO16 GPIO18 GPIO20
GND
GND
BM0
GND
HA22
HA29
HA23
HA19
HA13
NMI
DD
DD
DD
DD
DD
CLK
CONF RESET
ETHCR INT_
S
BADDR
31
V
V
V
G
H
GPIO22 GPIO17 GND GPIO15 BCTL0
CS1
ABB
PWE0 HA17
HA25
HA27
HA28
HA26
HA21
HA14
HD31
HD30
HD27
HA24
HA20
HA18
HA15
HA12
HD28
HD26
HD20
HD18
HD17
HD16
HD3
DD
DD
OUT
PSD
TEST
CAS
V
V
V
V
A31
GPIO21 GPIO24 CS4
TT4
HTA
DBB
AACK ARTRY BM1
PGTA
DDH
DD
DD
DD
DD
DD
BADDR PSDA
27
V
V
V
V
J
A30 GPIO25 GND GPIO23 BCTL1 PSDA10 TT3
GND
DBG
GND
BM2
GND
CLKIN
GND
GND
GND
GND
GND
DD
DD
MUX
BADDR
30
K
A28
A22
A21
A20
A19
A16
A14
A13
A11
A6
A29
A25
A24
A26
A27
GND
CS2
CS3
ALE
TT2
CLKOUT GND
GND
Res.
GND
POE
PWE1 PWE3 HA16
BADDR BADDR
V
V
V
V
V
DDH
L
GND
GND
HA11
DDH
DDH
DDH
DDH
29
28
HB
RST
V
V
V
V
V
V
M
N
GND
GND
GND
GND
GND
DDH
DDH
DDH
DDH
DD
DDH
HWBS
0
V
A23 GPIO26 PSDWE CS0
PSD
HCS
TEA
DP3
DP4
D26
D27
BG
BR
HRDS
TA
GND
HBCS
PWE2 HD24
HD29
HD25
GND
HD1
DDH
HWBS HWBS HWBS
1
V
V
GND
P
GND
A18
A15
A12
A10
A7
DP0
DP2
D30
GND
TT0
GND
GND HCLKIN
HD23
HD22
HD0
D2
DDH
CCSYN SYN
VAL
2
3
HWBS HWBS
V
V
V
V
V
R
A17
TS
DP6
DP5
D25
D24
HD33
DP7
D23
D22
GND
GBL
TBST
D11
TSZ3
TSZ2
D9
TSZ1
DD
DD
DD
DDH
4
6
HWBS HWBS
T
GND
DP1
D28
D21
TT1
D17
D18
GND
D16
D15
D13
TSZ0
D8
HD21
HD19
DD
5
7
V
U
D31
D19
D14
D12
D6
D3
HD2
DDH
V
V
A9
A8
D29
D20
D10
D7
D5
D4
D1
D0
GND
HD4
DDH
V
V
V
V
V
W
Y
GND
GND
HD34
HD35
HD39
HD32
HD37
HD38
HD41
HD40
HD43
HDST0 HDST1 GND
GND
GND
HD9
HD10
HD8
HD5
HD6
DDH
DDH
DDH
DDH
DDH
HD60
HD59
HD61
V
V
V
V
V
V
A5
A4
GND
HD42
HD44
GND
HD46
HD47
GND
HD51
HD52
HD53
GND
HD58
GND
HD15
HD14
HD13
HD7
DDH
DDH
DDH
DDH
DD
DDH
V
V
V
V
AA
AB
A3
A2
A0
GND
GND
HD54
HD55
HD63
HD62
HD12
HD11
DDH
DDH
DDH
DD
V
A1
HD36
HD45
HD48
HD49
HD50
HD56
HD57
GND
DD
Figure 3-2. MSC8122 Package, Bottom View
MSC8122 Technical Data, Rev. 4
Freescale Semiconductor
3-3
Packaging
Table 3-1. MSC8122 Signal Listing By Name
Location
Designator
Location
Designator
Signal Name
Signal Name
A0
A1
AA20
AB21
AA21
AA22
Y21
Y22
W22
W21
V19
V20
V21
V22
U21
U22
T22
T21
R22
R20
R21
P22
N22
M22
L22
BADDR27
BADDR28
BADDR29
BADDR30
BADDR31
BCTL0
BCTL1
BG
J8
L7
A2
L8
A3
K8
A4
G10
G18
J18
N16
G11
H10
J11
G11
H10
J11
P16
B19
C18
C17
D17
J10
K14
W3
N18
G17
K18
L18
H17
K16
J18
J16
H16
V5
A5
A6
A7
A8
BNKSEL0
BNKSEL1
BNKSEL2
BM0
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
AACK
ABB
ALE
ARTRY
BM1
BM2
BR
CHIP_ID0
CHIP_ID1
CHIP_ID2
CHIP_ID3
CLKIN
CLKOUT
CNFGS
CS0
N21
M21
L21
CS1
CS2
CS3
K20
L20
CS4
CS5
K22
K21
J22
CS5
CS6
CS7
H22
H12
G12
K17
H11
D0
D1
V6
D2
U5
D3
U6
D4
V7
MSC8122 Technical Data, Rev. 4
3-4
Freescale Semiconductor
Package Description
Table 3-1. MSC8122 Signal Listing By Name (Continued)
Location
Designator
Location
Designator
Signal Name
Signal Name
D5
V8
U7
D41
D42
AB18
AA17
Y14
D6
D7
V9
D43
D8
U8
D44
AB17
AB16
AA15
AB15
AB14
AB13
AB12
Y11
D9
U9
D45
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
D33
D34
D35
D36
D37
D38
D39
D40
V10
U10
V11
V12
U11
U12
T12
U13
V13
U14
V14
T14
U15
T15
V16
U16
U17
V17
U18
V18
T19
U19
W18
W16
Y19
AA19
AB20
Y18
AA18
AB19
W14
D46
D47
D48
D49
D50
D51
D52
AA11
AB11
AA10
AB10
AB9
AB8
Y8
D53
D54
D55
D56
D57
D58
D59
AA7
Y7
D60
D61
AB7
AB6
AA6
G21
T18
D62
D63
DACK1
DACK1
DACK2
DACK2
DACK3
DACK4
DBB
DBG
DONE1
DONE2
DP0
F22
R19
T17
T16
H13
J12
F19
G22
P19
DP1
T18
DP2
R19
MSC8122 Technical Data, Rev. 4
Freescale Semiconductor
3-5
Packaging
Table 3-1. MSC8122 Signal Listing By Name (Continued)
Location
Designator
Location
Designator
Signal Name
Signal Name
DP3
DP4
R17
T17
T16
R16
R15
F19
G22
E6
ETHRXD0
ETHRXD0
ETHRXD1
ETHRXD1
ETHRXD2
ETHRXD2
ETHRXD3
ETHRXD3
ETHSYNC
ETHSYNC_IN
ETHTX_CLK
ETHTX_EN
ETHTX_EN
ETHTX_ER
ETHTX_ER
ETHTXD
ETHTXD0
ETHTXD0
ETHTXD1
ETHTXD1
ETHTXD2
ETHTXD2
ETHTXD3
ETHTXD3
EXT_BG2
EXT_BG3
EXT_BR2
EXT_BR3
EXT_DBG2
EXT_DBG3
GBL
F21
W14
E22
AB18
C22
AA17
C21
Y14
E22
F15
F16
D17
AA10
D19
AB10
F20
B19
AA15
C18
AB15
C20
AB14
C19
AB13
T18
T16
P19
R17
R19
T17
R10
B4
DP5
DP6
DP7
DRACK1
DRACK2
DREQ1
DREQ1
G19
P19
C6
DREQ1
DREQ2
DREQ2
F18
R17
R16
R15
U4
DREQ2
DREQ3
DREQ4
DSI64
DSISYNC
EE0
T4
D3
EE1
D4
ETHCLOCK
ETHCOL
ETHCOL
ETHCRS
ETHCRS_DV
ETHCRS_DV
ETHMDC
ETHMDC
ETHMDIO
ETHMDIO
ETHREF_CLK
ETHRX_CLK
ETHRX_DV
ETHRX_DV
ETHRX_ER
ETHRX_ER
ETHRXD
F16
D22
Y7
G15
E21
AB9
E20
Y8
E19
AA7
F16
F15
E21
AB9
F20
AB8
G15
GND
GND
B5
GND
B7
GND
B9
GND
B11
MSC8122 Technical Data, Rev. 4
3-6
Freescale Semiconductor
Package Description
Table 3-1. MSC8122 Signal Listing By Name (Continued)
Location
Designator
Location
Designator
Signal Name
Signal Name
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
B13
B15
B17
B22
C2
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GNDSYN
GPIO0
GPIO1
L14
L16
L17
M5
M6
C8
M7
C10
C12
C14
C15
D5
M10
M14
M19
N10
N14
P10
P13
P14
P21
R4
D9
D11
D13
D21
E8
E10
E12
E14
E15
E17
E18
F7
T20
V4
V15
W5
W6
W9
W13
W19
W20
Y9
F11
F13
G20
J6
Y12
Y15
Y17
AA8
AA13
AA16
AB2
P11
B19
C18
J14
J20
K10
K11
K12
K13
K19
L9
L10
MSC8122 Technical Data, Rev. 4
Freescale Semiconductor
3-7
Packaging
Table 3-1. MSC8122 Signal Listing By Name (Continued)
Location
Designator
Location
Designator
Signal Name
Signal Name
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21
GPIO22
GPIO23
GPIO24
GPIO25
GPIO26
GPIO27
GPIO28
GPIO29
GPIO30
GPIO31
HA7
C17
C20
D19
C21
C22
C19
D22
E19
E21
F20
E22
E20
F21
G19
F19
G21
F18
F22
F17
H19
G22
J19
H18
J21
N20
E6
HA13
HA14
HA15
HA16
HA17
HA18
HA19
HA20
HA21
HA22
HA23
HA24
HA25
HA26
HA27
HA28
HA29
HBCS
HBRST
HCID0
HCID1
HCID2
HCID3
HCLKIN
HCS
J5
L3
K2
K4
G6
J2
H5
H2
K3
F6
G5
G2
G4
J3
G3
H3
F5
N9
M16
E7
C7
D7
D8
P9
N17
T5
HD0
C6
HD1
T4
D17
C16
D16
R14
D8
HD2
U4
V2
W4
W3
W2
Y2
AB5
Y5
AA5
HD3
HD4
HD5
HA8
HD6
HA9
W11
W10
L4
HD7
HA10
HD8
HA11
HD9
HA12
L2
HD10
MSC8122 Technical Data, Rev. 4
3-8
Freescale Semiconductor
Package Description
Table 3-1. MSC8122 Signal Listing By Name (Continued)
Location
Designator
Location
Designator
Signal Name
Signal Name
HD11
HD12
HD13
HD14
HD15
HD16
HD17
HD18
HD19
HD20
HD21
HD22
HD23
HD24
HD25
HD26
HD27
HD28
HD29
HD30
HD31
HD32
HD33
HD34
HD35
HD36
HD37
HD38
HD39
HD40
HD41
HD42
HD43
HD44
HD45
HD46
AB4
AA4
AB3
AA3
Y3
HD47
HD48
AB15
AB14
AB13
AB12
Y11
AA11
AB11
AA10
AB10
AB9
AB8
Y8
HD49
HD50
HD51
U2
HD52
T2
HD53
R2
HD54
U3
HD55
P2
HD56
T3
HD57
R5
HD58
P5
HD59
AA7
Y7
N5
HD60
P4
HD61
AB7
AB6
AA6
N8
N2
HD62
P3
HD63
M2
HDBE0
HDBE1
HDBE2
HDBE3
HDBE4
HDBE5
HDBE6
HDBE7
HDBS0
HDBS1
HDBS2
HDBS3
HDBS4
HDBS5
HDBS6
HDBS7
HDST0
HDST1
HRDE
N4
P8
N3
P7
M3
P6
W18
W16
Y19
AA19
AB20
Y18
AA18
AB19
W14
AB18
AA17
Y14
AB17
AB16
AA15
R7
T7
R6
T6
N8
P8
P7
P6
R7
T7
R6
T6
W11
W10
N15
MSC8122 Technical Data, Rev. 4
Freescale Semiconductor
3-9
Packaging
Table 3-1. MSC8122 Signal Listing By Name (Continued)
Location
Designator
Location
Designator
Signal Name
Signal Name
HRDS
HRESET
HRW
N15
E5
IRQ5
IRQ5
H13
L8
N15
H14
N8
IRQ5
T16
C17
D22
R16
E19
G14
R15
E21
F20
E22
E20
F21
J19
H18
J21
V2
HTA
IRQ6
HWBE0
HWBE1
HWBE2
HWBE3
HWBE4
HWBE5
HWBE6
HWBE7
HWBS0
HWBS1
HWBS2
HWBS3
HWBS4
HWBS5
HWBS6
HWBS7
INT_OUT
IRQ1
IRQ6
P8
IRQ6
P7
IRQ7
P6
IRQ7
R7
IRQ7
T7
IRQ8
R6
IRQ9
T6
IRQ10
IRQ11
IRQ12
IRQ13
IRQ14
IRQ15
MODCK1
MODCK2
NC
N8
P8
P7
P6
R7
T7
R6
W4
E21
F21
F4
T6
G14
C20
R10
T18
D19
K8
NC
NMI
IRQ1
NMI_OUT
PBS0
PBS1
PBS2
PBS3
PBS4
PBS5
PBS6
PBS7
PGPL0
PGPL1
PGPL2
PGPL3
PGPL4
B6
IRQ1
G7
IRQ2
K6
IRQ2
N6
IRQ2
R19
C21
G10
R17
B19
C22
G12
T17
C18
C19
K5
IRQ3
R7
IRQ3
T7
IRQ3
R6
IRQ4
T6
IRQ4
J17
N19
K7
IRQ4
IRQ4
IRQ5
H7
IRQ5
H8
MSC8122 Technical Data, Rev. 4
3-10
Freescale Semiconductor
Package Description
Table 3-1. MSC8122 Signal Listing By Name (Continued)
Location
Designator
Location
Designator
Signal Name
Signal Name
PGPL5
PGTA
J7
H8
K7
TC0
G11
H10
J11
E2
TC1
POE
TC2
PORESET
PPBS
F2
TCK
H8
J17
J7
TDI
D2
PSDA10
PSDAMUX
PSDCAS
PSDDQM0
PSDDQM1
PSDDQM2
PSDDQM3
PSDDQM4
PSDDQM5
PSDDQM6
PSDDQM7
PSDRAS
PSDVAL
PSDWE
PWE0
TDM0RCLK
TDM0RDAT
TDM0RSYN
TDM0TCLK
TDM0TDAT
TDM0TSYN
TDM1RCLK
TDM1RDAT
TDM1RSYN
TDM1TCLK
TDM1TDAT
TDM1TSYN
TDM2RCLK
TDM2RDAT
TDM2RSYN
TDM2TCLK
TDM2TDAT
TDM2TSYN
TDM3RCLK
TDM3RDAT
TDM3RSYN
TDM3TCLK
TDM3TDAT
TDM3TSYN
TDO
J21
N20
H18
G22
J19
H19
F22
F17
F18
F19
G21
G19
E20
F21
E22
E21
F20
E19
C19
D22
C22
D19
C21
C20
C4
H7
G7
K6
N6
K5
R7
T7
R6
T6
K7
P18
N19
G7
K6
N6
K5
R7
T7
PWE1
PWE2
PWE3
PWE4
PWE5
PWE6
R6
T6
PWE7
PUPMWAIT
Reserved
RSTCONF
SCL
H8
K9
F3
D16
C16
C5
T5
TEA
P17
H6
SDA
TEST
SRESET
SWTE
TIMER0
C18
C17
C16
D16
TIMER1
TA
P15
T10
TIMER2
TBST
TIMER3
MSC8122 Technical Data, Rev. 4
Freescale Semiconductor
3-11
Packaging
Table 3-1. MSC8122 Signal Listing By Name (Continued)
Location
Designator
Location
Designator
Signal Name
Signal Name
TMCLK
TMS
TRST
TS
C16
E4
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
F8
F9
E3
F10
F12
F14
G8
R18
T8
TSZ0
TSZ1
TSZ2
TSZ3
TT0
R8
T9
G9
R9
G13
G16
H4
R14
T13
K16
J16
H16
E6
TT1
TT2
H9
TT3
H15
H20
J4
TT4
URXD
UTXD
VCCSYN
VDD
C6
J9
P12
B8
J13
J15
K15
M8
VDD
B10
B12
B14
B16
B18
B20
B21
C3
VDD
VDD
R11
R12
R13
T11
Y6
VDD
VDD
VDD
VDD
VDD
AA2
B3
VDD
C9
VDD
C11
C13
D10
D12
D14
D15
E9
AB22
D6
VDD
VDD
D18
D20
H21
L5
VDD
VDD
VDD
VDD
L6
VDD
E11
E13
E16
L15
L19
M4
VDD
VDD
MSC8122 Technical Data, Rev. 4
3-12
Freescale Semiconductor
Package Description
Table 3-1. MSC8122 Signal Listing By Name (Continued)
Location
Designator
Location
Designator
Signal Name
Signal Name
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
M9
M15
M17
M18
M20
N7
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
W12
W15
W17
Y4
Y10
Y13
P20
R3
Y16
Y20
U20
V3
AA9
AA12
AA14
W7
W8
Note: This table lists every signal name. Because many signals are multiplexed, an individual ball designator number may be listed
several times.
MSC8122 Technical Data, Rev. 4
Freescale Semiconductor
3-13
Packaging
Des.
Table 3-2. MSC8122 Signal Listing by Ball Designator
Signal Name
Des.
Signal Name
B3
B4
VDD
C18
C19
C20
C21
C22
D2
GPIO1/TIMER0/CHIP_ID1/IRQ5/ETHTXD1
GND
GPIO7/TDM3RCLK/IRQ5/ETHTXD3
B5
GND
GPIO3/TDM3TSYN/IRQ1/ETHTXD2
B6
NMI_OUT
GPIO5/TDM3TDAT/IRQ3/ETHRXD3
B7
GND
GPIO6/TDM3RSYN/IRQ4/ETHRXD2
B8
VDD
TDI
B9
GND
D3
EE0
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
C2
VDD
D4
EE1
GND
D5
GND
VDD
D6
VDDH
GND
D7
HCID2
VDD
D8
HCID3/HA8
GND
D9
GND
VDD
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
E2
VDD
GND
GND
VDD
VDD
GPIO0/CHIP_ID0/IRQ4/ETHTXD0
GND
VDD
VDD
VDD
VDD
GND
GPIO31/TIMER3/SCL
GND
GPIO29/CHIP_ID3/ETHTX_EN
C3
VDD
VDDH
C4
TDO
GPIO4/TDM3TCLK/IRQ2/ETHTX_ER
C5
SRESET
VDDH
C6
GPIO28/UTXD/DREQ2
GND
C7
HCID1
GPIO8/TDM3RDAT/IRQ6/ETHCOL
C8
GND
TCK
C9
VDD
E3
TRST
C10
C11
C12
C13
C14
C15
C16
C17
GND
E4
TMS
VDD
E5
HRESET
GND
E6
GPIO27/URXD/DREQ1
VDD
E7
HCID0
GND
VDD
GND
E8
GND
E9
GPIO30/TIMER2/TMCLK/SDA
GPIO2/TIMER1/CHIP_ID2/IRQ6
E10
E11
GND
VDD
MSC8122 Technical Data, Rev. 4
3-14
Freescale Semiconductor
Package Description
Table 3-2. MSC8122 Signal Listing by Ball Designator (Continued)
Des.
Signal Name
Des.
Signal Name
E12
E13
E14
E15
E16
E17
E18
E19
E20
E21
E22
F2
GND
G6
G7
HA17
VDD
PWE0/PSDDQM0/PBS0
GND
G8
VDD
GND
G9
VDD
VDD
G10
G11
G12
G13
G14
G15
G16
G17
G18
G19
G20
G21
G22
H2
IRQ3/BADDR31
GND
BM0/TC0/BNKSEL0
GND
ABB/IRQ4
GPIO9/TDM2TSYN/IRQ7/ETHMDIO
VDD
GPIO13/TDM2RCLK/IRQ11/ETHMDC
IRQ7/INT_OUT
GPIO10/TDM2TCLK/IRQ8/ETHRX_DV/ETHCRS_DV/NC
ETHCRS/ETHRXD
GPIO12/TDM2RSYN/IRQ10/ETHRXD1/ETHSYNC
VDD
PORESET
CS1
F3
RSTCONF
BCTL0
F4
NMI
GPIO15/TDM1TSYN/DREQ1
F5
HA29
GND
F6
HA22
GPIO17/TDM1TDAT/DACK1
F7
GND
GPIO22/TDM0TCLK/DONE2/DRACK2
F8
VDD
HA20
F9
VDD
H3
HA28
F10
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
F21
F22
G2
VDD
H4
VDD
GND
H5
HA19
VDD
H6
TEST
GND
VDD
H7
PSDCAS/PGPL3
H8
PGTA/PUPMWAIT/PGPL4/PPBS
ETHRX_CLK/ETHSYNC_IN
ETHTX_CLK/ETHREF_CLK/ETHCLOCK
GPIO20/TDM1RDAT
H9
VDD
H10
H11
H12
H13
H14
H15
H16
H17
H18
H19
H20
BM1/TC1/BNKSEL1
ARTRY
GPIO18/TDM1RSYN/DREQ2
GPIO16/TDM1TCLK/DONE1/DRACK1
GPIO11/TDM2TDAT/IRQ9/ETHRX_ER/ETHTXD
GPIO14/TDM2RDAT/IRQ12/ETHRXD0/NC
GPIO19/TDM1RCLK/DACK2
HA24
AACK
DBB/IRQ5
HTA
VDD
TT4/CS7
CS4
G3
HA27
GPIO24/TDM0RSYN/IRQ14
GPIO21/TDM0TSYN
VDD
G4
HA25
G5
HA23
MSC8122 Technical Data, Rev. 4
Freescale Semiconductor
3-15
Packaging
Des.
Table 3-2. MSC8122 Signal Listing by Ball Designator (Continued)
Signal Name
Des.
Signal Name
H21
H22
J2
VDDH
K15
K16
K17
K18
K19
K20
K21
K22
L2
VDD
TT2/CS5
ALE
A31
HA18
J3
HA26
CS2
J4
VDD
GND
J5
HA13
A26
J6
GND
A29
J7
PSDAMUX/PGPL5
A28
J8
BADDR27
HA12
HA14
HA11
VDDH
VDDH
BADDR28
IRQ5/BADDR29
GND
J9
VDD
L3
J10
J11
J12
J13
J14
J15
J16
J17
J18
J19
J20
J21
J22
K2
CLKIN
L4
BM2/TC2/BNKSEL2
L5
DBG
L6
VDD
L7
GND
L8
VDD
L9
TT3/CS6
L10
L14
L15
L16
L17
L18
L19
L20
L21
L22
M2
M3
M4
M5
M6
M7
M8
M9
M10
M14
GND
PSDA10/PGPL0
GND
BCTL1/CS5
VDDH
GND
GPIO23/TDM0TDAT/IRQ13
GND
GND
GPIO25/TDM0RCLK/IRQ15
CS3
A30
VDDH
A27
HA15
HA21
K3
A25
K4
HA16
A22
K5
PWE3/PSDDQM3/PBS3
PWE1/PSDDQM1/PBS1
POE/PSDRAS/PGPL2
IRQ2/BADDR30
Reserved
HD28
HD31
VDDH
GND
K6
K7
K8
K9
GND
K10
K11
K12
K13
K14
GND
GND
GND
VDD
GND
VDDH
GND
GND
CLKOUT
GND
MSC8122 Technical Data, Rev. 4
3-16
Freescale Semiconductor
Package Description
Table 3-2. MSC8122 Signal Listing by Ball Designator (Continued)
Des.
Signal Name
Des.
Signal Name
M15
M16
M17
M18
M19
M20
M21
M22
N2
VDDH
P12
P13
P14
P15
P16
P17
P18
P19
P20
P21
P22
R2
VCCSYN
HBRST
GND
VDDH
GND
VDDH
TA
GND
BR
VDDH
TEA
A24
PSDVAL
A21
DP0/DREQ1/EXT_BR2
HD26
VDDH
N3
HD30
GND
N4
HD29
A19
N5
HD24
HD18
N6
PWE2/PSDDQM2/PBS2
R3
VDDH
N7
VDDH
R4
GND
N8
HWBS0/HDBS0/HWBE0/HDBE0
R5
HD22
N9
HBCS
R6
HWBS6/HDBS6/HWBE6/HDBE6/PWE6/PSDDQM6/PBS6
N10
N14
N15
N16
N17
N18
N19
N20
N21
N22
P2
GND
R7
HWBS4/HDBS4/HWBE4/HDBE4/PWE4/PSDDQM4/PBS4
GND
R8
TSZ1
HRDS/HRW/HRDE
R9
TSZ3
BG
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
T2
IRQ1/GBL
HCS
VDD
CS0
VDD
PSDWE/PGPL1
VDD
GPIO26/TDM0RDAT
TT0/HA7
A23
IRQ7/DP7/DREQ4
A20
IRQ6/DP6/DREQ3
HD20
IRQ3/DP3/DREQ2/EXT_BR3
P3
HD27
TS
P4
HD25
IRQ2/DP2/DACK2/EXT_DBG2
P5
HD23
HWBS3/HDBS3/HWBE3/HDBE3
HWBS2/HDBS2/HWBE2/HDBE2
HWBS1/HDBS1/HWBE1/HDBE1
HCLKIN
A17
A18
P6
P7
A16
P8
HD17
P9
T3
HD21
P10
P11
GND
T4
HD1/DSISYNC
HD0/SWTE
GNDSYN
T5
MSC8122 Technical Data, Rev. 4
Freescale Semiconductor
3-17
Packaging
Des.
Table 3-2. MSC8122 Signal Listing by Ball Designator (Continued)
Signal Name
Des.
Signal Name
T6
T7
HWBS7/HDBS7/HWBE7/HDBE7/PWE7/PSDDQM7/PBS7
U21
U22
V2
A12
HWBS5/HDBS5/HWBE5/HDBE5/PWE5/PSDDQM5/PBS5
A13
T8
TSZ0
HD3/MODCK1
T9
TSZ2
V3
VDDH
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
U2
TBST
V4
GND
VDD
V5
D0
D16
V6
D1
TT1
V7
D4
D21
V8
D5
D23
V9
D7
IRQ5/DP5/DACK4/EXT_BG3
V10
V11
V12
V13
V14
V15
V16
V17
V18
V19
V20
V21
V22
W2
W3
W4
W5
W6
W7
W8
W9
W10
W11
W12
W13
W14
D10
IRQ4/DP4/DACK3/EXT_DBG3
D12
IRQ1/DP1/DACK1/EXT_BG2
D13
D30
GND
A15
D18
D20
GND
A14
D24
HD16
HD19
HD2/DSI64
D2
D27
U3
D29
U4
A8
A9
U5
U6
D3
A10
U7
D6
A11
U8
D8
HD6
U9
D9
HD5/CNFGS
HD4/MODCK2
GND
U10
U11
U12
U13
U14
U15
U16
U17
U18
U19
U20
D11
D14
D15
GND
D17
VDDH
D19
VDDH
D22
GND
D25
HDST1/HA10
HDST0/HA9
VDDH
D26
D28
D31
GND
VDDH
HD40/D40/ETHRXD0
MSC8122 Technical Data, Rev. 4
3-18
Freescale Semiconductor
Package Description
Table 3-2. MSC8122 Signal Listing by Ball Designator (Continued)
Des.
Signal Name
Des.
Signal Name
W15
W16
W17
W18
W19
W20
W21
W22
Y2
VDDH
AA9
AA10
AA11
AA12
AA13
AA14
AA15
AA16
AA17
AA18
AA19
AA20
AA21
AA22
AB2
VDDH
HD33/D33/reserved
HD54/D54/ETHTX_EN
VDDH
HD52/D52
HD32/D32/reserved
VDDH
GND
GND
GND
VDDH
A7
HD46/D46/ETHTXT0
A6
GND
HD7
HD42/D42/ETHRXD2/reserved
Y3
HD15
HD38/D38/reserved
Y4
VDDH
HD35/D35/reserved
Y5
HD9
A0
Y6
VDD
A2
Y7
HD60/D60/ETHCOL/reserved
A3
GND
Y8
HD58/D58/ETHMDC
Y9
GND
AB3
HD13
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y20
Y21
Y22
AA2
AA3
AA4
AA5
AA6
AA7
AA8
VDDH
AB4
HD11
HD51/D51
AB5
HD8
GND
AB6
HD62/D62
VDDH
AB7
HD61/D61
HD43/D43/ETHRXD3/reserved
AB8
HD57/D57/ETHRX_ER
HD56/D56/ETHRX_DV/ETHCRS_DV
HD55/D55/ETHTX_ER/reserved
HD53/D53
GND
AB9
VDDH
AB10
AB11
AB12
AB13
AB14
AB15
AB16
AB17
AB18
AB19
AB20
AB21
AB22
GND
HD37/D37/reserved
HD50/D50
HD34/D34/reserved
HD49/D49/ETHTXD3/reserved
HD48/D48/ETHTXD2/reserved
HD47/D47/ETHTXD1
HD45/D45
VDDH
A4
A5
VDD
HD44/D44
HD14
HD41/D41/ETHRXD1
HD39/D39/reserved
HD36/D36/reserved
A1
HD12
HD10
HD63/D63
HD59/D59/ETHMDIO
GND
VDD
MSC8122 Technical Data, Rev. 4
Freescale Semiconductor
3-19
Packaging
3.2 MSC8122 Package Mechanical Drawing
Notes:
1. All dimensions in millimeters.
2. Dimensioning and tolerancing
per ASME Y14.5M–1994.
3. Featuresaresymmetrical about
the package center lines unless
dimensioned otherwise.
4. Maximum solder ball diameter
measured parallel to Datum A.
5. Datum A, the seating plane, is
determined by the spherical
crowns of the solder balls.
6. Parallelism measurement shall
exclude any effect of mark on
top surface of package.
7. Capacitors may not be present
on all devices.
8. Caution must be taken not to
short capacitors or exposed
metal capacitor pads on
package top.
CASE 1550-02
Figure 3-3. MSC8122 Mechanical Information, 431-pin FC-PBGA Package
MSC8122 Technical Data, Rev. 4
3-20
Freescale Semiconductor
Design Considerations
4
The following sections discuss areas to consider when the MSC8122 device is designed into a system.
4.1 Power Supply Design Considerations
External voltage applied to any input line must not exceed the I/O supply VDDH by more than 0.8 V at any time,
including during power-up.
Note: Some designs require pull-up voltages applied to selected input lines during power-up for configuration
purposes. This is an acceptable exception to the rule. However, each such input can draw up to 80 mA per
input pin per device in the system during start-up.
After power-up, VDDH must not exceed VDD/VCCSYN by more than 2.6 V.
Use the following guidelines for power-up and power-down sequences:
•
Assert PORESET before applying power and keep the signal driven low until the power reaches the required
minimum power levels. This can be implemented via a weak pull-down resistor.
•
CLKIN can be held low or allowed to toggle during the beginning of the power-up sequence. However, CLKIN
must start toggling before the deassertion of PORESET and after both power supplies have reached nominal
voltage levels.
•
If possible, bring up VDD/VCCSYN and VDDH together. If it is not possible, raise VDD/VCCSYN first and then bring up
V
DDH. VDDH should not exceed VDD/VCCSYN until VDD/VCCSYN reaches its nominal voltage level. Similarly, bring
both voltage levels down together. If that is not possible reverse the power-up sequence, with VDDH going down
first and then VDD/V
.
CCSYN
Note: This recommended power sequencing for the MSC8122 is different from the MSC8102.
When used as a drop-in replacement in MSC8102 applications or when implementing a new design, use the
guidelines described in Migrating Designs from the MSC8102 to the MSC8122 (AN2716) and the MSC8122
Design Checklist (AN2787) for optimal system performance. MSC8122 and MSC8126 Power Circuit Design
Recommendations and Examples (AN2937) provides detailed design information.
Figure 4-1 shows the recommended power decoupling circuit for the core power supply. The voltage regulator and
the decoupling capacitors should supply the required device current without any drop in voltage on the device pins.
The voltage on the package pins should not drop below the minimum specified voltage level even for a very short
spikes. This can be achieved by using the following guidelines:
•
For the core supply, use a voltage regulator rated at 1.2 V with nominal rating of at least 3 A. This rating does
not reflect actual average current draw, but is recommended because it resists changes imposed by transient
spikes and has better voltage recovery time than supplies with lower current ratings.
MSC8122 Technical Data, Rev. 4
Freescale Semiconductor
4-1
Design Considerations
•
Decouple the supply using low-ESR capacitors mounted as close as possible to the socket. Figure 4-1 shows
three capacitors in parallel to reduce the resistance. Three capacitors is a recommended minimum number. If
possible, mount at least one of the capacitors directly below the MSC8122 device.
Maximum IR drop
of 15 mV at 1 A
Lmax = 2 cm
1.2 V
One 0.01 µF capacitor
for every 3 core supply
pads.
Power supply
or
MSC8122
Voltage Regulator
+
-
Bulk/Tantalum capacitors
with low ESR and ESL
(Imin = 3 A)
High frequency capacitors
(very low ESR and ESL)
Note: Use at least three capacitors.
Each capacitor must be at least 150 µF.
Figure 4-1. Core Power Supply Decoupling
Each VCC and VDD pin on the MSC8122 device should have a low-impedance path to the board power supply.
Similarly, each GND pin should have a low-impedance path to the ground plane. The power supply pins drive
distinct groups of logic on the chip. The VCC power supply should have at least four 0.1 µF by-pass capacitors to
ground located as closely as possible to the four sides of the package. The capacitor leads and associated printed
circuit traces connecting to chip VCC, VDD, and GND should be kept to less than half an inch per capacitor lead. A
four-layer board is recommended, employing two inner layers as VCC and GND planes.
All output pins on the MSC8122 have fast rise and fall times. PCB trace interconnection length should be
minimized to minimize undershoot and reflections caused by these fast output switching times. This
recommendation particularly applies to the address and data buses. Maximum PCB trace lengths of six inches are
recommended. For the DSI control signals in synchronous mode, ensure that the layout supports the DSI AC
timing requirements and minimizes any signal crosstalk. Capacitance calculations should consider all device loads
as well as parasitic capacitances due to the PCB traces. Attention to proper PCB layout and bypassing becomes
especially critical in systems with higher capacitive loads because these loads create higher transient currents in the
V
CC, VDD, and GND circuits. Pull up all unused inputs or signals that will be inputs during reset.
Special care should be taken to minimize the noise levels on the PLL supply pins. There is one pair of PLL supply
pins: VCCSYN-GNDSYN. To ensure internal clock stability, filter the power to the VCCSYN input with a circuit similar to
the one in Figure 4-2. For optimal noise filtering, place the circuit as close as possible to VCCSYN. The 0.01-µF
capacitor should be closest to VCCSYN, followed by the 10-µF capacitor, the 10-nH inductor, and finally the 10-Ω
resistor to VDD. These traces should be kept short and direct. Provide an extremely low impedance path to the
ground plane for GNDSYN. Bypass GNDSYN to VCCSYN by a 0.01-µF capacitor located as close as possible to the chip
package. For best results, place this capacitor on the backside of the PCB aligned with the depopulated void on the
MSC8122 located in the square defined by positions, L11, L12, L13, M11, M12, M13, N11, N12, and N13.
V
V
CCSYN
DD
10nH
10Ω
10 µF
0.01 µF
Figure 4-2.
V
Bypass
CCSYN
MSC8122 Technical Data, Rev. 4
4-2
Freescale Semiconductor
Connectivity Guidelines
4.2 Connectivity Guidelines
Unused output pins can be disconnected, and unused input pins should be connected to the non-active value, except
for the following:
•
•
•
•
•
If the DSI is unused (DDR[DSIDIS] is set), HCS and HBCS must be tied to VDD and all the rest of the DSI
signals can be disconnected.
When the DSI uses synchronous mode, HTA must be pulled up. In asynchronous mode, HTA should be pulled
either up or down, depending on design requirements.
HDST can be disconnected if the DSI is in big-endian mode, or if the DSI is in little-endian mode and the
DCR[DSRFA] bit is set.
When the DSI is in 64-bit data bus mode and DCR[BEM] is cleared, tie HWBS[1–3]/HDBS[1–3]/HWBE[1–3]/
HDBE[1–3] and HWBS[4–7]/HDBS[4–7]/HWBE[4–7]/HDBE[4–7]/PWE[4–7]/PSDDQM[4–7]/PBS[4–7] to V
.
DD
When the DSI is in 32-bit data bus mode and DCR[BEM] is cleared,
HWBS[1–3]/HDBS[1–3]/HWBE[1–3]/HDBE[1–3] must be tied to V
.
DD
•
•
•
When the DSI is in asynchronous mode, HBRST and HCLKIN should either be disconnected or tied to V
The following signals must be pulled up: HRESET, SRESET, ARTRY, TA, TEA, PSDVAL, and AACK.
In single-master mode (BCR[EBM] = 0) with internal arbitration (PPC_ACR[EARB] = 0):
— BG, DBG, and TS can be left unconnected.
.
DD
— EXT_BG[2–3], EXT_DBG[2–3], and GBL can be left unconnected if they are multiplexed to the system bus
functionality. For any other functionality, connect the signal lines based on the multiplexed functionality.
— BR must be pulled up.
— EXT_BR[2–3] must be pulled up if multiplexed to the system bus functionality.
•
•
If there is an external bus master (BCR[EBM] = 1):
— BR, BG, DBG, and TS must be pulled up.
— EXT_BR[2–3], EXT_BG[2–3], and EXT_DBG[2–3] must be pulled up if multiplexed to the system bus
functionality.
In single-master mode, ABB and DBB can be selected as IRQ inputs and be connected to the non-active value. In
other modes, they must be pulled up.
Note: The MSC8122 does not support DLL-enabled mode. For the following two clock schemes, ensure that the
DLL is disabled (that is, the DLLDIS bit in the Hard Reset Configuration Word is set).
•
•
If no system synchronization is required (for example, the design does not use SDRAM), you can use any of
the available clock modes.
In the new MSC8122 clock scheme (PLL skew elimination mode), use the following connections:
— Connect the oscillator output through a buffer to CLKIN.
— Connect the CLKIN buffer output to the slave device (for example, SDRAM) making sure that the delay
path between the clock buffer to the MSC8122 and the SDRAM is equal (that is, has a skew less than 100
ps).
— Valid clock modes in this scheme are: 0, 7, 15, 19, 21, 23, 28, 29, 30, and 31.
MSC8122 Technical Data, Rev. 4
Freescale Semiconductor
4-3
Design Considerations
•
In MSC8102 back-compatible mode (for 1.2 V parts only), CLKOUT is the main clock to SDRAM. Use the
following connections:
— Connect the oscillator output through a buffer to CLKIN.
— Connect CLKOUT through a zero-delay buffer to the slave device (for example, SDRAM) using the
following guidelines:
•
•
•
The maximum delay between the slave and CLKOUT must not exceed 0.7 ns.
The maximum load on CLKOUT must not exceed 10 pF.
Use a zero-delay buffer with a jitter less than 0.3 ns.
— All clock modes are valid in this clock scheme.
Note: See Migrating Designs from the MSC8102 to the MSC8122 (AN2716) for details on timing specifications
that apply in back-compatible mode. Also see the Clock chapter in the MSC8122 Reference Manual.
•
If the 60x-compatible system bus is not used and SIUMCR[PBSE] is set, PPBS can be disconnected.
Otherwise, it should be pulled up.
•
The following signals: SWTE, DSISYNC, DSI64, MODCK[1–2], CNFGS, CHIPID[0–3], RSTCONF and BM[0–2] are
used to configure the MSC8122 and are sampled on the deassertion of the PORESET signal. Therefore, they
should be tied to GND or VDDH or through a pull-down or a pull-up resistor until the deassertion of the PORESET
signal.
•
•
When they are used, INT_OUT (if SIUMCR[INTODC] is cleared), NMI_OUT, and IRQxx (if not full drive)
signals must be pulled up.
When the Ethernet controller is enabled and the SMII mode is selected, GPIO10 and GPIO14 must not be
connected externally to any signal line.
Note: For details on configuration, see the MSC8122 User’s Guide and MSC8122 Reference Manual. For
additional information, refer to the MSC8122 Design Checklist (AN2787).
4.3 External SDRAM Selection
The external bus speed implemented in a system determines the speed of the SDRAM used on that bus. However,
because of differences in timing characteristics among various SDRAM manufacturers, you may have use a faster
speed rated SDRAM to assure efficient data transfer across the bus. For example, for 166 MHz operation, you may
have to use 183 or 200 MHz SDRAM. Always perform a detailed timing analysis using the MSC8122 bus timing
values and the manufacturer specifications for the SDRAM to ensure correct operation within your system design.
The output delay listed in SDRAM specifications is usually given for a load of 30 pF. Scale the number to your
specific board load using the typical scaling number provided by the SDRAM manufacturer.
MSC8122 Technical Data, Rev. 4
4-4
Freescale Semiconductor
Power Considerations
4.4 Power Considerations
The internal power dissipation consists of three components:
P
= P
+ P
+ P
+ P
BUSES PERIPH
INT
TCORE
SIU
The power dissipation depends on the operating frequency of the different portions of the chip. To determine the
power dissipation at a given frequency, the following equations should be applied:
P
P
P
P
P
(f ) = ((P
– P
)/400) × f + P
LCO c LCO
CORE
c
CORE
(f ) = (P × 4)
TCORE
c
CORE
(f ) = ((P
– P )/133) × f + P
LSI c LSI
SIU
c
SIU
(f ) = ((P
– P )/133) × f + P
PERIPH
c
PERIPH
LPE c LPE
(f ) = P
/133 × f
BUSES
c
BUSES
c
Where,
f is the operating frequency in MHz and all power numbers are in mW
c
P
P
P
is the SC140 Core leakage power
is the SIU leakage power
is the peripheral leakage power
LCO
LSI
LPE
To determine a total power dissipation in a specific application, the following equation should be applied for each
I/O output pin:
2
–3
P = K × C × V
× f × 10
Equation 1
DDH
s
Where:
P = power in mW
C = load capacitance in pF
f = output switching frequency in MHz
s
K = activity factor for each pin
MSC8122 Technical Data, Rev. 4
Freescale Semiconductor
4-5
Design Considerations
4.5 Thermal Considerations
An estimation of the chip-junction temperature, T , in ° C can be obtained from the following:
J
T = T + (R
× P )
Equation 2
J
A
JA
D
θ
where
T = ambient temperature near the package (° C)
A
R
= junction-to-ambient thermal resistance (° C/W)
JA
θ
P = P
+ P = power dissipation in the package (W)
D
INT
I/O
P
P
= I × V = internal power dissipation (W)
INT
I/O
DD DD
= power dissipated from device on output pins (W)
The power dissipation values for the MSC8122 are listed in Table 2-3. The ambient temperature for the device is
the air temperature in the immediate vicinity that would cool the device. The junction-to-ambient thermal
resistances are JEDEC standard values that provide a quick and easy estimation of thermal performance. There are
two values in common usage: the value determined on a single layer board and the value obtained on a board with
two planes. The value that more closely approximates a specific application depends on the power dissipated by
other components on the printed circuit board (PCB). The value obtained using a single layer board is appropriate
for tightly packed PCB configurations. The value obtained using a board with internal planes is more appropriate
2
for boards with low power dissipation (less than 0.02 W/cm with natural convection) and well separated
components. Based on an estimation of junction temperature using this technique, determine whether a more
detailed thermal analysis is required. Standard thermal management techniques can be used to maintain the device
thermal junction temperature below its maximum. If T appears to be too high, either lower the ambient
J
temperature or the power dissipation of the chip. You can verify the junction temperature by measuring the case
temperature using a small diameter thermocouple (40 gauge is recommended) or an infrared temperature sensor on
a spot on the device case that is painted black. The MSC8122 device case surface is too shiny (low emissivity) to
yield an accurate infrared temperature measurement. Use the following equation to determine T :
J
T = T + (θ × P )
Equation 3
J
T
JA
D
where
T = thermocouple (or infrared) temperature on top of the package (° C)
T
θ
= thermal characterization parameter (° C/W)
JA
P = power dissipation in the package (W)
D
Note: See MSC8102, MSC8122, and MSC8126 Thermal Management Design Guidelines (AN2601/D).
MSC8122 Technical Data, Rev. 4
4-6
Freescale Semiconductor
Ordering Information
Consult a Freescale Semiconductor sales office or authorized distributor to determine product availability and place
an order.
Core
Core
Operating
Part
Package Type
Spheres
Frequency Order Number
(MHz)
Voltage Temperature
MSC8122 Flip Chip Plastic Ball Grid Array (FC-PBGA)
Lead-free
Lead-bearing
Lead-free
1.1 V
1.2 V
0° to 90°C
–40° to 105°C
0° to 90°C
300
MSC8122VT4800V
MSC8122MP4800V
MSC8122TVT4800V
MSC8122TMP4800V
MSC8122VT4800
MSC8122MP4800
MSC8122TVT4800
MSC8122TMP4800
MSC8122VT6400
MSC8122MP6400
MSC8122TVT6400
MSC8122TMP6400
MSC8122VT8000
MSC8122MP8000
Lead-bearing
Lead-free
Lead-bearing
Lead-free
–40° to 105°C
0° to 90°C
Lead-bearing
Lead-free
400
500
Lead-bearing
Lead-free
–40° to 105°C
0° to 90°C
Lead-bearing
Lead-free
Lead-bearing
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MSC8122
Rev. 4
1/2005
相关型号:
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