MSC8126MP8000 [FREESCALE]
Quad Digital Signal Processor; 四核数字信号处理器
| 型号： | MSC8126MP8000 |
| 厂家： | 
Freescale |
| 描述： | Quad Digital Signal Processor |
| 文件： | 总48页 (文件大小：840K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Freescale Semiconductor
Data Sheet:
Document Number: MSC8126
Rev. 13, 12/2007
MSC8126
FC PBGA–431
20 mm × 20 mm
Quad Digital Signal
Processor
•
Four StarCore™ SC140 DSP extended cores, each with an SC140
DSP core, 224 Kbyte of internal SRAM M1 memory (1436 Kbyte
total), 16 way 16 Kbyte instruction cache (ICache), four-entry
write buffer, external cache support, programmable interrupt
controller (PIC), local interrupt controller (LIC), and low-power
Wait and Stop processing modes.
levels or round-robin time-multiplexing between channels,
flexible channel configuration with connection to local bus or
system bus, and flyby transfer support that bypasses the FIFO.
Up to four independent TDM modules with programmable word
size (2, 4, 8, or 16-bit), hardware-base A-law/μ-law conversion,
up to 128 Mbps data rate for all channels, with glueless interface
to E1 or T1 framers, and can interface with H-MVIP/H.110
devices, TSI, and codecs such as AC-97.
Ethernet controller: support for 10/100 Mbps MII/RMII/SMII
including full- and half-duplex operation, full-duplex flow
controls, out-of-sequence transmit queues, programmable
maximum frame length including jumbo frames and VLAN tags
and priority, retransmission after collision, CRC generation and
verification of inbound/outbound packets, address recognition
(including exact match, broadcast address, individual hash check,
group hash check, and promiscuous mode), pattern matching,
insertion with expansion or replacement for transmit frames,
VLAN tag insertion, RMON statistics, local bus master DMA for
descriptor fetching and buffer access, and optional multiplexing
with GPIO (MII/RMII/SMII) or DSI/system bus signals lines
(MII/RMII).
•
•
•
•
•
475 Kbyte M2 memory for critical data/temporary data buffering.
4 Kbyte boot ROM.
M2-accessible multi-core MQBus connecting the M2 memory
with all four cores, operating at the core frequency, with data bus
access of up to 128-bit reads and up to 64-bit writes, central
efficient round-robin arbiter for core access to the bus, and atomic
control of M2 memory access by the cores and local bus.
Internal PLL configured are reset by configuration signal values.
60x-compatible system bus with 64 or 32 bit data and 32-bit
address bus, support for multi-master designs, four-beat burst
transfers (eight-beat in 32-bit data mode), port size of 64/32/16/8
bits controlled by the internal memory controller,.access to
external memory or peripherals, access by an external host to
internal resources, slave support with direct access to internal
resources including M1 and M2 memories, and on-device
arbitration for up to four master devices.
Direct slave interface (DSI) using a 32/64-bit slave interface with
21–25 bit addressing and 32/64-bit data transfers, direct access by
an external host to internal/external resources, synchronous or
asynchronous accesses with burst capability in synchronous
mode, dual or single strobe mode, write and read buffers to
improve host bandwidth, byte enable signals for 1/2/4/8-byte
write granularity, sliding window mode for access using a reduced
number of address pins, chip ID decoding to allow one CS signal
to control multiple DSPs, broadcast mode to write to multiple
DSPs, and big-endian/little-endian/munged support.
Three mode signal multiplexing: 64-bit DSI/32-bit system bus,
32-bit DSI/64-bit system bus, or 32-bit DSI/32-bit system bus.
Flexible memory controller with three UPMs, a GPCM, a
page-mode SDRAM machine, glueless interface to a variety of
memories and devices, byte enables for 64-/32-bit bus widths, 8
memory banks for external memories, and 2 memory banks for
IPBus peripherals and internal memories.
Multi-channel DMA controller with 16 time-multiplexed single
channels, up to four external peripherals, DONE or DRACK
protocol for two external peripherals,.service for up to 16 internal
requests from up to 8 internal FIFOs per channel, FIFO generated
watermarks and hungry requests, priority-based
•
•
•
•
•
•
•
•
UART with full-duplex operation up to 6.25 Mbps.
•
Up to 32 general-purpose input/output (GPIO) ports.
I2C interface that allows booting from EEPROM devices.
Two timer modules, each with sixteen configurable 16-bit timers.
Eight programmable hardware semaphores.
Global interrupt controller (GIC) with interrupt consolidation and
routing to INT_OUT, NMI_OUT, and the cores; thirty-two virtual
maskable interrupts (8 per core) and four virtual NMI (one per
core) that can be generated by a simple write access.
Boot options: external memory, external host, UART, TDM, or
I2C.
VCOP with fully programmable feed-forward channel decoding,
feed-forward channel equalization and traceback sessions. Up to
400 3GPP 12.2 kbps AMR channels (channel decoding, number
of channels linear to frequency). Up to 200 blind transport format
detect (BTFD) channels according to the 3GPP standard. Number
of channels linear to frequency.
TCOP with full support for 3GPP and CDMA2000 standards in
Turbo decode; up to 20 turbo-coding 384 kbps channels; 8 state
PCCC with polynomial as supported by the 3G standards;
iterative decoding structure based on Maximum A-Posteriori
probability (MAP), with calculations performed in the LOG
domain.
•
•
•
•
•
•
time-multiplexing between channels using 16 internal priority
© Freescale Semiconductor, Inc., 2004, 2007. All rights reserved.
Table of Contents
1
2
Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Figure 9. Timing Diagram for a Reset Configuration Write. . . . . . 21
Figure 10.Internal Tick Spacing for Memory Controller Signals. . . 22
Figure 11.SIU Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 12.CLKOUT and CLKIN Signals. . . . . . . . . . . . . . . . . . . . . 26
Figure 13.DMA Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 14.Asynchronous Single- and Dual-Strobe Modes Read
Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
1.1 FC-PBGA Ball Layout Diagrams. . . . . . . . . . . . . . . . . . .4
1.2 Signal List By Ball Location. . . . . . . . . . . . . . . . . . . . . . .7
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
2.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
2.2 Recommended Operating Conditions. . . . . . . . . . . . . .14
2.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .14
2.4 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . .15
2.5 AC Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Hardware Design Considerations. . . . . . . . . . . . . . . . . . . . . .40
3.1 Start-up Sequencing Recommendations . . . . . . . . . . .40
3.2 Power Supply Design Considerations. . . . . . . . . . . . . .40
3.3 Connectivity Guidelines . . . . . . . . . . . . . . . . . . . . . . . .42
3.4 External SDRAM Selection. . . . . . . . . . . . . . . . . . . . . .43
3.5 Thermal Considerations . . . . . . . . . . . . . . . . . . . . . . . .44
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Package Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Product Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Figure 15.Asynchronous Single- and Dual-Strobe Modes Write
Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3
Figure 16.Asynchronous Broadcast Write Timing Diagram. . . . . . 30
Figure 17.DSI Synchronous Mode Signals Timing Diagram . . . . . 31
Figure 18.TDM Inputs Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 19.TDM Output Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 20.UART Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 21.UART Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 22.Timer Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 23.MDIO Timing Relationship to MDC . . . . . . . . . . . . . . . . 34
Figure 24.MII Mode Signal Timing. . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 26.SMII Mode Signal Timing. . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 27.GPIO Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 28.EE Pin Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 29.Test Clock Input Timing Diagram. . . . . . . . . . . . . . . . . . 38
Figure 30.Boundary Scan (JTAG) Timing Diagram . . . . . . . . . . . . 38
Figure 31.Test Access Port Timing Diagram . . . . . . . . . . . . . . . . . 39
Figure 32.TRST Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 33.Core Power Supply Decoupling. . . . . . . . . . . . . . . . . . . 41
4
5
6
7
List of Figures
Figure 1. MSC8126 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 3
Figure 2. StarCore SC140 DSP Extended Core Block Diagram . . 3
Figure 3. MSC8126 Package, Top View . . . . . . . . . . . . . . . . . . . . 5
Figure 4. MSC8126 Package, Bottom View. . . . . . . . . . . . . . . . . . 6
Figure 5. Overshoot/Undershoot Voltage for V and V . . . . . . . 16
Figure 6. Start-Up Sequence: V and V
IH
IL
Raised Together. . 17
DD
DDH
Figure 34.V
Bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
CCSYN
Figure 7. Start-Up Sequence: V Raised Before V
with CLKIN
DD
DDH
Figure 35.MSC8126 Mechanical Information, 431-pin FC-PBGA
Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Started with V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
DDH
Figure 8. Power-Up Sequence for V
and V /V
. . . . . 18
DDH
DD CCSYN
MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 13
2
Freescale Semiconductor
SC140
Extended Core
SC140
Extended Core
SC140
Extended Core
SC140
Extended Core
MQBus
128
128
64
SQBus
Local Bus
Boot
ROM
IP Master
32 Timers
M2
RAM
Memory
Controller
M2
RAM
RS-232
UART
4 TDMs
TCOP
VCOP
GPIO Pins
Interrupts
IPBus
32
IP Master
GPIO
GIC
IPBus2
8 Hardware
Semaphores
PLL/Clock
JTAG Port
PLL
MII/RMII/SMII
DSI Port
Ethernet
JTAG
Internal Local Bus
SIU
64
Direct
Slave
Interface
(DSI)
System
Interface
32/64
DMA
Bridge
Registers
System Bus
32/64
64
Memory
Controller
Internal System Bus
Figure 1. MSC8126 Block Diagram
Address
Data ALU
Register
File
Program
Register
File
Sequencer
Address
ALU
Data
ALU
SC140
Core
JTAG
EOnCE
Power
Management
M1
RAM
SC140 Core
64
Xa
64
Xb
P
128
Instruction
Cache
QBus
Interface
QBC
128
QBus
PIC
IRQs
QBus
Bank 1
QBus
Bank 3
LIC
IRQs
MQBus
SQBus
128
128
64
Local Bus
Notes: 1. The arrows show the data transfer direction.
2. The QBus interface includes a bus switch, write buffer, fetch unit, and a control unit that defines
four QBus banks. In addition, the QBC handles internal memory contentions.
Figure 2. StarCore SC140 DSP Extended Core Block Diagram
MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 13
Freescale Semiconductor
3
Pin Assignments
1
Pin Assignments
This section includes diagrams of the MSC8126 package ball grid array layouts and pinout allocation tables.
1.1
FC-PBGA Ball Layout Diagrams
Top and bottom views of the FC-PBGA package are shown in Figure 3 and Figure 4 with their ball location index numbers.
MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 13
4
Freescale Semiconductor
Pin Assignments
Top View
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
NMI_
OUT
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
B
C
D
GND
GND
GND
GND
GND
VDD
GND
GND
GND
GPIO0
GND
S
VDD
EE0
VDD
VDD
GND
TDI
TDO
EE1
GPIO28 HCID1 GND
GND
VDD
GND
VDD
GND
VDD
GND GPIO30 GPIO2 GPIO1 GPIO7 GPIO3 GPIO5 GPIO6
RESET
VDDH
VDD
VDDH
VDDH
GND
HCID2 HCID3 GND
GND
VDD
GND
VDD
GPIO31 GPIO29
GPIO4
GND GPIO8
VDD
VDD
VDD
VDD
VDD
VDD
TCK
PO
TRST
RST
TMS HRESET GPIO27 HCID0 GND
GND
VDD
GND
VDD
GND
VDD
GND
GND
GND GPIO9 GPIO13 GPIO10 GPIO12
E
F
ETHRX_ ETHTX_
VDD
NMI
HA25
VDD
HA29
HA23
HA19
HA13
HA22
GND
GND
BM0
GND
VDD
GPIO20 GPIO18 GPIO16 GPIO11 GPIO14 GPIO19
RESET CONF
CLK
CLK
BADDR
31
INT_ ETHCR
OUT
VDD
VDD
G
H
J
HA24
HA20
HA18
HA15
HA12
HD28
HD26
HD20
HD18
HA27
HA28
HA26
HA21
HA14
HD31
HD30
HD27
VDDH
HA17 PWE0
ABB
CS1
BCTL0 GPIO15 GND GPIO17 GPIO22
S
PSD
TEST
VDD
VDD
VDDH
PGTA
BM1 ARTRY AACK
DBB
VDD
HTA
TT4
CS4 GPIO24 GPIO21
A31
CAS
PSDA BADDR
VDD
VDD
GND
CLKIN
GND
GND
GND
GND
BM2
GND
DBG
GND
GND
TT3 PSDA10 BCTL1 GPIO23 GND GPIO25 A30
MUX
27
BADDR
30
VDD
K
HA16 PWE3 PWE1
POE
Res.
GND
VDDH
GND CLKOUT
GND
TT2
ALE
GND
VDDH
CS2
CS3
GND
VDDH
A26
A27
A29
A25
A24
A28
A22
A21
A20
A19
A16
BADDR BADDR
VDDH
GND
VDDH
GND
VDDH
VDDH
HRDS
TA
L
HA11
VDDH
GND
28
29
HB
RST
VDDH
VDD
VDDH
VDDH
M
N
P
GND
GND
HWBS
0
VDDH
HD29
HD25
HD24 PWE2
HBCS
GND
BG
BR
HCS
TEA
DP3
CS0 PSDWE GPIO26 A23
PSD
HWBS HWBS HWBS
3
GNDSYN VCCSYN
VDDH
HD23
HD22
HD0
D2
HCLKIN GND
GND
VDD
GND
TT0
DP0
DP2
D30
GND
A18
A15
A12
A10
A7
2
1
VAL
HWBS HWBS
6
VDD
VDD
D14
D12
VDD
R
T
GND
HD1
HD2
GND
HD4
VDDH
TSZ1
TSZ3
TSZ2
D9
GBL
TBST
D11
DP7
DP6
DP5
D25
TS
A17
GND
VDDH
4
HWBS HWBS
7
HD17
HD16
HD3
HD6
HD7
VDD
HD21
HD19
VDDH
TSZ0
D8
D16
D15
TT1
D17
D21
D19
D23
D22
DP4
D26
DP1
D28
A14
A13
A11
A6
5
U
V
D3
D6
D31
D0
D1
D4
D5
D7
D10
D13
D18
D20
GND
VDDH
D24
D27
D29
A8
A9
VDDH
VDDH
VDDH
VDDH
W
Y
HD5
HD15
HD14
HD13
GND
HD9
HD10
HD8
GND
VDD
GND HDST1 HDST0
GND
VDDH
HD40
HD43
VDDH
HD33
VDDH
HD32
HD37
HD38
HD41
GND
HD34
HD35
HD39
GND
VDDH
VDDH
HD54
HD55
HD60
HD59
HD61
HD58
GND
GND
VDDH
HD51
HD52
HD53
GND
VDDH
GND
HD46
HD47
GND
HD42
HD44
A4
A5
AA
HD12
HD11
HD63
HD62
GND
GND
A0
A2
A3
VDD
AB GND
HD57
HD56
HD50
HD49
HD48
HD45
HD36
A1
Figure 3. MSC8126 Package, Top View
MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 13
Freescale Semiconductor
5
Pin Assignments
Bottom View
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
NMI_
OUT
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
B
C
D
GND
GPIO0
GND
GND
GND
GND
GND
GND
GND
GND
S
VDD
VDD
VDD
VDD
EE0
GPIO6 GPIO5 GPIO3 GPIO7 GPIO1 GPIO2 GPIO30 GND
GND
VDD
GND
VDD
GND
VDD
GND HCID1 GPIO28
TDO
EE1
GND
TDI
RESET
VDDH
VDDH
VDD
VDDH
GPIO8 GND
GPIO4
GPIO29 GPIO31
GND
VDD
GND
VDD
GND HCID3 HCID2
GND
VDD
VDD
VDD
VDD
VDD
VDD
GPIO12 GPIO10 GPIO13 GPIO9 GND
GND
GND
GND
VDD
GND
VDD
GND
VDD
GND HCID0 GPIO27 HRESET TMS
TRST
RST
TCK
PO
E
F
ETHTX_ ETHRX_
CLK
VDD
GPIO19 GPIO14 GPIO11 GPIO16 GPIO18 GPIO20
GND
VDD
GND
BM0
GND
HA22
HA29
HA23
HA19
HA13
NMI
HA25
VDD
CLK
CONF RESET
ETHCR INT_
BADDR
31
VDD
VDD
G
H
GPIO22 GPIO17 GND GPIO15 BCTL0
CS1
ABB
PWE0 HA17
HA27
HA28
HA26
HA21
HA14
HD31
HD30
HD27
VDDH
HA24
HA20
HA18
HA15
HA12
HD28
HD26
HD20
HD18
S
OUT
PSD
TEST
CAS
VDDH
VDD
VDD
A31
GPIO21 GPIO24 CS4
TT4
HTA
DBB
VDD
AACK ARTRY BM1
PGTA
BADDR PSDA
27
VDD
VDD
J
A30 GPIO25 GND GPIO23 BCTL1 PSDA10 TT3
GND
DBG
GND
BM2
GND
CLKIN
GND
GND
GND
GND
GND
MUX
BADDR
30
VDD
K
A28
A22
A21
A20
A19
A16
A29
A25
A24
A26
A27
GND
VDDH
CS2
CS3
ALE
GND
VDDH
TT2
CLKOUT GND
GND
Res.
GND
VDDH
POE
PWE1 PWE3 HA16
BADDR BADDR
29
VDDH
VDDH
HRDS
TA
VDDH
GND
VDDH
GND
L
GND
HA11
VDDH
28
HB
RST
VDDH
VDDH
VDD
VDDH
M
N
GND
GND
HWBS
0
VDDH
A23 GPIO26 PSDWE CS0
PSD
HCS
TEA
DP3
BG
BR
GND
HBCS
PWE2 HD24
HD29
HD25
HWBS HWBS HWBS
VDDH
VCCSYN GNDSYN
P
GND
A18
A15
A12
A10
A7
DP0
DP2
D30
GND
TT0
GND
VDD
GND HCLKIN
HD23
HD22
HD0
D2
VAL
1
2
3
HWBS HWBS
VDD
VDD
VDD
D14
D12
R
A17
GND
VDDH
TS
DP6
DP5
D25
DP7
GBL
TBST
D11
TSZ3
TSZ2
D9
TSZ1
GND
HD1
HD2
GND
HD4
VDDH
4
6
HWBS HWBS
T
A14
A13
A11
A6
DP1
D28
DP4
D26
D23
D22
D21
D19
TT1
D17
D16
D15
TSZ0
D8
HD21
HD19
VDDH
HD17
HD16
HD3
HD6
HD7
VDD
5
7
U
D31
D6
D3
V
A9
A8
D29
D27
D24
GND
VDDH
D20
D18
D13
D10
D7
D5
D4
D1
D0
VDDH
VDDH
VDDH
VDDH
W
Y
GND
VDDH
GND
HD34
HD35
HD39
HD32
HD37
HD38
HD41
HD33
VDDH
HD40
HD43
VDDH
GND
VDDH
HDST0 HDST1 GND
GND
VDD
GND
HD9
HD10
HD8
HD5
HD15
HD14
HD13
VDDH
HD54
HD55
A5
A4
GND
HD42
HD44
GND
HD46
HD47
GND
VDDH
HD51
HD52
HD53
GND
VDDH
HD58
GND
HD60
HD59
HD61
AA
AB
A3
A2
A0
GND
GND
HD63
HD62
HD12
HD11
VDD
A1
HD36
HD45
HD48
HD49
HD50
HD56
HD57
GND
Figure 4. MSC8126 Package, Bottom View
MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 13
6
Freescale Semiconductor
Pin Assignments
1.2
Signal List By Ball Location
Table 1 presents signal list sorted by ball number. -
Table 1. MSC8126 Signal Listing by Ball Designator
Des.
Signal Name
Des.
Signal Name
B3
B4
V
C18
C19
C20
C21
C22
D2
GPIO1/TIMER0/CHIP_ID1/IRQ5/ETHTXD1
DD
GND
GND
GPIO7/TDM3RCLK/IRQ5/ETHTXD3
B5
GPIO3/TDM3TSYN/IRQ1/ETHTXD2
B6
NMI_OUT
GND
GPIO5/TDM3TDAT/IRQ3/ETHRXD3
B7
GPIO6/TDM3RSYN/IRQ4/ETHRXD2
B8
V
TDI
EE0
EE1
GND
DD
B9
GND
D3
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
C2
V
D4
DD
GND
D5
V
D6
V
DDH
DD
GND
D7
HCID2
HCID3/HA8
GND
V
D8
DD
GND
D9
V
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
E2
V
DD
DD
GND
GND
V
V
DD
DD
GPIO0/CHIP_ID0/IRQ4/ETHTXD0
GND
V
V
V
V
DD
DD
DD
DD
GND
GND
GPIO31/TIMER3/SCL
GPIO29/CHIP_ID3/ETHTX_EN
C3
V
V
DDH
DD
C4
TDO
SRESET
GPIO4/TDM3TCLK/IRQ2/ETHTX_ER
C5
V
DDH
C6
GPIO28/DREQ2/UTXD
HCID1
GND
C7
GPIO8/TDM3RDAT/IRQ6/ETHCOL
C8
GND
TCK
TRST
C9
V
E3
DD
C10
C11
C12
C13
C14
C15
C16
C17
GND
E4
TMS
V
E5
HRESET
GPIO27/DREQ1/URXD
HCID0
DD
GND
E6
V
E7
DD
GND
E8
GND
GND
E9
V
DD
GPIO30/TIMER2/TMCLK/SDA
GPIO2/TIMER1/CHIP_ID2/IRQ6
E10
E11
GND
V
DD
MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 13
Freescale Semiconductor
7
Pin Assignments
Des.
Table 1. MSC8126 Signal Listing by Ball Designator (continued)
Signal Name
Des.
Signal Name
E12
E13
E14
E15
E16
E17
E18
E19
E20
GND
G6
G7
HA17
V
PWE0/PSDDQM0/PBS0
DD
GND
GND
G8
V
V
DD
DD
G9
V
G10
G11
G12
G13
G14
G15
G16
G17
G18
G19
G20
G21
G22
H2
IRQ3/BADDR31
BM0/TC0/BNKSEL0
ABB/IRQ4
DD
GND
GND
GPIO9/TDM2TSYN/IRQ7/ETHMDIO
GPIO13/TDM2RCLK/IRQ11/ETHMDC
V
DD
IRQ7/INT_OUT
E21
E22
F2
GPIO10/TDM2TCLK/IRQ8/ETHRX_DV/ETHCRS_DV/NC
ETHCRS/ETHRXD
GPIO12/TDM2RSYN/IRQ10/ETHRXD1/ETHSYNC
V
DD
PORESET
RSTCONF
NMI
CS1
F3
BCTL0
F4
GPIO15/TDM1TSYN/DREQ1
F5
HA29
GND
GPIO17/TDM1TDAT/DACK1
GPIO22/TDM0TCLK/DONE2/DRACK2
HA20
F6
HA22
F7
GND
F8
V
V
V
DD
DD
DD
F9
H3
HA28
F10
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
F21
F22
G2
H4
V
DD
GND
H5
HA19
TEST
V
H6
DD
GND
H7
PSDCAS/PGPL3
PGTA/PUPMWAIT/PGPL4/PPBS
V
H8
DD
ETHRX_CLK/ETHSYNC_IN
ETHTX_CLK/ETHREF_CLK/ETHCLOCK
GPIO20/TDM1RDAT
H9
V
DD
H10
H11
H12
H13
H14
H15
H16
H17
H18
H19
H20
K15
K16
K17
BM1/TC1/BNKSEL1
ARTRY
GPIO18/TDM1RSYN/DREQ2
GPIO16/TDM1TCLK/DONE1/DRACK1
GPIO11/TDM2TDAT/IRQ9/ETHRX_ER/ETHTXD
GPIO14/TDM2RDAT/IRQ12/ETHRXD0/NC
GPIO19/TDM1RCLK/DACK2
HA24
AACK
DBB/IRQ5
HTA
V
DD
TT4/CS7
CS4
G3
HA27
GPIO24/TDM0RSYN/IRQ14
GPIO21/TDM0TSYN
G4
HA25
G5
HA23
V
V
DD
DD
H21
H22
J2
V
DDH
A31
TT2/CS5
ALE
HA18
MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 13
8
Freescale Semiconductor
Pin Assignments
Table 1. MSC8126 Signal Listing by Ball Designator (continued)
Des.
Signal Name
Des.
Signal Name
J3
J4
HA26
K18
K19
K20
K21
K22
L2
CS2
GND
A26
V
DD
J5
HA13
GND
J6
A29
J7
PSDAMUX/PGPL5
BADDR27
A28
J8
HA12
HA14
HA11
J9
V
L3
DD
J10
J11
J12
J13
J14
J15
J16
J17
J18
J19
J20
J21
J22
K2
CLKIN
BM2/TC2/BNKSEL2
DBG
L4
L5
V
V
DDH
DDH
L6
V
L7
BADDR28
IRQ5/BADDR29
GND
DD
GND
L8
V
L9
DD
TT3/CS6
L10
L14
L15
L16
L17
L18
L19
L20
L21
L22
M2
GND
PSDA10/PGPL0
GND
BCTL1/CS5
V
DDH
GPIO23/TDM0TDAT/IRQ13
GND
GND
CS3
GND
GPIO25/TDM0RCLK/IRQ15
A30
V
DDH
HA15
HA21
A27
A25
K3
K4
HA16
A22
K5
PWE3/PSDDQM3/PBS3
PWE1/PSDDQM1/PBS1
POE/PSDRAS/PGPL2
IRQ2/BADDR30
Reserved
HD28
HD31
K6
M3
K7
M4
V
DDH
K8
M5
GND
GND
K9
M6
K10
K11
K12
K13
K14
M15
M16
M17
M18
M19
M20
GND
M7
V
DDH
GND
M8
V
DD
GND
M9
V
DDH
GND
M10
M14
P12
P13
P14
P15
P16
P17
GND
GND
CLKOUT
V
V
CCSYN
DDH
HBRST
GND
V
V
GND
TA
DDH
DDH
GND
BR
V
TEA
DDH
MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 13
Freescale Semiconductor
9
Pin Assignments
Des.
Table 1. MSC8126 Signal Listing by Ball Designator (continued)
Signal Name
Des.
Signal Name
M21
M22
N2
A24
P18
P19
P20
P21
P22
R2
PSDVAL
A21
DP0/DREQ1/EXT_BR2
HD26
V
DDH
N3
HD30
HD29
GND
A19
N4
N5
HD24
HD18
N6
PWE2/PSDDQM2/PBS2
R3
V
DDH
N7
V
R4
GND
DDH
N8
HWBS0/HDBS0/HWBE0/HDBE0
R5
HD22
N9
HBCS
R6
HWBS6/HDBS6/HWBE6/HDBE6/PWE6/PSDDQM6/PBS6
N10
N14
N15
N16
N17
N18
N19
N20
N21
N22
P2
GND
R7
HWBS4/HDBS4/HWBE4/HDBE4/PWE4/PSDDQM4/PBS4
GND
R8
TSZ1
TSZ3
HRDS/HRW/HRDE
R9
BG
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
T2
IRQ1/GBL
HCS
V
V
V
DD
DD
DD
CS0
PSDWE/PGPL1
GPIO26/TDM0RDAT
TT0/HA7
A23
IRQ7/DP7/DREQ4
A20
IRQ6/DP6/DREQ3
HD20
IRQ3/DP3/DREQ2/EXT_BR3
P3
HD27
TS
P4
HD25
HD23
IRQ2/DP2/DACK2/EXT_DBG2
P5
A17
A18
P6
HWBS3/HDBS3/HWBE3/HDBE3
HWBS2/HDBS2/HWBE2/HDBE2
HWBS1/HDBS1/HWBE1/HDBE1
HCLKIN
P7
A16
P8
HD17
P9
T3
HD21
P10
P11
GND
T4
HD1/DSISYNC
HD0/SWTE
A12
GND
T5
SYN
T6
T7
HWBS7/HDBS7/HWBE7/HDBE7/PWE7/PSDDQM7/PBS7
U21
U22
V2
HWBS5/HDBS5/HWBE5/HDBE5/PWE5/PSDDQM5/PBS5
A13
T8
TSZ0
TSZ2
TBST
HD3/MODCK1
T9
V3
V
DDH
T10
T11
T12
T13
T14
V4
GND
D0
V
V5
DD
D16
TT1
D21
V6
D1
V7
D4
V8
D5
MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 13
10
Freescale Semiconductor
Pin Assignments
Table 1. MSC8126 Signal Listing by Ball Designator (continued)
Des.
Signal Name
Des.
Signal Name
T15
T16
T17
T18
T19
T20
T21
T22
U2
D23
V9
V10
V11
V12
V13
V14
V15
V16
V17
V18
V19
V20
V21
V22
W2
D7
D10
IRQ5/DP5/DACK4/EXT_BG3
IRQ4/DP4/DACK3/EXT_DBG3
D12
IRQ1/DP1/DACK1/EXT_BG2
D13
D30
GND
A15
D18
D20
GND
D24
A14
HD16
HD19
HD2/DSI64
D2
D27
U3
D29
U4
A8
U5
A9
U6
D3
A10
U7
D6
A11
U8
D8
HD6
U9
D9
W3
HD5/CNFGS
HD4/MODCK2
GND
GND
U10
U11
U12
U13
U14
U15
U16
U17
U18
U19
U20
W15
W16
W17
W18
W19
W20
W21
W22
Y2
D11
D14
D15
D17
D19
D22
D25
D26
D28
D31
W4
W5
W6
W7
V
V
DDH
DDH
W8
W9
GND
W10
W11
W12
W13
W14
AA9
AA10
AA11
AA12
AA13
AA14
AA15
AA16
AA17
AA18
AA19
AA20
HDST1/HA10
HDST0/HA9
V
DDH
GND
V
V
HD40/D40/ETHRXD0
DDH
DDH
V
DDH
HD33/D33/reserved
HD54/D54/ETHTX_EN
HD52/D52
V
DDH
HD32/D32/reserved
V
DDH
GND
GND
A7
GND
V
DDH
HD46/D46/ETHTXT0
GND
A6
HD7
HD15
HD42/D42/ETHRXD2/reserved
HD38/D38/reserved
HD35/D35/reserved
A0
Y3
Y4
V
DDH
Y5
HD9
MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 13
Freescale Semiconductor
11
Pin Assignments
Des.
Table 1. MSC8126 Signal Listing by Ball Designator (continued)
Signal Name
Des.
Signal Name
Y6
V
AA21
AA22
AB2
A2
DD
Y7
HD60/D60/ETHCOL/reserved
HD58/D58/ETHMDC
GND
A3
GND
Y8
Y9
AB3
HD13
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y20
Y21
Y22
AA2
AA3
AA4
AA5
AA6
AA7
AA8
V
AB4
HD11
DDH
HD51/D51
GND
AB5
HD8
AB6
HD62/D62
V
AB7
HD61/D61
DDH
HD43/D43/ETHRXD3/reserved
GND
AB8
HD57/D57/ETHRX_ER
HD56/D56/ETHRX_DV/ETHCRS_DV
HD55/D55/ETHTX_ER/reserved
HD53/D53
AB9
V
AB10
AB11
AB12
AB13
AB14
AB15
AB16
AB17
AB18
AB19
AB20
AB21
AB22
DDH
GND
HD37/D37/reserved
HD34/D34/reserved
HD50/D50
HD49/D49/ETHTXD3/reserved
HD48/D48/ETHTXD2/reserved
HD47/D47/ETHTXD1
HD45/D45
V
DDH
A4
A5
V
HD44/D44
DD
HD14
HD12
HD41/D41/ETHRXD1
HD39/D39/reserved
HD36/D36/reserved
A1
HD10
HD63/D63
HD59/D59/ETHMDIO
GND
V
DD
MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 13
12
Freescale Semiconductor
Electrical Characteristics
2
Electrical Characteristics
This document contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing
specifications. For additional information, see the MSC8126 Reference Manual.
2.1
Maximum Ratings
CAUTION
This device contains circuitry protecting against damage
due to high static voltage or electrical fields; however,
normal precautions should be taken to avoid exceeding
maximum voltage ratings. Reliability is enhanced if unused
inputs are tied to an appropriate logic voltage level (for
example, either GND or V ).
DD
In calculating timing requirements, adding a maximum value of one specification to a minimum value of another specification
does not yield a reasonable sum. A maximum specification is calculated using a worst case variation of process parameter values
in one direction. The minimum specification is calculated using the worst case for the same parameters in the opposite direction.
Therefore, a “maximum” value for a specification never occurs in the same device with a “minimum” value for another
specification; adding a maximum to a minimum represents a condition that can never exist.
Table 2 describes the maximum electrical ratings for the MSC8126.
Table 2. Absolute Maximum Ratings
Rating
Symbol
Value
Unit
Core and PLL supply voltage
I/O supply voltage
V
–0.2 to 1.6
–0.2 to 4.0
–0.2 to 4.0
V
V
V
DD
V
DDH
Input voltage
V
IN
Maximum operating temperature:
• 400 MHz
• 500 MHz
T
J
J
105
90
°C
°C
Minimum operating temperature
• 400 MHz
• 500 MHz
T
–40
0
°C
°C
Storage temperature range
T
–55 to +150
°C
STG
Notes: 1. Functional operating conditions are given in Table 3.
2. Absolute maximum ratings are stress ratings only, and functional operation at the maximum is not guaranteed. Stress beyond
the listed limits may affect device reliability or cause permanent damage.
3. Section 3.5, Thermal Considerations includes a formula for computing the chip junction temperature (T ).
J
MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 13
Freescale Semiconductor
13
Electrical Characteristics
2.2
Recommended Operating Conditions
Table 3 lists recommended operating conditions. Proper device operation outside of these conditions is not guaranteed.
Table 3. Recommended Operating Conditions
Rating
Symbol
Value
Unit
Core and PLL supply voltage:
• Standard
V
DD
V
CCSYN
— 400 MHz
— 500 MHz
• Reduced (300 and 400 MHz)
1.14 to 1.26
1.16 to 1.24
1.07 to 1.13
V
V
V
I/O supply voltage
Input voltage
V
3.135 to 3.465
V
V
DDH
V
–0.2 to V
+0.2
DDH
IN
Operating temperature range:
• Standard
• Extended
T
T
0 to 90
–40 to 105
°C
°C
J
J
2.3
Thermal Characteristics
Table 4 describes thermal characteristics of the MSC8126 for the FC-PBGA packages.
Table 4. Thermal Characteristics for the MSC8126
FC-PBGA
20 × 20 mm5
Characteristic
Symbol
Unit
Natural
200 ft/min
Convection
(1 m/s) airflow
1, 2
Junction-to-ambient
R
R
R
R
26
19
9
21
15
°C/W
°C/W
°C/W
°C/W
°C/W
θJA
θJA
θJB
θJC
1, 3
Junction-to-ambient, four-layer board
4
Junction-to-board (bottom)
5
Junction-to-case
0.9
1
6
Junction-to-package-top
Ψ
JT
Notes: 1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)
temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal
resistance.
2. Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal.
3. Per JEDEC JESD51-6 with the board horizontal.
4. Thermal resistance between the die and the printed circuit board per JEDEC JESD 51-8. Board temperature is measured on
the top surface of the board near the package.
5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method
1012.1).
6. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature
per JEDEC JESD51-2.
Section 3.5, Thermal Considerations provides a detailed explanation of these characteristics.
MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 13
14
Freescale Semiconductor
Electrical Characteristics
2.4
DC Electrical Characteristics
This section describes the DC electrical characteristics for the MSC8126. The measurements in Table 5 assume the
following system conditions:
•
•
T = 25 °C
A
VDD
=
— 400 MHz = 1.14–1.26 V
— 500 MHz = 1.16–1.24 V
DC
DC
•
•
VDDH = 3.3 V ± 5% V
DC
GND = 0 V
DC
Note: The leakage current is measured for nominal VDDH and VDD
.
Table 5. DC Electrical Characteristics
Characteristic
Symbol
Min
Typical
Max
Unit
1
Input high voltage , all inputs except CLKIN
V
2.0
GND
2.4
—
0
3.465
0.4
3.465
0.4
1
V
V
IH
1
Input low voltage
V
IL
CLKIN input high voltage
CLKIN input low voltage
V
3.0
0
V
IHC
V
I
GND
–1.0
–1.0
–1.0
–1.0
2.0
V
ILC
Input leakage current, V = V
0.09
0.09
0.09
0.09
3.0
µA
µA
µA
µA
V
IN
DDH
IN
Tri-state (high impedance off state) leakage current, V = V
I
1
IN
DDH
OZ
2
Signal low input current, V = 0.4 V
I
1
IL
L
2
Signal high input current, V = 2.0 V
I
1
IH
H
Output high voltage, I = –2 mA,
V
—
OH
OH
except open drain pins
Output low voltage, I = 3.2 mA
V
—
—
0
2
0.4
4
V
OL
OL
V
PLL supply current
I
mA
CCSYN
VCCSYN
Internal supply current:
3
•
•
Wait mode
Stop mode
I
I
—
—
375
290
—
—
mA
mA
DDW
3
DDS
4
Typical power 400 MHz at 1.2 V
P
—
1.15
—
W
Notes: 1. See Figure 5 for undershoot and overshoot voltages.
2. Not tested. Guaranteed by design.
3. Measured for 1.2 V core at 25°C junction temperature.
4. The typical power values were measured using an EFR code with the device running at a junction temperature of 25°C. No
peripherals were enabled and the ICache was not enabled. The source code was optimized to use all the ALUs and AGUs and
®
all four cores. It was created using CodeWarrior 2.5. These values are provided as examples only. Power consumption is
application dependent and varies widely. To assure proper board design with regard to thermal dissipation and maintaining
proper operating temperatures, evaluate power consumption for your application and use the design guidelines in Chapter 4 of
this document and in MSC8102, MSC8122, and MSC8126 Thermal Management Design Guidelines (AN2601).
MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 13
Freescale Semiconductor
15
Electrical Characteristics
VDDH + 17%
VIH
V
DDH + 8%
VDDH
GND
GND – 0.3 V
GND – 0.7 V
VIL
Must not exceed 10% of clock period
Figure 5. Overshoot/Undershoot Voltage for VIH and VIL
2.5
AC Timings
The following sections include illustrations and tables of clock diagrams, signals, and parallel I/O outputs and inputs. When
systems such as DSP farms are developed using the DSI, use a device loading of 4 pF per pin. AC timings are based on a 20 pF
load, except where noted otherwise, and a 50 Ω transmission line. For loads smaller than 20 pF, subtract 0.06 ns per pF down
to 10 pF load. For loads larger than 20 pF, add 0.06 ns for SIU/Ethernet/DSI delay and 0.07 ns for GPIO/TDM/timer delay.
When calculating overall loading, also consider additional RC delay.
2.5.1
Output Buffer Impedances
Table 6. Output Buffer Impedances
Output Buffers
Typical Impedance (Ω)
System bus
50
50
50
Memory controller
Parallel I/O
Note:
These are typical values at 65°C. The impedance may vary by ±25% depending on device process and operating temperature.
2.5.2
Start-Up Timing
Starting the device requires coordination among several input sequences including clocking, reset, and power. Section 2.5.3
describes the clocking characteristics. Section 2.5.4 describes the reset and power-up characteristics. You must use the
following guidelines when starting up an MSC8126 device:
•
•
PORESET and TRST must be asserted externally for the duration of the power-up sequence. See Table 11 for timing.
If possible, bring up the VDD and VDDH levels together. For designs with separate power supplies, bring up the VDD
levels and then the VDDH levels (see Figure 7).
•
•
CLKIN should start toggling at least 16 cycles (starting after VDDH reaches its nominal level) before PORESET
deassertion to guarantee correct device operation (see Figure 6 and Figure 7).
CLKIN must not be pulled high during VDDH power-up. CLKIN can toggle during this period.
Note: See Section 3.1 for start-up sequencing recommendations and Section 3.2 for power supply design
recommendations.
The following figures show acceptable start-up sequence examples. Figure 6 shows a sequence in which VDD and VDDH are
raised together. Figure 7 shows a sequence in which VDDH is raised after VDD and CLKIN begins to toggle as VDDH rises.
MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 13
16
Freescale Semiconductor
Electrical Characteristics
V
V
= Nominal Value
= Nominal Value
DDH
DD
1
V
Nominal Level
3.3 V
2.2 V
DDH
1.2 V
o.5 V
V
Nominal Level
DD
Time
PORESET/TRST Deasserted
CLKIN Starts Toggling
PORESET/TRST Asserted
V
/V
Applied
DD DDH
Figure 6. Start-Up Sequence: VDD and VDDH Raised Together
V
V
= Nominal
= Nominal
DDH
DD
1
V
Nominal
3.3 V
DDH
1.2 V
o.5 V
V
Nominal
DD
Time
PORESET/TRST asserted
PORESET/TRST deasserted
CLKIN starts toggling
applied
V
applied
DD
V
DDH
Figure 7. Start-Up Sequence: VDD Raised Before VDDH with CLKIN Started with VDDH
MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 13
Freescale Semiconductor
17
Electrical Characteristics
In all cases, the power-up sequence must follow the guidelines shown in Figure 8.
V
3.3 V
B
VDDH (IO)
A
1.2 V
VDD/VCCSYN
t (time)
Figure 8. Power-Up Sequence for VDDH and VDD/VCCSYN
The following rules apply:
1. During time interval A, VDDH should always be equal to or less than the VDD/VCCSYN voltage level.
The duration of interval A should be kept below 10 ms.
2. The duration of timing interval B should be kept as small as possible and less than 10 ms.
2.5.3
Clock and Timing Signals
The following sections include a description of clock signal characteristics. Table 7 shows the maximum frequency values for
internal (Core, Reference, Bus, and DSI) and external (CLKIN and CLKOUT) clocks. The user must ensure that maximum
frequency values are not exceeded.
Table 7. Maximum Frequencies
Characteristic
Maximum in MHz
Core frequency
400/500
Reference frequency (REFCLK)
Internal bus frequency (BLCK)
133/166
133/166
DSI clock frequency (HCLKIN)
HCLKIN ≤ (min{100 MHz, CLKOUT})
133/166
External clock frequency (CLKIN or CLKOUT)
Table 8. Clock Frequencies
400 MHz Device
500 MHz Device
Characteristics
Symbol
Min
Max
Min
Max
CLKIN frequency
F
20
40
133.3
133.3
133.3
133.3
400
20
40
166.7
166.7
166.7
166.7
500
CLKIN
BCLK frequency
F
BCLK
Reference clock (REFCLK) frequency
Output clock (CLKOUT) frequency
SC140 core clock frequency
F
40
40
REFCLK
CLKOUT
F
40
40
F
200
200
CORE
Note:
The rise and fall time of external clocks should be 5 ns maximum
MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 13
18
Freescale Semiconductor
Electrical Characteristics
Table 9. System Clock Parameters
Min
Characteristic
Max
Unit
Phase jitter between BCLK and CLKIN
—
20
0.3
ns
MHz
ns
CLKIN frequency
see Table 8
CLKIN slope
—
3
PLL input clock (after predivider)
20
100
MHz
PLL output frequency (VCO output)
800
MHz
MHz
MHz
•
•
400 MHz core
500 MHz core
1600
2000
1
CLKOUT frequency jitter
—
200
500
ps
ps
1
CLKOUT phase jitter with CLKIN phase jitter of ±100 ps
—
Notes: 1. Peak-to-peak.
2. Not tested. Guaranteed by design.
2.5.4
Reset Timing
The MSC8126 has several inputs to the reset logic:
•
•
•
•
•
•
Power-on reset (PORESET)
External hard reset (HRESET)
External soft reset (SRESET)
Software watchdog reset
Bus monitor reset
Host reset command through JTAG
All MSC8126 reset sources are fed into the reset controller, which takes different actions depending on the source of the reset.
The reset status register indicates the most recent sources to cause a reset. Table 10 describes the reset sources.
Table 10. Reset Sources
Name
Direction
Description
Power-on reset
(PORESET)
Input
Initiates the power-on reset flow that resets the MSC8126 and configures various attributes of the
MSC8126. On PORESET, the entire MSC8126 device is reset. SPLL states is reset, HRESET and
SRESET are driven, the SC140 extended cores are reset, and system configuration is sampled. The
clock mode (MODCK bits), reset configuration mode, boot mode, Chip ID, and use of either a DSI 64
bits port or a System Bus 64 bits port are configured only when PORESET is asserted.
External hard
reset (HRESET)
Input/ Output
Initiates the hard reset flow that configures various attributes of the MSC8126. While HRESET is
asserted, SRESET is also asserted. HRESET is an open-drain pin. Upon hard reset, HRESET and
SRESET are driven, the SC140 extended cores are reset, and system configuration is sampled. The
most configurable features are reconfigured. These features are defined in the 32-bit hard reset
configuration word described in Hard Reset Configuration Word section of the Reset chapter in the
MSC8126 Reference Manual.
External soft reset
(SRESET)
Input/ Output
Initiates the soft reset flow. The MSC8126 detects an external assertion of SRESET only if it occurs
while the MSC8126 is not asserting reset. SRESET is an open-drain pin. Upon soft reset, SRESET is
driven, the SC140 extended cores are reset, and system configuration is maintained.
Software
watchdog reset
Internal
Internal
Internal
When the MSC8126 watchdog count reaches zero, a software watchdog reset is signalled. The
enabled software watchdog event then generates an internal hard reset sequence.
Bus monitor reset
When the MSC8126 bus monitor count reaches zero, a bus monitor hard reset is asserted. The
enabled bus monitor event then generates an internal hard reset sequence.
Host reset
command through
the TAP
When a host reset command is written through the Test Access Port (TAP), the TAP logic asserts the
soft reset signal and an internal soft reset sequence is generated.
Table 11 summarizes the reset actions that occur as a result of the different reset sources.
MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 13
Freescale Semiconductor
19
Electrical Characteristics
Table 11. Reset Actions for Each Reset Source
Power-On
Reset
(PORESET)
Hard Reset (HRESET)
Soft Reset (SRESET)
JTAG Command:
Reset Action/Reset Source
External or Internal
External only (SoftwareWatchdogor
Bus Monitor)
External
EXTEST, CLAMP, or
HIGHZ
Configuration pins sampled (Refer to
Yes
No
No
No
Section 2.5.4.1 for details).
SPLL state reset
Yes
Yes
No
No
No
No
No
No
System reset configuration write through
the DSI
System reset configuration write though
the system bus
Yes
Yes
No
No
HRESET driven
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
SIU registers reset
IPBus modules reset (TDM, UART,
Timers, DSI, IPBus master, GIC, HS, and
GPIO)
Yes
Yes
SRESET driven
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Depends on command
SC140 extended cores reset
MQBS reset
Yes
Yes
2.5.4.1
Power-On Reset (PORESET) Pin
Asserting PORESET initiates the power-on reset flow. PORESET must be asserted externally for at least 16 CLKIN cycles after
VDD and VDDH are both at their nominal levels.
2.5.4.2
Reset Configuration
The MSC8126 has two mechanisms for writing the reset configuration:
•
•
Through the direct slave interface (DSI)
Through the system bus. When the reset configuration is written through the system bus, the MSC8126 acts as a
configuration master or a configuration slave. If configuration slave is selected, but no special configuration word is
written, a default configuration word is applied.
Fourteen signal levels (see Chapter 1 for signal description details) are sampled on PORESET deassertion to define the Reset
Configuration Mode and boot and operating conditions:
•
•
•
•
•
•
•
•
RSTCONF
CNFGS
DSISYNC
DSI64
CHIP_ID[0–3]
BM[0–2]
SWTE
MODCK[1–2]
MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 13
20
Freescale Semiconductor
Electrical Characteristics
2.5.4.3
Reset Timing Tables
Table 12 and Figure 9 describe the reset timing for a reset configuration write through the direct slave interface (DSI) or
through the system bus.
Table 12. Timing for a Reset Configuration Write through the DSI or System Bus
No.
Characteristics
Expression
Min
Max
Unit
1
Required external PORESET duration minimum
16/CLKIN
•
•
•
CLKIN = 20 MHz
CLKIN = 133 MHz (400 MHz core)
CLKIN = 166 MHz (500 MHz core)
800
120
96
800
—
—
ns
ns
ns
2
3
Delay from deassertion of external PORESET to deassertion of internal
PORESET
1024/CLKIN
•
CLKIN = 20 MHz to 166 MHz
6.17
51.2
µs
Delay from de-assertion of internal PORESET to SPLL lock
6400/(CLKIN/RDF)
(PLL reference
clock-division factor)
•
•
•
CLKIN = 20 MHz (RDF = 1)
CLKIN = 133 MHz (RDF = 2) (400 MHz core)
CLKIN = 166 MHz (RDF = 2) (500 MHz core)
320
96
77
320
96
77
µs
µs
µs
5
6
7
Delay from SPLL to HRESET deassertion
REFCLK = 40 MHz to 166 MHz
•
512/REFCLK
515/REFCLK
3.08
12.8
µs
Delay from SPLL lock to SRESET deassertion
REFCLK = 40 MHz to 166 MHz
•
3.10
3
12.88
—
µs
ns
Setup time from assertion of RSTCONF, CNFGS, DSISYNC, DSI64,
CHIP_ID[0–3], BM[0–2], SWTE, and MODCK[1–2] before deassertion of
PORESET
8
Hold time from deassertion of PORESET to deassertion of RSTCONF,
CNFGS, DSISYNC, DSI64, CHIP_ID[0–3], BM[0–2], SWTE, and
MODCK[1–2]
5
—
ns
Note:
Timings are not tested, but are guaranteed by design.
RSTCONF, CNFGS, DSISYNC, DSI64
CHIP_ID[0–3], BM[0–2], SWTE, MODCK[1–2]
pins are sampled
1
PORESET
Input
Host programs
Reset Configuration
Word
PORESET
Internal
SPLL is locked
(no external indication)
1 + 2
MODCK[3–5]
HRESET
Output (I/O)
3
2
SRESET
Output (I/O)
SPLL
locking period
Reset configuration write
sequence during this
period.
5
6
Figure 9. Timing Diagram for a Reset Configuration Write
MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 13
Freescale Semiconductor
21
Electrical Characteristics
2.5.5
System Bus Access Timing
Core Data Transfers
2.5.5.1
Generally, all MSC8126 bus and system output signals are driven from the rising edge of the reference clock (REFCLK). The
REFCLK is the CLKIN signal. Memory controller signals, however, trigger on four points within a REFCLK cycle. Each cycle
is divided by four internal ticks: T1, T2, T3, and T4. T1 always occurs at the rising edge of REFCLK (and T3 at the falling
edge), but the spacing of T2 and T4 depends on the PLL clock ratio selected, as Table 13 shows.
Table 13. Tick Spacing for Memory Controller Signals
Tick Spacing (T1 Occurs at the Rising Edge of REFCLK)
BCLK/SC140 clock
T2
T3
T4
1:4, 1:6, 1:8, 1:10
1/4 REFCLK
1/6 REFCLK
2/10 REFCLK
1/2 REFCLK
1/2 REFCLK
1/2 REFCLK
3/4 REFCLK
4/6 REFCLK
7/10 REFCLK
1:3
1:5
Figure 10 is a graphical representation of Table 13.
REFCLK
for 1:4, 1:6, 1:8, 1:10
T1
T1
T1
T2
T3
T3
T3
T4
REFCLK
REFCLK
for 1:3
T2
T4
for 1:5
T2
T4
Figure 10. Internal Tick Spacing for Memory Controller Signals
MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 13
22
Freescale Semiconductor
Electrical Characteristics
The UPM machine and GPCM machine outputs change on the internal tick selected by the memory controller
configuration. The AC timing specifications are relative to the internal tick. SDRAM machine outputs change only
on the REFCLK rising edge.
Table 14. AC Timing for SIU Inputs
Value for Bus Speed in MHz
Ref =
No.
Characteristic
Ref = CLKIN
Units
CLKOUT
133
166
133
10
Hold time for all signals after the 50% level of the REFCLK rising edge
0.5
3.0
0.5
3.0
0.5
3.0
ns
ns
11a
ARTRY/ABB set-up time before the 50% level of the REFCLK rising
edge
11b
DBG/DBB/BG/BR/TC set-up time before the 50% level of the
REFCLK rising edge
3.3
2.9
3.3
2.9
3.3
2.9
ns
ns
11c
11d
AACK set-up time before the 50% level of the REFCLK rising edge
TA/TEA/PSDVAL set-up time before the 50% level of the REFCLK
rising edge
•
•
Data-pipeline mode
Non-pipeline mode
3.4
4.0
3.4
4.0
3.4
4.0
ns
ns
12
Data bus set-up time before REFCLK rising edge in Normal mode
•
•
Data-pipeline mode
Non-pipeline mode
1.8
4.0
1.7
4.0
1.8
4.0
ns
ns
1
13
Data bus set-up time before the 50% level of the REFCLK rising edge
in ECC and PARITY modes
•
•
Data-pipeline mode
Non-pipeline mode
2.0
7.3
2.0
7.3
2.0
7.3
ns
ns
1
14
DP set-up time before the 50% level of the REFCLK rising edge
•
•
Data-pipeline mode
Non-pipeline mode
2.0
6.1
2.0
6.1
2.0
6.1
ns
ns
15a
15b
16
TS and Address bus set-up time before the 50% level of the REFCLK
rising edge
•
•
Extra cycle mode (SIUBCR[EXDD] = 0)
No extra cycle mode (SIUBCR[EXDD] = 1)
3.6
5.0
3.6
5.0
3.8
5.0
ns
ns
Address attributes: TT/TBST/TSZ/GBL set-up time before the 50%
level of the REFCLK rising edge
•
•
Extra cycle mode (SIUBCR[EXDD] = 0)
No extra cycle mode (SIUBCR[EXDD] = 1)
3.5
4.4
3.5
4.4
3.5
4.4
ns
ns
PUPMWAIT signal set-up time before the 50% level of the REFCLK
rising edge
3.7
3.7
3.7
ns
3
17
18
IRQx setup time before the 50% level; of the REFCLK rising edge
4.0
4.0
4.0
ns
ns
3
IRQx minimum pulse width
6.0 + T
6.0 + T
6.0 + T
REFCLK
REFCLK
REFCLK
Notes: 1. Timings specifications 13 and 14 in non-pipeline mode are more restrictive than MSC8102 timings.
2. Values are measured from the 50% TTL transition level relative to the 50% level of the REFCLK rising edge.
3. Guaranteed by design
MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 13
Freescale Semiconductor
23
Electrical Characteristics
Table 15. AC Timing for SIU Outputs
Value for Bus Speed in MHz
No.
Characteristic
Ref = CLKIN
133
Ref = CLKOUT Units
133
166
2
30
31
Minimum delay from the 50% level of the REFCLK for all signals
0.8
4.9
0.8
4.9
1.0
5.8
ns
ns
PSDVAL/TEA/TA max delay from the 50% level of the REFCLK
rising edge
32a
Address bus max delay from the 50% level of the REFCLK rising
edge
•
•
Multi-master mode (SIUBCR[EBM] = 1)
Single-master mode (SIUBCR[EBM] = 0)
5.5
4.2
5.5
3.9
6.4
5.1
ns
ns
32b
32c
Address attributes: TT[0–1]/TBST/TSZ/GBL max delay from the 50%
level of the REFCLK rising edge
5.1
5.7
4.2
5.1
5.7
4.2
6.0
6.6
5.1
ns
ns
ns
Address attributes: TT[2–4]/TC max delay from the 50% level of the
REFCLK rising edge
32d
33a
BADDR max delay from the 50% level of the REFCLK rising edge
Data bus max delay from the 50% level of the REFCLK rising edge
•
•
Data-pipeline mode
Non-pipeline mode
3.9
6.1
3.7
6.1
4.8
7.0
ns
ns
33b
DP max delay from the 50% level of the REFCLK rising edge
•
•
Data-pipeline mode
Non-pipeline mode
5.3
6.5
5.3
6.5
6.2
7.4
ns
ns
34
Memory controller signals/ALE/CS[0–4] max delay from the 50%
level of the REFCLK rising edge
4.2
4.7
4.5
3.9
4.7
4.5
5.1
5.6
5.4
ns
ns
ns
35a
35b
DBG/BG/BR/DBB max delay from the 50% level of the REFCLK
rising edge
AACK/ABB/TS/CS[5–7] max delay from the 50% level of the
REFCLK rising edge
Notes: 1. Values are measured from the 50% level of the REFCLK rising edge to the 50% signal level and assume a 20 pF load except
where otherwise specified.
2. The load for specification 30 is 10 pF. The load for the other specifications in this table is 20 pF. For a 15 pF load, subtract 0.3
ns from the listed value.
3. The maximum bus frequency depends on the mode:
4. In 60x-compatible mode connected to another MSC8126 device, the frequency is determined by adding the input and output
longest timing values, which results in the total delay for 20 pF output capacitance. You must also account for other
influences that can affect timing, such as on-board clock skews, on-board noise delays, and so on.
• In single-master mode, the frequency depends on the timing of the devices connected to the MSC8126.
• To achieve maximum performance on the bus in single-master mode, disable the DBB signal by writing a 1 to the
SIUMCR[BDD] bit. See the SIU chapter in the MSC8122 Reference Manual for details.
MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 13
24
Freescale Semiconductor
Electrical Characteristics
REFCLK
10
11
AACK/ARTRY/TA/TEA/DBG/BG/BR
PSDVAL/ABB/DBB inputs
10
12
13
Data bus inputs—normal mode
10
Data bus inputs—ECC and parity modes
DP inputs
14
15
10
18
Address bus/TS /TT[0–4]/TC[0–2]/
TBST/TSZ[0–3]/GBL inputs
PUPMWAIT input
16
17
IRQx inputs
30
Min delay for all output pins
31
PSDVAL/TEA/TA outputs
32a/b
Address bus/TT[0–4]/TC[0–2]/TBST/TSZ[0–3]/GBL outputs
32c
33a
BADDR outputs
Data bus outputs
DP outputs
33b
34
Memory controller/ALE outputs
35
AACK/ABB/TS/DBG/BG/BR/DBB/CS outputs
Figure 11. SIU Timing Diagram
MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 13
Freescale Semiconductor
25
Electrical Characteristics
2.5.5.2
CLKIN to CLKOUT Skew
Table 17 describes the CLKOUT-to-CLKIN skew timing.
Table 16. CLKOUT Skew
Characteristic
No.
Min1
Max1
Units
20
21
22
Rise-to-rise skew
Fall-to-fall skew
0
0.85
1.0
—
ns
ns
ns
–0.8
2.8
CLKOUT phase high and low (1.2 V, 133 MHz)
Notes: 1. A positive number indicates that CLKOUT precedes CLKIN, A negative number indicates that CLKOUT follows CLKIN.
2. Skews are measured in clock mode 29, with a CLKIN:CLKOUT ratio of 1:1. The same skew is valid for all clock modes.
3. CLKOUT skews are measured using a load of 10 pF.
4. CLKOUT skews and phase are not measured for 500/166 Mhz parts because these parts only use CLKIN mode.
For designs that use the CLKOUT synchronization mode, use the skew values listed in Table 16 to adjust the rise-to-fall timing
values specified for CLKIN synchronization. Figure 12 shows the relationship between the CLKOUT and CLKIN timings.
CLKIN
CLKOUT
21
20
Figure 12. CLKOUT and CLKIN Signals.
MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 13
26
Freescale Semiconductor
Electrical Characteristics
2.5.5.3
DMA Data Transfers
Table 17 describes the DMA signal timing.
Table 17. DMA Signals
Ref = CLKOUT
(1.2 V only)
Ref = CLKIN
No.
Characteristic
Units
Min
Max
Min
Max
37
38
39
40
41
DREQ set-up time before the 50% level of the falling edge of REFCLK
DREQ hold time after the 50% level of the falling edge of REFCLK
DONE set-up time before the 50% level of the rising edge of REFCLK
DONE hold time after the 50% level of the rising edge of REFCLK
DACK/DRACK/DONE delay after the 50% level of the REFCLK rising edge
5.0
0.5
5.0
0.5
0.5
—
—
5.0
0.5
5.0
0.5
0.5
—
—
ns
ns
ns
ns
ns
—
—
—
—
7.5
8.4
The DREQ signal is synchronized with REFCLK. To achieve fast response, a synchronized peripheral should assert DREQ
according to the timings in Table 17. Figure 13 shows synchronous peripheral interaction.
REFCLK
38
37
DREQ
40
39
DONE
41
DACK/DONE/DRACK
Figure 13. DMA Signals
MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 13
Freescale Semiconductor
27
Electrical Characteristics
2.5.6
DSI Timing
The timings in the following sections are based on a 20 pF capacitive load.
2.5.6.1 DSI Asynchronous Mode
Table 18. DSI Asynchronous Mode Timing
No.
Characteristics
Min
Max
Unit
1
100
101
102
Attributes set-up time before strobe (HWBS[n]) assertion
1.5
1.3
—
—
—
ns
ns
1
Attributes hold time after data strobe deassertion
Read/Write data strobe deassertion width:
•
DCR[HTAAD] = 1
— Consecutive access to the same DSI
— Different device with DCR[HTADT] = 01
— Different device with DCR[HTADT] = 10
— Different device with DCR[HTADT] = 11
DCR[HTAAD] = 0
1.8 + T
5 + T
5 + (1.5 × T
5 + (2.5 × T
1.8 + T
ns
ns
ns
ns
ns
REFCLK
REFCLK
)
)
REFCLK
REFCLK
•
REFCLK
103
104
105
106
107
108
Read data strobe deassertion to output data high impedance
Read data strobe assertion to output data active from high impedance
Output data hold time after read data strobe deassertion
Read/Write data strobe assertion to HTA active from high impedance
Output data valid to HTA assertion
—
8.5
—
—
—
—
ns
ns
ns
ns
ns
2.0
2.2
2.2
3.2
2
Read/Write data strobe assertion to HTA valid
•
•
1.1 V core
1.2 V core
—
—
7.4
6.7
ns
ns
109
110
111
Read/Write data strobe deassertion to output HTA high impedance.
(DCR[HTAAD] = 0, HTA at end of access released at logic 0)
—
—
—
6.5
ns
Read/Write data strobe deassertion to output HTA deassertion.
(DCR[HTAAD] = 1, HTA at end of access released at logic 1)
6.5
ns
Read/Write data strobe deassertion to output HTA high impedance.
(DCR[HTAAD] = 1, HTA at end of access released at logic 1
•
•
•
DCR[HTADT] = 01
DCR[HTADT] = 10
DCR[HTADT] = 11
5 + T
5 + (1.5 × T
5 + (2.5 × T
ns
ns
ns
REFCLK
)
)
REFCLK
REFCLK
112
201
202
Read/Write data strobe assertion width
1.8 + T
—
—
ns
ns
REFCLK
Host data input set-up time before write data strobe deassertion
1.0
Host data input hold time after write data strobe deassertion
•
•
1.1 V core
1.2 V core
1.7
1.5
—
—
ns
ns
Notes: 1. Attributes refers to the following signals: HCS, HA[11–29], HCID[0–4], HDST, HRW, HRDS, and HWBSn.
2. This specification is tested in dual-strobe mode. Timing in single-strobe mode is guaranteed by design.
3. All values listed in this table are tested or guaranteed by design.
MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 13
28
Freescale Semiconductor
Electrical Characteristics
Figure 14 shows DSI asynchronous read signals timing.
HCS
HA[11–29]
HCID[0–4]
HDST
1
HRW
HWBSn
2
100
101
112
1
HDBSn
2
HRDS
102
103
107
105
104
HD[0–63]
109
106
3
HTA
108
110
4
HTA
111
Notes: 1. Used for single-strobe mode access.
2. Used for dual-strobe mode access.
3. HTA released at logic 0 (DCR[HTAAD] = 0) at end of access; used with
pull-down implementation.
4. HTA released at logic 1 (DCR[HTAAD] = 1) at end of access; used with pull-up
implementation.
Figure 14. Asynchronous Single- and Dual-Strobe Modes Read Timing Diagram
MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 13
Freescale Semiconductor
29
Electrical Characteristics
Figure 15 shows DSI asynchronous write signals timing.
HCS
HA[11–29]
HCID[0–4]
HDST
1
101
102
HRW
100
2
HRDS
112
1
2
HDBSn
HWBSn
201
202
HD[0–63]
109
106
108
3
HTA
110
4
HTA
111
Notes: 1. Used for single-strobe mode access.
2. Used for dual-strobe mode access.
3. HTA released at logic 0 (DCR[HTAAD] = 0) at end of access; used with pull-down implementation.
4. HTA released at logic 1 (DCR[HTAAD] = 1) at end of access; used with pull-up implementation.
Figure 15. Asynchronous Single- and Dual-Strobe Modes Write Timing Diagram
Figure 16 shows DSI asynchronous broadcast write signals timing.
HCS
HA[11–29]
HCID[0–4]
HDST
1
101
102
HRW
100
2
HRDS
112
1
2
HDBSn
HWBSn
201
202
HD[0–63]
Notes: 1. Used for single-strobe mode access.
2. Used for dual-strobe mode access.
Figure 16. Asynchronous Broadcast Write Timing Diagram
MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 13
30
Freescale Semiconductor
Electrical Characteristics
2.5.6.2 DSI Synchronous Mode
Table 19. DSI Inputs—Synchronous Mode
No.
Characteristic
Expression
Min
Max
Units
1, 2
120
121
122
123
124
125
126
127
HCLKIN Cycle Time
HTC
10.0
4.0
4.0
1.2
0.4
1.3
1.2
1.5
55.6
33.3
33.3
—
ns
ns
ns
ns
ns
ns
ns
ns
HCLKIN high Pulse Width
HCLKIN low Pulse Width
HA[11–29] inputs set-up time
HD[0–63] inputs set-up time
HCID[0–4] inputs set-up time
All other inputs set-up time
All inputs hold time
(0.5 0.1) × HTC
(0.5 0.1) × HTC
—
—
—
—
—
—
—
—
—
Notes: 1. Values are based on a frequency range of 18–100 MHz.
2. Refer to Table 7 for HCLKIN frequency limits.
Table 20. DSI Outputs—Synchronous Mode
Characteristic
No.
Min
Max
Units
128
129
130
131
132
133
134
135
HCLKIN high to HD[0–63] output active
2.0
—
—
6.3
—
ns
ns
ns
ns
ns
ns
ns
ns
HCLKIN high to HD[0–63] output valid
HD[0–63] output hold time
1.7
—
HCLKIN high to HD[0–63] output high impedance
HCLKIN high to HTA output active
HCLKIN high to HTA output valid
HTA output hold time
7.6
—
2.0
—
5.9
—
1.7
—
HCLKIN high to HTA high impedance
6.3
120
122
121
127
HCLKIN
123
HA[11–29] input signals
127
127
124
HD[0–63] input signals
125
HCID[0–4] input signals
127
126
All other input signals
131
130
129
128
HD[0–63] output signals
135
134
133
132
HTA output signal
Figure 17. DSI Synchronous Mode Signals Timing Diagram
MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 13
Freescale Semiconductor
31
Electrical Characteristics
2.5.7
TDM Timing
Table 21. TDM Timing
Ref = CLKIN
No.
Characteristic
Expression
Units
Min
Max
1
300
301
302
303
304
305
306
307
308
309
310
TDMxRCLK/TDMxTCLK
TC
16
7
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TDMxRCLK/TDMxTCLK high pulse width
TDMxRCLK/TDMxTCLK low pulse width
TDM receive all input set-up time
(0.5 0.1) × TC
(0.5 0.1) × TC
7
—
1.3
1.0
2.8
—
—
TDM receive all input hold time
—
2,3
TDMxTCLK high to TDMxTDAT/TDMxRCLK output active
—
2,3
TDMxTCLK high to TDMxTDAT/TDMxRCLK output valid
8.8
—
5
All output hold time
2.5
—
2,3
TDMxTCLK high to TDmXTDAT/TDMxRCLK output high impedance
10.5
8.5
—
2
TDMxTCLK high to TDMXTSYN output valid
—
5
TDMxTSYN output hold time
2.5
Notes: 1. Values are based on a a maximum frequency of 62.5 MHz. The TDM interface supports any frequency below 62.5 MHz.
2. Values are based on 20 pF capacitive load.
3. When configured as an output, TDMxRCLK acts as a second data link. See the MSC8126 Reference Manual for details.
4. CLKOUT synchronization is not supported for cores operating at above 400 MHz.
5. Values are based on 10 pF capacitive load.
300
302
301
304
TDMxRCLK
TDMxRDAT
303
304
303
TDMxRSYN
Figure 18. TDM Inputs Signals
300
302
301
TDMxTCLK
308
307
306
305
TDMxTDAT
TDMxRCLK
309
310
TDMxTSYN
Figure 19. TDM Output Signals
MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 13
32
Freescale Semiconductor
2.5.8
UART Timing
Table 22. UART Timing
No.
Characteristics
Expression
Min
Max
Unit
400
401
402
URXD and UTXD inputs high/low duration
URXD and UTXD inputs rise/fall time
UTXD output rise/fall time
16 × T
160.0
—
10
10
ns
ns
ns
REFCLK
401
401
UTXD, URXD
inputs
400
400
Figure 20. UART Input Timing
402
402
UTXD output
Figure 21. UART Output Timing
MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 13
Freescale Semiconductor
33
2.5.9
Timer Timing
Table 23. Timer Timing
Characteristics
Ref = CLKIN
No.
Unit
Min
Max
500
501
502
503
TIMERx frequency
10.0
4.0
—
—
—
ns
ns
ns
TIMERx Input high period
TIMERx Output low period
4.0
TIMERx Propagations delay from its clock input
•
•
1.1 V core
1.2 V core
3.1
2.8
9.5
8.1
ns
ns
500
501
502
TIMERx (Input)
503
TIMERx (Output)
Figure 22. Timer Timing
2.5.10 Ethernet Timing
2.5.10.1 Management Interface Timing
Table 24. Ethernet Controller Management Interface Timing
Characteristics
No.
Min
Max
Unit
801
802
ETHMDIO to ETHMDC rising edge set-up time
ETHMDC rising edge to ETHMDIO hold time
10
10
—
—
ns
ns
ETHMDC
801
802
Valid
ETHMDIO
Figure 23. MDIO Timing Relationship to MDC
MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 13
34
Freescale Semiconductor
2.5.10.2 MII Mode Timing
Table 25. MII Mode Signal Timing
Characteristics
No.
Min
Max
Unit
803
804
805
ETHRX_DV, ETHRXD[0–3], ETHRX_ER to ETHRX_CLK rising edge set-up time
3.5
3.5
—
—
ns
ns
ETHRX_CLK rising edge to ETHRX_DV, ETHRXD[0–3], ETHRX_ER hold time
ETHTX_CLK to ETHTX_EN, ETHTXD[0–3], ETHTX_ER output delay
•
•
1.1 V core
1.2 V core
1
1
14.6
12.6
ns
ns
ETHRX_CLK
803
804
ETHRX_DV
ETHRXD[0–3]
ETHRX_ER
Valid
ETHTX_CLK
805
ETHTX_EN
Valid
Valid
ETHTXD[0–3]
ETHTX_ER
Figure 24. MII Mode Signal Timing
2.5.10.3 RMII Mode
Table 26. RMII Mode Signal Timing
1.1 V Core
1.2 V Core
No.
Characteristics
Unit
ns
Min
Max
Min
Max
806
807
811
ETHTX_EN,ETHRXD[0–1], ETHCRS_DV, ETHRX_ER to ETHREF_CLK rising
edge set-up time
1.6
—
2
—
—
11
ETHREF_CLK rising edge to ETHRXD[0–1], ETHCRS_DV, ETHRX_ER hold
time
1.6
3
—
1.6
3
ns
ETHREF_CLK rising edge to ETHTXD[0–1], ETHTX_EN output delay.
ETHREF_CLK
12.5
ns
806
807
ETHCRS_DV
ETHRXD[0–1]
ETHRX_ER
Valid
811
ETHTX_EN
ETHTXD[0–1]
Valid
Valid
Figure 25. RMII Mode Signal Timing
MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 13
Freescale Semiconductor
35
2.5.10.4 SMII Mode
Table 27. SMII Mode Signal Timing
Characteristics
No.
Min
Max
Unit
808
809
810
ETHSYNC_IN, ETHRXD to ETHCLOCK rising edge set-up time
ETHCLOCK rising edge to ETHSYNC_IN, ETHRXD hold time
ETHCLOCK rising edge to ETHSYNC, ETHTXD output delay
1.0
1.0
—
—
ns
ns
1
2
•
•
1.1 V core.
1.2 V core.
1.5
6.0
ns
ns
1
2
1.5
5.0
Notes: 1. Measured using a 5 pF load.
2. Measured using a 15 pF load.
ETHCLOCK
808
809
ETHSYNC_IN
ETHRXD
Valid
810
ETHSYNC
ETHTXD
Valid
Valid
Figure 26. SMII Mode Signal Timing
2.5.11 GPIO Timing
Table 28. GPIO Timing
Ref = CLKIN
Ref = CLKOUT
No.
Characteristics
Unit
Min
Max
Min
Max
601
602
603
604
605
REFCLK edge to GPIO out valid (GPIO out delay time)
REFCLK edge to GPIO out not valid (GPIO out hold time)
REFCLK edge to high impedance on GPIO out
—
1.1
—
6.1
—
—
1.3
—
6.9
—
ns
ns
ns
ns
ns
5.4
—
6.2
—
GPIO in valid to REFCLK edge (GPIO in set-up time)
REFCLK edge to GPIO in not valid (GPIO in hold time)
3.5
0.5
3.7
0.5
—
—
MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 13
36
Freescale Semiconductor
REFCLK
601
603
602
GPIO
(Output)
High Impedance
604
605
GPIO
(Input)
Valid
Figure 27. GPIO Timing
2.5.12 EE Signals
Table 29. EE Pin Timing
Type
Number
Characteristics
Min
65
66
EE0 (input)
Asynchronous
4 core clock periods
1 core clock period
EE1 (output)
Synchronous to Core clock
Notes: 1. The core clock is the SC140 core clock. The ratio between the core clock and CLKOUT is configured during power-on-reset.
2. Refer to Table 1-4 on page 1-6 for details on EE pin functionality.
Figure 28 shows the signal behavior of the EE pins.
65
EE0 in
66
EE1 out
Figure 28. EE Pin Timing
2.5.13 JTAG Signals
Table 30. JTAG Timing
All
frequencies
No.
Characteristics
Unit
Min
Max
700
701
702
TCK frequency of operation (1/(T × 4); maximum 25 MHz)
TCK cycle time
0.0
25
—
MHz
ns
C
40.0
TCK clock pulse width measured at V = 1.6 V
M
•
•
High
Low
20.0
16.0
—
—
ns
ns
703
TCK rise and fall times
0.0
3.0
ns
MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 13
Freescale Semiconductor
37
Table 30. JTAG Timing (continued)
Characteristics
All
frequencies
No.
Unit
Min
Max
704
705
706
707
708
709
710
711
712
713
Note:
Boundary scan input data set-up time
Boundary scan input data hold time
TCK low to output data valid
TCK low to output high impedance
TMS, TDI data set-up time
5.0
20.0
0.0
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
30.0
30.0
—
0.0
5.0
TMS, TDI data hold time
20.0
0.0
—
TCK low to TDO data valid
TCK low to TDO high impedance
TRST assert time
20.0
20.0
—
0.0
100.0
30.0
TRST set-up time to TCK low
—
All timings apply to OnCE module data transfers as well as any other transfers via the JTAG port.
701
702
V
M
V
M
V
TCK
(Input)
IH
V
IL
703
703
Figure 29. Test Clock Input Timing Diagram
V
TCK
(Input)
IH
V
IL
704
705
Data
Inputs
Input Data Valid
706
707
Data
Outputs
Output Data Valid
Data
Outputs
Figure 30. Boundary Scan (JTAG) Timing Diagram
MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 13
38
Freescale Semiconductor
V
IH
TCK
(Input)
V
IL
709
708
Input Data Valid
TDI
TMS
(Input)
710
TDO
(Output)
Output Data Valid
711
TDO
(Output)
Figure 31. Test Access Port Timing Diagram
TCK
(Input)
713
TRST
(Input)
712
Figure 32. TRST Timing Diagram
MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 13
Freescale Semiconductor
39
Hardware Design Considerations
3
Hardware Design Considerations
The following sections discuss areas to consider when the MSC8126 device is designed into a system.
3.1
Start-up Sequencing Recommendations
Use the following guidelines for start-up and power-down sequences:
•
•
•
Assert PORESET and TRST before applying power and keep the signals driven low until the power reaches the
required minimum power levels. This can be implemented via weak pull-down resistors.
CLKIN can be held low or allowed to toggle during the beginning of the power-up sequence. However, CLKIN must
start toggling before the deassertion of PORESET and after both power supplies have reached nominal voltage levels.
If possible, bring up VDD/VCCSYN and VDDH together. If it is not possible, raise VDD/VCCSYN first and then bring up
VDDH. VDDH should not exceed VDD/VCCSYN until VDD/VCCSYN reaches its nominal voltage level. Similarly, bring both
voltage levels down together. If that is not possible reverse the power-up sequence, with VDDH going down first and
then VDD/VCCSYN
.
Note: This recommended power sequencing for the MSC8126 is different from the MSC8102. See Section 2.5.2 for
start-up timing specifications.
External voltage applied to any input line must not exceed the I/O supply VDDH by more than 0.8 V at any time, including during
power-up. Some designs require pull-up voltages applied to selected input lines during power-up for configuration purposes.
This is an acceptable exception to the rule. However, each such input can draw up to 80 mA per input pin per device in the
system during start-up.
During the power-up sequence, if VDD rises before VDDH (see Figure 6), current can pass from the VDD supply through the
device ESD protection circuits to the VDDH supply. The ESD protection diode can allow this to occur when VDD exceeds VDDH
by more than 0.8 V. Design the power supply to prevent or minimize this effect using one of the following optional methods:
•
•
Never allow VDD to exceed VDDH + 0.8V.
Design the VDDH supply to prevent reverse current flow by adding a minimum 10 Ω resistor to GND to limit the
current. Such a design yields an initial VDDH level of VDD – 0.8 V before it is enabled.
After power-up, VDDH must not exceed VDD/VCCSYN by more than 2.6 V.
3.2
Power Supply Design Considerations
When used as a drop-in replacement in MSC8102 applications or when implementing a new design, use the guidelines
described in Migrating Designs from the MSC8102 to the MSC8122 (AN2716) and the MSC8126 Design Checklist (AN3374
for optimal system performance. MSC8122 and MSC8126 Power Circuit Design Recommendations and Examples (AN2937)
provides detailed design information. See Section 2.5.2 for start-up timing specifications.
Figure 33 shows the recommended power decoupling circuit for the core power supply. The voltage regulator and the
decoupling capacitors should supply the required device current without any drop in voltage on the device pins. The voltage on
the package pins should not drop below the minimum specified voltage level even for a very short spikes. This can be achieved
by using the following guidelines:
•
For the core supply, use a voltage regulator rated at 1.2 V with nominal rating of at least 3 A. This rating does not
reflect actual average current draw, but is recommended because it resists changes imposed by transient spikes and has
better voltage recovery time than supplies with lower current ratings.
MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 13
40
Freescale Semiconductor
Hardware Design Considerations
•
Decouple the supply using low-ESR capacitors mounted as close as possible to the socket. Figure 33 shows three
capacitors in parallel to reduce the resistance. Three capacitors is a recommended minimum number. If possible, mount
at least one of the capacitors directly below the MSC8126 device.
Maximum IR drop
of 15 mV at 1 A
L
= 2 cm
max
1.2 V
One 0.01 µF capacitor
for every 3 core supply
pads.
Power supply
or
MSC8122
Voltage Regulator
+
-
Bulk/Tantalum capacitors
with low ESR and ESL
(I
= 3 A)
min
High frequency capacitors
(very low ESR and ESL)
Note: Use at least three capacitors.
Each capacitor must be at least 150 μF.
Figure 33. Core Power Supply Decoupling
Each VCC and VDD pin on the MSC8126 device should have a low-impedance path to the board power supply. Similarly, each
GND pin should have a low-impedance path to the ground plane. The power supply pins drive distinct groups of logic on the
chip. The VCC power supply should have at least four 0.1 µF by-pass capacitors to ground located as closely as possible to the
four sides of the package. The capacitor leads and associated printed circuit traces connecting to chip VCC, VDD, and GND should
be kept to less than half an inch per capacitor lead. A four-layer board is recommended, employing two inner layers as VCC and
GND planes.
All output pins on the MSC8126 have fast rise and fall times. PCB trace interconnection length should be minimized to
minimize undershoot and reflections caused by these fast output switching times. This recommendation particularly applies to
the address and data buses. Maximum PCB trace lengths of six inches are recommended. For the DSI control signals in
synchronous mode, ensure that the layout supports the DSI AC timing requirements and minimizes any signal crosstalk.
Capacitance calculations should consider all device loads as well as parasitic capacitances due to the PCB traces. Attention to
proper PCB layout and bypassing becomes especially critical in systems with higher capacitive loads because these loads create
higher transient currents in the VCC, VDD, and GND circuits. Pull up all unused inputs or signals that will be inputs during reset.
Special care should be taken to minimize the noise levels on the PLL supply pins. There is one pair of PLL supply pins:
VCCSYN-GNDSYN. To ensure internal clock stability, filter the power to the VCCSYN input with a circuit similar to the one in
Figure 34. For optimal noise filtering, place the circuit as close as possible to VCCSYN. The 0.01-µF capacitor should be closest
to VCCSYN, followed by the 10-µF capacitor, the 10-nH inductor, and finally the 10-Ω resistor to VDD. These traces should be
kept short and direct. Provide an extremely low impedance path to the ground plane for GNDSYN. Bypass GNDSYN to VCCSYN
by a 0.01-µF capacitor located as close as possible to the chip package. For best results, place this capacitor on the backside of
the PCB aligned with the depopulated void on the MSC8126 located in the square defined by positions, L11, L12, L13, M11,
M12, M13, N11, N12, and N13.
VCCSYN
VDD
10nH
10Ω
10 µF
0.01 µF
Figure 34. VCCSYN Bypass
MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 13
Freescale Semiconductor
41
Hardware Design Considerations
3.3
Connectivity Guidelines
Unused output pins can be disconnected, and unused input pins should be connected to the non-active value, via resistors to
VDDH or GND, except for the following:
•
•
•
•
•
If the DSI is unused (DDR[DSIDIS] is set), HCS and HBCS must pulled up and all the rest of the DSI signals can be
disconnected.
When the DSI uses synchronous mode, HTA must be pulled up. In asynchronous mode, HTA should be pulled either
up or down, depending on design requirements.
HDST can be disconnected if the DSI is in big-endian mode, or if the DSI is in little-endian mode and the
DCR[DSRFA] bit is set.
When the DSI is in 64-bit data bus mode and DCR[BEM] is cleared, pull up HWBS[1–3]/HDBS[1–3]/HWBE[1–3]/
HDBE[1–3] and HWBS[4–7]/HDBS[4–7]/HWBE[4–7]/HDBE[4–7]/PWE[4–7]/PSDDQM[4–7]/PBS[4–7].
When the DSI is in 32-bit data bus mode and DCR[BEM] is cleared, HWBS[1–3]/HDBS[1–3]/HWBE[1–3]/HDBE[1–3]
must be pulled up.
•
•
When the DSI is in asynchronous mode, HBRST and HCLKIN should either be disconnected or pulled up.
When the DSI uses sliding window address mode (DCR[SLDWA] = 1), the external HA[11–13] signals must be
connected (tied) to the correct voltage levels so that the host can perform the first access to the DCR. After reset, the
DSI expects full address mode (DCR[SLDWA] = 0). The DCR address in the DSI memory map is 0x1BE000, which
requires the following connections:
— HA11 must be pulled high (1)
— HA12 must be pulled high (1)
— HA13 must be pulled low (0)
•
•
The following signals must be pulled up: HRESET, SRESET, ARTRY, TA, TEA, PSDVAL, and AACK.
In single-master mode (BCR[EBM] = 0) with internal arbitration (PPC_ACR[EARB] = 0):
— BG, DBG, and TS can be left unconnected.
— EXT_BG[2–3], EXT_DBG[2–3], and GBL can be left unconnected if they are multiplexed to the system bus
functionality. For any other functionality, connect the signal lines based on the multiplexed functionality.
— BR must be pulled up.
— EXT_BR[2–3] must be pulled up if multiplexed to the system bus functionality.
If there is an external bus master (BCR[EBM] = 1):
— BR, BG, DBG, and TS must be pulled up.
•
•
— EXT_BR[2–3], EXT_BG[2–3], and EXT_DBG[2–3] must be pulled up if multiplexed to the system bus
functionality.
In single-master mode, ABB and DBB can be selected as IRQ inputs and be connected to the non-active value. In other
modes, they must be pulled up.
Note: The MSC8126 does not support DLL-enabled mode. For the following two clock schemes, ensure that the DLL is
disabled (that is, the DLLDIS bit in the Hard Reset Configuration Word is set).
•
•
If no system synchronization is required (for example, the design does not use SDRAM), you can use any of the
available clock modes.
In the CLKIN synchronization mode, use the following connections:
— Connect the oscillator output through a buffer to CLKIN.
— Connect the CLKIN buffer output to the slave device (for example, SDRAM) making sure that the delay path
between the clock buffer to the MSC8126 and the SDRAM is equal (that is, has a skew less than 100 ps).
— Valid clock modes in this scheme are: 0, 7, 15, 19, 21, 23, 28, 29, 30, and 31.
•
In CLKOUT synchronization mode (for 1.2 V devices), CLKOUT is the main clock to SDRAM. Use the following
connections:
— Connect the oscillator output through a buffer to CLKIN.
— Connect CLKOUT through a zero-delay buffer to the slave device (for example, SDRAM) using the following
guidelines:
–
The maximum delay between the slave and CLKOUT must not exceed 0.7 ns.
MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 13
42
Freescale Semiconductor
Hardware Design Considerations
–
–
The maximum load on CLKOUT must not exceed 10 pF.
Use a zero-delay buffer with a jitter less than 0.3 ns.
— All clock modes are valid in this clock scheme.
Note: See the Clock chapter in the MSC8122 Reference Manual for details.
•
If the 60x-compatible system bus is not used and SIUMCR[PBSE] is set, PPBS can be disconnected. Otherwise, it
should be pulled up.
•
The following signals: SWTE, DSISYNC, DSI64, MODCK[1–2], CNFGS, CHIPID[0–3], RSTCONF and BM[0–2] are
used to configure the MSC8126 and are sampled on the deassertion of the PORESET signal. Therefore, they should
be tied to GND or VDDH or through a pull-down or a pull-up resistor until the deassertion of the PORESET signal.
•
•
When they are used, INT_OUT (if SIUMCR[INTODC] is cleared), NMI_OUT, and IRQxx (if not full drive) signals must
be pulled up.
When the Ethernet controller is enabled and the SMII mode is selected, GPIO10 and GPIO14 must not be connected
externally to any signal line.
Note: For details on configuration, see the MSC8126 User’s Guide and MSC8126 Reference Manual. For additional
information, refer to the MSC8126 Design Checklist (AN2903).
3.4
External SDRAM Selection
The external bus speed implemented in a system determines the speed of the SDRAM used on that bus. However, because of
differences in timing characteristics among various SDRAM manufacturers, you may have use a faster speed rated SDRAM to
assure efficient data transfer across the bus. For example, for 166 MHz operation, you may have to use 183 or 200 MHz
SDRAM. Always perform a detailed timing analysis using the MSC8126 bus timing values and the manufacturer specifications
for the SDRAM to ensure correct operation within your system design. The output delay listed in SDRAM specifications is
usually given for a load of 30 pF. Scale the number to your specific board load using the typical scaling number provided by
the SDRAM manufacturer.
MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 13
Freescale Semiconductor
43
Ordering Information
3.5
Thermal Considerations
An estimation of the chip-junction temperature, TJ, in °C can be obtained from the following:
TJ = TA + (R JA × PD)
Eqn. 1
θ
where
TA = ambient temperature near the package (°C)
R
JA = junction-to-ambient thermal resistance (°C/W)
θ
PD = PINT + PI/O = power dissipation in the package (W)
PINT = IDD × VDD = internal power dissipation (W)
PI/O = power dissipated from device on output pins (W)
The power dissipation values for the MSC8126 are listed in Table 2-3. The ambient temperature for the device is the air
temperature in the immediate vicinity that would cool the device. The junction-to-ambient thermal resistances are JEDEC
standard values that provide a quick and easy estimation of thermal performance. There are two values in common usage: the
value determined on a single layer board and the value obtained on a board with two planes. The value that more closely
approximates a specific application depends on the power dissipated by other components on the printed circuit board (PCB).
The value obtained using a single layer board is appropriate for tightly packed PCB configurations. The value obtained using a
board with internal planes is more appropriate for boards with low power dissipation (less than 0.02 W/cm2 with natural
convection) and well separated components. Based on an estimation of junction temperature using this technique, determine
whether a more detailed thermal analysis is required. Standard thermal management techniques can be used to maintain the
device thermal junction temperature below its maximum. If TJ appears to be too high, either lower the ambient temperature or
the power dissipation of the chip. You can verify the junction temperature by measuring the case temperature using a small
diameter thermocouple (40 gauge is recommended) or an infrared temperature sensor on a spot on the device case that is painted
black. The MSC8126 device case surface is too shiny (low emissivity) to yield an accurate infrared temperature measurement.
Use the following equation to determine TJ:
TJ = TT + (θJA × PD)
Eqn. 2
where
TT = thermocouple (or infrared) temperature on top of the package (°C)
θ
JA = thermal characterization parameter (°C/W)
PD = power dissipation in the package (W)
Note: See MSC8102, MSC8122, and MSC8126 Thermal Management Design Guidelines (AN2601/D).
4
Ordering Information
Consult a Freescale Semiconductor sales office or authorized distributor to determine product availability and place an order.
Core
Core
Operating
Part
Package Type
Spheres
Frequency Order Number
(MHz)
Voltage Temperature
MSC8126 Flip Chip Plastic Ball Grid Array (FC-PBGA)
Lead-free
Lead-bearing
Lead-free
1.2 V
–40° to 105°C
0° to 90°C
400
MSC8126TVT6400
MSC8126TMP6400
MSC8126VT8000
MSC8126MP8000
500
Lead-bearing
MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 13
44
Freescale Semiconductor
Package Information
5
Package Information
Notes:
1. All dimensions in millimeters.
2. Dimensioning and tolerancing
per ASME Y14.5M–1994.
3. Features are symmetrical about
the package center lines unless
dimensioned otherwise.
4. Maximum solder ball diameter
measured parallel to Datum A.
5. Datum A, the seating plane, is
determined by the spherical
crowns of the solder balls.
6. Parallelism measurement shall
exclude any effect of mark on
top surface of package.
7. Capacitors may not be present
on all devices.
8. Caution must be taken not to
short capacitors or exposed
metal capacitor pads on
package top.
9. FC CBGA (Ceramic) package
code: 5238.
FC PBGA (Plastic) package
code: 5263.
10.Pin 1 indicator can be in the
form of number 1 marking or an
“L” shape marking.
Figure 35. MSC8126 Mechanical Information, 431-pin FC-PBGA Package
6
Product Documentation
•
•
MSC8126 Technical Data Sheet (MSC8126). Details the signals, AC/DC characteristics, clock signal characteristics,
package and pinout, and electrical design considerations of the MSC8126 device.
MSC8126 Reference Manual (MSC8126RM). Includes functional descriptions of the extended cores and all the
internal subsystems including configuration and programming information.
•
•
Application Notes. Cover various programming topics related to the StarCore DSP core and the MSC8126 device.
SC140 DSP Core Reference Manual. Covers the SC3400 core architecture, control registers, clock registers, program
control, and instruction set.
MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 13
Freescale Semiconductor
45
Revision History
7
Revision History
Table 31 provides a revision history for this data sheet.
Table 31. Document Revision History
Revision
Date
Description
0
1
May 2004
Jun. 2004
•
Initial release.
•
•
Updated timing number 32b.
Updated DSI timing specifications.
2
Sep 2004
•
•
•
•
New orderable parts added with other core voltage and temperature options.
Updated thermal characteristics.
In Table 2-14, removed references to 30 pF.
Design guidelines and layout recommendations updated.
3
Nov. 2004
•
•
•
•
•
Added 500 MHz core and 166 MHz bus speed options.
Definitions of GPIO[27–28] updated.
Bus, TDM, and GPIO timing updated. I2C timing changed to GPIO timing.
GPIO[27–28] connections updated. MWBEn replaced with correct name HWBEn.
Design guidelines update.
4
Jan. 2005
•
•
•
•
•
•
Package type changed to FC-PBGA for all frequencies.
Low-voltage 300 MHz power changed to 1.1 V.
HRESET and SRESET definitions updated.
Undershoot and overshoot values added for VDDH
RMII timing updated.
.
Design guidelines updated and reorganized.
5
6
7
8
9
May 2005
May 2005
Jul. 2005
Jul. 2005
Sep. 2005
•
•
•
•
Multiple AC timing specifications updated.
Multiple AC timing specifications updated.
Multiple AC timing specifications updated.
AC specification table layout modified.
•
•
•
•
ETHTX_EN type and TRST description updated.
Package drawing updated.
Clock specifications updated.
Start-up sequence updated.
10
Oct 2005
•
•
VDDH + 10% changed to VDDH + 8% in Figure 2-1.
VDDH +20% changed to VDDH + 17% in Figure 2-1.
11
12
13
Apr 2006
Oct. 2006
Dec. 2007
•
•
Reset timing updated to reflect actual values in Table 2-11.
Added new timings 17 and 18 for IRQ set time and pulse width in Table 2-13
•
•
•
Converted to new data sheet format.
Added PLL supply current to Table 5 in Section 2.4.
Modified Figure 5 in Section 2.4 to make it clear that the time limits for undershoot referred to values
below –0.3 V and not GND.
•
•
•
•
•
Added cross-references between Sections 2.5.2 and Section 3.1 and 3.2.
Added power-sequence guidelines to Sections 2.5.2.
Added CLKIN jitter characteristic specifications to Table 9.
Added additional guidelines to prevent reverse current to Section 3.1.
Added connectivity guidelines for DSI in sliding windows mode to Section 3.3.
MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 13
46
Freescale Semiconductor
Revision History
MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 13
Freescale Semiconductor
47
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Document Number: MSC8126
Rev. 13
12/2007
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