EDC4BV7244-60TG-S [FUJITSU]
Memory IC, 4MX72, CMOS, PDMA168;
| 型号： | EDC4BV7244-60TG-S |
| 厂家： | 
FUJITSU |
| 描述： | Memory IC, 4MX72, CMOS, PDMA168 光电二极管 |
| 文件： | 总8页 (文件大小：134K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
November 1996
Revision 1.0
DATA SHEET
EDC4BV724(2/4)-(60/70)(J/T)G-S
32MByte (4M x 72) CMOS
EDO DRAM Module - 3.3V (ECC), Buffered
General Description
The EDC4BV724(2/4)-(60/70)(J/T)G-S is a high performance, EDO (Extended Data Out) 32-megabyte dynamic RAM module
organized as 4M words by 72 bits, in a 168-pins, dual-in-line (DIMM) memory module with ECC.
The module utilizes eighteen, Fujitsu MB81V1(7/6)405A-(60/70)(PJ/FN) CMOS 4Mx4 EDO dynamic RAMs in a surface mount
package on an epoxy laminate substrate. Each device is accompanied by a decoupling capacitor for improved noise immunity.
Control lines provided are such that Dword control is possible. All signals are buffered (74ABT16244 or equivalent) except RAS,
data and IDs.
Features
• High Density: 32MByte
• Fast Access Time of 60/70 ns (max.)
• Low Power:
7.2/6.2 W (max.) - Active (60-70ns): 2KR
5.4/4.8 W (max.) -Active (60/70 ns): 4KR
360mW (max.) - Standby (LVTTL)
296mW (max.) - Standby (CMOS)
• LVTTL-compatible inputs and outputs
• Separate power and ground planes to improve noise immunity
• Single power supply of 3.3V±0.3V
• Height: 1.00 inch
• 2K/4K Refresh Cycles
ABSOLUTE MAXIMUM RATINGS
Item
Symbol
Ratings
-0.5 to +4.6
22
Unit
V
Voltage on any pin relative to V
V
P
SS
T
Power Dissipation
W
T
T
Operating Temperature
Storage Temperate
0 to +70
-55 to +125
-50 to +50
°C
°C
mA
opr
T
stg
OS
I
Short Circuit Output Current
RECOMMENDED DC OPERATING CONDITIONS
(TA = 0 to +70 °C)
Symbol
Parameter
Supply Voltage
Min
Typ
Max
3.6
0
Unit
V
V
V
V
3.0
0
3.3
V
V
V
V
CC
SS
IH
Ground
0
-
V
+0.3
Input High voltage
Input Low voltage
2.0
-0.3
CC
-
0.8
IL
Fujitsu Microelectronics, Inc.
1
November 1996
Revision 1.0
EDC4BV724(2/4)-(60/70)(J/T)G-S
Functional Diagram
RAS0*
CAS0*
WE0*
OE0*
A0
RAS2*
CAS4*
WE2*
OE2*
B0
4M x 36
BLOCK
4M x 36
BLOCK
DQ0~DQ35
DQ36~DQ71
DQ0~DQ71
Notes: 1. All signals including PDs (with the exception of RAS*, data and
IDs) are buffered.
V
V
SS
CC
Decoupling capacitors
to all devices
2. “*” signifies active low signal.
3. Addresses A1~A10/A11 (A11 is NC for 2K Refresh modules) are
connected to all devices.
4. Each 4Mx36 Block comprises of nine 4Mx4 EDO devices.
5. All specifications of this device are subject to change without
notice.
Fujitsu Microelectronics, Inc.
2
November 1996
Revision 1.0
EDC4BV724(2/4)-(60/70)(J/T)G-S
Pin Name
A0~A10, B0
A0~A9
Rows and Column Addresses for 2KR
VCC
VSS
NC
PD1~PD8
PDE*
PD
PD6
PD7
Power Supply
Ground
ColumnAddresses for 4KR
Row Addresses for 4KR
Data Inputs/Outputs
Write Enable
Row Address Strobes
Output Enable
A0~A11
No Connection
Presence Detect
Presence Detect Enable
60ns
NC
DQ0~DQ71
WE0*, WE2*
RAS0*~RAS2*
OE0*, OE2*
CAS0*, CAS4*
70ns
VOL
NC
Column Address Strobes
NC
Pin No.
Pin Designation
Pin No.
Pin Designation
Pin No.
Pin Designation
Pin No.
127
Pin Designation
VSS
VSS
VSS
VSS
1
2
3
4
5
6
43
44
45
46
47
48
85
86
87
88
89
90
DQ0
DQ1
DQ2
DQ3
VCC
OE2*
RAS2*
CAS4*
NC
†
†
†
DQ36
DQ37
DQ38
DQ39
VCC
128
NC
129
NC
130
NC
131
NC
WE2*
VCC
132
PDE*
VCC
7
8
DQ4
DQ5
DQ6
DQ7
DQ8
VSS
49
50
51
52
53
54
55
56
57
58
59
91
92
DQ40
DQ41
DQ42
DQ43
DQ44
VSS
133
134
135
136
137
138
139
140
141
142
143
NC
NC
9
NC
93
NC
10
11
12
13
14
15
16
17
DQ18
DQ19
VSS
94
DQ54
DQ55
VSS
95
96
DQ9
DQ20
DQ21
DQ22‘
DQ23
VCC
97
DQ45
DQ46
DQ47
DQ48
DQ49
VCC
DQ56
DQ57
DQ58
DQ59
VCC
DQ10
DQ11
DQ12
DQ13
VCC
98
99
100
101
18
19
20
21
22
23
24
25
26
27
28
29
30
31
60
61
62
63
64
65
66
67
68
69
70
71
72
73
DQ24
NC
102
103
104
105
106
107
108
109
110
111
112
113
114
115
144
145
146
147
148
149
150
151
152
153
154
155
156
157
DQ60
NC
DQ14
DQ15
DQ16
DQ17
VSS
DQ50
DQ51
DQ52
DQ53
VSS
NC
NC
NC
NC
NC
NC
DQ25
DQ26
DQ27
VSS
DQ61
DQ62
DQ63
VSS
NC
NC
VCC
NC
NC
VCC
WE0*
CAS0*
NC
†
†
DQ28
DQ29
DQ30
DQ31
VCC
NC
NC
NC
NC
NC
VSS
DQ64
DQ65
DQ66
DQ67
VCC
RAS0*
OE0*
VSS
†
32
33
34
35
36
37
38
39
40
74
75
76
77
78
79
80
81
82
DQ32
DQ33
DQ34
DQ35
VSS
116
117
118
119
120
121
122
123
124
158
159
160
161
162
163
164
165
166
DQ68
DQ69
DQ70
DQ71
VSS
A0
†
†
†
†
†
†
A1
†
†
†
†
†
†
A2
A3
A4
A5
A6
A7
A8
PD1 (NC)
A9
PD2 (NC)
PD4 (NC)
PD6
PD3 (VOL
PD5 (NC)
PD7
)
†
A10
NC
VCC
A11 (Note)
NC
VCC
PD8 (VOL
)
†
ID0 (VSS
)
ID1 (VSS
)
41
42
NC
NC
83
84
125
126
NC
B0
167
168
VCC
VCC
†
Notes:
1. Signals marked with “†” are buffered.
2. A11 is NC for 2K refresh module.
Fujitsu Microelectronics, Inc.
3
November 1996
Revision 1.0
EDC4BV724(2/4)-(60/70)(J/T)G-S
DC CHARACTERISTICS
(VCC = 3.3V±0.3V, VSS = 0V, TA = 0 to +70 °C)
60
70
Parameter
Symbol
Test Condition
Unit
Note
Min.
Max.
1990
1504
Min.
Max.
1720
1324
2KR
4KR
-
-
-
-
I
RAS*, CAS* cycling; t = min.
Operating Current
mA
1, 2
CC1
RC
LVTTL Interface
RAS*, CAS* ≥ V
-
-
46
28
-
-
46
28
mA
mA
IH
D
= High-Z
out
I
Standby current
CC2
CMOS Interface
RAS*, CAS* ≥ V - 0.2V
cc
D
= High-Z
out
2KR
4KR
2KR
4KR
2KR
4KR
-
1990
1504
1990
1504
1864
1684
90
-
1720
1324
1720
1324
1684
1504
90
CAS* ≥ V ; RAS*, Address
RAS* -only Refresh
Current
IH
I
mA
mA
2
CC3
cycling @ t = min
RC
-
-
-
-
RAS*, CAS* cycling @
CAS*-before-RAS*
Refresh Current
I
CC4
t
= min.
RC
-
-
-
-
RAS* ≤ V CAS*, Address
Hyper Page Mode
Current
IL
I
mA
µA
µA
1, 3
CC5
cycling @ t = min
PC
-
-
I
0V ≤ Vin ≤ V +0.3V
Input Leakage Current
Output Leakage Current
-90
-90
LI
CC
0V ≤ Vout ≤ V
CC
I
-10
10
-10
10
LO
D
= Disable
out
V
High I = -2mA
Output High Voltage
Output Low Voltage
2.4
-
-
2.4
-
-
V
V
OH
out
V
Low I = 2 mA
0.4
0.4
OL
out
Notes:
1. Values depend on output load condition when the device is selected. Maximum Values are specified at the output open condition.
2. Address can be changed once or less while RAS* = V .
IL
3. Address can be changed once or less while CAS* = V
.
IH
CAPACITANCE
(TA =+25°C, VCC = 3.3V±0.3V)
Parameter
Symbol
Max.
13
Unit
pF
Note
1
C
Input Capacitance (Address, CAS*, WE*, OE*)
Input Capacitance (RAS*)
I1
C
70
pF
1
I2
C
Input/Output Capacitance (DQ0~DQ71)
12
pF
1, 2
I/O
Notes:
1. Capacitance is measured with Boonton Meter or effective capacitance method.
2. CAS* = V to disable D
.
out
IH
Fujitsu Microelectronics, Inc.
4
November 1996
Revision 1.0
EDC4BV724(2/4)-(60/70)(J/T)G-S
AC CHARACTERISTICS
(TA = 0 to +70°C, VCC = 3.3V±0.3V, VSS = 0V)
60
70
Parameter
Symbol
Unit
Notes
Min
110
-
Max
Min
130
-
Max
t
Random read/write cycle time
Access time from RAS*
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RC
t
60
70
3,4
3,4,5
3, 10
2
RAC
t
Access time from CAS*
-
20
-
25
CAC
t
Access time from column address
Transition time (rise and fall)
RAS* precharge time
-
35
-
40
AA
t
2
50
2
50
T
t
40
60
20
44
10
20
14
5
-
50
70
25
49
15
20
14
5
-
RP
t
RAS* pulse width
10000
10000
RAS
t
RAS* hold time
-
-
RSH
t
CAS* hold time
-
-
CSH
t
CAS* pulse width
10000
10000
CAS
t
RAS* to CAS* delay time
RAS* to column address delay time
CAS* to RAS* precharge time
Row address set-up time
Row address hold time
45
25
-
50
30
-
4
RCD
t
10
RAD
t
CRP
t
5
-
5
-
ASR
t
9
-
9
-
RAH
t
Column address set-up time
Column address hold time
Column address to RAS* lead time
Read command set-up time
Read command hold time to CAS*
Read command hold time to RAS*
Write command hold time
Write command pulse width
Write command to RAS* lead time
Write command to CAS* lead time
Data-in set-up time
0
-
0
-
ASC
t
10
35
0
-
15
40
0
-
CAH
t
-
-
RAL
t
-
-
RCS
t
0
-
0
-
8
RCH
t
-1
10
10
20
10
-1
-
-1
15
15
25
15
-1
-
RRH
t
-
-
WCH
t
-
-
WP
t
-
-
RWL
t
-
-
CWL
t
-
-
9
9
DS
t
Data-in hold time
15
-
-
20
-
-
DH
2KR
4KR
32
64
-
32
64
-
t
Refresh period
ms
REF
-
-
t
Write command set-up time
0
0
ns
ns
ns
ns
ns
ns
ns
ns
7
1
1
WCS
t
CAS* set-up time (CBR refresh)
CAS* hold time (CBR refresh)
RAS* precharge to CAS* hold time
Access time from CAS* precharge
Hyper page mode cycle time
15
9
-
15
14
4
-
CSR
t
-
-
CHR
t
4
-
-
RPC
t
-
40
-
45
3, 11
12
CPA
t
25
10
60
-
30
10
70
-
HPC
t
CAS* precharge time (Hyper page)
RAS* pulse width (Hyper page)
-
-
CP
t
100000
100000
RASP
Fujitsu Microelectronics, Inc.
5
November 1996
Revision 1.0
EDC4BV724(2/4)-(60/70)(J/T)G-S
Notes:
1. An initial pulse of at least 200µs is required after power-up followed by a minimum of eight RAS* cycles before device operation
is achieved.
2.
V
(min.) and V (max.) are reference levels for measuring timing of input signals. Transition times are measured between V
IH IL IH
(min.) and V (max.) and are assumed to be 5 ns for all inputs.
IL
3. Measure with a load equivalent of 2 TTL loads and 100pF.
4. Operation within the t (max.) limit ensures that t (max.) limit can be met; t (max.) is specified as a reference point
RCD
RCD
RAC
only. If t
is greater than the specified t
(max) limit, then access time is controlled exclusively by t
.
RCD
RCD
CAC
5. Assumes that tRCD ≥ t
(max.).
RACD
6. This parameter defines the time at which the output achieves open circuit condition and is not referenced to V or V
.
OH
OL
7.
t
t
is a non restrictive operating parameter. It is included in the data sheet as an electrical characteristic only. If t
WCS
(min.) the cycle is an early write cycle and the data out pin will remain at high impedance for the duration of the cycle.
WCS
WCS
8. Either t
or t must be satisfied for a read cycle.
RCH
RRH
9. These parameters are referenced to the CAS* leading edge in early write cycles.
10. Operation within the t (max.) limit ensures that t (max.) limit can be met. t (max.) is specified as a reference point only.
RAD
RAD
RAC
If t
is greater than the specified t
(max.) limit, then access time is controlled by t
.
RAD
RAD
AA
11. Access time is determined by the longer of t , t
, or t
.
AA CAC
ACP
12.
t
defines RAS* pulse width in fast page mode cycles.
RASC
Physical Dimensions
168-pin (84x2) 3.3V DIMM
5.250
Note
5.171
5.014
0.158
1
11
40
41
84
0.118
2.150
0.450
1.450
0.250
0.250
1.700
2.507
0.050
0.004
4.550 (Ref.)
5.014
0.350
Front View
Notes:
1. All dimensions are in inches.
2. Pin 85 is behind pin 1 on the back side.
3. Thickness = 0.350 for SOJ devices.
= 0.280 for TSOP devices.
Fujitsu Microelectronics, Inc.
6
November 1996
Revision 1.0
EDC4BV724(2/4)-(60/70)(J/T)G-S
All Rights Reserved.
Circuit diagrams using Fujitsu products are included to illustrate typical semiconductor applications.
Information sufficient for construction purpose may not be shown.
The information contained in this document has been carefully checked and is believed to be reliable.
However, Fujitsu Microelectronics, Inc. assumes no responsibility for inaccuracies.
The information conveyed in this document does not convey any license under the copyrights, patent
rights or trademarks claimed and owned by Fujitsu Limited, its subsidiaries, or Fujitsu
Microelectronics, Inc.
Fujitsu Microelectronics, Inc. reserves the right to change products or specifications without notice.
No part of the publication may be copied or reproduced in any form or by any means, or transferred
to any third party without prior written consent of Fujitsu Microelectronics, Inc.
7
November 1996
Revision 1.0
EDC4BV724(2/4)-(60/70)(J/T)G-S
Worldwide Headquarters
Fujitsu Limited
Fujitsu Microelectronics
Japan
Asia
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#06-04/07
Tel: +81 44 754 3753
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Tel: +1 408 922 9000
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All Right Reserved.
The information contained in this document has been carefully checked and is believed to be reliable. However,
Fujitsu Microelectronics, Inc. assumes no responsibility for inaccuracies.
The information conveyed in this document does not convey any license under the copyrights, patent rights or
trademarks claimed and owned by Fujitsu Limited, its subsidiaries, or Fujitsu Microelectronics, Inc.
Fujitsu Microelectronics, Inc. reserves the right to change products or specifications without notice.
No part of the publication may be copied or reproduced in any form or by any means, or transferred to any third
party without prior written consent of Fujitsu Microelectronics, Inc.
MP-DRAMM-DS-20437-11/96
8
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