MB15E06SRPV1_技术文档

FUJITSU SEMICONDUCTOR

DATA SHEET

DS04-21379-1E

ASSP

Single Serial Input

PLL Frequency Synthesizer

On-chip 3.0 GHz Prescaler

MB15E06SR

■ DESCRIPTION

The Fujitsu MB15E06SR is a serial input Phase Locked Loop (PLL) frequency synthesizer with a 3.0 GHz

prescaler. The 3.0 GHz prescaler has a dual modulus division ratio of 64/65 or 128/129 enabling pulse swallowing

operation.

The supply voltage range is between 2.7 V and 4.0 V. A refined charge pump supplies well-balanced output

currents of 4.0 mA.

The phase noise of MB15E06SR was drastically improved comparing with the former single PLL, MB15E06. The

data format of serial data and the pin assignments except for φP and φR pins are same as the former one, so it

is easy to replace the former one.

MB15E06SR is ideally suited for the high frequency wireless system such as ETC (Electronic Toll Collection

System).

■ FEATURES

• High frequency operation: 3.0 GHz Max

• Low power supply voltage: VCC = 2.7 V to 4.0 V

• Ultra Low power supply current: I^CC= 8.0 mA Typ (VCC = Vp = 3.0 V, Ta = +25°C, in locking state)

• Direct power saving function:Power supply current in power saving mode

Typ 0.1 µA (VCC = Vp = 3.0 V, Ta = +25°C)

(Continued)

■ PACKAGES

16-pin plastic TSSOP

16-pad plastic BCC

(FPT-16P-M07)

(LCC-16P-M06)

MB15E06SR

(Continued)

• Dual modulus prescaler: 64/65 or 128/129

• Serial input 14-bit programmable reference divider: R = 3 to 16,383

• Serial input programmable divider consisting of:

- Binary 7-bit swallow counter: 0 to 127

- Binary 11-bit programmable counter: 3 to 2,047

• Software selectable charge pump current

• On-chip phase control for phase comparator

• Built-in digital locking detector circuit to detect PLL locking and unlocking.

• Operating temperature: Ta = –40 °C to +85 °C

■ PIN ASSIGNMENTS

16-pin TSSOP

16-pad BCC

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

OSCIN

OSCout

VP

N.C.

LD/fout

N.C.

PS

OSCIN N.C.

1

16 15 14

13

OSCout

VP

N.C.

LD/fout

N.C.

PS

2

3

4

5

6

VCC

12

VCC

DO

Top view

DO

11

10

GND

Xfin

LE

GND

Xfin

7

8

9

Data

Clock

fin

fin Clock

(LCC-16P-M06)

(FPT-16P-M07)

2

MB15E06SR

■ PIN DESCRIPTIONS

Pin no.

I/O

Descriptions

name

TSSOP BCC

1

2

3

4

16

1

OSC^IN

OSCOUT

V^P

I

Programmable reference divider input. Connection to a TCXO.

Oscillator output.

O

–

2

Power supply voltage input for the charge pump.

Power supply voltage input.

3

V^CC

Charge pump output.

Phase of the charge pump can be selected via programming of the FC bit.

5

4

DO

O

6

7

5

6

GND

Xfin

–

I

Ground.

Prescaler complementary input, which should be grounded via a capacitor.

Prescaler input.

8

9

7

8

fin

Clock

Data

LE

I

Connection to an external VCO should be done via AC coupling.

Clock input for the 19-bit shift register.

Data is shifted into the shift register on the rising edge of the clock.

(Open is prohibited.)

Serial data input using binary code.

The last bit of the data is a control bit. (Open is prohibited.)

10

11

9

Load enable signal input. (Open is prohibited.)

When LE is set high, the data in the shift register is transferred to a latch

according to the control bit in the serial data.

10

Power saving mode control. This pin must be set at “L” at Power-ON.

(Open is prohibited.)

12

13

14

11

12

13

PS

N.C.

I

PS = “H”; Normal mode

PS = “L”; Power saving mode

–

No connection.

Lock detect signal output (LD)/phase comparator monitoring output (fout).

The output signal is selected via programming of the LDS bit.

LDS = “H”; outputs fout (fr/fp monitoring output)

LD/fout

O

LDS = “L”; outputs LD (“H” at locking, “L” at unlocking.)

15

16

14

15

N.C.

–

No connection.

3

MB15E06SR

■ BLOCK DIAGRAM

1

^OSCIN(16)

SW

LDS

FC

Reference

oscillator circuit

Binary 14-bit

reference couter

Phase

comparator

2

^OSCOUT(1)

3-bit latch

14-bit latch

Intermittent

mode control

(power save)

Lock

detector

12

PS

C

N

T

(11)

19-bit shift register

LD/fr/fp

selector

1-bit

control

latch

14

(13)

LD/fout

11

LE

(10)

(2)

3

VP

Charge

pump

11-bit latch

7-bit latch

5

(4)

DO

Binary 7-bit

swallow

counter

Binary 11-bit

programmable

counter

10

Data

(9)

9

(8)

Clock

fp

7

(6)

Prescaler

64/65

Xfin

8

(7)

128/129

SW

fin

6

GND

(5)

4

^VCC(3)

: TSSOP

( ) : BCC

4

MB15E06SR

■ ABSOLUTE MAXIMUM RATINGS

Rating

Parameter

Symbol

Condition

Unit

Remark

Min

–0.5

VCC

Max

5.0

V^CC

V^P

–

V

Power supply voltage

Input voltage

–

6.0

V^I

–

–0.5

GND

–55

VCC +0.5

VCC

V

V^O

Except Do

V

Output voltage

V^O

Do

–

VP

V

Storage temperature

Tstg

+125

°C

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

■ RECOMMENDED OPERATING CONDITIONS

Value

Parameter

Symbol

Unit

Remark

Min

2.7

Typ

3.0

–

Max

4.0

V^CC

V^P

VI

V

Power supply voltage

VCC

5.5

Input voltage

GND

–40

–

VCC

+85

V

Operating temperature

Ta

–

°C

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the

semiconductor device. All of the device’s electrical characteristics are warranted when the device is

operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges. Operation

outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on

the data sheet. Users considering application outside the listed conditions are advised to contact their

FUJITSU representatives beforehand.

5

MB15E06SR

■ ELECTRICAL CHARACTERISTICS

(VCC = 2.7 V to 4.0 V, Ta = –40 °C to +85 °C)

Value

Unit

Parameter

Symbol

Condition

Min

6.0

–

Typ

8.0

0.1^*2

–

Max

11.5

20

Power supply current*¹

Power saving current

ICC

I^PS

fin = 3000 MHz, VCC = VP = 3.0 V

mA

PS = “L”

µA

fin

f^IN

–

700

3

3000 MHz

Operating frequency

OSC^IN

fosc

–

40

MHz

50 Ω system

Pfin (Refer to the measurement

circuit.)

*3

fin

–10

–

+2

dBm

Input sensitivity

*3

OSCIN

VOSC

–

0.5

–

VCC

Vp-p

V

“H” level input voltage

“L” level input voltage

“H” level input current

“L” level input current

Data,

Clock,

LE, PS

V^IH

VCC × 0.7

–

V^IL

–

VCC × 0.3

+1.0

*4

Data,

Clock,

LE, PS

I^IH

–1.0

µA

*4

I^IL

+1.0

“H” level input current

“L” level input current

“H” level output voltage

“L” level output voltage

“H” level output voltage

“L” level output voltage

IIH

–

0

–100

VCC – 0.4

–

+100

0

OSC^IN

µA

*4

I^IL

–

V^OH

VOL

VCC = VP = 3.0 V, IOH = –1 mA

VCC = VP = 3.0 V, IOL = 1 mA

–

LD/fout

V

0.4

–

V^DOH

V^DOL

VCC = VP = 3.0 V, IDOH = –0.5 mA VP – 0.4

Do

V

VCC = VP = 3.0 V, IDOL = 0.5 mA

–

0.4

VCC = VP = 3.0 V,

VOFF = 0.5 V to VP – 0.5 V

High impedance cutoff

current

IOFF

–

2.5

nA

mA

“H” level output current

“L” level output current

“H” level output current

“L” level output current

I^OH

I^OL

VCC = VP = 3.0 V

–

–1.0

–

LD/fout

1.0

–5.2

2.8

*4

IDOH

–4.0

4.0

–2.8

5.2

VCC = VP = 3.0 V, VDO = VP/2,

Do

mA

%

Ta = +25°C

IDOL

IDOL/

IDOH

*5

VDO = VP/2

–

5

–

IDOMT

Charge pump current

rate

*6

*7

vs V^DO

0.5 V ≤ VDO ≤ VP – 0.7 V

–

10

5

–

%

IDOVD

vs Ta I_DOTA

– 40°C ≤ Ta ≤ +85°C, VDO = VP/2

*1: Conditions; fosc = 13 MHz, Vosc = 1.2 V^PP, Ta = +25°C, in locking state.

*2: VCC = VP = 3.0 V, fosc = 13 MHz, Vosc = 1.2 VPP, Ta = +25°C, in power saving mode

*3: AC coupling. 1000 pF capacitor is connected under the condition of min. operating frequency.

*4: The symbol “–” (minus) means direction of current flow.

*5: V^CC= VP = 3.0 V, Ta = +25°C (||I3| – |I4||) / [(|I3| + |I4|) /2] × 100(%)

*6: V^CC= VP = 3.0 V, Ta = +25°C [(||I2| – |I1||) /2] / [(|I1| + |I2|) /2] × 100(%) (Applied to each IDOL, IDOH)

(Continued)

6

MB15E06SR

(Continued)

*7: VCC = VP = 3.0 V, VDO = VP/2 (||IDO(+85°C)| – |IDO(–40°C)| |/2) / (||IDO(+85°C)| + |IDO(–40°C)|| /2) × 100(%)

(Applied to each I^DOL, IDOH)

I1

I3

I4

I2

IDOL

IDOH

I2

I1

0.5

VP/2

VP − 0.7

VP

Charge Pump Output Voltage (V)

7

MB15E06SR

■ FUNCTIONAL DESCRIPTION

1. Pulse Swallow Function

The divide ratio can be calculated using the following equation:

f^VCO= [(P × N) + A] × fOSC ÷ R (A < N)

fVCO : Output frequency of external voltage controlled oscillator (VCO)

N

A

: Preset divide ratio of binary 11-bit programmable counter (3 to 2,047)

: Preset divide ratio of binary 7-bit swallow counter (0 ≤ A ≤ 127)

fOSC : Output frequency of the reference frequency oscillator

R

P

: Preset divide ratio of binary 14-bit programmable reference counter (3 to 16,383)

: Preset divide ratio of modulus prescaler (64 or 128)

2. Serial Data Input

Serial data is processed using the Data, Clock, and LE pins. Serial data controls the programmable reference

divider and the programmable divider separately.

Binary serial data is entered through the Data pin.

One bit of data is shifted into the shift register on the rising edge of the Clock. When the LE signal pin is taken

high, stored data is latched according to the control bit data as follows:

Table 1. Control Bit

Control bit (CNT)

Destination of serial data

For the programmable reference divider

For the programmable divider

H

L

(1) Shift Register Configuration

Programmable Reference Counter

LSB

1

MSB

Data Flow

10 11 12 13 14 15 16 17 18

LDS

2

3

4

5

6

7

8

9

CNT R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 SW FC

CNT

: Control bit

[Table 1]

R1 to R14 : Divide ratio setting bit for the programmable reference counter (3 to 16,383) [Table 2]

SW

FC

LDS

: Divide ratio setting bit for the prescaler (64/65 or 128/129)

: Phase control bit for the phase comparator

: LD/f^OUTsignal select bit

[Table 5]

[Table 7]

[Table 6]

Note: Start data input with MSB first.

8

MB15E06SR

Programmable Counter

MSB

LSB

1

Data Flow

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19

CNT A1 A2 A3 A4 A5 A6 A7 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11

CNT

: Control bit

[Table 1]

[Table 3]

[Table 4]

N1 to N11: Divide ratio setting bits for the programmable counter (3 to 2,047)

A1 to A7 : Divide ratio setting bits for the swallow counter (0 to 127)

Note: Data input with MSB first.

Table 2. Binary 14-bit Programmable Reference Counter Data Setting

Divide

R14 R13 R12 R11 R10 R9

R8

R7

R6

R5

R4

R3

R2

R1

ratio(R)

3

4

0

1

0

1

0

16383

1

Note: Divide ratio less than 3 is prohibited.

Table 3. Binary 11-bit Programmable Counter Data Setting

Divide

N11 N10

N9

N8

N7

N6

N5

N4

N3

N2

N1

ratio(N)

3

4

0

1

0

1

0

2047

1

Note: Divide ratio less than 3 is prohibited.

9

MB15E06SR

Table 4. Binary 7-bit Swallow Counter Data Setting

Divide ratio (A) A7

A6

0

A5

0

A4

0

A3

0

A2

0

A1

0

1

0

1

127

1

Table 5. Prescaler Data Setting

SW

1

Prescaler divide ratio

64/65

0

128/129

Table 6. LD/fout Output Select Data Setting

LDS

LD/fout output signal

fout signal

1

0

LD signal

(2) Relation between the FC Input and Phase Characteristics

The FC bit changes the phase characteristics of the phase comparator. The internal charge pump output level (D^O)

is reversed according to the FC bit. Also, the monitor pin (fout) output is controlled by the FC bit. The relationship

between the FC bit and DO is shown below.

Table 7. FC Bit Data Setting (LDS = “1”)

FC = 1

LD/fout

FC = 0

LD/fout

D^O

H

L

DO

L

fr > fP

fr < fP

fr = f^P

fout = fr

H

Z

fout = fp

Z

Z : High impedance

10

MB15E06SR

When designing a synthesizer, the FC pin setting depends on the VCO and LPF characteristics.

• When the LPF and VCO characteristics are

similar to (1), set FC bit high.

(1)

• When the VCO characteristics are similar to

(2), set FC bit low.

VCO

Output

Frequency

PLL

LPF

VCO

(2)

LPF Output Voltage

Note : Give attention to the polarity for using active type LPF.

11

MB15E06SR

3. Power Saving Mode (Intermittent Mode Control Circuit)

Table 10. PS Pin Setting

PS pin

Status

H

L

Normal mode

Power saving mode

The intermittent mode control circuit reduces the PLL power consumption.

By setting the PS pin low, the device enters into the power saving mode, reducing the current consumption. See

the Electrical Characteristics chart for the specific value.

The phase detector output, Do, becomes high impedance.

For the signal PLL, the lock detector, LD, remains high, indicating a locked condition.

Setting the PS pin high, releases the power saving mode, and the device works normally.

The intermittent mode control circuit also ensures a smooth startup when the device returns to normal operation.

When the PLL is returned to normal operation, the phase comparator output signal is unpredictable. This is because

of the unknown relationship between the comparison frequency (fp) and the reference frequency (fr) which can

cause a major change in the comparator output, resulting in a VCO frequency jump and an increase in lockup time.

To prevent a major VCO frequency jump, the intermittent mode control circuit limits the magnitude of the error

signal from the phase detector when it returns to normal operation.

Notes : • When power (VCC) is first applied, the device must be in standby mode, PS = Low.

• The serial data input after the power supply becomes stable and the the power saving mode is released

after completed the data input..

OFF

ON

tV ≥ 1 µs

VCC

Clock

Data

LE

tPS ≥ 100 ns

PS

(1)

(2)

(3)

(1) PS = L (power saving mode) at Power ON

(2) Set serial data 1 µs later after power supply remains stable (VCC > 2.2 V).

(3) Release power saving mode (PS: “L” → “H”) 100 ns later after setting serial data.

12

MB15E06SR

■ SERIAL DATA INPUT TIMING

1st data

2nd data

Control bit Invalid data

Data

MSB

LSB

Clock

t1

t2

t3

t6

t0

LE

t4

t5

On the rising edge of the clock, one bit of data is transferred into the shift register.

Parameter Min

Typ

–

Max Unit

Parameter Min

Typ

–

Max Unit

t¹

t²

t³

t4

20

30

–

ns

t⁵

t⁶

t⁷

100

20

–

ns

–

100

–

Note: LE should be “L” when the data is transferred into the shift register.

13

MB15E06SR

■ PHASE COMPARATOR OUTPUT WAVEFORM

fr

fp

tWU

tWL

LD

[FC = “1”]

DO

[FC = “0”]

DO

Notes: • Phase error detection range: –2π to +2π

• Pulses on Do signal during locked state are output to prevent dead zone.

• LDoutputbecomeslowwhenphaseistWU ormore.LDoutputbecomeshighwhenphaseerror istWL

or less and continues to be so for three cycles or more.

• tWU and tWL depend on OSCIN input frequency.

tWU > 2/fosc (s) (e. g. tWU > 153.8 ns, fosc = 13 MHz)

tWU < 4/fosc (s) (e. g. tWL < 307.7 ns, fosc = 13 MHz)

• LD becomes high during the power saving mode (PS = “L”).

14

MB15E06SR

■ MEASURMENT CIRCUIT (for Measuring Input Sensitivity fin/OSC^IN)

1000 pF

0.1 µF

1000 pF

0.1 µF

1000 pF

S.G.

OSCOUT

2

fin

8

Xfin GND DO

VCC VP

OSCIN

50 Ω

7

6

5

4

3

1

9

10

11

12

13

14

15

16

Clock Data LE

N.C. N.C.

PS N.C. LD/fout

VCC

Oscilloscope

Controller (setting divide ratio)

Note: TSSOP-16

15

MB15E06SR

■ TYPICAL CHARACTERISTICS

1. fin input sensitivity

Input sensitivity - Input frequency

Ta = +25 °C

10

5

0

Catalog guaranteed range

−5

−10

−15

−20

−25

−30

−35

VCC = 2.7 V

VCC = 3.0 V

VCC = 4.0 V

SPEC

0

500

1000

1500

2000

2500

3000

3500

4000

4500

Input frequency fIN (MHz)

2. OSC^INinput sensitivity

Input sensitivity - Input frequency

Ta = +25 °C

10.0

Catalog

guaranteed

range

0.0

−10.0

−20.0

−30.0

−40.0

−50.0

VCC = 2.7 V

VCC = 3.0 V

VCC = 3.75 V

SPEC

0

20

40

60

80

100

120

140

160

180

Input frequency fOSC (MHz)

16

MB15E06SR

3. Do output current

• 4.0 mA

V^DO- I^DO

2.00 mA/div

10.00

Ta = +25˚C, VCC = VP = 3.0 V

0.00

−10.00

0

1

2

3

4

5

6

7

Charge pump output voltage VDO (V)

4. fin input impedance

4: 75.418 Ω

63.625 Ω

3.3754 nH

3 000.000 000 MHz

1 : 27.688 Ω

−105.31 Ω

700 MHz

18.004 Ω

−64.969 Ω

1 GHz

2 :

4

18.395 Ω

1.0674 Ω

2 GHz

3 :

3

1

2

STOP 3 000.000 000 MHz

START

700.000 000 MHz

17

MB15E06SR

5. OSCIN input impedance

4: 56.25 Ω

−1.3356 kΩ

2.979 pF

40.000 000 MHz

1 : 5.771 kΩ

−15.199 kΩ

3 MHz

133.63 Ω

2 :

−2.5508 kΩ

20 MHz

56.25 Ω

−1.3956 kΩ

3 :

40 MHz

4

1

2

3

STOP 40.000 000 MHz

START

3.000 000 MHz

18

MB15E06SR

■ REFERENCE INFORMATION

Test Circuit

VCC =VP = 3.0 V

VVCO = 3.0 V

Ta = +25 °C

fVCO = 1619 MHz

KV = 44 MHz/V

fr = 100 kHz

S.G.

OSCIN

fin

CP : 4 mA

fOSC = 10 MHz (1.2 VPP)

LPF

Do

LPF

27 kΩ

3.3 kΩ

2200 pF

120 pF

Spectrum

Analyzer

VCO

15000 pF

• PLL Reference Leakage

ATTEN 10 dB

RL −10.0 dBm

VAVG 16

10 dB/

∆MKR −77.67 dB

100.0 kHz

∆MKR

100.0 kHz

−77.67 dB

CENTER 1.6190000 GHz

VBW 3.0 kHz

SPAN 300.0 kHz

SWP 84.0 ms

RBW 3.0 kHz

• PLL Phase Noise

∆MKR −78.84 dB/Hz

ATTEN 10 dB

VAVG 16

1.000 kHz

RL −10.0 dBm

10 dB/

∆MKR

1.000 kHz

−78.84 dB/Hz

CENTER 1.619000000 GHz

SPAN 5.000 kHz

SWP 969 ms

VBW 30 Hz

RBW 30 Hz

(Continued)

19

MB15E06SR

(Continued)

• PLL Lock Up time

1597.2 MHz 1672 MHz ± 1 kHz

Lch Hch 1.06 ms

∆Mkr

x : −289.99777 µs

y : −23.8776 MHz

1.672003384 GHz

1.671999384 GHz

1.671995384 GHz

0.00 s

2.500 ms

5.000 ms

• PLL Lock Up time

1672 MHz 1597.2 MHz ±1kHz

Hch Lch 0.9 ms

x : −300.00071 µs

∆Mkr

y : −23.8754 MHz

1.597203471 GHz

1.597199471 GHz

1.597195471 GHz

0.00 s

2.500 ms

5.000 ms

20

MB15E06SR

■ APPLICATION EXAMPLE

OUTPUT

VCO

LPF

Lock Det.

From

a controller

N.C.

16

N.C.

15

N.C.

13

LE

11

Data

10

Clock

9

LD/fout

14

PS

12

MB15E06SR

1

2

3

4

5

6

7

8

OSCIN

VP

GND

fin

DO

Xfin

VCC

OSCOUT

1000 pF

TCXO

0.1 µF

VP: 5.5 V Max

Note: TSSOP-16

■ USAGE PRECAUTIONS

To protect against damage by electrostatic discharge, note the following handling precautions:

-Store and transport devices in conductive containers.

-Use properly grounded workstations, tools, and equipment.

-Turn off power before inserting device into or removing device from a socket.

-Protect leads with a conductive sheet when transporting a board-mounted device.

21

MB15E06SR

■ ORDERING INFORMATION

Part number

Package

Remarks

16-pin, Plastic TSSOP

(FPT-16P-M07)

MB15E06SRPFT

16-pad, Plastic BCC

(LCC-16P-M06)

MB15E06SRPV1

22

MB15E06SR

■ PACKAGE DIMENSIONS

Note 1) *1 : Resin protrusion. (Each side : +0.15 (.006) Max) .

Note 2) *2 : These dimensions do not include resin protrusion.

Note 3) Pins width and pins thickness include plating thickness.

Note 4) Pins width do not include tie bar cutting remainder.

16-pin, Plastic TSSOP

(FPT-16P-M07)

¹5.00±0.10(.197±.004)

0.17±0.05

*

(.007±.002)

16

9

²4.40±0.10 6.40±0.20

(.173±.004) (.252±.008)

*

INDEX

Details of "A" part

1.05±0.05

(.041±.002)

(Mounting height)

1

8

LEAD No.

"A"

0.65(.026)

0.24±0.08

(.009±.003)

0~8˚

M

0.13(.005)

0.07 ⁺^–0⁰^.^.⁰⁰⁷³.003 ^–⁺^.^.⁰⁰⁰⁰³¹

(0.50(.020))

(Stand off)

0.25(.010)

0.60±0.15

(.024±.006)

0.10(.004)

C

2003 FUJITSU LIMITED F16020S-c-3-3

Dimensions in mm (inches) .

Note : The values in parentheses are reference values.

(Continued)

23

MB15E06SR

(Continued)

16-pad plastic BCC

(LCC-16P-M06)

4.55±0.10

(.179±.004)

0.80(.031)MAX

Mounting height

3.40(.134)TYP

0.65(.026)

0.325±0.10

(.013±.004)

TYP

0.40±0.10

(.016±.004)

14

9

14

0.80(.031)

REF

INDEX AREA

3.40±0.10

(.134±.004)

2.45(.096)

TYP

1.15(.045)

REF

"B"

"A"

0.075±0.025

(.003±.001)

(Stand off)

1.725(.068)

REF

1

6

1

Details of "A" part

0.75±0.10

Details of "B" part

0.60±0.10

(.024±.004)

(.030±.004)

0.05(.002)

0.40±0.10

0.60±0.10

(.016±.004)

(.024±.004)

C

1999 FUJITSU LIMITED C16017S-1C-1

Dimensions in mm (inches) .

Note : The values in parentheses are reference values.

24

MB15E06SR

FUJITSU LIMITED

The contents of this document are subject to change without notice.

Customers are advised to consult with FUJITSU sales

representatives before ordering.

The information, such as descriptions of function and application

circuit examples, in this document are presented solely for the

purpose of reference to show examples of operations and uses of

Fujitsu semiconductor device; Fujitsu does not warrant proper

operation of the device with respect to use based on such

information. When you develop equipment incorporating the

device based on such information, you must assume any

responsibility arising out of such use of the information. Fujitsu

assumes no liability for any damages whatsoever arising out of

the use of the information.

Any information in this document, including descriptions of

function and schematic diagrams, shall not be construed as license

of the use or exercise of any intellectual property right, such as

patent right or copyright, or any other right of Fujitsu or any third

party or does Fujitsu warrant non-infringement of any third-party’s

intellectual property right or other right by using such information.

Fujitsu assumes no liability for any infringement of the intellectual

property rights or other rights of third parties which would result

from the use of information contained herein.

The products described in this document are designed, developed

and manufactured as contemplated for general use, including

without limitation, ordinary industrial use, general office use,

personal use, and household use, but are not designed, developed

and manufactured as contemplated (1) for use accompanying fatal

risks or dangers that, unless extremely high safety is secured, could

have a serious effect to the public, and could lead directly to death,

personal injury, severe physical damage or other loss (i.e., nuclear

reaction control in nuclear facility, aircraft flight control, air traffic

control, mass transport control, medical life support system, missile

launch control in weapon system), or (2) for use requiring

extremely high reliability (i.e., submersible repeater and artificial

satellite).

Please note that Fujitsu will not be liable against you and/or any

third party for any claims or damages arising in connection with

above-mentioned uses of the products.

Any semiconductor devices have an inherent chance of failure. You

must protect against injury, damage or loss from such failures by

incorporating safety design measures into your facility and

equipment such as redundancy, fire protection, and prevention of

over-current levels and other abnormal operating conditions.

If any products described in this document represent goods or

technologies subject to certain restrictions on export under the

Foreign Exchange and Foreign Trade Law of Japan, the prior

authorization by Japanese government will be required for export

of those products from Japan.

F0401

FUJITSU LIMITED Printed in Japan


型号：	MB15E06SRPV1
厂家：	FUJITSU
描述：	Single Serial Input PLL Frequency Synthesizer On-chip 3.0 GHz Prescaler 单串行输入锁相环频率合成片3.0 GHz的预分频器预分频器信号电路锁相环或频率合成电路
文件：	总25页 (文件大小：206K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MB15E06SRPV1 [FUJITSU]

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