MB15E07 [FUJITSU]
Single Serial Input PLL Frequency Synthesizer On-Chip 2.5 GHz Prescaler; 单串行输入锁相环频率合成片2.5 GHz的预分频器
| 型号： | MB15E07 |
| 厂家： | 
FUJITSU |
| 描述： | Single Serial Input PLL Frequency Synthesizer On-Chip 2.5 GHz Prescaler |
| 文件： | 总22页 (文件大小：225K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FUJITSU SEMICONDUCTOR
DATA SHEET
DS04-21343-1E
ASSP
Single Serial Input
PLL Frequency Synthesizer
On-Chip 2.5 GHz Prescaler
MB15E07
■ DESCRIPTION
The Fujitsu MB15E07 is serial input Phase Locked Loop (PLL) frequency synthesizer with a 2.5 GHz prescaler.
A 32/33 or a 64/65 can be selected for the prescaler that enables pulse swallow operation.
The latest BiCMOS process technology is used, resuItantly a supply current is limited as low as 8 mA typ. This
operates with a supply voltage of 3.0 V (typ.)
Furthermore, a super charger circuit is included to get a fast tuning as well as low noise performance. As a result
of this, MB15E07 is ideally suitable for digital mobile communications, such as GSM (Global System for Mobile
Communications).
■ FEATURES
• High frequency operation: 2.5 GHz max (@ P= 64/65)
1.8 GHz max (@P = 32/33)
• Low power supply voltage: VCC = 2.7 to 3.6 V
• Very Low power supply current : ICC = 8.0 mA typ. (VCC = 3 V)
• Power saving function : IPS = 0.1 µA typ.
• Pulse swallow function: 32/33 or 64/65
• Serial input 14-bit programmable reference divider: R = 5 to 16,383
• Serial input 18-bit programmable divider consisting of:
- Binary 7-bit swallow counter: 0 to 127
- Binary 11-bit programmable counter: 5 to 2,047
• Wide operating temperature: Ta = –40 to 85°C
• Plastic 16-pin SSOP package (FPT-16P-M05)
■ PACKAGE
16-pin, Plastic SSOP
(FPT-16P-M05)
MB15E07
■ PIN ASSIGNMENT
(Top View)
OSCin
OSCout
Vp
1
2
3
4
5
6
7
8
16
φR
15
14
13
12
11
10
9
φP
LD/fout
ZC
V CC
Do
PS
GND
Xfin
LE
Data
Clock
fin
2
MB15E07
■ PIN DESCRIPTIONS
Pin no.
Pin name
I/O
Descriptions
Programmable reference divider input.
Oscillator input.
Connection for an crystal or a TCXO.
TCXO should be connected with a coupling capacitor.
1
OSCIN
I
Oscillator output.
Connection for an external crystal.
2
OSCOUT
O
3
4
VP
–
–
Power supply voltage input for the charge pump.
Power supply voltage input.
VCC
Charge pump output.
Phase of the charge pump can be reversed by FC bit.
5
DO
O
6
7
GND
Xfin
–
I
Ground.
Prescaler complementary input, and should be grounded via a capacitor.
Prescaler input.
8
9
fin
I
I
Connection with an external VCO should be done with AC coupling.
Clock input for the 19-bit shift register.
Data is shifted into the shift register on the rising edge of the clock. (Open
is prohibited.)
Clock
Serial data input using binary code.
The last bit of the data is a control bit. (Open is prohibited.)
Control bit = “H” ;Data is transmitted to the programmable reference
counter.
10
Data
I
Control bit = “L” ;Data is transmitted to the programmable counter.
Load enable signal input (Open is prohibited.)
When LE is high, the data in the shift register is transferred to a latch,
according to the control bit in the serial data.
11
12
LE
PS
I
I
Power saving mode control. This pin must be set at “L” at Power-ON.
(Open is prohibited.)
PS = “H” ; Normal mode
PS = “L” ; Power saving mode
Forced high-impedance control for the charge pump (with internal pull up
resistor.)
ZC = “H” ; Normal Do output.
13
14
ZC
I
ZC = “L” ; Do becomes high impedance.
Lock detect signal output(LD)/phase comparator monitoring
output (fout).
The output signal is selected by LDS bit in the serial data.
LDS = “H” ; outputs fout (fr/fp monitoring output)
LDS = “L” ; outputs LD (“H” at locking, “L” at unlocking.)
LD/fout
O
Phase comparator output for an external charge pump. Nch open drain
output.
15
16
φP
φR
O
O
Phase comparator output for an external charge pump. CMOS output.
3
MB15E07
■ BLOCK DIAGRAM
1
2
OSCIN
fr
Crystal
Oscillator
circuit
16
15
φR
φP
fp
Phase
comparator
Programmable
reference divider
OSCOUT
LD
Binary 14-bit
reference counter
fr
Lock
detector
Intermittent
mode control
(power save)
SW
LDS
FC
12
11
PS
LE
17-bit latch
LD/fr/fp
selector
14-bit latch
3-bit latch
LE
14
LD/fout
fp
1-bit
control
latch
19-bit shift register
C
N
T
13
3
ZC
VP
Charge
pump
19-bit shift register
Data
10
9
Super
charger
Clock
5 Do
18-bit latch
7-bit latch 11-bit latch
LE
SW
Programmable divider
Prescaler
32/33,
XfIN
7
8
fIN
Binary 7-bit Binary 11-bit
64/65
swallow
counter
programma-
ble counter
fp
GND 6
Control Circuit
MD
V CC
4
4
MB15E07
■ ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
VCC
VP
Rating
Unit
V
Remark
–0.5 to +4.0
Power supply voltage
VCC to +6.0
V
Input voltage
VI
–0.5 to VCC +0.5
–0.5 to VCC +0.5
–55 to +125
V
Output voltage
Storage temperature
VO
V
Tstg
°C
Note: Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional
operation should be restricted to the conditions as detailed in the operational sections of this data sheet.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
■ RECOMMENDED OPERATING CONDITIONS
Value
Parameter
Symbol
Unit
Remark
Min.
2.7
Typ.
3.0
–
Max.
3.6
VCC
VP
VI
V
V
Power supply voltage
VCC
6.0
Input voltage
GND
–40
–
VCC
+85
V
Operating temperature
Ta
–
°C
Handling Precautions
• This device should be transported and stores in anti-static containers.
• This is a static-sensitive device; take proper anti-ESD precautions. Ensure that personnel and equipment are
properly grounded. Cover workbenches with grounded conductive mats.
• Always turn the power supply off before inserting or removing the device from its socket.
• Protect leads with a conductive sheet when handling or transporting PC boards with devices.
5
MB15E07
■ ELECTRICAL CHARACTERISTICS
(VCC = 2.7 to 3.6 V, Ta = –40 to +85°C)
Value
Unit
Parameter
Symbol
Condition
Min.
Typ.
Max.
fin = 1800 MHz,
fosc = 12 MHz, P = 32/33
Power supply current*1
Power saving current
ICC
–
8.0
–
mA
Ips
ZC = “H” or open
P = 32/33
–
0.1
–
10
1800
2500
40
µA
100
100
3
MHz
MHz
MHz
Operating frequency
fin
P = 64/65
–
Crystal oscillator operating frequency
fOSC
Vfin
VOSC
VIH
min. 500 mVp-p
–
50 Ω system
(Refer to the test circuit.)
fin
–10
500
–
–
–
+2
VCC
–
dBm
Input sensitivity
OSCin
mVp-p
Vcc ×
0.7
Data, Clock,
Input voltage
V
LE, PS, ZC
Vcc ×
0.3
VIL
–
–
IIH
IIL
–1.0
–1.0
–1.0
–100
0
–
–
–
–
–
–
–
+1.0
+1.0
+1.0
0
Data, Clock,
LE, PS
µA
µA
IIH
IIL
Input current
ZC
Pull up input
IIH
IIL
+100
0
OSCin
µA
–100
–
φP
VOL
Open drain output
0.4
V
Vcc –
0.4
VOH
VOL
–
–
–
–
–
–
φR,
LD/fout
V
V
Output voltage
–
0.4
–
Vp –
0.4
VDOH
VDOL
IOFF
Do
–
–
0.4
1.1
High impedance
cutoff current
Do
µA
φP
IOL
IOH
IOL
Open drain output
–
–
–
–
–
1.0
–1.0
–
mA
φR,
LD/fout
mA
mA
1.0
VCC = 3.0 V,
Vp = 5 V,
VDOH = 4.0 V, Ta = 25°C
Output current
IDOH
–
–
–10.0
10.0
–
–
Do
VCC = 3.0 V,
Vp = 5 V,
IDOL
VDOL = 1.0 V, Ta = 25°C
*1: Conditions; VCC = 3.0 V, Ta = 25°C, in locking state.
6
MB15E07
■ FUNCTION DESCRIPTIONS
Pulse Swallow Function
The divide ratio can be calculated using the following equation:
fVCO = [(P x N) + A] x fOSC ÷ R (A < N)
fVCO : Output frequency of external voltage controlled oscillator (VCO)
N
A
: Preset divide ratio of binary 11-bit programmable counter (5 to 2,047)
: Preset divide ratio of binary 7-bit swallow counter (0 ≤ A ≤ 127)
fOSC : Output frequency of the reference frequency oscillator
R
P
: Preset divide ratio of binary 14-bit programmable reference counter (5 to 16,383)
: Preset divide ratio of modules prescaler (32 or 64)
Serial Data Input
Serial data is processed using the Data, Clock, and LE pins. Serial data controls the programmable reference
divider and the programmable divider separately.
Binary serial data is entered through the Data pin.
One bit of data is shifted into the shift register on the rising edge of the clock. When the load enable pin is high,
stored data is latched according to the control bit data as follows:
Table.1 Control Bit
Control bit (CNT)
Destination of serial data
17 bit latch (for the programmable reference divider)
18 bit latch (for the programmable divider)
H
L
Shift Register Configuration
Programmable Reference Counter
Data Flow
LSB
1
MSB
18
2
3
4
5
6
7
8
9
10
11 12
13
14 15
16
17
C
N
T
R
1
R
2
R
3
R
4
R
5
R
6
R
7
R
8
R
9
R
10
R
11
R
12
R
13
R
14
SW FC LDS
CNT
R1 to R14
SW
FC
LDS
[Table. 1]
: Control bit
[Table. 2]
[Table. 5]
[Table. 7]
[Table. 6]
: Divide ratio setting bit for the programmable reference counter (5 to 16,383)
: Divide ratio setting bit for the prescaler (32/33 or 64/65)
: Phase control bit for the phase comparator
: LD/fout signal select bit
Note : Start data input with MSB first
7
MB15E07
Programmable Reference Counter
Data Flow
LSB
1
MSB
19
2
3
4
5
6
7
8
9
10
11 12
13
14 15
16
17
18
C
N
T
A
1
A
2
A
3
A
4
A
5
A
6
A
7
N
1
N
2
N
3
N
4
N
5
N
6
N
7
N
8
N
9
N
10
N
11
CNT
: Control bit
[Table. 1]
[Table. 2]
[Table. 4]
N1 to N11 : Divide ratio setting bits for the programmable counter (5 to 2,047)
A1 to A7 : Divide ratio setting bits for the swallow counter (0 to 127)
Note : Start data input with MSB first
Table2. Binary 14-bit Programmable Reference Counter Data Setting
Divide
ratio
(R)
R
14
R
13
R
12
R
11
R
10
R
9
R
8
R
7
R
6
R
5
R
4
R
3
R
2
R
1
5
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
1
1
•
0
1
•
1
0
•
6
•
16383
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Note: • Divide ratio less than 5 is prohibited.
Table.3 Binary 11-bit Programmable Counter Data Setting
Divide
ratio
(N)
N
11
N
10
N
9
N
8
N
7
N
6
N
5
N
4
N
3
N
2
N
1
5
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
1
1
•
0
1
•
1
0
•
6
•
2047
1
1
1
1
1
1
1
1
1
1
1
Note: • Divide ratio less than 5 is prohibited.
• Divide ratio (N) range = 5 to 2,047
8
MB15E07
Table.4 Binary 7-bit Swallow Counter Data Setting
Divide
A
7
A
6
A
5
A
4
A
3
A
2
A
1
ratio
(A)
0
1
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
0
1
•
•
127
1
1
1
1
1
1
1
Note: • Divide ratio (A) range = 0 to 127
Table. 5 Prescaler Data Setting
SW
H
Prescaler Divide ratio
32/33
64/65
L
Table. 6 LD/fout Output Select Data Setting
LDS
LD/fout output signal
H
L
fout signal
LD signal
Relation between the FC input and phase characteristics
The FC bit changes the phase characteristics of the phase comparator. Both the internal charge pump output level
(DO) and the phase comparator output (φR, φP) are reversed according to the FC bit. Also, the monitor pin (fOUT)
output is controlled by the FC bit.The relationship between the FC bit and each of DO, φR, and φP is shown below.
Table. 7 FC Bit Data Setting (LDS = “H”)
FC = High
FC = Low
φR
Do
H
φR
φP
L
LD/fout
(fr)
Do
L
φP
Z*
L
LD/fout
(fp)
fr > fp
fr < fp
fr = fp
L
H
L
H
L
L
L
Z*
Z*
(fr)
H
(fp)
Z*
(fr)
Z*
Z*
(fp)
* : High impedance
9
MB15E07
When designing a synthesizer, the FC pin setting depends on the VCO and LPF characteristics.
➀ꢀ
: When the LPF and VCO characteristics are
similar to ➀, set FC bit high.
: When the VCO characteristics are similar to
ꢀ ➁, set FC bit low.
VCO
Output
Frequency
PLL
LPF
VCO
➁ꢀ
LPF Input Voltage
Power Saving Mode (Intermittent Mode Control Circuit)
Setting a PS pin to Low, the IC enters into power saving mode resultatly current sonsumption can be limited to
10µA (max.). Setting PS pin to High, power saving mode is released so that the IC works normally.
In addition, the intermittent operation control circuit is included which helps smooth start up from the power saving
mode. In general, the power consumption can be saved by the intermittent operation that powering down or waking
up the synthesizer. Such case, if the PLL is powered up uncontrolled, the resulting phase comparator output signal
is unpredictable due to an undefined phase relation between reference frequency (fr) and comparison frequency
(fp) and may in the worst case take longer time for lock up of the loop.
To prevent this, the intermittent operation control circuit enforces a limited error signal output of the phase detector
during power up, thus keeping the loop locked.
During the power saving mode, the corresponding section except for indispensable circuit for the power saving
function stops working, then current consumption is reduced to 10 µA (max.).
At that time, the Do and LD become the same state as when a loop is locking. That is, the Do becomes high
impedance.
A VCO control voltage is naturally kept at the locking voltage which defined by a LPF”s time constant. As a result
of this, VCO’s frequency is kept at the locking frequency.
Note: • While the power saving mode is executed, ZC pin should be set at “H” or open. If ZC is set at “L”
during power saving mode, approximately 10 µA current flows.
• PS pin must be set “L” at Power-ON.
• The power saving mode can be released (PS : L → H) 1µs later after power supply remains stable.
• During the power saving mode, it is possible to input the serial data.
Table.8 PS Pin Setting
PS pin
Status
H
L
Normal mode
Power saving mode
Table.9 ZC Pin Setting
Do output
ZC pin
H
L
Normal output
High impedance
10
MB15E07
■ SERIAL DATA INPUT TIMING
Data
MSB
LSB
Clock
LE
t2
t3
t4
t1
t5
t7
t6
On rising edge of the clock, one bit of the data is transferred into the shift register.
Parameter
Min.
Typ. Max.
Unit
Parameter
Min.
Typ. Max.
Unit
ns
ns
ns
ns
ns
t1
t2
t3
t4
t5
t6
t7
20
20
30
30
–
–
–
–
–
–
–
–
100
20
–
–
–
–
–
–
ns
ns
100
11
MB15E07
■ PHASE COMPARATOR OUTPUT WAVEFORM
fr
fp
tWU
tWL
LD
[ FC = ”H” ]
φP
φR
H
Do
Z
L
[ FC = ”L” ]
φP
φR
H
Do
Z
L
Notes: 1. Phase error detection range:–2πto +2π
2. Pulses on Do output signal during locked state are output to prevent dead zone.
.
3. LD output becomes low when phase is tWU or more. LD output becomes high when phase error is tWL
or less and continues to be so for three cysles or more.
4. tWU and tWL depend on OSCin input frequency.
tWU ≥ 8/fosc (e g.tWU ≥ 625ns, foscin = 12.8 MHz)
tWL ≤ 16/fosc (e g.tWL ≤ 1250ns, foscin = 12.8 MHz)
5. LD becomes high during the power saving mode (PS = ”L”.)
12
MB15E07
■ TEST CIRCUIT (for Measuring Input Sensitivity fin/OSCin)
V P
V CC
0.1µF
1000pF
1000pF
1000pF
P.G
P.G
0.1µF
50Ω
50Ω
8
9
7
6
5
4
3
2
1
12 13
10 11
14 15 16
Oscilloscope
Controller
(setting devide ratio)
V CC
13
MB15E07
■ APPLICATION EXAMPLE
Output
LPF
VCO
10kΩ
12kΩ
12kΩ
To a lock detect.
10kΩ
From
φR
φP
LD/F OUT ZC
PS
12
LE
Data
10
Clock
16
15
14
13
11
9
8
MB15E07
1
2
3
4
5
6
7
OSC IN
X’ tal
OSC OUT
V P
V CC
D O
GND
Xf IN
f IN
1000pF
1000pF
C 1
C 2
0.1 µF 0.1 µF
C 1, C 2 : Depend on the crystal parameters
(Continued)
14
MB15E07
■ TYPICAL CHARACTERISTICS
Do Output Current
[Ta = + 25˚C]
[V CC = 3 V, Vp = 3 V, 5 V]
[Ta = + 25˚C]
[V CC = 3 V, Vp = 3 V, 5 V]
Vp = 3 V
Vp = 5 V
Vp = 3 V
Vp = 5 V
5.0
4.0
3.0
2.0
1.0
0
5.0
4.0
3.0
2.0
1.0
0
0
0
–10
–15
–20
10
15
20
–5
5
I
OH (mA)
I
OL (mA)
fin Input Sensitivity
Prescalar = 64/65
Main. counter div. ratio = 4104
Swallow = “ON”
Vfin vs. fin
[Ta = +25˚C]
V
CC = Vp
+10
0
SPEC
–10
–20
–30
–40
V
CC = 2.7 V
V
V
CC = 3.0 V
CC = 3.6 V
1000
4000
0
2000
fin (MHz)
3000
(Continued)
15
MB15E07
(Continued)
fin Input Snsitivity
Prescaler = 32/33
Main, counter div. ratio = 1860
Swallow = “ON”
[Ta = 25˚C]
+10
0
SPEC
–10
–20
–30
–40
: VDD = 2.7 V
: VDD = 3.0 V
: VDD = 3.6 V
0
1000
2000
3000
fin (MHz)
OSCin Input Characteristics
Vf OSC vs. f OSC
[Ta = +25˚C]
+10
Ref. counter div. ratio = 767
fin, Xfin : OPEN
SPEC
0
–10
–20
–30
V CC = 2.7 V
V CC = 3.0 V
V CC = 3.6 V
–40
0
50
200
100
f OSC (MHz)
150
(Continued)
16
MB15E07
(Continued)
fin Input Impedance
4 : 39.314Ω – 50.516 kΩ 3.2159 pF
2 500.000 000 MHz
1 : 10.188Ω
– 36.666Ω
1 GHz
2 : 10.371Ω
1.4438Ω
1.5 GHz
4
3
3 : 16.474Ω
31.454Ω
2 GHz
fin
2
1
OSCin Input Impedance
3 : 030.13Ω
-2.389 kΩ 3.331 pF
20.000 000 MHz
1 : 3.516Ω
– 43.99 kΩ
1 MHz
2 : 150.5Ω
– 4.8388 kΩ
10 MHz
4 : 12.844Ω
– 948.37Ω
50 MHz
3
1
2
OSCin
4
17
MB15E07
■ REFERENCE INFORMATION
Test Circuit Diagram
(PCN Application)
3.65 V
Data
interface
board
&
3.65 V
PC
φ R
φ P
15
LD fout
14
ZC
13
LE
11
Data
10
Clock
PS
12
9
16
-Comparison freq ; 200 kHz
-R div ratio ; 65
47 k 47 k 47 k
-Prescaler Div ; 64/65
-foL = 1604 MHz
MB15E07
-foM = 1642 MHz
-foH = 1679 MHz
8
1
5
2
6
4
7
3
fin
OSCin
Vp
xfin
1 nF
-Spectrum Analyzer
-Time Interval Analyzer
OSCout
V CC
GND
D O
f OSC = 13 MHz
cox.
33 pF
100 pF
51
18
Output
18
18
Signal Generator
HP8642B
0.1 µ
0.1 µ
NC GND
P
Kv = 43 MHz/V
(MQE523-1619)
cox.
Vsupply = 3.65 V
C
GND
B
+
27 k
V VCO = 3.65 V
10 µ
cox.
+
1 k
33 n
(film cap)
120 p
1 n
+
10 µ
0.1 µ
10 µ
(Continued)
18
MB15E07
(Continued)
PLL Phase Noise
@within loop band = –77.5 dBc/Hz
PLL Lock Up toem = 420 µs
(1604 MHz→1679 MHz, within = 1kHz)
MKR ∆13.02 kHz
∆Mkr x : 420.01163 µs
y : –74.9991 MHz
ATT 00 dB
REF –7.7 dBm
10 dB/
–52.7 dB
30.00500
MHz
RBW
300 kHz
2.00
kHz/div
VBW
300 kHz
29.99500
KHz
CENTER 1.6420000 GHz
SPAN 60.0 MHz
1.9953872 µs
5.1372 µs
PLL Lock Up toem = 400 µs
PLL Reference Leakage
(1679 MHz→1604 MHz, within ±1 kHz)
200 MHz offset = –70.0 dBc
MKR ∆–200 kHz
∆Mkr x : 400.01227 µs
ATT 00 dB
REF –7.2 dBm
10 dB/
–70 dB
y : –75.0020 MHz
30.00500
MHz
RBW
10 kHz
2.00
kHz/div
VBW
10 kHz
29.99500
KHz
CENTER 1.67900 GHz
SPAN 1.00 MHz
1.9953866 µs
5.1366 µs
19
MB15E07
■ ORDERING INFORMATION
Part number
Package
Remarks
16-pin Plastic SSOP
(FPT-16P-M05)
MB15E07PFV1
20
MB15E07
■ PACKAGE DIMENSION
16 pins, Plastic SSOP
(FPT-16P-M05)
* : These dimensions do not include resin protrusion.
1.25 +–00..1200
.049+–..000048
*
5.00±0.10(.197±.004)
0.10(.004)
INDEX
*
4.40±0.10
6.40±0.20
5.40(.213)
NOM
(.173±.004) (.252±.008)
"A"
0.22 +–00..0150
.009+–..000024
0.15 +–00..0025
Details of "A" part
0.10±0.10(.004±.004)
0.65±0.12
(.0256±.0047)
.006–+..000012
(STAND OFF)
0
10°
0.50±0.20
(.020±.008)
4.55(.179)REF
Dimensions in mm (inches)
C
1994 FUJITSU LIMITED F16013S-2C-4
21
FUJITSU LIMITED
For further information please contact:
Japan
FUJITSU LIMITED
Corporate Global Business Support Division
Electronic Devices
KAWASAKI PLANT, 4-1-1, Kamikodanaka
Nakahara-ku, Kawasaki-shi
Kanagawa 211-88, Japan
Tel: (044) 754-3763
All Rights Reserved.
The contents of this document are subject to change without
notice. Customers are advised to consult with FUJITSU sales
representatives before ordering.
Fax: (044) 754-3329
The information and circuit diagrams in this document presented
as examples of semiconductor device applications, and are not
intended to be incorporated in devices for actual use. Also,
FUJITSU is unable to assume responsibility for infringement of
any patent rights or other rights of third parties arising from the
use of this information or circuit diagrams.
North and South America
FUJITSU MICROELECTRONICS, INC.
Semiconductor Division
3545 North First Street
San Jose, CA 95134-1804, U.S.A.
Tel: (408) 922-9000
FUJITSU semiconductor devices are intended for use in
standard applications (computers, office automation and other
office equipment, industrial, communications, and measurement
equipment, personal or household devices, etc.).
CAUTION:
Customers considering the use of our products in special
applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage,
or where extremely high levels of reliability are demanded (such
as aerospace systems, atomic energy controls, sea floor
repeaters, vehicle operating controls, medical devices for life
support, etc.) are requested to consult with FUJITSU sales
representatives before such use. The company will not be
responsible for damages arising from such use without prior
approval.
Fax: (408) 432-9044/9045
Europe
FUJITSU MIKROELEKTRONIK GmbH
Am Siebenstein 6-10
63303 Dreieich-Buchschlag
Germany
Tel: (06103) 690-0
Fax: (06103) 690-122
Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE. LIMITED
#05-08, 151 Lorong Chuan
New Tech Park
Singapore 556741
Tel: (65) 281-0770
Fax: (65) 281-0220
Any semiconductor devices have inherently a certain rate of
failure. You must protect against injury, damage or loss from
such failures by incorporating safety design measures into your
facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating
conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Control Law of Japan, the
prior authorization by Japanese government should be required
for export of those products from Japan.
F9703
FUJITSU LIMITED Printed in Japan
相关型号：
MB15E07SLWQN
PLL Frequency Synthesizer, BICMOS, PQCC16, 4 X 4 MM, 0.80 MM HEIGHT, 0.50 MM PITCH, PLASTIC, QFN-16
FUJITSU
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