MB15F72UV [FUJITSU]
Dual Serial Input PLL Frequency Synthesizer; 双串行输入锁相环频率合成器
| 型号： | MB15F72UV |
| 厂家： | 
FUJITSU |
| 描述： | Dual Serial Input PLL Frequency Synthesizer |
| 文件： | 总26页 (文件大小：225K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FUJITSU SEMICONDUCTOR
DATA SHEET
DS04-21375-2E
ASSP
Dual Serial Input
PLL Frequency Synthesizer
MB15F72UV
■ DESCRIPTION
The Fujitsu MB15F72UV is a serial input Phase Locked Loop (PLL) frequency synthesizer with a 1300 MHz and
a 350 MHz prescalers. A 64/65 or a 128/129 for the 1300 MHz prescaler, and a 8/9 or a 16/17 for the 350 MHz
prescaler can be selected for the prescaler that enables pulse swallow operation.
The BiCMOS process is used, as a result a supply current is typically 2.5 mA at 2.7 V. The supply voltage range
is from 2.4 V to 3.6 V. A refined charge pump supplies well-balanced output current with 1.5 mA and 6 mA
selectable by serial data. The data format is the same as the previous one MB15F02SL, MB12F72SP/UL. Fast
locking is achieved for adopting the new circuit.
MB15F72UV is in the new small package (BCC18) , which decreases a mount area of MB15F72UV about 50%
comparing with the former BCC20 (for dual PLL) .
MB15F72UV is ideally suited for wireless mobile communications, such as CDMA.
■ FEATURES
• High frequency operation : RF synthesizer : 1300 MHz Max
: IF synthesizer : 350 MHz Max
• Low power supply voltage : VCC = 2.4 V to 3.6 V
• Ultra low power supply current : ICC = 2.5 mA Typ
(VCC = 2.7 V, SWIF = SWRF = 0, Ta = +25 °C, in IF, RF locking state)
(Continued)
■ PACKAGE
18-pin plastic BCC
(LCC-18P-M05)
MB15F72UV
(Continued)
• Direct power saving function : Power supply current in power saving mode
Typ 0.1 µA (VCC = 2.7 V, Ta = +25 °C)
Max 10 µA (VCC = 2.7 V)
• Software selectable charge pump current : 1.5 mA/6.0 mA Typ
• Dual modulus prescaler : 1300 MHz prescaler (64/65 or 128/129 ) /350 MHz prescaler (8/9 or 16/17)
• 23 bit shift resister
• Serial input 14-bit programmable reference divider : R = 3 to 16,383
• Serial input programmable divider consisting of :
- Binary 7-bit swallow counter : 0 to 127
- Binary 11-bit programmable counter : 3 to 2,047
• On−chip phase control for phase comparator
• On−chip phase comparator for fast lock and low noise
• Built-in digital locking detector circuit to detect PLL locking and unlocking.
• Operating temperature : Ta = −40 °C to +85 °C
• Serial data format compatible with MB15F72UL
• Ultra small package BCC18 (2.4 mm × 2.7 mm × 0.45 mm)
2
MB15F72UV
■ PIN ASSIGNMENTS
(BCC-18)
TOP VIEW
Clock
OSCIN
Data
LE
1
2
3
4
5
6
18 17 16 15
14
GND
finIF
finRF
XfinRF
GNDRF
VCCRF
13
12
XfinIF
GNDIF
VCCIF
11
8
7
9
10
DoRF
DoIF
PSIF
PSRF
LD/fout
(LCC-18P-M05)
3
MB15F72UV
■ PIN DESCRIPTION
Pin no.
Pin name I/O
BCC
Descriptions
1
GND
Ground for OSC input buffer and the shift register circuit.
Prescaler input pin for the IF-PLL.
Connection to an external VCO should be via AC coupling.
2
finIF
I
I
Prescaler complimentary input pin for the IF-PLL section.
This pin should be grounded via a capacitor.
3
4
5
6
XfinIF
GNDIF
VCCIF
DOIF
Ground for the IF-PLL section.
Power supply voltage input pin for the IF-PLL section, the OSC input buffer and the
shift register circuit.
O
I
Charge pump output pin for the IF-PLL section.
Power saving mode control for the IF-PLL section. This pin must be set at “L” when
the power supply is started up. (Open is prohibited.)
PSIF = “H” ; Normal mode / PSIF = “L” ; Power saving mode
7
8
9
PSIF
LD/fout
PSRF
Lock detect signal output (LD) /phase comparator monitoring
output (fout) pins.The output signal is selected by LDS bit in the serial data.
LDS bit = “H” ; outputs fout signal / LDS bit = “L” ; outputs LD signal
O
Power saving mode control pin for the RF-PLL section. This pin must be set at “L”
when the power supply is started up. (Open is prohibited.)
I
PSRF = “H” ; Normal mode / PSRF = “L” ; Power saving mode
10
11
12
DORF
VCCRF
O
Charge pump output pin for the RF-PLL section.
Power supply voltage input pin for the RF-PLL section
Ground for the RF-PLL section
GNDRF
Prescaler complimentary input pin for the RF-PLL section.
This pin should be grounded via a capacitor.
13
14
XfinRF
finRF
I
I
Prescaler input pin for the RF-PLL.
Connection to an external VCO should be via AC coupling.
Load enable signal input pin (with the schmitt trigger circuit)
When LE is set “H”, data in the shift register is transferred to the corresponding latch
according to the control bit in the serial data.
15
16
LE
I
I
Serial data input pin (with the schmitt trigger circuit)
Data is transferred to the corresponding latch (IF-ref. counter, IF-prog. counter, RF-ref.
counter, RF-prog. counter) according to the control bit in the serial data.
Data
Clock input pin for the 23-bit shift register (with the schmitt trigger circuit)
One bit of data is shifted into the shift register on a rising edge of the clock.
17
18
Clock
I
I
The programmable reference divider input. TCXO should be connected with an AC
coupling capacitor.
OSCIN
4
MB15F72UV
■ BLOCK DIAGRAM
VCCIF GNDIF
5
4
Intermittent
mode control
(IF-PLL)
3 bit latch
PSIF 7
7 bit latch
Binary 7-bit
11 bit latch
Binary 11-bit
fpIF
Phase
comp.
(IF-PLL)
Charge
pump
(IF-PLL)
6
DoIF
Current
Switch
swallow counter programmable
(IF-PLL)
counter (IF-PLL)
finIF 2
Prescaler
(IF-PLL)
(8/9, 16/17
Lock Det.
(IF-PLL)
XfinIF 3
2 bit latch
14 bit latch
1 bit latch
LDIF
Binary 14-bit pro-
grammable ref.
counter(IF-PLL)
C/P setting
counter
T1 T2
frIF
Fast
lock
OSCIN 18
Tuning
Selector
AND
LDRF
frRF
LD
frIF
frRF
fpIF
fpRF
Binary 14-bit pro-
grammable ref.
counter (RF-PLL))
C/P setting
counter
T1 T2
8
LD/
OR
fout
2 bit latch
14 bit latch
1 bit latch
Prescaler
(RF-PLL)
(64/65, 128/129)
finRF 14
Lock Det.
(RF-PLL)
XfinRF 13
Phase
comp.
(RF-PLL)
Charge
pump
(RF-PLL)
Binary 11-bit
programmable
counter (RF-PLL)
Binary 7-bit
swallow counter
(RF-PLL)
Current
Switch
10
DoRF
Intermittent
mode control
(RF-PLL)
PSRF 9
fpRF
3 bit latch
7 bit latch
11 bit latch
Schmitt
circuit
LE 15
Latch selector
Schmitt
circuit
Schmitt
circuit
C
N
1
C
N
2
Data 16
23-bit shift register
Clock 17
1
11
12
VCCRF
GNDRF
GND
5
MB15F72UV
■ ABSOLUTE MAXIMUM RATINGS
Rating
Parameter
Symbol
Unit
Min
−0.5
−0.5
GND
GND
−55
Max
4.0
Power supply voltage
Input voltage
VCC
VI
V
V
VCC + 0.5
VCC
LD/fout
VO
V
Output voltage
DoIF, DoRF
VDO
Tstg
VCC
V
Storage temperature
+125
°C
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
■ RECOMMENDED OPERATING CONDITIONS
Value
Parameter
Symbol
Unit
Remarks
Min
2.4
Typ
Max
3.6
Power supply voltage
Input voltage
VCC
VI
2.7
V
VCCRF = VCCIF
GND
−40
VCC
+85
V
Operating temperature
Ta
°C
Notes : • VCCRF and VCCIF must supply equal voltage.
Even if either RF-PLL or IF-PLL is not used, power must be supplied to VCCRF, and VCCIF to keep them
equal.
It is recommended that the non-use PLL is controlled by power saving function.
• Although this device contains an anti-static element to prevent electrostatic breakdown and the circuitry
has been improved in electrostatic protection, observe the following precautions when handling the
device.
• When storing and transporting the device, put it in a conductive case.
• Before handling the device, confirm the (jigs and) tools to be used have been uncharged (grounded)
as well as yourself. Use a conductive sheet on working bench.
• Before fitting the device into or removing it from the socket, turn the power supply off.
• When handling (such as transporting) the device mounted board, protect the leads with a conductive
sheet.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
6
MB15F72UV
■ ELECTRICAL CHARACTERISTICS
(VCC = 2.4 V to 3.6 V, Ta = −40 °C to +85 °C)
Value
Unit
Sym-
Parameter
bol
Condition
Min
Typ
Max
finIF = 270 MHz,
VCCIF = VpIF = 2.7 V
ICCIF *1
0.6
1.0
1.4
mA
mA
Power supply current
finRF = 910 MHz,
VCCRF = VpRF = 2.7 V
ICCRF *1
1.0
1.5
2.1
IPSIF
PSIF = PSRF = “L”
PSIF = PSRF = “L”
0.1*2
0.1*2
10
10
µA
µA
Power saving current
Operating frequency
IPSRF
finIF *3
finRF *3
OSCIN
finIF
finIF IF PLL
finRF RF PLL
fOSC
50
100
3
350
1300
40
MHz
MHz
MHz
dBm
dBm
VP − P
PfinIF IF PLL, 50 Ω system
PfinRF RF PLL, 50 Ω system
VOSC
−15
−15
0.5
+2
Input sensitivity
finRF
+2
OSCIN
VCC
Data,
LE,
Clock
“H” level input voltage
“L” level input voltage
VIH
Schmitt trigger input
Schmitt trigger input
0.7 VCC + 0.4
V
V
VIL
0.3 VCC − 0.4
“H” level input voltage
“L” level input voltage
VIH
VIL
0.7 VCC
V
V
PSIF,
PSRF
0.3 VCC
Data,
LE,
Clock,
PSIF,
PSRF
“H” level input current
“L” level input current
IIH *4
−1.0
−1.0
+1.0
µA
µA
IIL *4
+1.0
“H” level input current
“L” level input current
IIH
0
+100
µA
µA
OSCIN
IIL *4
−100
0
VCC = 2.7 V,
IOH = −1 mA
“H” level output voltage
“L” level output voltage
“H” level output voltage
VOH
VOL
VCC − 0.4
VCC − 0.4
V
V
V
LD/fout
VCC = 2.7 V, IOL = 1 mA
0.4
0.4
VCC = 2.7 V,
IDOH = −0.5 mA
VDOH
DoIF,
DoRF
VCC = 2.7 V,
IDOL = 0.5 mA
“L” level output voltage
VDOL
V
High impedance
cutoff current
DoIF,
DoRF
VCC = 2.7 V,
VOFF = 0.5 V to VCC − 0.5 V
IOFF
2.5
nA
“H” level output current
“L” level output current
IOH *4 VCC = 2.7 V
−1.0
mA
mA
LD/fout
IOL
VCC = 2.7 V
1.0
(Continued)
7
MB15F72UV
(Continued)
(VCC = 2.4 V to 3.6 V, Ta = −40 °C to +85 °C)
Value
Unit
Parameter
Symbol
Condition
VCC = 2.7 V,
VDOH = VCC / 2,
Ta = +25 °C
Min
Typ
Max
CS bit = “1”
CS bit = “0”
CS bit = “1”
CS bit = “0”
−8.2
−6.0
−4.1
mA
mA
mA
mA
“H” level output
current
DoIF *8
DoRF
IDOH *4
−2.2
4.1
−1.5
6.0
−0.8
8.2
VCC = 2.7 V,
VDOL = VCC / 2,
Ta = +25 °C
“L” level output
current
DoIF *8
DoRF
IDOL
0.8
1.5
2.2
IDOL/IDOH IDOMT *5
vs. VDO IDOVD *6
VDO = VCC / 2
3
%
%
Charge pump
current rate
0.5 V ≤ VDO ≤ VCC − 0.5 V
10
−40 °C ≤ Ta ≤ +85 °C,
VDO = VCC / 2
vs.Ta
IDOTA *7
5
%
*1 : Conditions ; fosc = 12.8 MHz, Ta = +25 °C, SW = “0” in locking state.
*2 : VCCIF = VCCRF = 2.7 V, fosc = 12.8 MHz, Ta = +25 °C, in power saving mode PSIF = PSRF = GND, VIH = VCC VIL =
GND (at CLK, Data, LE)
*3 : AC coupling. 1000 pF capacitor is connected under the condition of minimum operating frequency.
*4 : The symbol “–” (minus) means the direction of current flow.
*5 : VCC = 2.7 V, Ta = +25 °C (||I3| − |I4||) / [ (|I3| + |I4|) / 2] × 100 (%)
*6 : VCC = 2.7 V, Ta = +25°C [ (||I2| − |I1||) / 2] / [ (|I1| + |I2|) / 2] × 100 (%) (Applied to both lDOL and lDOH)
*7 : VCC = 2.7 V, [||IDO (+85°C) | − |IDO (–40°C) || / 2] / [|IDO (+85°C) | + |IDO (–40°C) | / 2] × 100 (%) (Applied to both IDOL and IDOH)
*8 : When Charge pump current is measured, set LDS = “0” , T1 = “0” and T2 = “1”.
I1
I3
I4
I2
IDOL
IDOH
I1
VCC/2
VCC − 0.5 VCC
0.5
Charge pump output voltage (V)
8
MB15F72UV
■ FUNCTIONAL DESCRIPTION
1. Pulse swallow function :
fVCO = [ (P × N) + A] × fOSC ÷ R
fVCO : Output frequency of external voltage controlled oscillator (VCO)
P : Preset divide ratio of dual modulus prescaler (8 or 16 for IF-PLL, 64 or 128 for RF-PLL)
N : Preset divide ratio of binary 11-bit programmable counter (3 to 2,047)
A : Preset divide ratio of binary 7-bit swallow counter (0 ≤ A ≤ 127, A < N)
fOSC : Reference oscillation frequency (OSCIN input frequency)
R : Preset divide ratio of binary 14-bit programmable reference counter (3 to 16,383)
2. Serial Data Input
The serial data is entered using three pins, Data pin, Clock pin, and LE pin. Programmable dividers of IF/
RF-PLL sections, and programmable reference dividers of IF/RF-PLL sections are controlled individually.
The serial data of binary data is entered through Data pin.
On a rising edge of Clock, one bit of the serial data is transferred into the shift register. On a rising edge of load
enable signal, the data stored in the shift register is transferred to one of latches depending upon the control bit
data setting.
The programmable The programmable
The programmable
The programmable
reference counter
for the IF-PLL
reference counter counter and the swallow counter and the swallow
for the RF-PLL
counter for the IF-PLL
counter for the RF-PLL
CN1
CN2
0
0
1
0
0
1
1
1
(1) Shift Register Configuration
• Programmable Reference Counter
(LSB)
Data Flow
(MSB)
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
CN1 CN2 T1 T2 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 CS
X
X
X
X
CS
R1 to R14 : Divide ratio setting bits for the programmable reference counter (3 to 16,383)
T1, T2 : LD/fout output setting bit.
CN1, CN2 : Control bit
: Charge pump current select bit
X
: Dummy bits (Set “0” or “1”)
Note : Data input with MSB first.
9
MB15F72UV
• Programmable Counter
(LSB)
Data Flow
(MSB)
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
SWIF/RF FCIF/RF
CN1 CN2 LDS
A1 A2 A3 A4 A5 A6 A7 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11
A1 to A7
: Divide ratio setting bits for the swallow counter (0 to 127)
N1 to N11 : Divide ratio setting bits for the programmable counter (3 to 2,047)
LDS
: LD/fout signal select bit
SWIF/RF
FCIF/RF
: Divide ratio setting bit for the prescaler (IF : SWIF, RF : SWRF)
: Phase control bit for the phase detector (IF : FCIF, RF : FCRF)
CN1, CN2 : Control bit
Note : Data input with MSB first.
(2) Data setting
• Binary 14-bit Programmable Reference Counter Data Setting (R1 to R14)
Divide ratio
R14 R13 R12 R11 R10 R9
R8
R7
R6
R5
R4
R3 R2
R1
3
0
0
0
0
0
0
0
0
0
0
0
0
1
1
4
•
0
•
0
•
0
•
0
•
0
•
0
•
0
•
0
•
0
•
0
•
0
•
1
•
0
•
0
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
16383
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Note : Divide ratio less than 3 is prohibited.
• Binary 11-bit Programmable Counter Data Setting (N1 to N11)
Divide ratio
N11
N10
N9
N8
N7
N6
N5
N4
N3
N2
N1
3
0
0
0
0
0
0
0
0
0
1
1
4
•
0
•
0
•
0
•
0
•
0
•
0
•
0
•
0
•
1
•
0
•
0
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
2047
1
1
1
1
1
1
1
1
1
1
1
Note : Divide ratio less than 3 is prohibited.
• Binary 7-bit Swallow Counter Data Setting (A1 to A7)
Divide ratio
A7
A6
A5
A4
A3
A2
A1
0
0
0
0
0
0
0
0
1
•
0
•
0
•
0
•
0
•
0
•
0
•
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
127
1
1
1
1
1
1
1
10
MB15F72UV
• Prescaler Data Setting (SW)
Divide ratio
SW = “1”
8/9
SW = “0”
16/17
Prescaler divide ratio IF-PLL
Prescaler divide ratio RF-PLL
64/65
128/129
• Charge Pump Current Setting (CS)
Current value
±6.0 mA
CS
1
±1.5 mA
0
• LD/fout output Selectable Bit Setting
LD/fout pin state
LD output
frIF
LDS
0
T1
0
T2
0
0
1
0
0
1
1
1
0
0
frRF
fpIF
1
1
0
fout
outputs
1
0
1
fpRF
1
1
1
• Phase Comparator Phase Switching Data Setting (FCIF, FCRF)
FCIF = “1” FCRF = “1” FCIF = “0” FCRF = “0”
DoIF DoRF DoIF DoRF
Phase comparator input
fr > fp
fr < fp
H
L
L
H
Z
fr = fp
Z
Z : High-impedance
Depending upon the VCO and LPF polarity, FC bit should be set.
High
(1)
(1) VCO polarity FC = “1”
(2) VCO polarity FC = “0”
VCO Output
Frequency
(2)
Max
LPF Output voltage
Note : Give attention to the polarity for using active type LPF.
11
MB15F72UV
3. Power Saving Mode (Intermittent Mode Control Circuit)
Status
PSIF/PSRF pins
Normal mode
H
L
Power saving mode
The intermittent mode control circuit reduces the PLL power consumption.
By setting the PS pins low, the device enters into the power saving mode, reducing the current consumption.
See the Electrical Characteristics chart for the specific value.
The phase detector output, Do, becomes high impedance.
For the dual PLL, the lock detector, LD, is as shown in the LD Output Logic table.
Setting the PS pins high, releases the power saving mode, and the device works normally.
The intermittent mode control circuit also ensures a smooth startup when the device returns to normal operation.
When the PLL is returned to normal operation, the phase comparator output signal is unpredictable. This is
because of the unknown relationship between the comparison frequency (fp) and the reference frequency (fr)
which can cause a major change in the comparator output, resulting in a VCO frequency jump and an increase
in lockup time.
To prevent a major VCO frequency jump, the intermittent mode control circuit limits the magnitude of the error
signal from the phase detector when it returns to normal operation.
Notes : • When power (VCC) is first applied, the device must be in standby mode, PSIF = PSRF = Low.
• Serial data input are done after the power supply becomes stable, and then the Power saving mode is
released after completed the data input.
OFF
ON
VCC
tV
1 s
Clock
Data
LE
PSIF
tPS > 100 ns
PSRF
(1)
(2)
(3)
(1) PSIF = PSRF = “L” (power saving mode) at Power-ON
(2) Set serial data at least 1 µs after the power supply becomes stable (VCC ≥ 2.2 V) .
(3) Release power saving mode (PSIF, PSRF : “L” → “H”) at least 100 ns after setting serial
data.
12
MB15F72UV
4. Serial Data Input Timing
Frequency multiplier setting is performed through a serial interface using the Data pin, Clock pin, and LE pin.
Setting data is read into the shift register at the rise of the clock signal, and transferred to a latch at the rise of
the LE signal. The following diagram shows the data input timing.
1st data
2nd data
Control bit Invalid data
LSB
Data
MSB
Clock
t1
t2
t3
t6
t7
LE
t4
t5
Parameter
Min
20
Typ
Max Unit
Parameter
Min
100
20
Typ
Max Unit
t1
t2
t3
t4
ns
ns
ns
ns
t5
t6
t7
ns
ns
ns
20
30
100
30
Note : LE should be “L” when the data is transferred into the shift register.
13
MB15F72UV
■ PHASE COMPARATOR OUTPUT WAVEFORM
frIF/frRF
fpIF/fpRF
tWU
tWL
LD
(FC bit = "1")
H
DoIF/DoRF
DoIF/DoRF
Z
L
(FC bit = "0")
H
Z
L
• LD Output Logic
IF-PLL section
RF-PLL section
Locking state/Power saving state
Unlocking state
LD output
Locking state/Power saving state
Locking state/Power saving state
Unlocking state
H
L
L
L
Locking state/Power saving state
Unlocking state
Unlocking state
Notes : • Phase error detection range = −2π to +2π
• Pulses on DoIF/DoRF signals are output to prevent dead zone during locking state.
• LD output becomes low when phase error is tWU or more.
• LD output becomes high when phase error is tWL or less and continues to be so for three cycles
or more.
• tWU and tWL depend on OSCIN input frequency as follows.
tWU ≥ 2/fosc : e.g. tWU ≥ 156.3 ns when fosc = 12.8 MHz
tWU ≤ 4/fosc : e.g. tWL ≤ 312.5 ns when fosc = 12.8 MHz
14
MB15F72UV
■ TEST CIRCUIT (for Measuring Input Sensitivity fin/OSCIN)
S.G.
1000 pF
50 Ω
S.G.
1000 pF
Controller
(divided ratio setting)
50 Ω
OSCIN
Clock
Data
LE
GND
XfinIF
1
2
3
4
5
6
18
17
16
15
VCCRF
S.G.
1000 pF
finRF
14
13
12
11
10
finIF
50 Ω
XfinRF
1000 pF
1000 pF
MB15F72UV
0.1 µF
GNDRF
GNDIF
DoIF
VCCRF
DoRF
7
8
9
VCCIF
LD/
fout
PSRF
PSIF
0.1 µF
Oscilloscope
Note : Terminal number shows that of TSSOP-20.
15
MB15F72UV
■ TYPICAL CHARACTERISTICS
1. fin input sensitivity
RF-PLL input sensitivity vs. Input frequency
10
0
Catalog guaranteed range
−10
−20
−30
−40
−50
VCC = 2.4 V
VCC = 2.7 V
VCC = 3.0 V
VCC = 3.6 V
spec
0
200
400
600
800
1000
1200
1400
1600
1800
2000
finRF (MHz)
IF-PLL input sensitivity vs. Input frequency
10
0
Catalog guaranteed range
−10
−20
−30
−40
−50
VCC = 2.4 V
VCC = 2.7 V
VCC = 3.0 V
VCC = 3.6 V
spec
0
100
200
300
400
500
600
700
800
finIF (MHz)
16
MB15F72UV
2. OSCIN input sensitivity
Input sensitivity vs. Input frequency
10
Catalog guaranteed
range
0
−10
−20
−30
−40
−50
VCC = 2.4 V
VCC = 2.7 V
VCC = 3.0 V
VCC = 3.6 V
SPEC
0
50
100
150
Input frequency fOSC (MHz)
17
MB15F72UV
3. RF/IF-PLL Do output current
• 1.5 mA mode
IDO - VDO
2.50
VCC = 2.7 V, Ta = +25˚C
2.00
1.50
1.00
0.50
0.00
−0.50
−1.00
−1.50
−2.00
−2.50
0.0
0.5
1.0
1.5
2.0
2.5
3.0
Charge pump output voltage VDO (V)
• 6.0 mA mode
IDO - VDO
8.00
6.00
VCC = 2.7 V, Ta = +25˚C
4.00
2.00
0.00
−2.00
−4.00
−6.00
−8.00
0.0
0.5
1.0
1.5
2.0
2.5
3.0
Charge pump output voltage VDO (V)
18
MB15F72UV
4. fin input impedance
finIF input impedance
4 : 39.5 Ω
−258.98 Ω
1.7558 pF
350.000 000 MHz
1 : 906.94 Ω
−1.2097 kΩ
50 MHz
2 : 156.47 Ω
−588.44 Ω
150 MHz
3 : 65.719 Ω
−363.31 Ω
250 MHz
1
4
2
3
CENTER 275.000 000 MHz
SPAN 450.000 000 MHz
finRF input impedance
4 : 10.426 Ω
−50.781 Ω
2.4109 pF
1 300.000 000 MHz
1 : 30.711 Ω
−221.73 Ω
400 MHz
2 : 16.602 Ω
−120.77 Ω
700 MHz
3 : 12.367 Ω
−76.926 Ω
1 GHz
1
4
2
3
START 100.000 000 MHz
STOP 1 500.000 000 MHz
19
MB15F72UV
5. OSCIN input impedance
OSCIN input impedance
4 : 074.81 Ω
−1.3334 kΩ
2.9839 pF
40.000 000 MHz
1 :
882 Ω
−5.1865 kΩ
10 MHz
2 : 257.13 Ω
−2.6638 kΩ
20 MHz
3 : 121.69 Ω
−1.7799 kΩ
30 MHz
4
1
2
3
START 3.000 000 MHz
STOP 40.000 000 MHz
20
MB15F72UV
■ REFERENCE INFORMATION
(for Lock-up Time, Phase Noise and Reference Leakage)
fVCO = 738.5 MHz VCC = 2.7 V
Test Circuit
KV = 30 MHz/V
fr = 12.5 kHz
fOSC = 19.8 MHz CP : 6 mA mode
VVCO = 3.75 V
Ta = +25 °C
S.G.
OSCIN
LPF
DO
fin
LPF
8.2 kΩ
Spectrum
Analyzer
3 kΩ
VCO
3900 pF
5600 pF
56000 pF
• PLL Reference Leakage
ATTEN 10 dB
RL 0 dBm
VAVG 16
10 dB/
∆MKR −70.00 dB
12.3 kHz
∆MKR
12.3 kHz
−70.00 dB
CENTER 738.5000 MHz
SPAN 200.0 kHz
SWP 500 ms
RBW 1.0 kHz
VBW 1.0 kHz
• PLL Phase Noise
ATTEN 10 dB
RL 0 dBm
VAVG 16
10 dB/
∆MKR −58.16 dB
1.00 kHz
∆MKR
1.00 kHz
−58.16 dB
CENTER 738.50000 MHz
RBW 30 Hz VBW 30 Hz
SPAN 10.00 kHz
SWP 1.92 s
(Continued)
21
MB15F72UV
(Continued)
• PLL Lock Up time
• PLL Lock Up time
738.5 MHz→775.5 MHz within ± 1 kHz
Lch→Hch 3.267 ms
775.5 MHz→738.5 MHz within ± 1 kHz
Hch→Lch 3.2 ms
775.504000 MHz
738.504000 MHz
775.500000 MHz
738.500000 MHz
775.496000 MHz
738.496000 MHz
0.00 s
5.000 ms
1.000 ms/div
T2 3.800 µs
10.00 ms
∆3.267 ms
0.00 s
5.000 ms
1.000 ms/div
T2 3.733 µs
10.00 ms
∆3.200 ms
T1 533 µs
T1 533 µs
22
MB15F72UV
■ APPLICATION EXAMPLE
1000 pF
TCXO
Controller
(divided ratio setting)
OSCIN
Clock
Data
LE
OUTPUT
GND
OUTPUT
1
18
17
16
15
1000 pF
finIF
1000 pF
finRF
2
3
4
5
6
14
13
12
11
10
XfinIF
VCO
XfinRF
1000 pF
1000 pF
VCO
LPF
MB15F72UV
GNDRF
GNDIF
VCCRF
LPF
VCCIF
DoIF
VCCRF
DoRF
0.1 µF
7
8
9
VCCIF
PSRF
PSIF
0.1 µF
LD/
fout
Lock Detect
Note : Clock, Data, LE : The schmitt trigger circuit is provided (insert a pull-down or pull-up register
to prevent oscillation when open-circuit in the input) .
23
MB15F72UV
■ USAGE PRECAUTIONS
(1) VCCRF and VCCIF must be equal voltage.
Even if either RF-PLL or IF-PLL is not used, power must be supplied to VCCRF and VCCIF to keep them
equal. It is recommended that the non-use PLL is controlled by power saving function.
(2) To protect against damage by electrostatic discharge, note the following handling precautions :
-Store and transport devices in conductive containers.
-Use properly grounded workstations, tools, and equipment.
-Turn off power before inserting or removing this device into or from a socket.
-Protect leads with conductive sheet, when transporting a board mounted device.
■ ORDERING INFORMATION
Part number
MB15F72UVPVB
Package
Remarks
18-pin plastic BCC
(LCC-18P-M05)
24
MB15F72UV
■ PACKAGE DIMENSION
18-pin plastic BCC
(LCC-18P-M05)
2.31(.090)
TYP
0.45(.018)
TYP.
2.70±0.10
(.106±.004)
0.45±0.05
(.018±.002)
10
15
15
10
(Mount height)
2.01(.079)
TYP
INDEX AREA
2.40±0.10
(.094±.004)
0.90(.035)
REF
1.90(.075)
REF
"A"
0.45(.018)
TYP.
"C"
"B"
0.075±0.025
(.003±.001)
(Stand off)
1
6
1.35(.053)
REF
6
1
2.28(.090)
REF
Details of "A" part
Details of "B" part
C0.10(.004)
Details of "C" part
0.36±0.06
0.05(.002)
0.36±0.06
(.014±.002)
0.25±0.06
(.010±.002)
0.14(.006)
MIN.
(.014±.002)
0.25±0.06
0.28±0.06
0.28±0.06
(.010±.002)
(.011±.002)
(.011±.002)
C
2003 FUJITSU LIMITED C18058S-c-1-1
Dimensions in mm (inches)
Note : The values in parentheses are reference values.
25
MB15F72UV
FUJITSU LIMITED
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information, such as descriptions of function and application
circuit examples, in this document are presented solely for the
purpose of reference to show examples of operations and uses of
Fujitsu semiconductor device; Fujitsu does not warrant proper
operation of the device with respect to use based on such
information. When you develop equipment incorporating the
device based on such information, you must assume any
responsibility arising out of such use of the information. Fujitsu
assumes no liability for any damages whatsoever arising out of
the use of the information.
Any information in this document, including descriptions of
function and schematic diagrams, shall not be construed as license
of the use or exercise of any intellectual property right, such as
patent right or copyright, or any other right of Fujitsu or any third
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Fujitsu assumes no liability for any infringement of the intellectual
property rights or other rights of third parties which would result
from the use of information contained herein.
The products described in this document are designed, developed
and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use,
personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal
risks or dangers that, unless extremely high safety is secured, could
have a serious effect to the public, and could lead directly to death,
personal injury, severe physical damage or other loss (i.e., nuclear
reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile
launch control in weapon system), or (2) for use requiring
extremely high reliability (i.e., submersible repeater and artificial
satellite).
Please note that Fujitsu will not be liable against you and/or any
third party for any claims or damages arising in connection with
above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You
must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
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authorization by Japanese government will be required for export
of those products from Japan.
F0312
FUJITSU LIMITED Printed in Japan
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