MB39A123PVK-XXXE1 [FUJITSU]

Dual Switching Controller, 0.4A, 2000kHz Switching Freq-Max, PBCC48, 7 X 7 MM, 0.80 MM HEIGHT, 0.50 MM PITCH, ROHS COMPLIANT, PLASTIC, BCC-48;

MB39A123PVK-XXXE1


型号：	MB39A123PVK-XXXE1
厂家：	FUJITSU
描述：	Dual Switching Controller, 0.4A, 2000kHz Switching Freq-Max, PBCC48, 7 X 7 MM, 0.80 MM HEIGHT, 0.50 MM PITCH, ROHS COMPLIANT, PLASTIC, BCC-48 开关
文件：	总44页 (文件大小：433K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

FUJITSU MICROELECTRONICS

DATA SHEET

DS04-27257-2Ea

ASSP For Power Supply Applications

6 ch DC/DC Converter IC with

Synchronous Rectification

MB39A123

■ DESCRIPTION

MB39A123 is a 6-channel DC/DC converter IC using pulse width modulation (PWM) , and it is suitable for up

conversion, down conversion, and up/down conversion. MB39A123 is built in 6 channels into BCC-48++/LQFP-

48P package and this IC can control and soft-start at each channel. MB39A123 is suitable for power supply of

high performance potable instruments such as a digital still camera (DSC).

■ FEATURES

• Supports for step-down with synchronous rectification (ch.1)

• Supports for step-down and up/down Zeta conversion (ch.2 to ch.4)

• Supports for step-up and up/down Sepic conversion (ch.5, ch.6)

• Negative voltage output (Inverting amplifier) (ch.4)

• Low voltage start-up (ch.5, ch.6) : 1.7 V

• Power supply voltage range

• Reference voltage

: 2.5 V to 11 V

: 2.0 V 1%

• Error amplifier reference voltage : 1.0 V 1% (ch.1) , 1.23 V 1% (ch.2 to ch.6)

• Oscillation frequency range

: 200 kHz to 2.0 MHz

• Standby current

: 0 µA (Typ)

• Built-in soft-start circuit independent of loads

• Built-in totem-pole type output for MOS FET

• Short-circuit detection capability by external signal (−INS terminal)

• Two types of packages (BCC-48 pin : 1 type, LQFP-48 pin : 1 type)

■ APPLICATIONS

• Digital still camera(DSC)

• Digital video camera(DVC)

• Surveillance camera

etc.

Copyright©2006-2008 FUJITSU MICROELECTRONICS LIMITED All rights reserved

2007.3

MB39A123

■ PIN ASSIGNMENTS

(TOP VIEW)

1

48

47

46

45

44

43

42

41

40

39

38

37

CTL

2

3

36

35

34

33

32

31

30

29

28

27

26

CTL1

CTL2

CTL3

CTL4

CTL5

CTL6

−INS

VCCO

OUT1-1

4

OUT1-2

OUT2

OUT3

OUT4

OUT5

OUT6

GNDO

CS6

5

6

7

8

9

VREF

GND

10

11

12

RT

CT

−INE6

13

14

15

16

17

18

19

20

21

22

23

24

25

FB6

(LCC-48P-M08)

(Continued)

2

MB39A123

(Continued)

(TOP VIEW)

48 47 46 45 44 43 42 41 40 39 38 37

1

2

36

35

34

33

32

31

30

29

28

27

26

25

CTL

VCCO

CTL1

CTL2

CTL3

CTL4

OUT1-1

OUT1-2

3

4

OUT2

OUT3

OUT4

OUT5

OUT6

GNDO

CS6

5

6

CTL5

CTL6

−INS

VREF

GND

RT

7

8

9

10

11

12

−INE6

CT

FB6

13 14 15 16 17 18 19 20 21 22 23 24

(FPT-48P-M26)

3

MB39A123

■ PIN DESCRIPTIONS

Block

name

Pin No. Pin name I/O

Description

ch.1• Error amplifier output terminal

37

38

39

FB1

−INE1

CS1

O

I

ch.1• Error amplifier inverted input terminal

⎯

ch.1• Soft-start setting capacitor connection terminal

ch.1

ch.1• P-ch drive output terminal

(External main side FET gate driving)

35

34

OUT1-1

OUT1-2

O

O

ch.1• N-ch drive output terminal

(External synchronous rectification side FET gate driving)

43

42

41

40

33

44

45

46

47

32

14

15

16

17

31

19

18

23

22

21

20

30

24

25

26

27

29

DTC2

FB2

I

O

I

ch.2 • Dead time control terminal

ch.2 • Error amplifier output terminal

ch.2 • Error amplifier inverted input terminal

ch.2 • Soft-start setting capacitor connection terminal

ch.2 • P-ch drive output terminal

ch.2

ch.3

−INE2

CS2

⎯

O

I

OUT2

DTC3

FB3

ch.3 • Dead time control terminal

O

I

ch.3 • Error amplifier output terminal

ch.3 • Error amplifier inverted input terminal

ch.3 • Soft-start setting capacitor connection terminal

ch.3 • P-ch drive output terminal

−INE3

CS3

⎯

O

I

OUT3

DTC4

FB4

ch.4 • Dead time control terminal

O

I

ch.4 • Error amplifier output terminal

ch.4 • Error amplifier inverted input terminal

ch.4 • Soft-start setting capacitor connection terminal

ch.4 • P-ch drive output terminal

−INE4

CS4

ch.4

⎯

O

I

OUT4

−INA

OUTA

DTC5

FB5

Inverting amplifier input terminal

O

I

Inverting amplifier output terminal

ch.5 • Dead time control terminal

O

I

ch.5 • Error amplifier output terminal

ch.5 • Error amplifier inverted input terminal

ch.5 • Soft-start setting capacitor connection terminal

ch.5 • N-ch drive output terminal

ch.5

ch.6

−INE5

CS5

⎯

O

I

OUT5

DTC6

FB6

ch.6 • Dead time control terminal

O

I

ch.6 • Error amplifier output terminal

ch.6 • Error amplifier inverted input terminal

ch.6 • Soft-start setting capacitor connection terminal

ch.6 • N-ch drive output terminal

−INE6

CS6

⎯

O

OUT6

(Continued)

4

MB39A123

(Continued)

Block

name

Pin No. Pin name I/O

Description

12

11

1

CT

RT

⎯

⎯

I

Triangular wave frequency setting capacitor connection terminal

Triangular wave frequency setting resistor connection terminal

Power supply control terminal

OSC

CTL

2

CTL1

CTL2

CTL3

CTL4

CTL5

CTL6

CSCP

−INS

VCCO

VCC

I

ch.1 control terminal

3

I

ch.2 control terminal

4

I

ch.3 control terminal

Control

5

I

ch.4 control terminal

6

I

ch.5 control terminal

7

I

ch.6 control terminal

13

8

⎯

I

Short-circuit detection circuit capacitor connection terminal

Short-circuit detection comparator inverted input terminal

Drive output block power supply terminal

Power supply terminal

36

48

9

⎯

⎯

O

⎯

⎯

Power

VREF

GNDO

GND

Reference voltage output terminal

Drive output block ground terminal

Ground terminal

28

10

5

MB39A123

■ BLOCK DIAGRAM

Step-down

(Synchronous

Rectification)

A

L priority

VCCO

−INE1

<<ch.1>>

Io = 300 mA

at VCCO = 7 V

Drive1-1

P-ch

Vo1

(1.2 V)

A

38

39

36

35

VREF

Error

Amp1

1.1 µA

PWM

Comp.1

−

CS1

FB1

+

+

−

OUT1-1

+

(1.0 V)

37

Reference voltage

1.0 V 1 %

Drive1-2

N-ch

OUT1-2

34

Step-down

Dead Time

(td = 50 ns)

Io = 300 mA

B

at VCCO = 7 V

L priority

VREF

Vo2

(2.5 V)

−INE2

<<ch.2>>

41

40

B

C

D

L priority

VREF

Error

Amp2

Max Duty

92 % 5 %

±

PWM

1.1 µA

−

Comp.2

CS2

+

+

+

Drive2

P-ch

OUT2

+

33

−

1.23 V

FB2

42

43

Step-down

Io = 300 mA

at VCCO = 7 V

Reference voltage

1.23 V 1 %

DTC2

C

L priority

VREF

Vo3

(3.3 V)

−INE3

<<ch.3>>

46

47

L priority

PWM

VREF

Max Duty

92 % 5 %

Error

Amp3

±

1.1 µA

−

Comp.3

CS3

+

+

Drive3

P-ch

+

OUT3

+

32

−

1.23 V

FB3

45

44

Io = 300 mA

at VCCO = 7 V

DTC3

Reference voltage

1.23 V 1 %

−INA

<<ch.4>>

−

19

+

OUTA

18

INVAmp

D

Inverting

L priority

VREF

−INE4

Vo4

(−7.5 V)

16

L priority

PWM

VREF

VREF

VREF

Error

Amp4

Max Duty

92 % 5 %

V

IN

1.1 µA

1.1 µA

1.1 µA

(5 V-11 V)

−

Comp.4

CS4

+

+

Drive4

P-ch

17

+

+

OUT4

31

−

1.23 V

FB4

15

14

Io = 300 mA

at VCCO = 7 V

Reference voltage

1.23 V 1 %

DTC4

Step-up

L priority

VREF

E

<<ch.5>>

21

20

E

L priority

PWM

Max Duty

92 % 5 %

−INE5

Error

Amp5

Vo5

(15 V)

−

Comp.5

CS5

+

+

Drive5

N-ch

+

OUT5

+

30

−

1.23 V

FB5

22

23

Io = 300 mA

at VCCO = 7 V

Reference voltage

1.23 V 1 %

DTC5

F

Transformer

L priority

VREF

Vo6-1

(15 V)

Vo6-2

(5.0 V)

−INE6

<<ch.6>>

26

27

F

L priority

PWM

Max Duty

92 % 5 %

Error

Amp6

−

Comp.6

CS6

+

+

Drive6

N-ch

+

+

OUT6

29

28

−

1.23 V

GNDO

FB6

25

24

Io = 300 mA

at VCCO = 7 V

Reference voltage

1.23 V 1 %

DTC6

VREF

SCP

H:at SCP

−INS

Comp.

Short-circuit

−

8

detection signal

SCP

+

(L: at short-circuit)

1 V

Charge current

CSCP

1 µA

Error Amp power supply

SCP Comp. power supply

13

H:UVLO release

UVLO1

0.9 V

0.4 V

VCC

CTL

48

Error Amp

reference

1.0 V/1.23 V

2

3

4

5

6

7

CTL1

CTL2

CTL3

CTL4

CTL5

CTL6

H:ON (Power ON)

L:OFF(Standby mode)

VTH = 1.0 V

H:ON

L:OFF

VTH = 1.0 V

bias

Power

ON/OFF

CTL

1

OSC

VR

VREF

CHCTL

UVLO2

Precision

0.8 %

2.0 V

11

RT

12

9

10

CT

VREF

Precision

GND

Precision 0.5 %

(2.0 MHz)

1 %

<< 48 Pin >>

PKG:BCC-48++

:LQFP-48P

6

MB39A123

■ ABSOLUTE MAXIMUM RATINGS

Rating

Parameter

Symbol

Conditions

Unit

Min

Max

Power supply voltage

Output current

V^CC

I^O

VCC, VCCO terminals

⎯

12

V

OUT1-1, OUT1-2, OUT2 to OUT6

terminals

⎯

20

mA

OUT1-1, OUT1-2, OUT2 to OUT6

terminals

Duty ≤ 5%

Peak output current

I^OP

⎯

400

mA

Ta ≤ +25 °C (BCC-48++)

Ta ≤ +25 °C (LQFP-48P)

⎯

⎯

⎯

1670*

2000*

+125

mW

mW

°C

Power dissipation

P^D

Storage temperature

T^STG

−55

* : When mounted on a 117 mm × 84 mm × 0.8 mm FR-4 boards.

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

7

MB39A123

■ RECOMMENDED OPERATING CONDITIONS

Value

Typ

Parameter

Symbol

Conditions

Unit

Min

Max

ch.5, ch.6, VCC, VCCO

terminals

Start power supply voltage

V^CC

1.7

⎯

11

V

Power supply voltage

V^CC

I^REF

VCC, VCCO terminals

VREF terminal

2.5

−1

0

4

11

0

V

mA

V

Reference voltage output current

⎯

⎯

⎯

⎯

⎯

−INE1 to −INE6 terminals

−INA terminal

VCC − 0.9

V^CC− 1.8

V^REF

V^INE

− 0.2

0

V

Input voltage

−INS terminal

V

V^DTC

V^CTL

DTC2 to DTC6 terminals

0

VREF

V

CTL, CTL1 to CTL6

terminals

Control input voltage

Output current

0

⎯

⎯

11

V

OUT1-1, OUT1-2, OUT2 to

OUT6 terminals

I^O

−15

+15

mA

OUT1-1, OUT1-2, OUT2 to

OUT6 terminals

connection FET

Total gate charge of external FET

Qg

⎯

2.6

7.5

nC

fosc = 2 MHz

Oscillation frequency

Timing capacitor

f^OSC

C^T

⎯

0.2

27

3.0

⎯

1.0

100

6.8

0.1

0.1

2.0

680

39

MHz

pF

⎯

Timing resistor

R^T

⎯

CS1 to CS6 terminals

⎯

kΩ

µF

Soft-start capacitor

Short-circuit detection capacitor

C^S

1.0

1.0

C^SCP

⎯

µF

Reference voltage output

capacitor

C^REF

Ta

⎯

⎯

⎯

0.1

1.0

µF

°C

Operating ambient temperature

−30

+25

+85

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the

semiconductor device. All of the device’s electrical characteristics are warranted when the device is

operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges. Operation

outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on

the data sheet. Users considering application outside the listed conditions are advised to contact their

representatives beforehand.

8

MB39A123

■ ELECTRICAL CHARACTERISTICS

(VCC = VCCO = 4 V, Ta = +25 °C)

Value

Unit

Parameter

Symbol Pin No.

Conditions

VREF = 0 mA

Min

Typ

Max

V^REF1

V^REF2

V^REF3

Line

9

9

9

9

9

1.98

2.00

2.02

V

V

Output voltage

VCC = 2.5 V to 11 V

1.975 2.000 2.025

1.975 2.000 2.025

VREF = 0 mA to −1 mA

V^CC= 2.5 V to 11 V*

VREF = 0 mA to −1 mA*

V

Reference

Voltage Block

[VREF]

Input stability

Load stability

⎯

⎯

2

2

⎯

⎯

mV

mV

Load

Temperature

stability

∆V^REF/

9

9

Ta = 0 °C to +85 °C*

VREF = 0 V*

VCC =

⎯

⎯

0.20

−130

1.8

⎯

⎯

%

mA

V

V^REF

Short-circuit

output current

I^OS

Under voltage Threshold

V^TH1

35

1.7

1.9

lockout

voltage

protection

circuit Block

(ch.1 to ch.4)

[UVLO1]

Hysteresis

width

V^H1

V^RST1

V^TH2

35

35

30

⎯

0.05

1.55

1.35

0.1

1.7

1.5

0.2

V

V

V

Reset voltage

VCC =

1.85

1.65

Under voltage Threshold

lockout

VCC =

voltage

protection

circuit Block

(ch.5, ch.6)

[UVLO2]

Hysteresis

width

V^H2

V^RST2

V^TH

30

30

13

⎯

0.02

1.27

0.65

0.05

1.45

0.70

0.1

V

V

V

Reset voltage

VCC =

1.63

0.75

Threshold

voltage

⎯

Short-circuit

detection Block

[SCP]

Input source

current

I^CSCP

fosc¹

fosc²

13

⎯

−1.4

0.95

0.945

⎯

−1.0

1.0

1.0

1.0

−0.6

µA

C^T= 100 pF,

R^T= 6.8 kΩ

29 to 35

29 to 35

29 to 35

1.05 MHz

1.055 MHz

Oscillation

frequency

C^T= 100 pF, RT = 6.8 kΩ

V^CC= 2.5 V to 11 V

Triangular

Wave Oscilla-

tor Block

Frequency

Input stability

∆f^OSC/

f^OSC

C^T= 100 pF, RT = 6.8 kΩ

V^CC= 2.5 V to 11 V*

⎯

⎯

%

%

[OSC]

Frequency

temperature

stability

∆f^OSC/

f^OSC

C^T= 100 pF, RT = 6.8 kΩ

Ta = 0 °C to +85 °C*

29 to 35

⎯

1.0

Soft-Start Block

(ch.1 to ch.6)

[CS1 to CS6]

Charge

current

17,20,27,

39,40,47

I^CS

CS1 to CS6 = 0 V

−1.45 −1.1 −0.75 µA

(Continued)

9

MB39A123

(VCC = VCCO = 4 V, Ta = +25 °C)

Value

Unit

Parameter

Symbol Pin No.

Conditions

Min

Typ Max

V^CC= 2.5 V to 11 V

Ta = +25 °C

V^TH1

V^TH2

38

38

38

0.990 1.000 1.010

0.988 1.000 1.012

V

V

Reference

voltage

V^CC= 2.5 V to 11 V

Ta = 0 °C to +85 °C*

Temperature

stability

∆V^TH/

V^TH

Ta = 0 °C to +85 °C*

⎯

0.1

⎯

%

Input bias

current

I^B

38

37

37

−INE1 = 0 V

DC*

−120 −30

⎯

⎯

⎯

⎯

nA

dB

Error Amp Block

(ch.1)

[Error Amp1]

Voltage gain

A^V

⎯

⎯

100

1.4

Frequency

bandwidth

BW

A^V= 0 dB*

MHz

V

V^OH

V^OL

37

37

⎯

⎯

1.7

1.9

40

Output

voltage

⎯

200 mV

Output source

current

I^SOURCE

I^SINK

37

37

FB1 = 0.65 V

FB1 = 0.65 V

⎯

−2

−1

mA

Output sink

current

150

200

⎯

µA

16, 21,

26, 41,

46

V^CC= 2.5 V to 11 V

Ta = +25 °C

V^TH3

1.217 1.230 1.243

1.215 1.230 1.245

V

V

Reference

voltage

16, 21,

26, 41,

46

V^CC= 2.5 V to 11 V

Ta = 0 °C to +85 °C*

V^TH4

16, 21,

Temperature

stability

∆V^TH/

V^TH

26, 41, Ta = 0 °C to +85 °C*

46

⎯

0.1

⎯

⎯

⎯

⎯

⎯

%

16, 21,

Input bias

current

I^B

26, 41, −INE2 to −INE6 = 0 V

46

−120 −30

nA

dB

MHz

V

Error Amp Block

(ch.2 to ch.6)

[Error Amp2 to

Error Amp6]

15, 22,

25, 42, DC*

45

Voltage gain

A^V

⎯

⎯

100

1.4

1.9

40

15, 22,

25, 42, A^V= 0 dB*

45

Frequency

bandwidth

BW

V^OH

V^OL

15, 22,

25, 42,

45

⎯

⎯

1.7

⎯

Output

voltage

15, 22,

25, 42,

45

200 mV

(Continued)

10

MB39A123

(VCC = VCCO = 4 V, Ta = +25 °C)

Value

Unit

Parameter

Output source

Symbol Pin No.

Conditions

Min Typ Max

15, 22,

I^SOURCE

25, 42, FB2 to FB6 = 0.65 V

45

⎯

−2

−1

mA

Error Amp Block

(ch.2 to ch.6)

[Error Amp2 to

Error Amp6]

current

15, 22,

Output sink

current

I^SINK

25, 42, FB2 to FB6 = 0.65 V

45

150 200

⎯

µA

Input offset

voltage

V^IO

18

OUTA = 1.23V

−10

0

+ 10 mV

Input bias

current

I^B

19

18

18

− INA = 0V

DC*

−120 −30

⎯

⎯

⎯

⎯

nA

dB

Voltage gain

A^V

⎯

⎯

100

1.0

Frequency

bandwidth

Inverting Amp

Block (ch.4)

[Inv Amp]

BW

A^V= 0 dB*

MHz

V

V^OH

V^OL

18

18

⎯

1.7

1.9

40

Output

voltage

⎯

⎯

200 mV

Output source

current

I^SOURCE

18

18

OUTA = 1.23V

OUTA = 1.23V

⎯

−2

−1

mA

Output sink

current

I^SINK

V^T0

150 200

⎯

µA

PWM

34, 35 Duty cycle = 0%

0.35 0.4 0.45

V

Comparator

Block

(ch.1)

Threshold

voltage

V^T100

34, 35 Duty cycle = 100%

0.85 0.9 0.95

V

[PWM Comp.1]

PWM

Comparator

Block

V^T0

29 to 33 Duty cycle = 0%

29 to 33 Duty cycle = 100%

0.35 0.4 0.45

0.85 0.9 0.95

V

V

Threshold

voltage

V^T100

(ch.2 to ch.6)

[PWM Comp.2 to

PWM Comp.6]

Maximumduty

cycle

C^T= 100 pF,

29 to 33

Dtr

87

92

97

%

R^T= 6.8 kΩ

Output source

current

Duty ≤ 5%

OUT = 0 V

I^SOURCE29 to 35

⎯

−130 −75 mA

Output sink

current

Duty ≤ 5%

OUT = 4 V

I^SINK

29 to 35

75

130

⎯

mA

Output Block

(ch.1 to ch.6)

[Drive1 to Drive6]

R^OH

R^OL

t^D1

29 to 35 OUT = − 15 mA

29 to 35 OUT = 15 mA

⎯

⎯

⎯

⎯

18

18

50

50

27

27

⎯

⎯

Ω

Ω

Output on

resistor

34, 35 OUT2

34, 35 OUT1

− OUT1

− OUT2

*

*

ns

ns

Dead time

t^D2

(Continued)

11

MB39A123

(Continued)

(VCC = VCCO = 4 V, Ta = +25 °C)

Value

Unit

Parameter

Symbol Pin No.

Conditions

Min Typ Max

Short-Circuit

Detection

Comparator

Block

Threshold

voltage

V^TH

35

8

⎯

0.97 1.00 1.03

V

Input bias

current

I^B

−INS = 0 V

−25 −20 −17 µA

[SCP Comp.]

Output on

condition

V^IH

V^IL

1 to 7 CTL, CTL1 to CTL6

1 to 7 CTL, CTL1 to CTL6

1.5

0

⎯

⎯

11

V

V

Control Block

(CTL,

CTL1 to CTL6)

[CTL, CHCTL]

Output off

condition

0.5

I^CTLH

I^CTLL

I^CCS

1 to 7 CTL, CTL1 to CTL6 = 3 V

1 to 7 CTL, CTL1 to CTL6 = 0 V

5

30

⎯

0

60

1

µA

µA

µA

µA

Input current

⎯

⎯

⎯

48

36

CTL, CTL1 to CTL6 = 0 V

CTL = 0 V

2

Standby

current

I^CCSO

0

1

General

Power supply

current

I^CC

48

CTL = 3 V

⎯

4.5

6.8 mA

* : Standard design value

12

MB39A123

■ TYPICAL CHARACTERISTICS

Power Supply Current vs.

Power Supply Voltage

Reference Voltage vs.

Power Supply Voltage

5

5

4

3

2

1

0

Ta = + 25 °C

CTL = 3 V

Ta = + 25 °C

CTL = 3 V

VREF = 0 mA

4

3

2

1

0

0

2

4

6

8

10

12

0

2

4

6

8

10

12

Power Supply Voltage VCC (V)

Power Supply Voltage VCC (V)

Reference Voltage vs.

Operating Ambient Temperature

2.05

2.04

2.03

2.02

2.01

2.00

1.99

1.98

1.97

1.96

1.95

VCC = 4 V

CTL = 3 V

VREF = 0 mA

−40

−20

0

+20

+40

+60

+80

+100

Operating Ambient Temperature Ta ( °C)

Reference Voltage vs.

CTL Terminal Voltage

CTL Terminal Current vs.

CTL Terminal Voltage

5.0

4.0

3.0

2.0

1.0

0.0

200

150

100

50

Ta = + 25 °C

VCC = 4 V

Ta = + 25 °C

VCC = 4 V

VREF = 0 mA

0

0

2

4

6

8

10

12

0

2

4

6

8

10

12

CTL Terminal Voltage VCTL (V)

CTL Terminal Voltage VCTL (V)

(Continued)

13

MB39A123

Triangular Wave Oscillation Frequency vs.

Timing Resistor

Triangular Wave Oscillation Frequency vs.

Timing Capacity

10000

1000

100

10000

Ta = + 25 °C

VCC = 4 V

CTL = 3 V

Ta = + 25 °C

VCC = 4 V

CTL = 3 V

1000

100

10

CT = 27 pF

RT = 3 kΩ

CT = 100 pF

CT = 680 pF CT = 220 pF

RT = 6.8 kΩ

RT = 39 kΩ RT = 13 kΩ

10

1

10

100

1000

10

100

1000

10000

Timing Resistor RT (kΩ)

Timing Capacity CT (pF)

Triangular Wave Upper and Lower Limit Voltage

vs. Triangular Wave Oscillation Frequency

Triangular Wave Upper and Lower Limit Voltage

vs. Operating Ambient Temperature

1.20

1.20

Ta = + 25 °C

VCC = 4 V

1.10

1.10

1.00

0.90

0.80

0.70

0.60

0.50

0.40

0.30

0.20

VCC = 4 V

CTL = 3 V

CTL = 3 V

R = 6.8 kΩ

T

^T= 100 pF

R^T= 6.8 kΩ

C

1.00

Upper limit

Upper limit

0.90

0.80

0.70

0.60

0.50

0.40

Lower limit

Lower limit

0.30

0.20

0

200 400 600 800 1000 1200 1400 1600 1800 2000 2200

−40

−20

0

+20

+40

+60

+80

+100

Triangular Wave Oscillation Frequency fOSC (kHz)

Operating Ambient Temperature Ta ( °C)

Triangular Wave Oscillation Frequency

vs. Operating Ambient Temperature

1100

VCC = 4 V

1080

1060

1040

1020

1000

980

CTL = 3 V

R

= 6.8 kΩ

^T= 100 pF

C

T

960

940

920

900

−40

−20

0

+20

+40

+60

+80

+100

Operating Ambient Temperature Ta ( °C)

(Continued)

14

MB39A123

ON Duty Cycle vs. DTC Terminal Voltage

Maximum Duty Cycle vs. Oscillation Frequency

100

100

Ta = + 25 °C

VCC = 4 V

Ta = + 25 °C

VCC = CTL = 4 V

FB = 2 V

fosc = 200 kHz

95

90

85

80

75

70

65

60

55

50

CTL = 4 V

95

FB = 2 V

C^T= 100 pF

DTC = Open

fosc = 1 MHz

90

RT = 3 kΩ

RT = 39 kΩ

85

RT = 13 kΩ

fosc = 2 MHz

RT = 6.8 kΩ

80

75

70

0

200 400 600 800 1000 1200 1400 1600 1800 2000 2200

0.6

0.65

0.7

0.75

0.8

0.85

0.9

DTC Terminal Voltage VDTC (V)

Oscillation Frequency f^OSC(kHz)

Maximum Duty Cycle vs.

Operating Ambient Temperature

Maximum Duty Cycle vs. Power Supply Voltage

100

100

fosc = 200 kHz

fosc = 200 kHz

95

95

90

85

80

75

70

fosc = 1 MHz

90

fosc = 1 MHz

fosc = 2 MHz

Ta = + 25 °C

VCC = CTL

85

80

75

70

DTC pin open

FB = 2 V

fosc = 2 MHz

C^T= 100 pF

Ta = + 25 °C

VCC = CTL = 4 V

DTC pin open

FB = 2 V

CT

= 100 pF

0

2

4

6

8

10

12

−40

−20

0

+20

+40

+60 +80

+100

Power Supply Voltage VCC (V)

Operating Ambient Temperature Ta ( °C)

Start Power Supply Voltage vs. Timing Resistor

2

At evaluating Fujitsu EV board system

1.9

1.8

1.7

1.6

1.5

1.4

1.3

1.2

1.1

1

Ta = −30 °C

Ta = + 25 °C

VCTL = VCC

CT = 100 pF

1

10

100

Timing Resistor RT (kΩ)

(Continued)

15

MB39A123

(Continued)

Error Amp Voltage Gain, Phase vs. Frequency

50

40

225

180

135

90

Ta = +25 °C

VCC = 7 V

Av

2.0 V

240 kΩ

30

φ

20

10 kΩ

+

1 µF

10

45

37

38

−

0

0

2.4 kΩ

IN

36

+

+

−10

−20

−30

−40

−50

−45

−90

−135

−180

−225

OUT

Error Amp1

the same as other

channels

10 kΩ

1.5 V 1.0 V

1 k

10 k

100 k

1 M

10 M

Frequency f (Hz)

Maximum Power Dissipation vs.

Operating Ambient Temperature

(for BCC-48++)

Maximum Power Dissipation vs.

Operating Ambient Temperature

(for LQFP-48P)

2250

2250

2000

1800

1600

1400

1200

1000

800

2000

1800

1600

1400

1200

1000

800

600

600

400

400

200

200

0

0

−40

−20

0

+20

+40

+60

+80 +100

−40

−20

0

+20

+40

+60

+80 +100

Operating Ambient Temperature Ta ( °C)

Operating Ambient Temperature Ta ( °C)

16

MB39A123

■ FUNCTIONAL DESCRIPTION

1. DC/DC Converter Function

(1) Reference voltage block (VREF)

The reference voltage circuit uses the voltage supplied from VCC terminal (pin 48) to generate a temperature

compensated reference voltage (2.0 V Typ) used as the reference voltage for the internal circuits of the IC. It is

also possible to supply the load current of up to 1 mA to external circuits as a reference voltage through the

VREF terminal (pin 9) .

(2) Triangular wave oscillator block (OSC)

The triangular wave oscillator block generates the triangular wave oscillation waveform width of 0.4 V lower limit

and 0.5 V amplitude by the timing resistor (R^T) connected to the RT terminal (pin 11) , and the timing capacitor

(C^T) connected to the CT terminal (pin 12) . The triangular wave is input to the PWM comparator circuits on the IC.

(3) Error amplifier block (Error Amp1 to Error Amp6)

The error amplifier detects output voltage of the DC/DC converter and outputs PWM control signals. An arbitrary

loop gain can be set by connecting a feedback resistor and capacitor from the output terminal to inverted input

terminal of the error amplifier, enabling stable phase compensation for the system.

You can prevent surge currents when the IC is turned on by connecting soft-start capacitors to the CS1 terminal

(pin 39) to CS6 terminal (pin 27) which are the noninverting input terminals of the error amplifier. The IC is started

up at constant soft-start time intervals independent of the output load of the DC/DC converter.

(4) PWM comparator block (PWM Comp.1 to PWM Comp.6)

The PWM comparator block is a voltage-pulse width converter that controls the output duty depending on the

input/output voltage.

An output transistor is turned on, during intervals when the error amplifier output voltage and DTC voltage (ch.2

to ch.6) are higher than the triangular wave voltage.

(5) Output block (Drive1 to Drive6)

The output circuit uses a totem-pole configuration and is capable of driving an external P-ch MOS FET (main

side of ch.1, ch.2, ch.3 and ch.4) and N-ch MOS FET (synchronous rectification side of ch.1, ch.5 and ch.6).

17

MB39A123

2. Channel Control Function

Use the CTL terminal (pin 1), CTL1 terminal (pin 2), CTL2 terminal (pin 3), CTL3 terminal (pin 4), CTL4 terminal

(pin 5), CTL5 terminal (pin 6), and CTL6 terminal (pin 7) to set ON/OFF to the main and each channels.

ON/OFF setting conditions for each channel

CTL CTL1 CTL2 CTL3 CTL4 CTL5 CTL6 Power ch.1

ch.2

OFF

OFF

OFF

ON

ch.3

OFF

OFF

OFF

OFF

ON

ch.4

OFF

OFF

OFF

OFF

OFF

ON

ch.5

OFF

OFF

OFF

OFF

OFF

OFF

ON

ch.6

OFF

OFF

OFF

OFF

OFF

OFF

OFF

ON

L

X

L

H

L

L

L

L

L

H

X

L

L

H

L

L

L

L

H

X

L

L

L

H

L

L

L

H

X

L

L

L

L

H

L

L

H

X

L

L

L

L

L

H

L

H

X

L

L

L

L

L

L

H

H

OFF

ON

ON

ON

ON

ON

ON

ON

ON

OFF

OFF

ON

H

H

H

H

H

H

H

H

OFF

OFF

OFF

OFF

OFF

ON

OFF

OFF

OFF

OFF

ON

OFF

OFF

OFF

ON

OFF

OFF

ON

OFF

ON

ON

Note : Note that current which is over standby current flows into VCC terminal when the CTL terminal is in “L” level

and one of the terminals between CTL1 to CTL6 terminals is set to “H” level.

(Refer to the following circuit)

• CTL1 to CTL6 terminals equivalent circuit

VCC

48

CTL1

∼

200 kΩ

CTL6

86 kΩ

ESD

protection

element

223 kΩ

GND 10

18

MB39A123

3. Protection Function

(1) Timer-latch short-circuit protection circuit (SCP, SCP Comp.)

The short-circuit detection comparator (SCP) detects the output voltage level of each channel. If the output

voltage of any channel is lower than the short-circuit detection voltage, the timer circuit is actuated to start

charging to the capacitor (Cscp) externally connected to the CSCP terminal (pin 13).

When the capacitor (Cscp) voltage becomes about 0.7 V, the output transistor is turned off and the dead time

is set to 100%.

The short-circuit detection from external input is capable by using −INS terminal (pin 8) on short-circuit detection

comparator (SCP Comp.) .

When the protection circuit is actuated, the power supply is rebooted or the CTL terminal (pin 1) is set to "L"

level, resetting the latch as the voltage at the VREF terminal (pin 9) becomes 1.27 V (Min) or less (Refer to

“■SETTING THE TIME CONSTANT FOR TIMER-LATCH SHORT-CIRCUIT PROTECTION CIRCUIT”) .

(2) Under voltage lockout protection circuit block (UVLO)

The transient state or a momentary decrease in the power supply voltage, which occurs when the power supply

is turned on, may cause the control IC to malfunction, resulting in the breakdown or degradation of the system.

To prevent such malfunctions, under voltage lockout protection circuit detects a decrease in internal reference

voltage level with respect to the power supply voltage, turns off the output transistor, and sets the dead time to

100% while holding the CSCP terminal (pin 13) at the "L" level.

The system returns to the normal state when the power supply voltage reaches the reference voltage of the

under voltage lockout protection circuit.

(3) Protection circuit operating function table

The following table shows the output state that the protection circuit is operating.

Operation circuit

OUT1-1 OUT1-2 OUT2

OUT3

OUT4

OUT5

OUT6

Short-circuit protection circuit

H

H

L

L

H

H

H

H

H

H

L

L

L

L

Under voltage lockout protection circuit

19

MB39A123

■ SETTING THE OUTPUT VOLTAGE

• ch.1

R3

Vo

R1

R2

Error

Amp

−

38

39

37

−INE1

1.00 V

R2

+

+

V^O=

(R1 + R2)

FB1

1.00 V

V^O

(R1 + R3) ≥

100 µA

CS1

Set R1 and R3 to prevent the error amp’s response from decreasing by using above formula.

• ch.2 to ch.6

R3

Vo

R1

R2

Error

Amp

−

−INEX

+

+

1.23 V

R2

V^O=

(R1 + R2)

FBX

1.23 V

V^O

(R1 + R3) ≥

100 µA

CSX

X : Each channel number

Set R1 and R3 to prevent the error amp’s response from decreasing by using above formula.

20

MB39A123

• ch.4 (Negative voltage output)

Vo

R1

−INA

INVAmp

−

+

19

−1.23 V

Vo =

R1

R2

R2

R3

OUTA

FB4

18

15

Error

Amp

R4

−

16

17

−INE4

+

+

1.23 V

CS4

21

MB39A123

■ SETTING THE TRIANGULAR WAVE OSCILLATION FREQUENCY

The triangular wave oscillation frequency can be set by connecting a timing resistor (RT ) to the RT terminal (pin

11) and a timing capacitor (C^T) to the CT terminal (pin 12).

Triangular wave oscillation frequency : f^OSC

680000

fOSC (kHz) =:

C^T(pF) × RT (kΩ)

22

MB39A123

■ SETTING THE SOFT-START TIME

To prevent rush currents when the IC is turned on, you can set a soft-start by connecting soft-start capacitors

(C^S1to CS6) to the CS1 terminal (pin 39) to CS6 terminal (pin 27) respectively.

As illustrated below, when each CTLX is set to “H” from “L”, the soft-start capacitors (C^S1to CS6) externally

connected to the CS1 to CS6 terminals are charged at about 1.1 µA.

The error amplifier output (FB1 to FB6) is determined by comparison between the lower voltage of the two non-

inverted input terminal voltage (1.23 V (ch.1 : 1.0 V) , CS terminal voltage) and the inverted input terminal voltage

(−INE1 to −INE6) . The FB terminal voltage is decided for the soft-start period (CS terminal voltage < 1.23 V

(ch.1 : 1.0 V) ) by the comparison between −INE terminal voltage and CS terminal voltage. The DC/DC converter

output voltage rises in proportion to the CS terminal voltage as the soft-start capacitor externally connected to

the CS terminal is charged. The soft-start time is obtained from the following formula :

Soft-start time : ts (time until output voltage 100%)

ch.1

: ts (s) =: 0.91 × C^S1(µF)

ch.2 to ch.6 : ts (s) =: 1.12 × C^SX(µF)

X : Each channel number

Vo

R1

−INEX

VREF

R2

L priority

1.1 µA

Error

AmpX

−

CSX

+

+

CSX

1.23 V (ch.1 : 1.0 V)

FBX

H : CSX can be charged when CTLX is set to "H" and

normal operation is selected

L : CSX is discharged when CTLX is set to "L" and

protective operation is selected

CTLX

CHCTL

X : Each channel number

23

MB39A123

■ PROCESSING WHEN NOT USING CS TERMINAL

When soft-start function is not used, leave the CS1 terminal (pin 39), the CS2 terminal (pin 40), the CS3 terminal

(pin 47), the CS4 terminal (pin 17), the CS5 terminal (pin 20) and the CS6 terminal (pin 27) open.

• When not setting soft-start time

“Open”

“Open”

27

39 CS1

CS6

“Open”

“Open”

“Open”

“Open”

40

47

20

17

CS2

CS3

CS5

CS4

24

MB39A123

■ SETTING THE TIME CONSTANT FOR TIMER-LATCH SHORT-CIRCUIT PROTECTION

CIRCUIT

Each channel uses the short-circuit detection comparator (SCP) to always compare the error amplifier’s output

level to the reference voltage.

While DC/DC converter load conditions are stable on all channels, the short-circuit detection comparator output

remains at “L” level, and the CSCP terminal (pin 13) is held at “L” level.

If the load condition on a channel changes rapidly due to a short-circuit of the load, causing the output voltage

to drop, the output of the short-circuit detection comparator on that channel goes to “H” level.

This causes the external short-circuit protection capacitor C^SCPconnected to the CSCP terminal (pin 13) to be

charged at 1 µA.

Short-circuit detection time : t^CSCP

tCSCP (s) =: 0.70 × CSCP (µF)

When the capacitor C^SCPis charged to the threshold voltage (VTH =: 0.70 V) , the latch is set to and the external

FET is turned off (dead time is set to 100%) . At this time, the latch input is closed and CSCP terminal (pin 13)

is held at “L” level.

The short-circuit detection from external input is capable by using −INS terminal (pin 8) . In this case, the short-

circuit detection operates when the −INS terminal voltage becomes the level of the threshold voltage (V^TH=: IV)

or less.

Note that the latch is reset as the voltage at the VREF terminal (pin 9) is decreased to 1.27 V (Min) or less by

either recycling the power supply or setting the CTL terminal (pin 1) to “L” level.

25

MB39A123

• Timer-latch short-circuit protection circuit

Vo

FBX

R1

Error

AmpX

−

+

−INEX

R2

1.23 V (ch.1 : 1.0 V)

SCP

+

+

Comp.

−

1.1 V

1 µA

To each

channel drive

CSCP

13

CTL

R

VREF

UVLO

CTL

CSCP

S

Latch

X : Each channel

number

26

MB39A123

■ PROCESSING WHEN NOT USING CSCP TERMINAL

To disable the timer-latch short-circuit protection circuit, connect the CSCP terminal (pin 13) to GND in the

shortest distance.

• Processing when not using the CSCP terminal

13

10 GND

CSCP

27

MB39A123

■ SETTING THE DEAD TIME (ch.2 to ch.6)

When the device is set for step-up or inverted output based on the step-up, step-up/down Zeta method, step up/

down Sepic method, or flyback method, the FB terminal voltage may reach and exceed the triangular wave

voltage due to load fluctuation. If this is the case, the output transistor is fixed to a full-ON state (ON duty =

100%). To prevent this, set the maximum duty of the output transistor.

When the DTC terminal is opened, the maximum duty is 92% (Typ) because of this IC built-in resistor which

sets the DTC terminal voltage. This is based on the following setting: 1MHz (R^T= 6.8kΩ/CT = 100pF).

To disable the DTC terminal, connect it to the VREF terminal (pin 9) as illustrated below (when dead time is not

set).

• When dead time is set:

(Setting with built-in resistor:

1MHz [R^T= 6.8kΩ/CT = 100pF]=: 92%)

• When dead time is not set:

9

VREF

DTCX

“Open”

DTCX

X : ch.2 to ch.6

X : ch.2 to ch.6

To change the maximum duty using external resistors, set the DTC terminal voltage by dividing resistance using

the VREF voltage. Refer to “• When dead time is set : (Setting by external resistors)”.

It is possible to set without regard for the built-in resistance value (including tolerance) when setting the external

resistance value to 1/10 of the built-in resistance or less.

Note that the VREF load current must be set such that the total current for all the channels does not exceed 1 mA.

When the DTC terminal voltage is higher than the triangular wave voltage, the output transistor is turned on.

The formula for calculating the maximum duty is as follows, assuming that the triangular wave amplitude and

triangular wave lower limit voltage are about 0.5 V and 0.4 V, respectively.

Vdt − 0.4 V

DUTY (ON) Max =:

× 100 (%)

0.5 V

Rb

Vdt =

R1

10

R2

10

× VREF (V) (condition : Ra <

, Rb <

)

Ra + Rb

Note : DUTY obtained by the above-mentioned formula is a calculated value. For setting, refer to “ON Duty cycle

vs. DTC terminal voltage”.

The maximum duty varies depending on the oscillation frequency, regardless of settings in built-in or external

resistors.

(This is due to the dependency of the peak value of a triangular wave on the oscillation frequency and R^T.

Therefore, if R^Tis greater, the maximum duty decreases, even when the same frequency is used.)

28

MB39A123

Furthermore, the maximum duty increases when the power supply voltage and the temperature are high. It is

therefore recommended to set the duty, based on the “■ TYPICAL CHARACTERISTICS” data, so that it does

not exceed 95% under the worst conditions.

ON duty cycle vs. DTC terminal voltage

100

Ta = + 25 °C

fosc = 200 kHz

95

90

85

80

75

70

65

60

55

50

VCC = CTL = 4 V

FB = 2 V

CT = 100 pF

fosc = 1 MHz

Calculated value

fosc = 1 MHz

fosc = 2 MHz

0.6

0.65

0.7

0.75

0.8

0.85

0.9

DTC terminal voltage VDTC (V)

• When dead time is set

(Setting by external resistors)

VREF

9

Ra

R1 : 131.9 kΩ

DTCX

GND

To PWM Comp.X

Vdt

Rb

R2 : 97.5 kΩ

10

X: ch.2 to ch.6

29

MB39A123

Setting example (for an aim maximum ON duty of 80% (Vdt = 0.8 V) with Ra = 13.7 kΩ and Rb = 9.1 kΩ)

• Calculation using external resistors Ra and Rb only

Rb

Vdt =

× VREF =: 0.80 V

Vdt − 0.4 V

Ra + Rb

DUTY (ON) Max=:

× 100 (%) =: 80% ⋅ ⋅ ⋅ ⋅ (1)

0.5 V

• Calculation taking account of the built-in resistor (tolerance 20%) also

(Rb, R2 Combined resistance)

Vdt =

× VREF =: 0.80 V 0.13%

(Ra, R1 Combined resistance) + (Rb, R2 Combined resistance)

Vdt − 0.4 V

DUTY (ON) Max =:

× 100 (%) =: 80% 0.2% ⋅ ⋅ ⋅ ⋅ (2)

0.5 V

Based on (1) and (2) above, selecting external resistances to 1/10th or less of the built-in resistance enables

the built-in resistance to be ignored.

As for the duty dispersion, please expect 5% at (fosc = 1 MHz) due to the dispersion of a triangular wave

amplitude.

■ PROCESSING WHEN NOT USING ch.4 INV AMP

Short-circuit the - INA terminal (pin 19) and OUTA terminal (pin 18) in the shortest distance when not using ch.4

INV Amp.

• When not using ch.4 INV Amp

19

18 OUTA

−INA

30

MB39A123

■ OPERATION EXPLANATION WHEN CTL TURNING ON AND OFF

When CTL is turned on, internal reference voltage VR and VREF generate. When VREF exceeds each threshold

voltage (VTH) of UVLO (under voltage lockout protection circuit) , UVLO is released, and the operation of output

drive circuit of each channel becomes possible.

When CTL is off, the CS and CSCP terminals are always set to "L" as soon as output drive circuit of each channel

is fixed to full off even if UVLO is released. When VR and VREF fall and VREF decreases the threshold voltage

(VRST) of UVLO (under voltage lockout protection circuit), output drive circuit becomes the UVLO state.

• CTL block equivalent circuit

SCP

ch.1 to ch.4

To output drive circuit

H : at SCP

H : Possible to operate

L : Forced stop

UVLO1

CS1 to CS4

To SCP circuit

To charge/discharge circuit

H : Possible to charge

L : Forced discharge

H : UVLO release

H : Possible to

operate SCP

L : CSCP

ch.5, ch.6

terminal low

To output drive circuit

H : Possible to operate

L : Forced stop

UVLO2

CS5, CS6

H : UVLO release

To charge/discharge circuit

H : Possible to charge

L : Forced discharge

Error Amp reference

1.0 V/1.23 V

48

1

VCC

CTL

bias

Power

ON/OFF

CTL

VREF

VR

9

VREF

31

MB39A123

• Operation waveform when CTL turning on and off

∗2

∗1

H

CTL

L

1.23 V

VR

0 V

2 V

VTH1

VTH2

VRST1

VRST2

VREF

0 V

H

UVLO1

UVLO2

UVLO state

L

UVLO release

UVLO state

UVLO state

H

UVLO state

L

UVLO release

H

ch.1 to ch.4

Output Drive

circuit control

Fixed full off

L

Fixed full off

Possible operate

H

ch.5, ch.6

Output Drive

circuit control

Fixed full off

L

Fixed full off

Possible operate

*1 : Asshowninthesequenceontheabovefigure, whenturningoffCTLwhileeachCHCTListurnedon, intermission

state may be generated due to noise around the CTL threshold voltage. To prevent this, it is recommended

to turn off CTL with a slope of - 1 V/50 µs or higher so that the CTL voltage does not remain in the specified

threshold voltage range (0.5 V to 1.5 V) . If the above slope setting is difficult to achieve, it is recommended

to turn off CTL after turning off all CHCTLs.

Moreover, a voltage remains in the FB terminal, when VCC is turned off at the same time as CTL and CHCTL,

or when VCC is turned off at the same time as CTL while each CHCTL is still turned on. As this may lead to

an overshoot upon restart, it is recommended to turn off V^INand CTL after turning off all the CHCTLs to reduce

FB to 0V.

Likewise, it is recommended to turn off CHCTL with a slope of - 1 V/50 µs or higher.

*2 : When CTL and CHCTL are turned on at the same time, or when CTL is turned on while each CHCTL is turned

on, there exists a period (approx. 200 ns) when the error Amp output voltage (FB) is higher than the triangular

wave voltage (CT) upon the startup of VREF. As a result, when UVLO is released and then the Output Drive

circuit of each channel becomes operable, the output transistor is turned on, generating a voltage at the DC/

DC converter output.

Thevoltagetobegenerated(Vop)dependsonL, CoandV^IN. (See

at CHCTL ON.)

• Vocharacteristics(Vop)whenturningonCTL

It should be noted that the above event does not occur when CTL is turned on while CHCTL is turned off.

Therefore, it is recommended to turn on each CHCTL after turning on CTL.

32

MB39A123

• Vo characteristics (Vop) when turning on CTL at CHCTL ON

At evaluating Fujitsu EV board system

Step-down operation

V^IN= 7.2 V

10

CTL[V]

Vo = 5 V

5

0

CS[V]

CTTLL

L = 15 µH

2

3

2

1

0

Co = 2.2 µF

Load = 50 Ω

CHCTL = ON

CSS

Vo[V]

5

4

3

Vo

Generated voltage

Vop=: 0.4 V

L

VD

Voo

2

1

IL

0

Co

1

D

t[ms]

2

4

6

8

10 12 14 16 18 20

0

TON

Generated output voltage - Output capacitor value

600

At evaluating Fujitsu EV board system

VD

V^IN

500

Ta = + 25 °C

VCC = CTL = 7.2 V

When no load is

applied

400

300

200

100

0

IL

Ip = VIN / L × TON

Ip

L = 6.8 µH

L = 68 µH

This energy Q

moves to Co

Vo

Vop

1

10

100

Vop = Q / Co

Output capacitor value Co (µF)

33

MB39A123

■ ABOUT THE LOW VOLTAGE OPERATION

1.7 V or more is necessary for the VCC terminal (pin 48) and the VCCO terminal (pin 36) for the self-power

supply type to use the step-up circuit as the start voltage.

Even if thereafter V^INvoltage decreases to 1.5 V, operation is possible if the VCC terminal (pin 48) voltage and

the VCCO terminal (pin 36) voltage rise to 2.5 V or more after start-up. However, it is necessary not to exceed

the maximum duty set value by the duty due to the V^INdecrease. Including other channels, execute an enough

operation margin confirmation when using it.

VIN

A

Step-up

A

<<ch.5>>

VREF

R1

R2

VCCO

36

Error

Amp5

Vo5

(5 V)

PWM

Comp.5

−

+

21

−INE5

Drive5

N-ch

+

+

OUT5

+

30

−

1.23 V

CS5

20

0.9 V

0.4 V

Max Duty

92% 5%

VCC

48

DTC5

23

34

MB39A123

■ I/O EQUIVALENT CIRCUIT

• Control block (CTL, CTL1 to CTL6)

• Reference voltage block

VCC

48

VCC

ESD

protection

element

+

−

1.23 V

CTLX

VREF

9

86 kΩ

ESD

79 kΩ

protection

element

ESD

protection

element

223 kΩ

124 kΩ

GND

10

GND

• Soft-start block

• Short-circuit detection block

• Short-circuit detection

comparator block

VCC

VREF

(2.0 V)

VCC

CSX

100 kΩ

VREF

(2.0 V)

VREF

VCC

(2.0 V)

−INS

8

(1 V)

2 kΩ

13

CSCP

GND

GND

GND

• Triangular wave oscillator block (CT)

• Triangular wave oscillator block (RT)

VREF

(2.0 V)

VCC

VREF

(2.0 V)

VCC

+

−

0.64 V

12

CT

11

RT

GND

GND

• Error amplifier block (ch.1 to ch.6)

VCC

VREF

(2.0 V)

CSX

−INEX

FBX

1.0 V (ch.1)

1.23 V (ch.2 to ch.6)

GND

X : Each channel number

(Continued)

35

MB39A123

(Continued)

• Inverting amplifier block

VCC

VREF

(2.0 V)

OUTA

18

19

−INA

GND

• PWM comparator block

• Output block

VCC

36

VCCO

VREF

131.9 kΩ

97.5 kΩ

(2.0 V)

FB2 to FB6

DTCX

CT

OUTX

28

GNDO

GND

X : Each channel number

36

MB39A123

■ LAND MASK PATTERN (BCC-48++)

7 . 1 0

6 . 7 5

0 . 7 0

7 . 2 0

0 8 6 .

0 . 7 0

37

MB39A123

■ USAGE PRECAUTIONS

• Printed circuit board ground lines should be set up with consideration for common impedance.

• Take appropriate static electricity measures.

• Containers for semiconductor materials should have anti-static protection or be made of conductive material.

• After mounting, printed circuit boards should be stored and shipped in conductive bags or containers.

• Work platforms, tools, and instruments should be properly grounded.

• Working personnel should be grounded with resistance of 250 kΩ to 1 MΩ between body and ground.

• Do not apply a negative voltages.

• The use of negative voltages below −0.3 V may create parasitic transistors on LSI lines, which can cause

abnormal operation.

■ ORDERING INFORMATION

Part number

Package

Remarks

48-pin plastic LQFP

(FPT-48P- M26)

MB39A123PMT-❏❏❏E1

Lead Free version

48-pin plastic BCC

(LCC-48P-M08)

MB39A123PVK-❏❏❏E1

Lead Free version

■ EV BOARD ORDERING INFORMATION

EV board part No.

MB39A123EVB-02

EV board version No.

Board Rev.1.0

Remarks

LQFP-48P

■ RoHS COMPLIANCE INFORMATION OF LEAD (Pb) FREE VERSION

The LSI products of Fujitsu Microelectronics with “E1” are compliant with RoHS Directive , and has observed

the standard of lead, cadmium, mercury, Hexavalent chromium, polybrominated biphenyls (PBB) , and polybro-

minated diphenyl ethers (PBDE) .

The product that conforms to this standard is added “E1” at the end of the part number.

38

MB39A123

■ MARKING FORMAT (LEAD FREE VERSION)

MB39A123

XXXX XXX

E1

INDEX

LQFP-48P

(FPT-48P-M26)

Lead Free version

JAPAN

MB39A123

XXXX XXX

E1

INDEX

BCC-48++

(LCC-48P-M08)

Lead Free version

39

MB39A123

■ LABELING SAMPLE (LEAD FREE VERSION)

Lead-free mark

JEITA logo

JEDEC logo

MB123456P - 789 - GE1

(3N) 1MB123456P-789-GE1 1000

G

Pb

(3N)2 1561190005 107210

QC PASS

PCS

1,000

MB123456P - 789 - GE1

ASSEMBLED IN JAPAN

2006/03/01

MB123456P - 789 - GE1

1/1

1561190005

0605 - Z01A 1000

Lead Free version

40

MB39A123

■ MB39A123PMT-❏❏❏E1, MB39A123PVK-❏❏❏E1

RECOMMENDED CONDITIONS OF MOISTURE SENSITIVITY LEVEL

Item

Condition

Mounting Method

Mounting times

IR (infrared reflow) , Manual soldering (partial heating method)

2 times

Please use it within two years after

Before opening

Manufacture.

From opening to the 2nd

Less than 8 days

reflow

Storage period

When the storage period after

opening was exceeded

Please processes within 8 days

after baking (125 °C, 24H)

Storage conditions

5 °C to 30 °C, 70%RH or less (the lowest possible humidity)

[Temperature Profile for FJ Standard IR Reflow]

(1) IR (infrared reflow)

H rank : 260 °C Max

260 °C

255 °C

170 °C

to

190 °C

(b)

(c)

(d)

(e)

RT

(a)

(d')

(a) Temperature Increase gradient : Average 1 °C/s to 4 °C/s

(b) Preliminary heating : Temperature 170 °C to 190 °C, 60 s to 180 s

(c) Temperature Increase gradient : Average 1 °C/s to 4 °C/s

(d) Actual heating

: Temperature 260 °C Max; 255 °C or more, 10 s or less

(d’)

: Temperature 230 °C or more, 40 s or less

or

Temperature 225 °C or more, 60 s or less

or

Temperature 220 °C or more, 80 s or less

(e) Cooling

: Natural cooling or forced cooling

Note : Temperature : the top of the package body

(2) Manual soldering (partial heating method)

Conditions : Temperature 400 °C Max

Times

: 5 s max/pin

41

MB39A123

■ PACKAGE DIMENSIONS

48-pin plastic BCC

Lead pitch

0.50 mm

7.00 mm × 7.00 mm

Plastic mold

0.80 mm Max

0.07 g

Package width ×

package length

Sealing method

Mounting height

Weight

(LCC-48P-M08)

48-pin plastic BCC

(LCC-48P-M08)

6.20(.244)TYP

6.10(.240)TYP

0.50±0.10

(.020±.004)

0.80(.031)MAX

Mount height

7.00±0.10(.276±.004)

37

25

0.50(.020)

TYP

25

37

0.50(.020)

TYP

5.00±0.06

(.197±.002)

6.20(.244)

TYP

0.14(.006)

MIN

6.25(.246)

REF

4.60(.181)

6.10(.240)

TYP

7.00±0.10

5.00(.197)

(.276±.004)

INDEX AREA

REF

4.60(.181)

0.09(.004)

MIN

0.50±0.10

(.020±.004)

5.00±0.06

(.197±.002)

13

1

"B"

"C"

"A"

1

13

5.00(.197)REF

6.25(.246)REF

0.075±0.025

(.003±.001)

(Stand off)

Details of "A" part

Details of "B" part

0.55±0.06

Details of "C" part

C0.20(.008)

0.14(.006)

MIN

0.70±0.06

(.028±.002)

0.55±0.06

(.022±.002)

(.022±.002)

0.05(.002)

0.55±0.06

(.022±.002)

0.60±0.06

(.024±.002)

0.55±0.06

(.022±.002)

0.30±0.06

(.012±.002)

Dimensions in mm (inches).

Note: The values in parentheses are reference values.

C

2004 FUJITSU LIMITED C48061S-c-1-1

(Continued)

42

MB39A123

(Continued)

48-pin plastic LQFP

Lead pitch

0.50 mm

7 × 7 mm

Package width ×

package length

Lead shape

Sealing method

Mounting height

Weight

Gullwing

Plastic mold

1.70 mm MAX

0.17 g

Code

(Reference)

P-LFQFP48-7×7-0.50

(FPT-48P-M26)

48-pin plastic LQFP

(FPT-48P-M26)

Note 1) * : These dimensions include resin protrusion.

Note 2) Pins width and pins thickness include plating thickness.

Note 3) Pins width do not include tie bar cutting remainder.

9.00±0.20(.354±.008)SQ

+0.40

7.00 ^–0.10.276 ^–⁺^.^.⁰⁰⁰¹⁴⁶SQ

0.145±0.055

(.006±.002)

*

36

25

37

24

Details of "A" part

0.08(.003)

1.50 ⁺^–0⁰^.^.¹²⁰⁰

.059 ⁺^–.^.⁰⁰⁰⁰⁴⁸

(Mounting height)

INDEX

48

13

0.10±0.10

(.004±.004)

(Stand off)

"A"

0˚~8˚

1

12

LEAD No.

0.50(.020)

0.25(.010)

0.20±0.05

M

0.08(.003)

(.008±.002)

0.60±0.15

(.024±.006)

Dimensions in mm (inches).

Note: The values in parentheses are reference values.

C

2003 FUJITSU LIMITED F48040S-c-2-2

43

FUJITSU MICROELECTRONICS LIMITED

Shinjuku Dai-Ichi Seimei Bldg. 7-1, Nishishinjuku 2-chome, Shinjuku-ku,

Tokyo 163-0722, Japan

Tel: +81-3-5322-3347 Fax: +81-3-5322-3387

http://jp.fujitsu.com/fml/en/

For further information please contact:

North and South America

Asia Pacific

FUJITSU MICROELECTRONICS AMERICA, INC.

1250 E. Arques Avenue, M/S 333

Sunnyvale, CA 94085-5401, U.S.A.

Tel: +1-408-737-5600 Fax: +1-408-737-5999

http://www.fma.fujitsu.com/

FUJITSU MICROELECTRONICS ASIA PTE LTD.

151 Lorong Chuan, #05-08 New Tech Park,

Singapore 556741

Tel: +65-6281-0770 Fax: +65-6281-0220

http://www.fujitsu.com/sg/services/micro/semiconductor/

Europe

FUJITSU MICROELECTRONICS SHANGHAI CO., LTD.

Rm.3102, Bund Center, No.222 Yan An Road(E),

Shanghai 200002, China

FUJITSU MICROELECTRONICS EUROPE GmbH

Pittlerstrasse 47, 63225 Langen,

Germany

Tel: +86-21-6335-1560 Fax: +86-21-6335-1605

http://cn.fujitsu.com/fmc/

Tel: +49-6103-690-0 Fax: +49-6103-690-122

http://emea.fujitsu.com/microelectronics/

FUJITSU MICROELECTRONICS PACIFIC ASIA LTD.

10/F., World Commerce Centre, 11 Canton Road

Tsimshatsui, Kowloon

Korea

FUJITSU MICROELECTRONICS KOREA LTD.

206 KOSMO TOWER, 1002 Daechi-Dong,

Kangnam-Gu,Seoul 135-280

Korea

Hong Kong

Tel: +852-2377-0226 Fax: +852-2376-3269

http://cn.fujitsu.com/fmc/tw

Tel: +82-2-3484-7100 Fax: +82-2-3484-7111

http://www.fmk.fujitsu.com/

All Rights Reserved.

The contents of this document are subject to change without notice.

Customers are advised to consult with sales representatives before ordering.

The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose

of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device; FUJITSU MICROELECTRONICS

does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporat-

ing the device based on such information, you must assume any responsibility arising out of such use of the information.

FUJITSU MICROELECTRONICS assumes no liability for any damages whatsoever arising out of the use of the information.

Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use

or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU MICROELECTRONICS

or any third party or does FUJITSU MICROELECTRONICS warrant non-infringement of any third-party's intellectual property right or

other right by using such information. FUJITSU MICROELECTRONICS assumes no liability for any infringement of the intellectual

property rights or other rights of third parties which would result from the use of information contained herein.

The products described in this document are designed, developed and manufactured as contemplated for general use, including without

limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured

as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect

to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in

nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in

weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite).

Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any claims or damages arising

in connection with above-mentioned uses of the products.

Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by

incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current

levels and other abnormal operating conditions.

Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations of

the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.

The company names and brand names herein are the trademarks or registered trademarks of their respective owners.

Edited Strategic Business Development Dept.

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