MB86064 [FUJITSU]

Dual 14-bit 1GSa/s DAC; 双14位1GSa / s的DAC


型号：	MB86064
厂家：	FUJITSU
描述：	Dual 14-bit 1GSa/s DAC 双14位1GSa / s的DAC 转换器数模转换器
文件：	总4页 (文件大小：124K)
中文：	中文翻译
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Product Flyer

Mixed Signal Division

October 2004

Version 1.1

MB86064

FME/MS/DAC80/FL/5085

Dual 14-bit 1GSa/s DAC

The Fujitsu MB86064 is a Dual 14-bit 1GSa/s digital to analog

converter (DAC), delivering exceptional dynamic performance.

Each high performance DAC core is capable of generating

multi-standard, multi-carrier communication transmit signals,

suitable for 2, 2.5 and 3G systems. DAC data is input via two

high-speed LVDS ports. These operate in a pseudo double data

rate (DDR) mode, with data latched on both rising and falling

edges. Alternatively, the device can be configured as a

multiplexed dual-port single DAC. To simplify system

integration the DAC operates from a clock running at half the

DAC conversion rate.

PLASTIC PACKAGE

EFBGA-120

Package Dimensions

12 mm x 12 mm

Features

• Dual 14-bit, 1GSa/s Digital to Analog conversion

• Exceptional dynamic performance

PIN ASSIGNMENT

• 74dBc ACLR for 4 UMTS carriers @ 276MHz direct-IF

• 100MHz image-free generated bandwidth capability

• supports UMTS plus digital pre-distortion bandwidth

• Proprietary performance enhancement features

• LVDS data interface

AC19

AA19

AC17

AA17

AC15

AA15

AC13

AA13

AC11

AA11

AC9

AA9

AC7

AA7

AC5

AA5

AB18

Y18

AB16

Y16

AB14

Y14

AB12

Y12

AB10

Y10

AB8

AB6

• Register selectable on-chip LVDS termination resistors

• Fujitsu 4-wire serial control interface

W23

U23

R23

N23

L23

J23

W21

U21

R21

N21

L21

J21

G21

E21

X_A9

X_A10

A10

X_B10

B10

X_B9

V22

T22

P22

V20

T20

P20

M20

K20

H20

F20

DVSS

X_B8

DVDD

DVSS

X_A8

DVDD

X_B7

• Two 16k point programmable on-chip waveform memories

• Low power 3.3V analog and 1.8V digital operation

• 750mW per DAC power dissipation at 1GSa/s

• 0.18µm CMOS technology with Triple Well

• Performance enhanced EFBGA package

X_A7

R14

R12

R10

P15

P13

M13

K13

P11

X_B6

X_B5

X_A6

X_A5

N14

L14

J14

N12

L12

J12

N10

L10

J10

M22

M15

M11

DVSS

X_B3

DVSS

X_A3

DVDD

X_A4

X_B4

K22

K15

K11

X_A1

X_B1

X_B2

X_A2

H22

F22

All centre pins : TG

G23

E23

DVSS

DVDD

DVSS

DVDD

DVSS

• Industrial temperature range (-40°C to +85°C)

D18

B18

D16

B16

D14

B14

D12

B12

D10

B10

C19

A19

C17

A17

C15

A15

C13

A13

C11

A11

Index

Applications

• Multi-carrier, Multi-standard cellular infrastructure

• CDMA, W-CDMA, GSM/EDGE, UMTS

• Wideband communications systems

• High Direct-IF architectures

Not to scale. Viewed from above.

• Arbitrary waveform generation

• Test equipment

• Radar, video & display systems

Production

Page 1 of 4

Disclaimer: The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before

ordering.The information and circuit diagrams in this document are presented “as is”, no license is granted by implication or otherwise.

October 2004 Version 1.1

FME/MS/DAC80/FL/5085

MB86064 Dual 14-bit 1GSa/s DAC

Functional Overview

The MB86064 is a high performance Dual 14-bit 1GSa/s DAC. In addition to two DAC cores the

device features a host of features designed to help both system integration and operation. A

functional block diagram is shown in Figure 1. Analog performance at high frequencies is enhanced

by novel current switch and switch driver designs which provide constant data-independent switching

delay, reducing jitter and distortion.

Clock output 1

LVDS

Control Interface

1.8V LVCMOS

1, 2, 4, 8

4-wire Serial Control Interface

Clock output 2

LVDS

1, 2, 4, 8

RF Clock input

e.g. 500MHz

Double-Edge

clocked

(1GSa/s)

Port A data input

14-bit LVDS

Waveform

Memory

DAC A

Loop clock input

LVDS

Analog output A

Analog output B

(14-bit)

(16K Points)

Waveform

Memory

Loop clock output

LVDS

DAC B

(16K Points)

(14-bit)

(16K Points)

Port B data input

14-bit LVDS

EFBGA-120

Figure 1 MB86064 Functional Block Diagram

The device requires an input clock at half the DAC conversion rate as each DAC core is clocked on

both edges of the input clock. Each DAC core can be regarded as two interleaved DACs, each

running at half rate. The main reason for adopting this approach is that the switch driver inherently

includes a multiplex function through its two input ports. Compared to a conventional switch driver

this allows twice as long to acquire and convert, though because the two paths share current sources

they match exactly at low frequencies. A characteristic of this architecture is a suppressed image

appearing reflected about Fs(dac)/4 of Fclk-Fsig. Duty cycle error in the input clock will exacerbate

this image, but can be minimised by trimming the differential DC offset at the clock input pins.

The big advantage of this approach compared to a single DAC running at half the rate is much

reduced sinx/x roll off, which gives increased output power and better in-band flatness when

generating high output frequencies (e.g. 200MHz and above). This is illustrated in Figure 2 as line 1.

An alternative approach using a return-to-zero output stage has the same sinx/x roll off (and switch

driver speed) but 6dB lower output power and a large image at Fclk-Fout. See Line 2.

Page 2 of 4

Production

Disclaimer: The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before

ordering.The information and circuit diagrams in this document are presented “as is”, no license is granted by implication or otherwise.

October 2004 Version 1.1

FME/MS/DAC80/FL/5085

MB86064 Dual 14-bit 1GSa/s DAC

Line 3 illustrates a conventional DAC

running at half rate.

dBFS

-6

Input Data

Unsigned binary data to each DAC core is

input via a dedicated parallel LVDS port. As

with the DAC core, data is latched on every

rising and falling edge of the clock in a

pseudo DDR mode. For synchronisation of

data generator(s) two LVDS clock outputs

and a Loop-Clock facility are provided.

Frequency

Target high direct-IF

generating region

Figure 2 Benefits of DAC core architecture to

Sinx/x response

Loop-Clock

Maintaining valid clock-to-data timing becomes increasingly difficult at higher clock rates, particularly

taking into account device-to-device variations. The MB86064 minimises potential problems through

its DDR data interface and by providing a loop-clock facility. The on-chip ‘loop’ consists of an LVDS

input connected to an LVDS output, through a programmable delay stage. This loop-through, and the

associated tracking from the data generating device, should be incorporated in the feedback loop of

a Delay-Locked Loop (DLL) or Phase-Locked Loop (PLL) clock generator, within the data generating

device. This enables the system to compensate for variations in input/output delays in both the data

generating device and the DAC.

Performance Enhancement Features

Each DAC core integrates a number of performance enhancing features. Performance levels now

reach the level sought after for next generation systems and high direct-IF architectures.

Serial Control Interface

A Fujitsu 4-wire serial interface is provided for configuration and control of the DAC. Programmed

data is stored in a number of read/writable registers.

Waveform Memory Module

The MB86064 incorporates a Waveform Memory Module featuring two 16k point on-chip waveform

memories. These allow the DAC cores to be driven with user programmed waveforms without the

need for external high speed, pattern generators.

Development Kit

A comprehensive Development Kit (DK),

DK86064, is available which comprises a

number of modules. A base motherboard

provides an interface to the DAC, Clock and

Data modules. Also included is a PC USB

Interface Lead & Control Software.

For further details, please refer to the

associated documentation.

Production

Page 3 of 4

Disclaimer: The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before

ordering.The information and circuit diagrams in this document are presented “as is”, no license is granted by implication or otherwise.

October 2004 Version 1.1

FME/MS/DAC80/FL/5085

MB86064 Dual 14-bit 1GSa/s DAC

Worldwide Headquarters

Japan

Asia

Tel: +81 44 754 3753

Fax: +81 44 754 3329

Tel: +65 281 0770

Fax: +65 281 0220

Fujitsu Limited

Kamikodanaka 4-1-1

Nakahara-ku

Fujitsu Microelectronics Asia Pte Ltd

151 Lorong Chauan

New Tech Park

Kawasaki-shi

Kanagawa-ken 211-8588

Japan

#05-08

Singapore 556741

http://www.fujitsu.com

http://www.fmal.fujitsu.com

USA

Europe

Tel: +1 408 737 5600

Fax: +1 408 737 5999

Fujitsu Microelectronics America, Inc. Tel: +49 6103 6900

Fujitsu Microelectronics Europe GmbH

Fax: +49 6103 690122

1250 E. Arques Avenue, M/S 333

Sunnyvale, CA 94088-3470

USA

Am Siebenstein 6-10

D-63303 Dreieich-Buchschlag

Germany

Tel: +1 800 866 8608 Customer Response Center

Fax: +1 408 737 5984 Mon-Fri: 7am-5pm (PST)

http://www.fma.fujitsu.com/

http://www.fme.fujitsu.com/

The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales

representatives before ordering.

The information and circuit diagrams in this document presented as examples of semiconductor device applications, and are not

intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent

rights or other rights of third parties arising from the use of this information or circuit diagrams. No license is granted by implication

or otherwise under any patent or patent rights of Fujitsu Microelectronics Europe GmbH.

FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office

equipment, industrial, communications, and measurement equipment, personal or household devices, etc.).

CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly

affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as

aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.)

are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages

arising from such use without prior approval.

Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such

failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention

of over-current levels and other abnormal operating conditions.

If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign

Exchange and Foreign Trade Control Law of Japan, the prior authorization by Japanese government should be required for export

of those products from Japan.

FME/MS/DAC80/FL/5085 1.1

Page 4 of 4

Production

Disclaimer: The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before

ordering.The information and circuit diagrams in this document are presented “as is”, no license is granted by implication or otherwise.

MB86064 [FUJITSU]

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