MB86606APMT2_技术文档

FUJITSU SEMICONDUCTOR

DATA SHEET

DS04-22420-3E

ASSP Communication Control

CMOS

FAST-20 SCSI Protocol Controller

MB86606A

■ DESCRIPTION

The MB86606A is an intelligent SCSI protocol controller (SPC) conforming to the ANSI (FAST-20) standard

and integrating a PCI local bus interface function. The specification of SCSI controller block is based on the

MB86605’s one which is a Wide SCSI protocol controller, but the device functions/features to achieve the

FAST-20 data transfer rate of maximum 40 Mbyte/sec at 16-bit FAST-20 SCSI, such as the size of internal data

register FIFO, are larged on the MB86606A. As for the SCSI bus pins, a totem pole type single-ended driver/

receiver is incorporated in the device so that it can drive the SCSI bus directly. Furthermore, the MB86606A is

capable of connecting the external differential type driver/receiver.

The SCSI bus sequence is controlled by commands issued via the system interface. So, it supports sequential

commands that perform the phase-to-phase sequences to reduce the overhead of system’s sequence

operations.

As another key feature to reduce the system overhead, the device has a 2 Kbytes user program memory to store

the user program with the commands. Due to this, all the SCSI bus sequences including the data transfer can

be performed automatically.

As the system interface block, it incorporates a 32-bit PCI local bus interface that easily realizes the SCSI

interface on the motherboards of PCI bus based PCs and WSs, in addition to a 16-bit separate MPU and DMA

buses. For the on-chip PCI bus interface, the MB86606A also incorporates a 32-bit DMA controller that is capable

of supporting the scatter-gather function so that the data transfers can be controlled by both user program and

the host system.

The device is fabricated by the advanced CMOS process and is housed in an 144-pin plastic Quad Flat Package

(Suffix: -PMT2).

■ PACKAGE

144 pin plastic LQFP

(FPT-144P-M08)

MB86606A

■ FEATURES

SCSI Protocol Controller Block:

• Operable as initiator and target

• WIDE and FAST-20 data transfers

Synchronous transfer (max. 40 Mbytes/s: Up to 256 offset values can be set.)

Asynchronous transfer (max. 10 Mbytes/s)

• 512-byte FIFO register for data phase

• Two types (send-only and receive-only) of 32-byte data buffers for message, command, and status phases

(MCS Buffers)

• On-chip totem pole type SCSI single-ended driver/receiver

• Supports external SCSI differential driver/receiver connectivity

• On-chip memory to store transfer parameters for each ID (up to 15 connected devices)

• On-chip 16-bit transfer block counter and 24-bit transfer byte counter

Maximum Transfer Byte : 1 Tbyte at fixed length data transfer

: 16 Mbyte at variable length data transfer

• Supports various control commands:

Sequential Commands

: can perform phase-to-phase sequential operations (functions only when issuing

from a system side.)

Discrete Commands

: can perform any desired sequence to program in the user program memory

Data Transfer Commands : can program the transfer data length at the user program operation.

• On-chip direct control register for SCAM (SCSI Configured AutoMatically) Level-1 Protocol

• Supports Multi Selection/Reselection Responses

Selection and Reselection responses can be done to plural IDs.

• On-chip 2 Kbyte User Program Memory

Two Modes : 2 Kbyte × 1 bank and 1 Kbyte × 2 banks

(While 1 Kbyte × 2 banks are selected, host system can access another bank even if the user

program is executing.)

Access to User program : Burst transfer via I/O access port

: Direct access to 2 Kbyte user program memory (only for PCI bus I/F mode)

• User Selectable Interrupt Report

Unnecessary interrupt reports can be disabled depending on user’s applications to reduce a system ISR

overhead.

• Two automatic receive modes

Initiator : can automatically receive information for new phase to which target switched

Target : can automatically receive attention condition generated by initiator

• Automatic selection/reselection

For command issues

: automatically performs to receive MSG/CMD to the selection/reselection

request from partner device

For user program operation : pauses the program currently executed and automatically jumps to the

specified selection /reselection routine in response to the selection/reselection

request from partner device.

• Operation Clock

System Clock: Max. 40 MHz

Internal Processor Operating Clock: Max. 20 MHz

(Continued)

2

MB86606A

(Continued)

System Interface Block:

• Separate MPU and DMA buses called 16-bit Bus Mode

Directly connectable to 68-series or 80-series MPU

Two transfer modes (Program transfer and DMA transfer (slave mode))

• PCI Bus Interface Mode

Directly connectable to the 32-bit PCI local bus.

On-chip 32-bit DMAC for PCI bus master

Supports the PERR&SERR function

Supports the INTA# Interrupt Signals

Max. 64 bytes burst transfer

PCI system clock: Max. 33 MHz

• Data Bus Parity and Address Bus Parity (only for PCI bus interface mode) generation/check function

Others

• Compact 144-Pin Plastic Quad Flat Package (LQFP, Package Suffix: –PMT2)

• Pin compatible with MB86605

• Supply Voltage: 5V ± 5%

3

MB86606A

■ PIN ASSIGNMENT

• 16-Bit Bus Mode

(TOP VIEW)

1

5

DMD9

V SS

DMD8

DMD7

DMD6

V ^DD

DMD5

V ^SS

DMD4

DMD3

DMD2

V ^SS

LDBOEP

V ^DD

DB12

DB13

DB14

DB15

V ^SS

UDBP

DB0

DB1

V ^SS

DB2

DB3

DB4

DB5

V ^SS

DB6

DB7

LDBP

ATN

V ^SS

BSY

ACK

RST

MSG

SEL

105

100

95

INDEX

10

15

20

25

30

35

DMD1

DMD0

LDMDP

V ^SS

UDP

V ^DD

D15

D14

V ^SS

D13

D12

D11

V ^SS

D10

D9

D8

D7

V ^SS

V DD

D6

D5

90

85

V ^SS

C/D

REQ

I/O

DB8

V ^SS

DB9

DB10

DB11

V ^DD

80

75

D4

V ^SS

D3

(FPT-144P-M08)

4

MB86606A

• PCI Bus Interface Mode

(TOP VIEW)

1

5

AD23

V ^SS

AD22

AD21

AD20

V ^DD

AD19

V SS

AD18

AD17

AD16

V ^SS

LDBOEP

V ^DD

DB12

105

100

95

DB13

DB14

DB15

V ^SS

UDBP

DB0

DB1

V ^SS

DB2

DB3

DB4

DB5

V ^SS

DB6

DB7

LDBP

ATN

V ^SS

BSY

ACK

RST

MSG

SEL

V ^SS

C/D

REQ

I/O

INDEX

10

15

20

25

30

35

C/BE2

FRAME

IRDY

V ^SS

TRDY

V ^DD

DEVSEL

STOP

V ^SS

PERR

PAR

C/BE1

V ^SS

AD15

AD14

AD13

AD12

V ^SS

90

85

80

V DD

DB8

V ^SS

DB9

DB10

DB11

V ^DD

AD11

AD10

AD9

V ^SS

AD8

75

(FPT-144P-M08)

5

MB86606A

■ PIN LIST

PCI bus I/F

mode

PCI bus I/F

mode

16-bit bus mode

no.

Mode 3 (PCI I/F)

Mode 0 (68 I/F) Mode 1 (80 I/F)

no. Mode 0 (68 I/F) Mode 1 (80 I/F)

Mode 3 (PCI I/F)

I/O Pin name I/O Pin name I/O Pin name

1

2

3

4

5

6

7

8

9

I/O DMD9

— V^SS

I/O AD23

31 — V^DD

32 I/O D6

33 I/O D5

34 I/O D4

35 — V^SS

36 I/O D3

37 I/O D2

38 I/O D1

39 I/O D0

40 — V^SS

41 I/O LDP

I/O AD11

I/O AD10

I/O AD9

I/O DMD8

I/O DMD7

I/O DMD6

— V^DD

I/O AD22

I/O AD21

I/O AD20

I/O AD8

I/O C/BE0

I/O AD7

I/O AD6

I/O DMD5

— V^SS

I/O AD19

I/O DMD4

I/O AD18

I/O AD17

I/O AD16

10 I/O DMD3

11 I/O DMD2

12 — V^SS

I/O AD5

I/O AD4

42

43 — V^DD

44 LDS

45 — V^SS

I

UDS

I

BHE

WR

RD

13 I/O DMD1

14 I/O DMD0

15 I/O LDMDP

16 — V^SS

I/O C/BE2

I/O FRAME

I/O IRDY

I

I/O AD3

46

47

48

I

R/W

CS1

CS0

I/O AD2

I/O AD1

I/O AD0

17 I/O UDP

18 — V^DD

I/O TRDY

19 I/O D15

I/O DEVSEL

I/O STOP

49 — V^DD

O/

20 I/O D14

50

INT

OD

21 — V^SS

22 I/O D13

23 I/O D12

24 I/O D11

25 — V^SS

26 I/O D10

27 I/O D9

28 I/O D8

29 I/O D7

30 — V^SS

51

52

I

A4

A3

O

PO1

PO0

I/O PERR

I/O PAR

53 — V^SS

54 SCLK

I/O C/BE1

I

55 IU A2

56 IU A1

57 IU A0

58 — V^SS

IU PI1

I/O AD15

I/O AD14

I/O AD13

I/O AD12

IU PI0

IU N.C.

59

60

I

MODE1

MODE2

(Continued)

6

MB86606A

(Continued)

PCI bus I/F

mode

PCI bus I/F

mode

16-bit bus mode

no.

Mode 3 (PCI I/F)

Mode 0 (68 I/F) Mode 1 (80 I/F)

no. Mode 0 (68 I/F) Mode 1 (80 I/F)

Mode 3 (PCI I/F)

I/O Pin name I/O Pin name I/O Pin name

61

62

I

S/DSEL

TARG

91 I/O DB7

92 I/O DB6

O

63 — V^DD

93

— V^SS

64

65

O

INIT

94 I/O DB5

95 I/O DB4

96 I/O DB3

97 I/O DB2

SELOE

66 — V^SS

67

68

69

70

71

72

O

RSTOE

BSYOE

DBOE11

DBOE10

DBOE9

DBOE8

98

— V^SS

99 I/O DB1

100 I/O DB0

101 I/O UDBP

102

— V^SS

73 — V^DD

74 I/O DB11

75 I/O DB10

76 I/O DB9

77 — V^SS

78 I/O DB8

79 I/O I/O

103 I/O DB15

104 I/O DB14

105 I/O DB13

106 I/O DB12

107

108

109

110

111

112

113

114

115

116

117

118

119

120

—

O

—

O

—

O

V^DD

LDBOEP

DBOE7

DBOE6

DBOE5

V^SS

80 I/O REQ

81 I/O C/D

82 — V^SS

83 I/O SEL

84 I/O MSG

85 I/O RST

86 I/O ACK

87 I/O BSY

88 — V^SS

89 I/O ATN

90 I/O LDBP

DBOE4

DBOE3

DBOE2

V^DD

DBOE1

DBOE0

UDBOEP

DBOE15

(Continued)

7

MB86606A

(Continued)

PCI bus I/F

mode

PCI bus I/F

mode

16-bit bus mode

no.

Mode 3 (PCI I/F)

Mode 0 (68 I/F) Mode 1 (80 I/F)

no. Mode 0 (68 I/F) Mode 1 (80 I/F)

Mode 3 (PCI I/F)

I/O Pin name I/O Pin name I/O Pin name

121 O DBOE14

I/O Pin name I/O Pin name I/O Pin name

133

I

DMLDS

I

DMWR

I/O AD30

122 — V^SS

134 — V^SS

135 DMR/W

123 O DBOE13

124 O DBOE12

I

DMRD

I/O AD29

I/O AD28

136 I/O UDMDP

137 — V^DD

125

126

127

I

DMA0

TP

OD SERR

I

PCLK

138 I/O DMD15

139 I/O DMD14

140 — V^SS

I/O AD27

I/O AD26

RESET

128 — V^SS

129 DACK

I

GNT

141 I/O DMD13

142 I/O DMD12

143 I/O DMD11

144 I/O DMD10

I/O AD25

I/O AD24

I/O C/BE3

130 O DREQ

131 — V^DD

O

PREQ

132

I

DMUDS

I

DMBHE

I/O AD31

I

IDSEL

I

: Input pin

O : Output pin

I/O : Input/Output pin

IU : Input pin with pull-up resistor

OD : Open-drain output pin

8

MB86606A

■ PIN DESCRIPTION

1. SCSI Interface

Pin no.

Pin name

I/O

Function

These are the SCSI control signal input and output

pins.

84, 81

89, 79

MSG, C/D

ATN, I/O

They can be connected directly to a single-ended

SCSI connector.

I/O

Either open-drain or totem pole output can be

selected.

These are the SCSI control signal input and output

pins.

I/O They can be connected directly to a single-ended

SCSI connector.

80, 86

REQ, ACK

The output buffer is the totem pole type.

These are used for output control of SCSI control

signals.

They should be used as control signals for the

external differential driver/receiver circuit.

68

65

67

BSYOE

SELOE

RSTOE

O

These are the SCSI control signal input and output

pins.

I/O They can be connected directly to a single-ended

SCSI connector.

87

83

85

BSY

SEL

RST

The output buffer is the open-drain type.

120, 121, 123, 124, 69 to 72

DBOE15 to DBOE8

UDBOEP

DBOE7 to DBOE0

LDBOEP

These are used for output control of SCSI data bus

signals.

They should be used as control signals for the

external differential driver/receiver circuit.

119

109 to 111, 113 to 115, 117,

O

118

108

These are used to input and output SCSI data bus

signals.

They can be connected directly to a single-ended

SCSI connector.

Either open-drain or totem pole output buffer can be

selected.

103 to 106, 74 to 76, 78

DB15 to DB8

UDBP

DB7 to DB0

LDBP

101

I/O

91, 92, 94 to 97, 99, 100

90

These are used to output signals indicating the chip

operating status.

They should be used as control signals for the

64

62

INIT

TARG

O

external differential driver/receiver circuit.

This is used to input signal for selecting the chip

operation mode.

Single-ended: Input 0

Differential-ended: Input 1

While 0 is input to this pin, all the SCSI control signals,

data bus output control signals, INIT, and TARG

signals are fixed with L level.

61

54

S/DESL

SCLK

I

This pin is used for a system clock input for SCSI

protocol controller block. (Max. 40 MHz)

9

MB86606A

2. 16-Bit Bus Mode-MPU Interface

Pin no.

Pin name

CS0

I/O

Function

This is used to input signals for the MPU to select the SPC

as the I/O device.

48

I

This is used to input select signals (external circuit select

signals) for the MPU to input and output the DMA data bus

data via the SPC.

47

CS1

I

Upper byte and parity of data bus

I/O When CS0 input valid: I/O ports for internal registers in SPC

When CS1 input valid: I/O ports for DMA bus data

19, 20, 22 to 24, 26 to 28 D15 to D8

17

UDP

Lower byte and parity of data bus

I/O When CS0 input valid: I/O ports for internal registers in SPC

When CS1 input valid: I/O ports for DMA bus data

29, 32 to 34, 36 to 39

41

D7 to D0

LDP

These are used to input addresses for selecting the Internal

registers.

51, 52, 55 to 57

A4 to A0

IU

In 80-series mode: This is used to input the read strobe

signal for reading data from the SPC to

the MPU.

46

RD (R/W)

I

In 68-series mode: This is used to input the R/W control

signal for reading and writing data from

the MPU to the SPC.

In 80-series mode: This is used to input the write strobe

signal for writing data from the MPU to

the SPC.

44

42

WR (LDS)

I

In 68-series mode: This is used to input the LDS signal

output by the MPU when the lower byte

of the data bus is valid.

In 80-series mode: This is used to input the BHE signal

output by the MPU when the upper byte

of the data bus is valid.

In 68-series mode: This is used to input the UDS signal

BHE (UDS)

I

output by the MPU when the upper byte

of the data bus is valid.

10

MB86606A

3. 16-Bit Bus Mode – DMA Interface

Pin no.

Pin name

I/O

Function

This is used to output DMA transfer request signals to the

DMAC.

130

DREQ

O

DMA data transfer between the SPC and memory is

requested.

This is used to input DMA-enabling signals from the DMAC.

When the DMA enabling signal is active, DMA reading and

writing are executed.

129

DACK

I

Upper byte and parity of DMA data bus

When CS1 input valid: The MPU data bus is directly

connected.

When 80-series mode: The 2nd data is input/output.

When 68-series mode: The 1st data is input/output.

138, 139, 141 to 144, 1, 3 DMD15 to 8

136 UDMDP

I/O

Lower byte and parity of DMA data bus

When CS1 input valid: The MPU data bus is directly

connected.

When 80-series mode: The 1st data is input/output.

When 68-series mode: The 2nd data is input/output.

4, 5, 7, 9 to 11, 13, 14 DMD7 to 0

I/O

15

LDMDP

In 80-series mode: This is used to input the IORD or RD

signal for outputting data from the SPC

to the DMA bus.

In 68-series mode: This is used to input the R/W control

signal for outputting and inputting data

from the DMAC to the SPC.

135

DMRD (DMR/W)

I

In 80-series mode: This is used to input the IOWR or WR

signal for inputting data from the DMA

bus to the SPC.

In 68-series mode: This is used to input the LDS signal

output by the DMAC when the lower

byte of the DMA data bus is valid.

133

132

DMWR (DMLDS)

I

In 80-series mode: This is used to input the BHE signal

output by the DMAC when the upper

byte of the DMA data bus is valid.

In 68-series mode: This is used to input the UDS signal

output by the DMAC when the upper

DMBHE (DMUDS)

DMA0

byte of the DMA data bus is valid.

This is used to input the address data A0 signal output by

the DMAC in the 80-series mode.

In 68-series mode: Connect to power supply pin (V^DD).

125

126

I

This is used to input DMA-transfer-enabling signals.

When the TP signal is active, the SPC performs the DMA

transfer.

When this signal becomes inactive during DMA transfer, the

transfer stops temporarily at the block boundary.

TP

(Transfer

permission)

11

MB86606A

4. PCI Bus Interface Mode

Pin no.

Pin name

PREQ

I/O

Function

130

129

O

This pin is used to request the bus arbiter for use of the bus.

This is the response signal input pin to the REQ signal from

the bus arbiter.

GNT

I

132, 133, 135, 136,

138, 139, 141, 142, 1, 3

to 5, 7, 9 to 11, 26 to 29, AD31 to AD0

32 to 34, 36, 38, 39, 41,

I/O PCI 32-bit address and data multiplexed pins

42, 44, 46 to 48

143, 13, 24, 37

23

C/BE3 to C/BE0 I/O Bus command and Byte Enable signals multiplexed pins.

This is an even parity signal pin for the AD31 to AD0 and C/

PAR

I/O BE3 to C/BE0 signals. This PAR signal becomes valid after

one clock.

This is a frame signal pin that indicates data are transferring

on the bus.

14

FRAME

I/O

17

15

TRDY

IRDY

I/O Data Ready signal of Target side.

I/O Data Ready signal of Initiator (Bus master) side.

This is a stop request signal to stop the data transfer from

target to master.

20

STOP

I/O

Device select pin. While the device is a target, this pin

outputs the select signal that indicates the self device is

selected. While the device is a master this pin functions as

19

DEVSEL

I/O

an input pin to indicate that a device on the bus is selected.

This is a chip select signal that indicates the configuration

access.

144

126

IDSEL

PCLK

I

PCI bus clock input pin. The maximum clock frequency is 33

MHz.

I

22

PERR

SERR

I/O Data parity error input and output pin.

OD Address parity error output pin.

125

12

MB86606A

5. Other Signals

Pin No.

Pin name

RESET

I/O

Function

127

O

This pin is used to input system reset signals.

These pins are used for setting the device operation mode

as listed in the table below.

MODE1 MODE0

Operation Mode

16-bit bus mode (68 series mode)

16-bit bus mode (80 series mode)

Reserved

0

1

0

1

0

1

59, 60

MODE1, MODE0

I

PCI bus interface mode

Interrupt output pin. Either totem pole or open-drain output

buffer can be selected. This pin has an internal pull-up

resistor.

O/

OD

50

INT

V^DD

6, 18, 31, 43, 49, 63,

73, 107, 116, 131, 137

—

Power supply pin

2, 8, 12, 16, 21, 25, 30,

35, 40, 45, 53, 58, 66,

77, 82, 88, 93, 98, 102, V^SS

112, 122, 128,

Ground pin

134, 140

General purpose output ports that can control the external

active SCSI bus terminator etc. Initial signal level on each

pin is “L”. Those pins are available only for PCI bus interface

mode.

51, 52

PO1, PO0

O

General purpose input ports. Available only for PCI bus

interface mode.

55, 56

57

PI1, PI0

N.C.

IU

—

No connection and unused pins. These pins exist on the only

PCI bus mode. These are internally pulled-up, and do not

connect to the pins.

I

: Input pin

O : Output pin

I/O : Input and Output pin

OD : Open-drain output pin

IU : Input pin with pull-up resistor

13

MB86606A

■ BLOCK DIAGRAM

1. 16-Bit Bus Mode

MPU Interface

MSG

C/D

1

5

I/O

Internal

Various

Processor

Registers

ATN

BSYOE

BSY

2

3

4

SELOE

SEL

Timer

6

(32 Bytes)

Receive

MSG, CMD,

Status Buffer

DREQ

RSTOE

RST

DACK

Phase

Controller

DMBHE (DMUDS)

DMA0

7

(32 Bytes)

REQ

ACK

Send

MSG, CMD,

Status Buffer

Transfer

Controller

DMD15 to 8, UDMAP

DMD7 to 0, LDMDP

INIT

8

(2048 Bytes)

TARG

User

Program

Memory

IOWR (DMLDS)

IORD (DMR/W)

DB15 to 8,

UDBP

DB7 to 0,

LDBP

9

(512 Bytes)

DBOE15 to 8,

UDBOEP

TP

Data

Register

DBOE7 to 0,

LDBOEP

S/DSEL

14

MB86606A

2. PCI Bus Interface Mode

PCI Interface

MSG

C/D

1

5

6

I/O

Internal

Processor

Various

Registers

ATN

BSYOE

BSY

2

3

SELOE

SEL

Timer

(32 Bytes)

Receive

MSG, CMD,

Status Buffer

RSTOE

RST

Phase

11

Controller

7

(32 Bytes)

4

REQ

ACK

Send

MSG, CMD,

Status Buffer

Transfer

Controller

DMA

Controller

INIT

8

(2048 Bytes)

TARG

User

Program

Memory

DB15 to 8,

UDBP

DB7 to 0,

LDBP

9

(512 Bytes)

10

DBOE15 to 8,

UDBOEP

Data

Register

Burst-FIFO

(64 Bytes)

DBOE7 to 0,

LDBOEP

S/DSEL

15

MB86606A

■ BLOCK FUNCTIONS

1. Internal Processor

This processor provides the sequence control between each phase.

2. Timer

This timer manages the time specified by SCSI and the following time:

• REQ/ACK assertion time for data at asynchronous transfer

• Selection/reselection retry time

• Selection/reselection timeout time

• REQ/ACK timeout time during transfer

Asynchronous transfer (target)

Asynchronous transfer (initiator)

Synchronous transfer (target only)

: Time required for initiator to assert ACK signal after asserting REQ

signal

: Time required for target to negate REQ signal after asserting ACK

signal

: Time required for target to receive ACK signal for setting offset value

to 0 from initiator after sending REQ signal

3. Phase Controller

This controller controls the arbitration, selection/reselection, data-in/out, command, status, and message-in/out

phases executed on the SCSI bus.

4. Transfer Controller

This controller controls the information (data, command, status, message) transfer phases executed on the SCSI

bus.

There are two types of transfer for executing the information transfer phases.

• Asynchronous transfer : Control by interlocking REQ and ACK signals

• Synchronous transfer

: Control with maximum of 32-byte offset value in data-in/out phase

Depending on the data migration, there are the following two modes.

• Program transfer : Performed via MPU interface using data registers

• DMA transfer

: Performed via DMA interface using DREQ and DACK pins

At synchronous transfer, the transfer parameters (transfer mode, minimum cycle period of REQ or ACK signal

sent from SPC in synchronous transfer, and maximum value between REQ and ACK signals in synchronous

transfer) can be saved for each ID and are automatically set when the data phase is started. The transfer byte

count is determined by block length × number of blocks.

5. Various Registers

• Command register

This register specifies each command with an 8-bit code.

When using the user program, specify “1” at the Bit 7. The lower 7 bits (Bit 6 to Bit 0) are invalid.

• Nexus status register

This register indicates the chip’s operating condition, the nexused partner’s ID, and data register status.

• SCSI control signal status register

This register indicates the status of SCSI control signals.

16

MB86606A

• Interrupt status register

This register indicates the interrupt status with an 8-bit code.

• Command step register

This register indicates the execution status of each command with an 8-bit step code.

Error causes can be analyzed by referencing the interrupt status register and this register.

• Group 6/7 command length setting register

This register sets the group 6/7 command length not defined in the SCSI standard.

Setting this register determines the group 6/7 command length.

6. Receive MSG, CMD, Status Buffer (Receive MCS Buffer)

This is a 32-byte receive-only information buffer that holds the information for the message, command, and

status received from the SCSI bus.

7. Send MSG, CMD, Status Buffer (Send MCS Buffer)

This is a 32-byte send-only information buffer that holds the information for the message, command, and status

sent on the SCSI bus.

8. User Program Memory

This is a 2048-byte program memory that stores programmable commands. It can consist of 1024-byte × 2

banks or 2048-byte × 1 bank.

9. Data Register

This is a 512-byte FIFO data register that holds data in the data phase executed on the SCSI bus.

10.Burst FIFO

64-byte FIFO type data buffer to perform burst transfer during the PCI bus interface mode. The device has total

576-byte FIFO with Data Register and Burst FIFO in the PCI bus interface mode.

11.DMA Controller

This is a 32-bit DMA Controller that performs data transfer. This DMAC is a bus master during the PCI bus

interface mode.

17

MB86606A

■ ABSOLUTE MAXIMUM RATINGS

Rating

Parameter

Symbol

Unit

Min.

V^SS–0.5

–25

Max.

6.0

Supply voltage*

V^DD

V^I

V

Input voltage*

V^DD+0.5

+85

Output voltage*

V^O

V

Operating ambient temperature

Storage temperature

Top

Tstg

°C

–40

+125

* : The voltages are based on V^SS(= 0V)

Note: Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional

operation should be restricted to the conditions as detailed in the operational sections of this data sheet.

Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

■ RECOMMENDED OPERATING CONDITIONS

Value

Parameter

Symbol

Unit

Min.

4.75

20.0

—

Typ.

5.0

—

Max.

5.25

40.0

33.0

+70

Supply voltage*

V^DD

f^SCSI

f^PCI

Ta

V

SCSI clock input frequency

PCI clock input frequency

MHz

°C

—

Operating temperature

0

—

* : The voltages are based on V^SS(= 0V)

Note: The recommended operating conditions are the recommended values for assuring normal logic operation of

the LSI. Requirements in electrical characteristics (DC and AC characteristics) are assured within the range

of the recommended operating conditions.

18

MB86606A

■ ELECTRICAL CHARACTERISTICS

1. DC Characteristics

(V^DD= +5 V±5%, V^SS= 0 V, Ta = 0 to +70°C)

Value

Parameter

Symbol

Condition

Unit

Min. Max.

V^IH

V^IL

V^IH

V^IL

V^IH

V^IL

—

1.9

—

1.0

—

V

SCSI pins

—

2.4

—

V

Input

SCLK pins

voltage*¹SDSEL pins

—

0.8

—

V

—

2.0

—

V

Other pins

—

0.8

—

V

SCSI-pin input hysteresis*¹

VHW

—

0.3

2.0

—

V

V^OH

V^OL

V^OH

V^OL

V^OH

V^OL

V^OH

V^OL

V^OH

V^OL

I^LI

I^OH= –7.0 mA

I^OL= +48.0 mA

I^OH= –7.0 mA

I^OL= +48.0 mA

I^OH= –7.0 mA

I^OL= +3.2 mA

I^OH= –2.0 mA

I^OL= +6.0 mA

I^OH= –2.0 mA

I^OL= +3.2 mA

V^IN= 0 to V^DD

—

3.24

0.5

3.24

0.5

3.24

0.4

—

V

REQ, ACK

V

RST, BSY, SEL

—

V

In single-

end mode

Non-3ST.

—

V

SCSI pins

Others

2.0

—

V

3ST.

V

Output

voltage*¹

2.0

—

V

In differential mode

V

4.2

—

V

PCI bus interface pins

Other pins

0.55

—

V

4.2

—

V

0.4

+10

150

V

Input leakage current

Input/output leakage current*²

Supply current

–10

—

µA

mA

I^LOZ

I^DD

3ST. : Three-state mode

*1

: SCSI pins are; UDBP, DB15 to DB8, LDBP, DB7 to DB0, BSY, SEL, RST, ATN, REQ, ACK, MSG, C/D and

I/O. (Total 27 pins)

*2

: Leak current when the three-state output pin output and the bidirectional bus pin output are in a high

impedance state.

19

MB86606A

2. Input/Output Pin Capacitance

Parameter

(V^DD= V^IN= 0 V, f = 1 MHz, Ta = +25°C)

Conditions

Pin name

Symbol

Unit

Min.

—

Max.

12

8

SCLK, PCLK (TP)

Other input pins

pF

Input-pin capacitance

C^IN

C^OUT

C^I/O

—

Output-pin capacitance

Input/output-pin capacitance

—

10

25

Non-SCSI pins

SCSI pins

—

3. Load Conditions for Measurement of AC Characteristics

(1) Non-SCSI pins

(V^DD= +5 V±5%, V^SS= 0 V, Ta = 0 to +70°C)

16-bit bus mode

Pin name

Measurement

point

C^L

INT, DREQ

60 pF

D15 to D8, UDP, D7 to D0, LDP,

DMD15 to DMD8, UDMDP,

DMD7 to DMD0, LDMDP

MB86606A

85 pF

Measurement

PCI bus interface mode

C

L

Pin name

C^L

PCI bus pins

50 pF

(2) SCSI pins

(V^DD= +5 V±5%, V^SS= 0 V, Ta = 0 to +70°C)

Measurement

point

R^L1= 110Ω

R L1

Load resistance

Load capacitance

MB86606A

R^L2= 165Ω

C^L= 200 pF

Measurement

C L

R ^L2

20

MB86606A

4. AC Characteristics

(1) System clock

• SCSI clock (SCLK pin)

Value

Typ.

—

Parameter

Symbol

Unit

Min.

25.0

10.0

—

Max.

Clock period

t^CLF

t^CLCH

t^CHCL

t^CR

50.0

—

ns

Clock pulse width (Low)

Clock pulse width (High)

Clock pulse rise time

Clock pulse fall time

—

5.0

t^CF

—

Note: When the internal operating clock frequency is the same as the input clock frequency, (when using the device

in divide-by-1 mode), the clock pulse width for L and H levels must have minimum 20.0 ns or longer.

(i.e. When the clock conversion register value is 0Bh (address: 10h in the initial setting registers) and input

clock frequency = 20 MHz.)

t CLCH

t CLF

t ^CF

t CR

SCLK

2.4 V

0.8 V

2.4 V

0.8 V

2.4 V

0.8 V

t CHCL

21

MB86606A

• PCI clock (PCLK pin)

Parameter

Value

Typ.

—

Symbol

Unit

Min.

30.0

12.0

1.0

Max.

—

Clock frequency

t^PCY

t^PLO

ns

Clock pulse width (Low)

Clock pulse width (High)

Clock slew rate

—

t^PHI

—

ns

t^PSR

—

4.0

—

V/ns

V

Clock amplitude

V^IHP– V^ILP

2.0

—

t PHI

t PCY

V IHP

PCLK

2.0 V

0.8 V

2.0 V

0.8 V

2.0 V

0.8 V

2.0 V

0.8 V

V ILP

t PLO

(2) System reset

Parameter

Value

Typ.

—

Symbol

Unit

Min.

4 t^CLF

Max.

Reset (RESET) pulse “L” level pulse width

t^WRSL

—

ns

t WRSL

RESET

22

MB86606A

5. MPU Interface

(1) Register write timing for 80 series

Value

Parameter

Symbol

Unit

Min.

20

10

5

Max.

Address (A4 to A0), BHE setup time (1)

Address (A4 to A0) hold time (1)

Address (A4 to A0), BHE setup time (2)

Address (A4 to A0) hold time (2)

CS0 setup time

t^AWS

t^AWH

t^ACS

t^ACH

t^CWS

t^CWH

t^DWS

t^DWH

t^WR

—

ns

10

5

CS0 hold time

Data set up time

25

10

70

Data hold time

WR “L” level pulse width

A4 to A0

BHE

t AWS

tACS

t AWH

t ACH

CS0

t CWS

tWR

t CWH

WR

t DWS

t DWH

D15 to 8, UDP

D7 to 0, LDP

Data

23

MB86606A

(2) Register read timing for 80 series

Parameter

Value

Symbol

Unit

Min.

20

10

5

Max.

—

Address (A4 to A0), BHE setup time (1)

Address (A4 to A0) hold time (1)

Address (A4 to A0), BHE setup time (2)

Address (A4 to A0) hold time (2)

CS0 setup time

t^ARS

t^ARH

t^ACS

t^ACH

t^CRS

t^CRH

t^RLD

t^RHD

t^RD

ns

—

10

5

—

CS0 hold time

—

RD set Low → data output defined time

RD set High → data output defined time

RD pulse duration at Low

—

5

40

—

70

—

Interrupt non-hold mode

Interrupt hold mode

t^DL

50

INT signal clear time

t^DL2

n•t^CLF+50

A4 to A0

BHE

t

ARH

t

ARS

t

ACS

t

ACH

CS0

t

CRS

t

RD

t

CRH

RD

t

RLD

t

RHD

D15 to 8, UDP

D7 to 0, LDP

Valid data

t

DL

INT

*

DL2

t

(n is the division ratio)

INT

*: t DL2 is defined by the rising edge of strobe signal that reads out the step code for the last interrupt source.

24

MB86606A

(3) Register write timing for 80 series (for external access)

Value

Parameter

Symbol

Unit

Min.

20

10

5

Max.

Address (A0), BHE setup time (1)

Address (A0) hold time (1)

t^AWSE

t^AWHE

t^ACSE

t^ACHD

t^CWSE

t^CWHE

t^WHLD

t^WHHD

t^DHD

—

40

—

20

ns

Address (A0), BHE setup time (2)

Address (A0) hold time (2)

CS1 setup time

10

5

CS1 hold time

WR set Low → DMA bus output delay time

WR set High → DMA bus output undefined time

MPU data bus → DMA bus output delay time

—

5

—

A0

BHE

t AWHE

t AWSE

t ACSE

t ACHD

CS1

t CWSE

t CWHE

WR

tWLHD

tWHHD

D15 to 8, UDP

D7 to 0, LDP

Data

t DHD

DMD15 to 8, UDMDP

DMD7 to 0, LDMDP

Valid data

25

MB86606A

(4) Register read timing for 80 series (for external access)

Value

Parameter

Symbol

Unit

Min.

20

10

5

Max.

—

Address (A0), BHE setup time (1)

Address (A0), BHE hold time (1)

Address (A0), BHE setup time (2)

Address (A0), BHE hold time (2)

CS1 setup time

t^ARSE

t^ARHE

t^ACSE

t^ACHD

t^CRSE

t^CRHE

t^RLNZ

t^RHHZ

t^HDD

ns

—

10

5

—

CS1 hold time

—

RD set Low → MPU bus output enable time

RD set High → MPU bus output disable time

DMA data bus → MPU bus output delay time

—

5

40

—

20

A0

BHE

t ARSE

t ACSE

t ARHE

t ACHD

CS1

t CRSE

t CRHE

RD

DMD15 to 8,

UDMDP

Data

DMD7 to 0,

LDMDP

t HDD

t RLNZ

t RHHZ

D15 to 8, UDP

D7 to 0, LDP

Valid data

26

MB86606A

(5) Register write timing for 68 series

Parameter

Value

Symbol

Unit

Min.

20

10

5

Max.

Address (A4 to A0) setup time (1)

Address (A4 to A0) hold time (1)

Address (A4 to A0) setup time (2)

Address (A4 to A0) hold time (2)

CS0 setup time

t^AWS

t^AWH

t^ACS

t^ACH

t^CWS

t^CWH

t^DWS

t^DWH

t^DS

—

ns

10

5

CS0 hold time

Data setup time

25

10

70

10

Data hold time

UDS/LDS “L” level pulse width

R/W setup time

t^RWS

t^RWH

R/W hold time

A4 to A0

t AWS

t ACS

t AWH

t ACH

CS0

t CWS

t CWH

R/W

t RWS

t DS

t RWH

UDS/LDS

t ^DWS

t DWH

D15 to 8, UDP

D7 to 0, LDP

Data

27

MB86606A

(6) Register read timing for 68 series

Parameter

Value

Symbol

Unit

Min.

20

10

5

Max.

—

Address (A4 to A0) setup time (1)

Address (A4 to A0) hold time (1)

Address (A4 to A0) setup time (2)

Address (A4 to A0) hold time (2)

CS0 setup time

t^ARS

t^ARH

t^ACS

t^ACH

t^CRS

t^CRH

t^RLD

t^RHD

t^DS

ns

—

10

5

—

CS0 hold time

—

Data output defined time

Data output disable time

UDS/LDS “L” level pulse width

R/W setup time

—

5

40

—

70

10

—

t^RWS

t^RWH

t^DH

—

R/W hold time

—

50

INT signal clear time

ns

t^DH2

n•t^CLK+50

A4 to A0

t

ARS

t

ARH

ACH

t

ACS

t

CS0

R/W

t

CRS

t

CRH

t

RWS

t

DS

t

RWH

UDS/LDS

t

RLD

RHD

D15 to 8, UDP

D7 to 0, LDP

Valid data

t

DH

INT

(n is the division ratio)

*

t

DH2

*: t ^DH2is defined by the rising edge of strobe signal that reads out the step code for the last interrupt source.

28

MB86606A

(7) Register write timing for 68 series (for external access)

Parameter Symbol

Address (A0) setup time (1)

Value

Unit

Min.

20

10

5

Max.

t^AWSE

t^AWHE

t^ACSE

t^ACHD

t^CWSE

t^CWHE

t^WLHD

t^WHHD

t^DHD

—

40

—

20

—

ns

Address (A0) hold time (1)

Address (A0) setup time (2)

Address (A0) hold time (2)

CS1 setup time

10

5

CS1 hold time

UDS/LDS set Low → DMA bus output delay time

UDS/LDS set High → DMA bus output undefined time

MPU data bus → DMA bus output delay time

R/W setup time

—

5

—

10

t^RWS

R/W hold time

t^RWH

A0

t AWSE

t AWHE

t ACHD

t ACSE

CS1

t CWSE

t CWHE

R/W

t RWS

t DS

t RWH

UDS/LDS

tWHHD

t^WLHD

D15 to 8, UDP

Data

D7 to 0, LDP

t ^DHD

DMD15 to 8, UDMDP

DMD7 to 0, LDMDP

Valid data

29

MB86606A

(8) Register read timing for 68 series (for external access)

Value

Parameter

Address (A0) setup time (1)

Symbol

Unit

Min.

20

10

5

Max.

—

t^ARSE

t^ARHE

t^ACSE

t^ACHD

t^CRSE

t^CRHE

t^RLNZ

t^RHH

ns

Address (A0) hold time (1)

—

Address (A0) setup time (2)

Address (A0) hold time (2)

—

CS1 setup time

10

5

—

CS1 hold time

—

UDS/LDS set Low → MPU data bus output enable time

UDS/LDS set High → MPU data bus output disable time

DMA bus → MPU data bus output delay time

R/W setup time

—

5

40

—

t^HDD

—

10

20

—

t^RWS

t^RWH

R/W hold time

—

A0

t ARSE

t ARHE

t ACHD

t ACSE

CS1

t CRHE

t CRSE

R/W

t RWS

t RWH

UDS/LDS

DMD15 to 8,

UDMDP

Data

DMD7 to 0,

LDMDP

t HDD

t RLNZ

t ^RHHZ

D15 to 8, UDP

Valid data

D7 to 0, LDP

30

MB86606A

6. DMA Interface

DMA access timing

The time regulations are not applicable in the following cases:

• During SCSI input and when data buffer EMPTY, or when one byte held

• During SCSI output and when data buffer FULL, or when 511 bytes held

• When parity error detected (target)

• When error stopping transfer occurs in SCSI interface

(1) Access cycle time (burst mode)

Value

Parameter

Symbol

Unit

Min.

2 t^CLF

3 t^CLF

4 t^CLF

1 t^CLF

Max.

t^DCY1

t^DCY2

t^DCY3

t^DCY4

—

ns

Address cycle time

t DCY2

IOWR/IORD

DMUDS/DMLDS

t DCY1

t DCY4

t DCY3

31

MB86606A

(2) Write timing (burst mode for 80 series)

Parameter

Value

Symbol

Unit

Min.

0

Max.

—

DREQ set High → DACK set Low

IOWR set Low → DREQ set Low

DREQ set Low → DREQ set High

DACK set Low → IOWR set Low

DMBHE, DMA0 setup time

IOWR “L” level pulse width

IOWR set High → DACK set High

DMBHE, DMA0 hold time

t^DHAL

t^ALDL

ns

—

0

25

—

t^DLDH

t^ALWL

t^DAWS

t^DWR

0

—

10

25

0

—

t^WHAH

t^DAWH

t^DDWS

t^DDWH

—

10

25

5

—

Input data setup time

—

Input data hold time

—

t DLDH

DREQ

t DHAL

tALDL

DACK

tALWL

t WHAH

DMBHE

DMA0

t DAWS

t DWR

t DAWH

IOWR

t DDWS

t DDWH

DMD15 to 0

UDMDP, LDMDP

Data

32

MB86606A

(3) Read timing (burst mode for 80 series)

Parameter

Value

Symbol

Unit

Min.

0

Max.

DREQ set High → DACK set Low

IORD set Low → DREQ set Low

DREQ set Low → DREQ set High

DACK set Low → IORD set Low

DMBHE, DMA0 setup time

IORD “L” level pulse width

t^DHAL

t^ALDL

t^DLDH

t^ALRL

t^DARS

t^DRD

—

25

—

25

—

ns

—

0

10

25

0

IORD set High → DACK set High

DMBHE, DMA0 hold time

t^RHAH

t^DARH

t^DRLD

t^DRHD

10

—

10

Data output defined time

Data output hold time

t DLDH

DREQ

t DHAL

tALDL

DACK

tALRL

t RHAH

DMBHE

DMA0

t DARS

t DRD

t DARH

IORD

t DRLD

t DRHD

DMD15 to 0

UDMDP, LDMDP

Valid data

33

MB86606A

(4) Write timing (burst mode for 68 series)

Parameter

Value

Symbol

Unit

Min.

0

Max.

—

DREQ set High → DACK set Low

DMUDS/DMLDS set Low → DREQ set Low

DREQ set Low → DREQ set High

DACK set Low → DMUDS/DMLDS set Low

R/W setup time

t^DHAL

t^ALDL

t^DLDH

t^ALDL

t^DRWS

t^DDS

ns

—

0

25

—

5

—

10

25

0

—

DMUDS/DMLDS “L” level pulse width

DMUDS/DMLDS set High → DACK set High

R/W hold time

—

t^DHAH

t^DRWH

t^DDWS

t^DDWH

—

10

25

5

—

Input data setup time

—

Input data hold time

—

t DLDH

DREQ

t DHAL

tALDL

DACK

tALDL

t DHAH

DMR/W

t DRWS

t DDS

t DRWH

DMUDS/DMLDS

t DDWS

t DDWH

DMD15 to 0

UDMDP, LDMDP

Data

34

MB86606A

(5) Read timing (burst mode for 68 series)

Parameter

Value

Symbol

Unit

Min.

0

Max.

DREQ set High → DACK set Low

DMUDS/DMLDS set Low → DREQ set Low

DREQ set Low → DREQ set High

DACK set Low → DMUDS/DMLDS set Low

R/W setup time

t^DHAL

t^ALDL

t^DLDH

t^ALDL

t^DRWS

t^DDS

—

25

—

25

—

ns

—

0

5

10

25

0

DMUDS/DMLDS “L” level pulse width

DMUDS/DMLDS set High → DACK set High

R/W hold time

t^DHAH

t^DRWH

t^DRLD

t^DRHD

10

—

10

Output data valid time

Output data hold time

t DLDH

DREQ

t DHAL

tALDL

DACK

tALDL

t DHAH

DMR/W

t DRWS

t DDS

t DRWH

DMUDS/DMLDS

t DRLD

t DRHD

DMD15 to 0

UDMDP, LDMDP

Valid data

35

MB86606A

7. PCI Interface

(1) PCI interface signal timing

Value

Parameter

Symbol

Unit

Min.

Max.

11/12*¹

28

Output signal valid time

Output disable time

Output enable time

Input setup time

t^PVAL

t^POFF

t^PON

t^PSU

2

—

ns

2

—

7/10*²

0

—

Input hold time

t^PHD

—

*1: Applicable to PREQ pin

*2: Applicable to GNT pin

2.4 V

0.4 V

1.5 V

PCICLK

OUTPUT

H to I

1.5 V

or L to H

t PVAL

OUTPUT

H/L to Hi-Z

t POFF

OUTPUT

Hi-Z to H/L

t PON

2.4 V

1.5 V

INPUT

0.4 V

t PSU

t PHD

36

MB86606A

(2) Configuration register read timing

PCICLK

FRAME

IDSEL

AD31 to 00

C/BE3 to 0

IRDY

TRDY

DEVSEL

STOP

(3) Configuration register write timing

PCICLK

FRAME

IDSEL

AD31 to 00

C/BE3 to 0

IRDY

TRDY

DEVSEL

STOP

Note:For the access to the configuration register, only one data transfer possible.

When a master device executes the burst transfer, a target device asserts STOP signal, and performs the target termination.

37

MB86606A

(4) BASIC control register read timing (target mode)

• Byte or word access

Burst read (target termination), single read

PCICLK

FRAME

AD31 to 00

C/BE3 to 0

IRDY

TRDY

DEVSEL

STOP

Note: Only one data transfer is possible for reading BASIC control regisuter.

When a master device does the burst transfer to the target device, it

asserts STOP signal and performs the target termination.

38

MB86606A

• Long-word access

Single read

PCICLK

FRAME

AD31 to 00

C/BE3 to 0

IRDY

TRDY

DEVSEL

STOP

Burst read (target termination)

PCICLK

FRAME

AD31 to 00

C/BE3 to 0

IRDY

TRDY

DEVSEL

STOP

For the read operation of BASIC control registers, only one data transfer possible.

Note:

When a master device executes the burst transfer, a target device asserts STOP signal and performs the target termination.

39

MB86606A

(5) Target mode – I/O, memory read timing (except BASIC control registers)

• Byte, word access

Single read

PCICLK

FRAME

AD31 to 00

C/BE3 to 0

IRDY

TRDY

DEVSEL

Burst read

PCICLK

FRAME

AD31 to 00

C/BE3 to 0

IRDY

TRDY

DEVSEL

40

MB86606A

• Long-word access

Single read

PCICLK

FRAME

AD31 to 00

C/BE3 to 0

IRDY

TRDY

DEVSEL

Burst read

PCICLK

FRAME

AD31 to 00

C/BE3 to 0

IRDY

TRDY

DEVSEL

41

MB86606A

(6) Target Mode – I/O, memory write timing

• Byte, word access

Single write burst write

PCICLK

FRAME

AD31 to 00

C/BE3 to 0

IRDY

TRDY

DEVSEL

42

MB86606A

• Long-word access

Single write

PCICLK

FRAME

AD31 to 00

C/BE3 to 0

IRDY

TRDY

DEVSEL

Burst write

PCICLK

FRAME

AD31 to 00

C/BE3 to 0

IRDY

TRDY

DEVSEL

43

MB86606A

(7) Data read timing (master mode)

• Burst length = 1 and 4

Burst = 1

Burst = 4

PCICLK

FRAME

AD31 to 00

C/BE3 to 0

IRDY

TRDY

DEVSEL

• Burst length = 8

PCICLK

FRAME

AD31 to 00

C/BE3 to 0

IRDY

TRDY

DEVSEL

• Burst length = 16

PCICLK

FRAME

AD31 to 00

C/BE3 to 0

IRDY

TRDY

DEVSEL

44

MB86606A

(8) Data write timing (master mode)

• Burst length = 1 and 4

Burst = 1

Burst = 4

PCICLK

FRAME

AD31 to 00

C/BE3 to 0

IRDY

TRDY

DEVSEL

• Burst length = 8

PCICLK

FRAME

AD31 to 00

C/BE3 to 0

IRDY

TRDY

DEVSEL

• Burst length = 16

PCICLK

FRAME

AD31 to 00

C/BE3 to 0

IRDY

TRDY

DEVSEL

45

MB86606A

8. SCSI Interface

(1) Initiator asynchronous input timing (target → initiator)

Value

Parameter

ACK set Low → REQ set High

Symbol

Unit

Min.

0

Max.

—

t^AOLR

t^RAOH

t^AOHR

t^DTSU

t^DHLD

t^RAOL

t^RACY

ns

REQ set High → ACK set High

ACK set High → REQ set Low

Data bus valid → REQ set Low

REQ set Low → data bus hold time

REQ set Low → ACK set Low

REQ set High → ACK set Low*

—

60

—

10

20

—

40

—

3 t^CLF+40

* : t^RACY(REQ set High → ACK set Low) is defined as either longer time of (t^RAOH+ t^AOHR+t^RAOL) or t^RACYitself

Note: Time requirements in this section do not apply in the following cases;

• When data register FULL in data phase

• When last byte transferred

t RACY

REQ

tAOLR

t RAOH

tAOHR

t RAOL

ACK

t DTSU

t DHLD

DB7 to 0, P

DB15 to 8, P

Data

46

MB86606A

(2) Initiator asynchronous output timing (initiator → target)

Value

Parameter

ACK set Low → REQ set High

Symbol

Unit

Min.

0

Max.

t^AOLR

t^RAOH

t^AOHR

t^DVLD

t^DIVD

—

60

—

40

ns

REQ set High → ACK set High

ACK set High → REQ set Low

—

10

Data bus output defined → ACK set Low*

REQ set High → data bus hold time

REQ set Low → ACK set Low

S•t^CLF–10

2 t^CLF

—

t^RAOL

* : The value of S varies with the setting condition of the asynchronous setup time register (address 17h).

Note: This output timing regulations are not applicable when the data register is EMPTY in the data phase.

*

t RACY

REQ

tAOLR

t RAOH

tAOHR

t RAOL

ACK

t DVLD

t DIVD

t DVLD

DB7 to 0, P

DB15 to 8, P

Valid data

* : The time (t^RACY) of REQ set High → ACK set Low is defined by the longer time either (t^RAOH+ t^AOHR+t^RAOL)

or (t^DIVD+ t^DVLD).

47

MB86606A

(3) Initiator synchronous transfer REQ/ACK timing

Parameter

Value

Symbol

Unit

Min.

Max.

—

ACK Assertion Period*

ACK Negation Period*

REQ Assertion Period

REQ Negation Period

REQ input cycle time (1)

REQ input cycle time (2)

t^AKAP

t^ANAP

t^RQAP

t^RNAP

t^RQF1

t^RQF2

A•t^CLF–4

N•t^CLF–6

20

ns

—

20

—

1 t^CLF

3 t^CLF

—

* : The values of A and N vary with the setting condition of the transfer period register (address 0Ch).

tAKAP

tANAP

ACK

REQ

t RQAP

t RNAP

t RQF1

t RQF2

48

MB86606A

(4) Initiator synchronous transfer input timing (target → initiator)

Value

Parameter

Symbol

Unit

Min.

5

Max.

Data bus defined → REQ set Low

REQ set Low → data bus hold time

t^DTSU

t^DHLD

—

ns

15

REQ

t DTSU

t DHLD

t DTSU

t DHLD

DB7 to 0, P

DB15 to 8, P

Data

(5) Initiator synchronous transfer output timing (initiator → target)

Value

Parameter

Symbol

Unit

Min.

Max.

—

Data bus defined → ACK set Low*

ACK set Low → data bus hold time*

t^DVAK

t^AKDH

N•t^CLF–10

A•t^CLF–5

ns

—

* : The values of A and N vary with the setting condition of the transfer period register (address 0Ch).

ACK

t DVAK

tAKDH

t DVAK

tAKDH

DB7 to 0, P

DB15 to 8, P

Valid data

49

MB86606A

(6) Target asynchronous input timing (initiator → target)

Value

Parameter

REQ set Low → ACK set Low

Symbol

Unit

Min.

0

Max.

—

t^ROLA

t^AROH

t^ROHA

t^DTSU

t^DHLD

t^AROL

t^RACY

ns

ACK set Low → REQ set High

REQ set High → ACK set High

Data bus defined → ACK set Low

ACK set Low → data bus hold time

ACK set High → REQ set Low

ACK set Low → REQ set Low*

—

0

60

—

10

20

—

40

3 t^CLF+ 40

* : t^RACY(ACK set Low → REQ set Low) is defined as either longer time of (t^AROH+ t^ROHA+t^AROL) or t^RACYitself

Note: The input timing regulations are not applicable when the data register is FULL in the data phase.

t RACY

REQ

tAROH

t ROLA

t ROHA

tAROL

ACK

t DTSU

t DHLD

DB7 to 0, P

DB15 to 8, P

Data

50

MB86606A

(7) Target asynchronous input timing (target → initiator)

Parameter Symbol

REQ set Low → ACK set Low

Value

Unit

Min.

0

Max.

t^ROLA

t^AROH

t^ROHA

t^DVLD

t^DIVD

—

60

—

40

ns

ACK set Low → REQ set High

REQ set High → ACK set High

Data bus defined → REQ set Low*

ACK set Low → data bus hold time

ACK set High → REQ set Low

—

0

S•t^CLF– 10

2 t^CLF

t^AROL

—

* : The value of S varies with the setting condition of the asynchronous setup time register (address 17h).

Note: The output timing regulations are not applicable when the data register is EMPTY in the data phase.

*

t RACY

REQ

tAROH

t ROLA

t ROHA

tAROL

ACK

t DVLD

t DIVD

t DVLD

DB7 to 0, P

DB15 to 8, P

Valid data

* : The time (t^RACY) of ACK set High → REQ set Low is defined by the longer time either (t^AROH+ t^ROHA+t^AROL)

or (t^DIVD+ t^DVLD).

51

MB86606A

(8) Target synchronous transfer REQ/ACK timing

Parameter

Value

Symbol

Unit

Min.

Max.

—

REQ Assertion Period*

REQ Negation Period*

ACK Assertion Period

ACK Negation Period

ACK input cycle time (1)

ACK input cycle time (2)

t^RQAP

t^RNAP

t^AKAP

t^ANAP

t^AKF1

t^AKF2

A•t^CLF– 4

N•t^CLF– 6

20

ns

—

20

—

1 t^CLF

3 t^CLF

—

* : The values of A and N vary with the setting condition of the transfer period register (address 0Ch).

t RQAP

t RNAP

REQ

ACK

tAKAP

tANAP

tAKF1

tAKF2

52

MB86606A

(9) Target synchronous transfer input timing (initiator → target)

Value

Parameter

Symbol

Unit

Min.

5

Max.

Data bus defined → ACK set Low

ACK set Low → data bus hold time

t^DTSU

t^DHLD

—

ns

15

ACK

t DTSU

t DHLD

t DTSU

t DHLD

DB7 to 0, P

DB15 to 8, P

Data

(10) Target synchronous transfer output timing (target → initiator)

Value

Parameter

Symbol

Unit

Min.

Max.

—

Data bus defined → REQ set Low*

REQ set Low → data bus hold time*

t^DVRQ

t^RQDH

N•t^CLF– 10

A•t^CLF– 5

ns

—

* : The values of A and N vary with the setting condition of the transfer period register (address 0Ch).

REQ

t DVRQ

t RQDH

t DVRQ

t RQDH

DB7 to 0, P

Valid data

DB15 to 8, P

53

MB86606A

(11) A, N, and S values in SCSI interface timing specifications

• Set value for transfer period register and A, N values

Transfer period register

A

N

A

N

4

0

1

3

0

1

0

2

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

4

1

0

3

0

1

0

2

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

(inhibited)

9

8

1

2

3

4

5

6

7

8

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

9

10

11

12

13

14

15

16

Note: The A and N values in the register setting represent the assertion and negation periods (in clock-cycle units).

The numerical value is applicable to the A and N values in AC characteristics.

54

MB86606A

• Set value for asynchronous setup time register and S value

Asynchronous setup time setting register

S

3

0

1

0

2

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

Note: The S (setup time) value of the setup time setting register in asynchronous data transfer represents the time

required to assert the REQ or ACK signal after setting data at the data bus (in clock-cycle units).

The numerical value is applicable to the S value in AC characteristics.

55

MB86606A

■ SYSTEM CONFIGURATION

1. 80-Series Separate Bus Type

MB86606A

OSC

RESET

circuit

CLK

DB15 to 8

UDBP

RESET

DB7 to 0

LDBP

MODE0

MODE1

DBOE15 to 8

UDBOEP

INT

MPU

DBOE7 to 0

LDBOEP

CS0

CS1

ADDRESS

DECODE

ACK

ATN

INIT

A4 to A0

ADDRESS BUS

DATA BUS

REQ

MSG

C/D

D15 to D0

UDP

LDP

BHE

RD

I/O

WR

TARG

DMD15 to 0

UDMDP

DMA BUS

LDMDP

BSY

BSYOE

DREQ

DACK

SEL

DATA

BUFFER

MEMORY

DMA

CONTROL

SELOE

DMBHE

IORD

ADDRESS

IOWR

RST

RSTOE

DMA0

TP

SDSEL

56

MB86606A

2. 68-Series Separate Bus Type

MB86606A

CLK

OSC

RESET

circuit

DB15 to 8

RESET

UDBP

DB7 to 0

LDBP

MODE0

MODE1

DBOE15 to 8

UDBOEP

INT

A0

MPU

DBOE7 to 0

LDBOEP

CS0

CS1

ADDRESS

DECODE

ACK

ATN

INIT

A4 to A1

ADDRESS BUS

DATA BUS

REQ

MSG

C/D

D15 to D0

UDP

LDP

R/W

UDS

LDS

I/O

TARG

DMD15 to 0

UDMDP

DMA BUS

LDMDP

BSY

BSYOE

DREQ

DACK

SEL

DATA

BUFFER

MEMORY

DMA

CONTROL

SELOE

DMR/W

DMUDS

DMLDS

ADDRESS

RST

RSTOE

DMA0

TP

SDSEL

57

MB86606A

3. 80-Series Common Bus Type

MB86606A

CLK

OSC

RESET

circuit

DB15 to 8

RESET

LDBP

DB7 to 0

UDBP

MODE0

MODE1

DBOE15 to 8

UDBOEP

INT

MPU

DBOE7 to 0

LDBOEP

CS1

CS0

ADDRESS

DECODE

ACK

ATN

INIT

A4 to A0

ADDRESS BUS

DATA BUS

REQ

MSG

C/D

D15 to D0

UDP

LDP

BHE

RD

I/O

WR

TARG

DMD15 to 0

UDMDP

DMA BUS

LDMDP

BSY

BSYOE

DREQ

DACK

SEL

DMA CONTROL

SELOE

DMBHE

IORD

IOWR

RST

RSTOE

DMA0

TP

SDSEL

58

MB86606A

4. 68-Series Common Bus Type

MB86606A

CLK

OSC

RESET

circuit

DB15 to 8

RESET

LDBP

DB7 to 0

UDBP

MODE0

MODE1

DBOE15 to 8

UDBOEP

INT

A0

MPU

DBOE7 to 0

LDBOEP

CS1

CS0

ADDRESS

DECODE

ACK

ATN

INIT

A4 to A1

ADDRESS BUS

DATA BUS

REQ

MSG

C/D

D15 to D0

UDP

LDP

R/W

UDS

LDS

I/O

TARG

DMD15 to 0

UDMDP

DMA BUS

LDMDP

BSY

BSYOE

DREQ

DACK

SEL

DMA CONTROL

SELOE

DMR/W

DMUDS

DMLDS

RST

RSTOE

DMA0

TP

SDSEL

59

MB86606A

5. Example of Connection in Differential Mode (Example of Driver/Receiver Connection)

(TOP VIEW)

RO 1

RE 2

DE 3

DI 4

8 V ^CC

R

7 DO, RI

6 DO, RI

5 GND

D

MB561

18

MB86606A

DB15 to 0

UDBP

LDBP

R

(+) SIGNAL

18

DBOE15 to 0

UDBOEP

(−) SIGNAL

LDBOEP

D

2

ACK, ATN

INIT

R

(+) SIGNAL

(−) SIGNAL

D

4

REQ, MSG

C/D, I/O

R

(+) SIGNAL

TARG

(−) SIGNAL

D

3

BSY, SEL

RST

R

(+) SIGNAL

BSYOE, SELOE

RSTOE

(−) SIGNAL

D

SDSEL

60

MB86606A

6. Example of Connection in Single-end Mode

MB86606A

DB15 to 0

UDBP

18

LDBP

(OPEN)

DBOE15 to 0

UDBOEP

LDBOEP

2

ACK, ATN

INIT

4

REQ, MSG

C/D, I/O

TARG

3

BSY, SEL

RST

BSYOE, SELOE

RSTOE

(OPEN)

SDSEL

61

MB86606A

■ ORDERING INFORMATION

Part number

Package

Remarks

144-pins, Plastic LQFP

(FPT-144P-M08)

MB86606APMT2

62

MB86606A

■ PACKAGE DIMENSION

144-pin plastic LQFP

(FPT-144P-M08)

22.00±0.30(.866±.012)SQ

1.70(.67)MAX

(Mounting height)

20.00±0.10(.787±.004)SQ

0(0)MIN

(STAND OFF)

108

109

73

72

21.00

(.827)

NOM

Details of "A" part

0.15(.006)

17.50

(.686)

REF

0.15(.006)

INDEX

0.15(.006)MAX

0.40(.016)MAX

144

37

"A"

1

36

LEAD No.

Details of "B" part

0.50(.0197)TYP

0.20±0.10

(.008±.004)

0.15±0.05

(.006±.002)

M

0.08(.003)

0

10°

0.50±0.20(.020±.008)

0.10(.004)

"B"

Dimensions in mm (inches)

C

1995 FUJITSU LIMITED F144019S-1C-2

63

MB86606A

FUJITSU LIMITED

For further information please contact:

Japan

FUJITSU LIMITED

Corporate Global Business Support Division

Electronic Devices

KAWASAKI PLANT, 4-1-1, Kamikodanaka

Nakahara-ku, Kawasaki-shi

Kanagawa 211-8588, Japan

Tel: 81(44) 754-3763

The contents of this document are subject to change without

notice. Customers are advised to consult with FUJITSU sales

representatives before ordering.

Fax: 81(44) 754-3329

http://www.fujitsu.co.jp/

The information and circuit diagrams in this document are

presented as examples of semiconductor device applications,

and are not intended to be incorporated in devices for actual use.

Also, FUJITSU is unable to assume responsibility for

infringement of any patent rights or other rights of third parties

arising from the use of this information or circuit diagrams.

North and South America

FUJITSU MICROELECTRONICS, INC.

Semiconductor Division

3545 North First Street

San Jose, CA 95134-1804, USA

Tel: (408) 922-9000

Fax: (408) 922-9179

FUJITSU semiconductor devices are intended for use in

standard applications (computers, office automation and other

office equipment, industrial, communications, and measurement

equipment, personal or household devices, etc.).

CAUTION:

Customers considering the use of our products in special

applications where failure or abnormal operation may directly

affect human lives or cause physical injury or property damage,

or where extremely high levels of reliability are demanded (such

as aerospace systems, atomic energy controls, sea floor

repeaters, vehicle operating controls, medical devices for life

support, etc.) are requested to consult with FUJITSU sales

representatives before such use. The company will not be

responsible for damages arising from such use without prior

approval.

Customer Response Center

Mon. - Fri.: 7 am - 5 pm (PST)

Tel: (800) 866-8608

Fax: (408) 922-9179

http://www.fujitsumicro.com/

Europe

FUJITSU MIKROELEKTRONIK GmbH

Am Siebenstein 6-10

D-63303 Dreieich-Buchschlag

Germany

Tel: (06103) 690-0

Fax: (06103) 690-122

Any semiconductor devices have an inherent chance of

failure. You must protect against injury, damage or loss from

such failures by incorporating safety design measures into your

facility and equipment such as redundancy, fire protection, and

prevention of over-current levels and other abnormal operating

conditions.

http://www.fujitsu-ede.com/

Asia Pacific

FUJITSU MICROELECTRONICS ASIA PTE LTD

#05-08, 151 Lorong Chuan

New Tech Park

Singapore 556741

Tel: (65) 281-0770

If any products described in this document represent goods or

technologies subject to certain restrictions on export under the

Foreign Exchange and Foreign Trade Law of Japan, the prior

authorization by Japanese government will be required for

export of those products from Japan.

Fax: (65) 281-0220

http://www.fmap.com.sg/

F9904

FUJITSU LIMITED Printed in Japan

64


型号：	MB86606APMT2
厂家：	FUJITSU
描述：	FAST-20 SCSI Protocol Controller FAST- 20 SCSI协议控制器总线控制器微控制器和处理器外围集成电路数据传输 PC 时钟
文件：	总64页 (文件大小：571K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MB86606APMT2 [FUJITSU]

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